Commit 29d26d20e5b4a9f28cdd9d072b407223e7b0e610
1 parent
980f8a0b
fix alpha cmovxx instruction
The CMOV instruction is defined by the alpha manual as: CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format Operation: IF TEST(Rav, Condition_based_on_Opcode) THEN Rc ← Rbv The current qemu behavior inverses Ra and Rb. This is fixed by this patch. Signed-off-by: Tristan Gingold <gingold@adacore.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162
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5 deletions
target-alpha/translate.c
| @@ -390,15 +390,15 @@ static always_inline void gen_cmov (DisasContext *ctx, | @@ -390,15 +390,15 @@ static always_inline void gen_cmov (DisasContext *ctx, | ||
| 390 | int islit, int8_t lit) | 390 | int islit, int8_t lit) |
| 391 | { | 391 | { |
| 392 | if (ra != 31) | 392 | if (ra != 31) |
| 393 | - tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]); | 393 | + tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); |
| 394 | else | 394 | else |
| 395 | - tcg_gen_movi_i64(cpu_T[1], 0); | 395 | + tcg_gen_movi_i64(cpu_T[0], 0); |
| 396 | if (islit) | 396 | if (islit) |
| 397 | - tcg_gen_movi_i64(cpu_T[0], lit); | 397 | + tcg_gen_movi_i64(cpu_T[1], lit); |
| 398 | else if (rb != 31) | 398 | else if (rb != 31) |
| 399 | - tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]); | 399 | + tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]); |
| 400 | else | 400 | else |
| 401 | - tcg_gen_movi_i64(cpu_T[0], 0); | 401 | + tcg_gen_movi_i64(cpu_T[1], 0); |
| 402 | (*gen_test_op)(); | 402 | (*gen_test_op)(); |
| 403 | gen_op_cmov_ir(rc); | 403 | gen_op_cmov_ir(rc); |
| 404 | } | 404 | } |