Commit 22555301adabad6ef2401a7f02bfc2337044ddbd

Authored by Nathan Froyd
Committed by Aurelien Jarno
1 parent 33890b3e

gdb-xml: fix hacks in powerpc register numbering

The powerpc xml files contained a hack--an empty, non-existent
register--for getting the register numbers to line up for
newer (XML-aware) and older (non-XML-aware) GDB.  While this hack worked
in some cases, it didn't work in all cases, notably when the user used
`finish' or `continue': GDB would attempt to read the non-existent
register and QEMU would complain.

This patch fixes things up properly.  Instead of inserting a fake
register, we explicitly declare the floating-point and SPE registers to
start at 71.  This action accomplishes the same thing as the nasty hack,
except that now GDB never tries to fetch the non-existant register 70.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
gdb-xml/power-core.xml
@@ -46,13 +46,4 @@ @@ -46,13 +46,4 @@
46 <reg name="lr" bitsize="32" type="code_ptr"/> 46 <reg name="lr" bitsize="32" type="code_ptr"/>
47 <reg name="ctr" bitsize="32" type="uint32"/> 47 <reg name="ctr" bitsize="32" type="uint32"/>
48 <reg name="xer" bitsize="32" type="uint32"/> 48 <reg name="xer" bitsize="32" type="uint32"/>
49 - <!-- HACK: The way the QEMU GDB stub code is currently written requires  
50 - the "integer" registers from the XML file to span the entirety of  
51 - NUM_CORE_REGS that non-XML-aware GDB requires. Otherwise, XML-aware  
52 - GDB thinks that "coprocessor" registers from XML, such as the  
53 - floating-point registers, have register numbers less than  
54 - NUM_CORE_REGS. This can lead to problems. Work around it by using  
55 - an unnamed register as padding; NUM_CORE_REGS on Power is 71 and  
56 - this register is 70. It would be fpscr for non-XML-aware GDB. -->  
57 - <reg name="" bitsize="32" type="uint32"/>  
58 </feature> 49 </feature>
gdb-xml/power-fpu.xml
@@ -7,7 +7,7 @@ @@ -7,7 +7,7 @@
7 7
8 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 8 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
9 <feature name="org.gnu.gdb.power.fpu"> 9 <feature name="org.gnu.gdb.power.fpu">
10 - <reg name="f0" bitsize="64" type="ieee_double"/> 10 + <reg name="f0" bitsize="64" type="ieee_double" regnum="71"/>
11 <reg name="f1" bitsize="64" type="ieee_double"/> 11 <reg name="f1" bitsize="64" type="ieee_double"/>
12 <reg name="f2" bitsize="64" type="ieee_double"/> 12 <reg name="f2" bitsize="64" type="ieee_double"/>
13 <reg name="f3" bitsize="64" type="ieee_double"/> 13 <reg name="f3" bitsize="64" type="ieee_double"/>
gdb-xml/power-spe.xml
@@ -7,7 +7,7 @@ @@ -7,7 +7,7 @@
7 7
8 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 8 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
9 <feature name="org.gnu.gdb.power.spe"> 9 <feature name="org.gnu.gdb.power.spe">
10 - <reg name="ev0h" bitsize="32"/> 10 + <reg name="ev0h" bitsize="32" regnum="71"/>
11 <reg name="ev1h" bitsize="32"/> 11 <reg name="ev1h" bitsize="32"/>
12 <reg name="ev2h" bitsize="32"/> 12 <reg name="ev2h" bitsize="32"/>
13 <reg name="ev3h" bitsize="32"/> 13 <reg name="ev3h" bitsize="32"/>
gdb-xml/power64-core.xml
@@ -46,13 +46,4 @@ @@ -46,13 +46,4 @@
46 <reg name="lr" bitsize="64" type="code_ptr"/> 46 <reg name="lr" bitsize="64" type="code_ptr"/>
47 <reg name="ctr" bitsize="64" type="uint64"/> 47 <reg name="ctr" bitsize="64" type="uint64"/>
48 <reg name="xer" bitsize="32" type="uint32"/> 48 <reg name="xer" bitsize="32" type="uint32"/>
49 - <!-- HACK: The way the QEMU GDB stub code is currently written requires  
50 - the "integer" registers from the XML file to span the entirety of  
51 - NUM_CORE_REGS that non-XML-aware GDB requires. Otherwise, XML-aware  
52 - GDB thinks that "coprocessor" registers from XML, such as the  
53 - floating-point registers, have register numbers less than  
54 - NUM_CORE_REGS. This can lead to problems. Work around it by using  
55 - an unnamed register as padding; NUM_CORE_REGS on Power is 71 and  
56 - this register is 70. It would be fpscr for non-XML-aware GDB. -->  
57 - <reg name="" bitsize="32" type="uint32"/>  
58 </feature> 49 </feature>