gwj / at91sam9263 · Commits

Commit 20e1fb525a399c0c10b90c7b73e65fc73d251b83

Authored by aurel32
1 parent af4b6c54

target-mips: optimize gen_cl() 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6932 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 11 additions and 15 deletions
target-mips/translate.c
  View file @20e1fb5
@@ -2128,42 +2128,36 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, @@ -2128,42 +2128,36 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
2128 int rd, int rs) 2128 int rd, int rs)
2129 { 2129 {
2130 const char *opn = "CLx"; 2130 const char *opn = "CLx";
2131 - TCGv t0 = tcg_temp_local_new(); 2131 + TCGv t0;
2132 2132
2133 if (rd == 0) { 2133 if (rd == 0) {
2134 /* Treat as NOP. */ 2134 /* Treat as NOP. */
2135 MIPS_DEBUG("NOP"); 2135 MIPS_DEBUG("NOP");
2136 - goto out; 2136 + return;
2137 } 2137 }
  2138 + t0 = tcg_temp_new();
2138 gen_load_gpr(t0, rs); 2139 gen_load_gpr(t0, rs);
2139 switch (opc) { 2140 switch (opc) {
2140 case OPC_CLO: 2141 case OPC_CLO:
2141 - gen_helper_clo(t0, t0); 2142 + gen_helper_clo(cpu_gpr[rd], t0);
2142 opn = "clo"; 2143 opn = "clo";
2143 break; 2144 break;
2144 case OPC_CLZ: 2145 case OPC_CLZ:
2145 - gen_helper_clz(t0, t0); 2146 + gen_helper_clz(cpu_gpr[rd], t0);
2146 opn = "clz"; 2147 opn = "clz";
2147 break; 2148 break;
2148 #if defined(TARGET_MIPS64) 2149 #if defined(TARGET_MIPS64)
2149 case OPC_DCLO: 2150 case OPC_DCLO:
2150 - gen_helper_dclo(t0, t0); 2151 + gen_helper_dclo(cpu_gpr[rd], t0);
2151 opn = "dclo"; 2152 opn = "dclo";
2152 break; 2153 break;
2153 case OPC_DCLZ: 2154 case OPC_DCLZ:
2154 - gen_helper_dclz(t0, t0); 2155 + gen_helper_dclz(cpu_gpr[rd], t0);
2155 opn = "dclz"; 2156 opn = "dclz";
2156 break; 2157 break;
2157 #endif 2158 #endif
2158 - default:  
2159 - MIPS_INVAL(opn);  
2160 - generate_exception(ctx, EXCP_RI);  
2161 - goto out;  
2162 } 2159 }
2163 - gen_store_gpr(t0, rd);  
2164 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); 2160 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
2165 -  
2166 - out:  
2167 tcg_temp_free(t0); 2161 tcg_temp_free(t0);
2168 } 2162 }
2169 2163
@@ -7711,7 +7705,8 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -7711,7 +7705,8 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7711 case OPC_MUL: 7705 case OPC_MUL:
7712 gen_arith(env, ctx, op1, rd, rs, rt); 7706 gen_arith(env, ctx, op1, rd, rs, rt);
7713 break; 7707 break;
7714 - case OPC_CLZ ... OPC_CLO: 7708 + case OPC_CLO:
  7709 + case OPC_CLZ:
7715 check_insn(env, ctx, ISA_MIPS32); 7710 check_insn(env, ctx, ISA_MIPS32);
7716 gen_cl(ctx, op1, rd, rs); 7711 gen_cl(ctx, op1, rd, rs);
7717 break; 7712 break;
@@ -7728,7 +7723,8 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -7728,7 +7723,8 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7728 /* Treat as NOP. */ 7723 /* Treat as NOP. */
7729 break; 7724 break;
7730 #if defined(TARGET_MIPS64) 7725 #if defined(TARGET_MIPS64)
7731 - case OPC_DCLZ ... OPC_DCLO: 7726 + case OPC_DCLO:
  7727 + case OPC_DCLZ:
7732 check_insn(env, ctx, ISA_MIPS64); 7728 check_insn(env, ctx, ISA_MIPS64);
7733 check_mips_64(ctx); 7729 check_mips_64(ctx);
7734 gen_cl(ctx, op1, rd, rs); 7730 gen_cl(ctx, op1, rd, rs);