gwj / at91sam9263 · Commits

Commit 20495218834824723ef81306c6e1fd27fc3ae560

Authored by bellard
1 parent 158142c2

use the generic soft float code 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1333 c046a42c-6fe2-441c-8c8c-71466251a162
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target-arm/nwfpe/ARM-gcc.h deleted 100644 → 0
  View file @158142c
1   -/*
2   --------------------------------------------------------------------------------
3   -The macro `BITS64' can be defined to indicate that 64-bit integer types are
4   -supported by the compiler.
5   --------------------------------------------------------------------------------
6   -*/
7   -#define BITS64
8   -
9   -/*
10   --------------------------------------------------------------------------------
11   -Each of the following `typedef's defines the most convenient type that holds
12   -integers of at least as many bits as specified. For example, `uint8' should
13   -be the most convenient type that can hold unsigned integers of as many as
14   -8 bits. The `flag' type must be able to hold either a 0 or 1. For most
15   -implementations of C, `flag', `uint8', and `int8' should all be `typedef'ed
16   -to the same as `int'.
17   --------------------------------------------------------------------------------
18   -*/
19   -typedef char flag;
20   -typedef unsigned char uint8;
21   -typedef signed char int8;
22   -typedef int uint16;
23   -typedef int int16;
24   -typedef unsigned int uint32;
25   -typedef signed int int32;
26   -#ifdef BITS64
27   -typedef unsigned long long int bits64;
28   -typedef signed long long int sbits64;
29   -#endif
30   -
31   -/*
32   --------------------------------------------------------------------------------
33   -Each of the following `typedef's defines a type that holds integers
34   -of _exactly_ the number of bits specified. For instance, for most
35   -implementation of C, `bits16' and `sbits16' should be `typedef'ed to
36   -`unsigned short int' and `signed short int' (or `short int'), respectively.
37   --------------------------------------------------------------------------------
38   -*/
39   -typedef unsigned char bits8;
40   -typedef signed char sbits8;
41   -typedef unsigned short int bits16;
42   -typedef signed short int sbits16;
43   -typedef unsigned int bits32;
44   -typedef signed int sbits32;
45   -#ifdef BITS64
46   -typedef unsigned long long int uint64;
47   -typedef signed long long int int64;
48   -#endif
49   -
50   -#ifdef BITS64
51   -/*
52   --------------------------------------------------------------------------------
53   -The `LIT64' macro takes as its argument a textual integer literal and if
54   -necessary ``marks'' the literal as having a 64-bit integer type. For
55   -example, the Gnu C Compiler (`gcc') requires that 64-bit literals be
56   -appended with the letters `LL' standing for `long long', which is `gcc's
57   -name for the 64-bit integer type. Some compilers may allow `LIT64' to be
58   -defined as the identity macro: `#define LIT64( a ) a'.
59   --------------------------------------------------------------------------------
60   -*/
61   -#define LIT64( a ) a##LL
62   -#endif
63   -
64   -/*
65   --------------------------------------------------------------------------------
66   -The macro `INLINE' can be used before functions that should be inlined. If
67   -a compiler does not support explicit inlining, this macro should be defined
68   -to be `static'.
69   --------------------------------------------------------------------------------
70   -*/
71   -#define INLINE extern __inline__
72   -
73   -
74   -/* For use as a GCC soft-float library we need some special function names. */
75   -
76   -#ifdef __LIBFLOAT__
77   -
78   -/* Some 32-bit ops can be mapped straight across by just changing the name. */
79   -#define float32_add __addsf3
80   -#define float32_sub __subsf3
81   -#define float32_mul __mulsf3
82   -#define float32_div __divsf3
83   -#define int32_to_float32 __floatsisf
84   -#define float32_to_int32_round_to_zero __fixsfsi
85   -#define float32_to_uint32_round_to_zero __fixunssfsi
86   -
87   -/* These ones go through the glue code. To avoid namespace pollution
88   - we rename the internal functions too. */
89   -#define float32_eq ___float32_eq
90   -#define float32_le ___float32_le
91   -#define float32_lt ___float32_lt
92   -
93   -/* All the 64-bit ops have to go through the glue, so we pull the same
94   - trick. */
95   -#define float64_add ___float64_add
96   -#define float64_sub ___float64_sub
97   -#define float64_mul ___float64_mul
98   -#define float64_div ___float64_div
99   -#define int32_to_float64 ___int32_to_float64
100   -#define float64_to_int32_round_to_zero ___float64_to_int32_round_to_zero
101   -#define float64_to_uint32_round_to_zero ___float64_to_uint32_round_to_zero
102   -#define float64_to_float32 ___float64_to_float32
103   -#define float32_to_float64 ___float32_to_float64
104   -#define float64_eq ___float64_eq
105   -#define float64_le ___float64_le
106   -#define float64_lt ___float64_lt
107   -
108   -#if 0
109   -#define float64_add __adddf3
110   -#define float64_sub __subdf3
111   -#define float64_mul __muldf3
112   -#define float64_div __divdf3
113   -#define int32_to_float64 __floatsidf
114   -#define float64_to_int32_round_to_zero __fixdfsi
115   -#define float64_to_uint32_round_to_zero __fixunsdfsi
116   -#define float64_to_float32 __truncdfsf2
117   -#define float32_to_float64 __extendsfdf2
118   -#endif
119   -
120   -#endif
target-arm/nwfpe/double_cpdo.c
  View file @2049521
... ... @@ -53,7 +53,7 @@ unsigned int DoubleCPDO(const unsigned int opcode)
53 53 switch (fpa11->fType[Fm])
54 54 {
55 55 case typeSingle:
56   - rFm = float32_to_float64(fpa11->fpreg[Fm].fSingle);
  56 + rFm = float32_to_float64(fpa11->fpreg[Fm].fSingle, &fpa11->fp_status);
57 57 break;
58 58  
59 59 case typeDouble:
... ... @@ -79,7 +79,7 @@ unsigned int DoubleCPDO(const unsigned int opcode)
79 79 switch (fpa11->fType[Fn])
80 80 {
81 81 case typeSingle:
82   - rFn = float32_to_float64(fpa11->fpreg[Fn].fSingle);
  82 + rFn = float32_to_float64(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status);
83 83 break;
84 84  
85 85 case typeDouble:
... ... @@ -96,30 +96,30 @@ unsigned int DoubleCPDO(const unsigned int opcode)
96 96 {
97 97 /* dyadic opcodes */
98 98 case ADF_CODE:
99   - fpa11->fpreg[Fd].fDouble = float64_add(rFn,rFm);
  99 + fpa11->fpreg[Fd].fDouble = float64_add(rFn,rFm, &fpa11->fp_status);
100 100 break;
101 101  
102 102 case MUF_CODE:
103 103 case FML_CODE:
104   - fpa11->fpreg[Fd].fDouble = float64_mul(rFn,rFm);
  104 + fpa11->fpreg[Fd].fDouble = float64_mul(rFn,rFm, &fpa11->fp_status);
105 105 break;
106 106  
107 107 case SUF_CODE:
108   - fpa11->fpreg[Fd].fDouble = float64_sub(rFn,rFm);
  108 + fpa11->fpreg[Fd].fDouble = float64_sub(rFn,rFm, &fpa11->fp_status);
109 109 break;
110 110  
111 111 case RSF_CODE:
112   - fpa11->fpreg[Fd].fDouble = float64_sub(rFm,rFn);
  112 + fpa11->fpreg[Fd].fDouble = float64_sub(rFm,rFn, &fpa11->fp_status);
113 113 break;
114 114  
115 115 case DVF_CODE:
116 116 case FDV_CODE:
117   - fpa11->fpreg[Fd].fDouble = float64_div(rFn,rFm);
  117 + fpa11->fpreg[Fd].fDouble = float64_div(rFn,rFm, &fpa11->fp_status);
118 118 break;
119 119  
120 120 case RDF_CODE:
121 121 case FRD_CODE:
122   - fpa11->fpreg[Fd].fDouble = float64_div(rFm,rFn);
  122 + fpa11->fpreg[Fd].fDouble = float64_div(rFm,rFn, &fpa11->fp_status);
123 123 break;
124 124  
125 125 #if 0
... ... @@ -133,7 +133,7 @@ unsigned int DoubleCPDO(const unsigned int opcode)
133 133 #endif
134 134  
135 135 case RMF_CODE:
136   - fpa11->fpreg[Fd].fDouble = float64_rem(rFn,rFm);
  136 + fpa11->fpreg[Fd].fDouble = float64_rem(rFn,rFm, &fpa11->fp_status);
137 137 break;
138 138  
139 139 #if 0
... ... @@ -173,11 +173,11 @@ unsigned int DoubleCPDO(const unsigned int opcode)
173 173  
174 174 case RND_CODE:
175 175 case URD_CODE:
176   - fpa11->fpreg[Fd].fDouble = float64_round_to_int(rFm);
  176 + fpa11->fpreg[Fd].fDouble = float64_round_to_int(rFm, &fpa11->fp_status);
177 177 break;
178 178  
179 179 case SQT_CODE:
180   - fpa11->fpreg[Fd].fDouble = float64_sqrt(rFm);
  180 + fpa11->fpreg[Fd].fDouble = float64_sqrt(rFm, &fpa11->fp_status);
181 181 break;
182 182  
183 183 #if 0
... ...
target-arm/nwfpe/extended_cpdo.c
  View file @2049521
... ... @@ -53,11 +53,11 @@ unsigned int ExtendedCPDO(const unsigned int opcode)
53 53 switch (fpa11->fType[Fm])
54 54 {
55 55 case typeSingle:
56   - rFm = float32_to_floatx80(fpa11->fpreg[Fm].fSingle);
  56 + rFm = float32_to_floatx80(fpa11->fpreg[Fm].fSingle, &fpa11->fp_status);
57 57 break;
58 58  
59 59 case typeDouble:
60   - rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble);
  60 + rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble, &fpa11->fp_status);
61 61 break;
62 62  
63 63 case typeExtended:
... ... @@ -74,11 +74,11 @@ unsigned int ExtendedCPDO(const unsigned int opcode)
74 74 switch (fpa11->fType[Fn])
75 75 {
76 76 case typeSingle:
77   - rFn = float32_to_floatx80(fpa11->fpreg[Fn].fSingle);
  77 + rFn = float32_to_floatx80(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status);
78 78 break;
79 79  
80 80 case typeDouble:
81   - rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble);
  81 + rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status);
82 82 break;
83 83  
84 84 case typeExtended:
... ... @@ -94,30 +94,30 @@ unsigned int ExtendedCPDO(const unsigned int opcode)
94 94 {
95 95 /* dyadic opcodes */
96 96 case ADF_CODE:
97   - fpa11->fpreg[Fd].fExtended = floatx80_add(rFn,rFm);
  97 + fpa11->fpreg[Fd].fExtended = floatx80_add(rFn,rFm, &fpa11->fp_status);
98 98 break;
99 99  
100 100 case MUF_CODE:
101 101 case FML_CODE:
102   - fpa11->fpreg[Fd].fExtended = floatx80_mul(rFn,rFm);
  102 + fpa11->fpreg[Fd].fExtended = floatx80_mul(rFn,rFm, &fpa11->fp_status);
103 103 break;
104 104  
105 105 case SUF_CODE:
106   - fpa11->fpreg[Fd].fExtended = floatx80_sub(rFn,rFm);
  106 + fpa11->fpreg[Fd].fExtended = floatx80_sub(rFn,rFm, &fpa11->fp_status);
107 107 break;
108 108  
109 109 case RSF_CODE:
110   - fpa11->fpreg[Fd].fExtended = floatx80_sub(rFm,rFn);
  110 + fpa11->fpreg[Fd].fExtended = floatx80_sub(rFm,rFn, &fpa11->fp_status);
111 111 break;
112 112  
113 113 case DVF_CODE:
114 114 case FDV_CODE:
115   - fpa11->fpreg[Fd].fExtended = floatx80_div(rFn,rFm);
  115 + fpa11->fpreg[Fd].fExtended = floatx80_div(rFn,rFm, &fpa11->fp_status);
116 116 break;
117 117  
118 118 case RDF_CODE:
119 119 case FRD_CODE:
120   - fpa11->fpreg[Fd].fExtended = floatx80_div(rFm,rFn);
  120 + fpa11->fpreg[Fd].fExtended = floatx80_div(rFm,rFn, &fpa11->fp_status);
121 121 break;
122 122  
123 123 #if 0
... ... @@ -131,7 +131,7 @@ unsigned int ExtendedCPDO(const unsigned int opcode)
131 131 #endif
132 132  
133 133 case RMF_CODE:
134   - fpa11->fpreg[Fd].fExtended = floatx80_rem(rFn,rFm);
  134 + fpa11->fpreg[Fd].fExtended = floatx80_rem(rFn,rFm, &fpa11->fp_status);
135 135 break;
136 136  
137 137 #if 0
... ... @@ -157,11 +157,11 @@ unsigned int ExtendedCPDO(const unsigned int opcode)
157 157  
158 158 case RND_CODE:
159 159 case URD_CODE:
160   - fpa11->fpreg[Fd].fExtended = floatx80_round_to_int(rFm);
  160 + fpa11->fpreg[Fd].fExtended = floatx80_round_to_int(rFm, &fpa11->fp_status);
161 161 break;
162 162  
163 163 case SQT_CODE:
164   - fpa11->fpreg[Fd].fExtended = floatx80_sqrt(rFm);
  164 + fpa11->fpreg[Fd].fExtended = floatx80_sqrt(rFm, &fpa11->fp_status);
165 165 break;
166 166  
167 167 #if 0
... ...
target-arm/nwfpe/fpa11.c
  View file @2049521
... ... @@ -61,74 +61,79 @@ void resetFPA11(void)
61 61  
62 62 void SetRoundingMode(const unsigned int opcode)
63 63 {
64   -#if MAINTAIN_FPCR
  64 + int rounding_mode;
65 65 FPA11 *fpa11 = GET_FPA11();
  66 +
  67 +#if MAINTAIN_FPCR
66 68 fpa11->fpcr &= ~MASK_ROUNDING_MODE;
67 69 #endif
68 70 switch (opcode & MASK_ROUNDING_MODE)
69 71 {
70 72 default:
71 73 case ROUND_TO_NEAREST:
72   - float_rounding_mode = float_round_nearest_even;
  74 + rounding_mode = float_round_nearest_even;
73 75 #if MAINTAIN_FPCR
74 76 fpa11->fpcr |= ROUND_TO_NEAREST;
75 77 #endif
76 78 break;
77 79  
78 80 case ROUND_TO_PLUS_INFINITY:
79   - float_rounding_mode = float_round_up;
  81 + rounding_mode = float_round_up;
80 82 #if MAINTAIN_FPCR
81 83 fpa11->fpcr |= ROUND_TO_PLUS_INFINITY;
82 84 #endif
83 85 break;
84 86  
85 87 case ROUND_TO_MINUS_INFINITY:
86   - float_rounding_mode = float_round_down;
  88 + rounding_mode = float_round_down;
87 89 #if MAINTAIN_FPCR
88 90 fpa11->fpcr |= ROUND_TO_MINUS_INFINITY;
89 91 #endif
90 92 break;
91 93  
92 94 case ROUND_TO_ZERO:
93   - float_rounding_mode = float_round_to_zero;
  95 + rounding_mode = float_round_to_zero;
94 96 #if MAINTAIN_FPCR
95 97 fpa11->fpcr |= ROUND_TO_ZERO;
96 98 #endif
97 99 break;
98 100 }
  101 + set_float_rounding_mode(rounding_mode, &fpa11->fp_status);
99 102 }
100 103  
101 104 void SetRoundingPrecision(const unsigned int opcode)
102 105 {
103   -#if MAINTAIN_FPCR
  106 + int rounding_precision;
104 107 FPA11 *fpa11 = GET_FPA11();
  108 +#if MAINTAIN_FPCR
105 109 fpa11->fpcr &= ~MASK_ROUNDING_PRECISION;
106 110 #endif
107 111 switch (opcode & MASK_ROUNDING_PRECISION)
108 112 {
109 113 case ROUND_SINGLE:
110   - floatx80_rounding_precision = 32;
  114 + rounding_precision = 32;
111 115 #if MAINTAIN_FPCR
112 116 fpa11->fpcr |= ROUND_SINGLE;
113 117 #endif
114 118 break;
115 119  
116 120 case ROUND_DOUBLE:
117   - floatx80_rounding_precision = 64;
  121 + rounding_precision = 64;
118 122 #if MAINTAIN_FPCR
119 123 fpa11->fpcr |= ROUND_DOUBLE;
120 124 #endif
121 125 break;
122 126  
123 127 case ROUND_EXTENDED:
124   - floatx80_rounding_precision = 80;
  128 + rounding_precision = 80;
125 129 #if MAINTAIN_FPCR
126 130 fpa11->fpcr |= ROUND_EXTENDED;
127 131 #endif
128 132 break;
129 133  
130   - default: floatx80_rounding_precision = 80;
  134 + default: rounding_precision = 80;
131 135 }
  136 + set_floatx80_rounding_precision(rounding_precision, &fpa11->fp_status);
132 137 }
133 138  
134 139 /* Emulate the instruction in the opcode. */
... ...
target-arm/nwfpe/fpa11.h
  View file @2049521
... ... @@ -83,6 +83,7 @@ typedef struct tagFPA11 {
83 83 so we can use it to detect whether this
84 84 instance of the emulator needs to be
85 85 initialised. */
  86 + float_status fp_status; /* QEMU float emulator status */
86 87 } FPA11;
87 88  
88 89 extern FPA11* qemufpa;
... ...
target-arm/nwfpe/fpa11_cpdo.c
  View file @2049521
... ... @@ -80,10 +80,10 @@ unsigned int EmulateCPDO(const unsigned int opcode)
80 80 {
81 81 if (typeDouble == nType)
82 82 fpa11->fpreg[Fd].fSingle =
83   - float64_to_float32(fpa11->fpreg[Fd].fDouble);
  83 + float64_to_float32(fpa11->fpreg[Fd].fDouble, &fpa11->fp_status);
84 84 else
85 85 fpa11->fpreg[Fd].fSingle =
86   - floatx80_to_float32(fpa11->fpreg[Fd].fExtended);
  86 + floatx80_to_float32(fpa11->fpreg[Fd].fExtended, &fpa11->fp_status);
87 87 }
88 88 break;
89 89  
... ... @@ -91,10 +91,10 @@ unsigned int EmulateCPDO(const unsigned int opcode)
91 91 {
92 92 if (typeSingle == nType)
93 93 fpa11->fpreg[Fd].fDouble =
94   - float32_to_float64(fpa11->fpreg[Fd].fSingle);
  94 + float32_to_float64(fpa11->fpreg[Fd].fSingle, &fpa11->fp_status);
95 95 else
96 96 fpa11->fpreg[Fd].fDouble =
97   - floatx80_to_float64(fpa11->fpreg[Fd].fExtended);
  97 + floatx80_to_float64(fpa11->fpreg[Fd].fExtended, &fpa11->fp_status);
98 98 }
99 99 break;
100 100  
... ... @@ -102,10 +102,10 @@ unsigned int EmulateCPDO(const unsigned int opcode)
102 102 {
103 103 if (typeSingle == nType)
104 104 fpa11->fpreg[Fd].fExtended =
105   - float32_to_floatx80(fpa11->fpreg[Fd].fSingle);
  105 + float32_to_floatx80(fpa11->fpreg[Fd].fSingle, &fpa11->fp_status);
106 106 else
107 107 fpa11->fpreg[Fd].fExtended =
108   - float64_to_floatx80(fpa11->fpreg[Fd].fDouble);
  108 + float64_to_floatx80(fpa11->fpreg[Fd].fDouble, &fpa11->fp_status);
109 109 }
110 110 break;
111 111 }
... ...
target-arm/nwfpe/fpa11_cpdt.c
  View file @2049521
... ... @@ -106,11 +106,11 @@ void storeSingle(const unsigned int Fn,unsigned int *pMem)
106 106 switch (fpa11->fType[Fn])
107 107 {
108 108 case typeDouble:
109   - val = float64_to_float32(fpa11->fpreg[Fn].fDouble);
  109 + val = float64_to_float32(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status);
110 110 break;
111 111  
112 112 case typeExtended:
113   - val = floatx80_to_float32(fpa11->fpreg[Fn].fExtended);
  113 + val = floatx80_to_float32(fpa11->fpreg[Fn].fExtended, &fpa11->fp_status);
114 114 break;
115 115  
116 116 default: val = fpa11->fpreg[Fn].fSingle;
... ... @@ -129,11 +129,11 @@ void storeDouble(const unsigned int Fn,unsigned int *pMem)
129 129 switch (fpa11->fType[Fn])
130 130 {
131 131 case typeSingle:
132   - val = float32_to_float64(fpa11->fpreg[Fn].fSingle);
  132 + val = float32_to_float64(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status);
133 133 break;
134 134  
135 135 case typeExtended:
136   - val = floatx80_to_float64(fpa11->fpreg[Fn].fExtended);
  136 + val = floatx80_to_float64(fpa11->fpreg[Fn].fExtended, &fpa11->fp_status);
137 137 break;
138 138  
139 139 default: val = fpa11->fpreg[Fn].fDouble;
... ... @@ -157,11 +157,11 @@ void storeExtended(const unsigned int Fn,unsigned int *pMem)
157 157 switch (fpa11->fType[Fn])
158 158 {
159 159 case typeSingle:
160   - val = float32_to_floatx80(fpa11->fpreg[Fn].fSingle);
  160 + val = float32_to_floatx80(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status);
161 161 break;
162 162  
163 163 case typeDouble:
164   - val = float64_to_floatx80(fpa11->fpreg[Fn].fDouble);
  164 + val = float64_to_floatx80(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status);
165 165 break;
166 166  
167 167 default: val = fpa11->fpreg[Fn].fExtended;
... ...
target-arm/nwfpe/fpa11_cprt.c
  View file @2049521
... ... @@ -21,7 +21,6 @@
21 21 */
22 22  
23 23 #include "fpa11.h"
24   -#include "milieu.h"
25 24 #include "softfloat.h"
26 25 #include "fpopcode.h"
27 26 #include "fpa11.inl"
... ... @@ -89,7 +88,7 @@ unsigned int PerformFLT(const unsigned int opcode)
89 88 {
90 89 fpa11->fType[getFn(opcode)] = typeSingle;
91 90 fpa11->fpreg[getFn(opcode)].fSingle =
92   - int32_to_float32(readRegister(getRd(opcode)));
  91 + int32_to_float32(readRegister(getRd(opcode)), &fpa11->fp_status);
93 92 }
94 93 break;
95 94  
... ... @@ -97,7 +96,7 @@ unsigned int PerformFLT(const unsigned int opcode)
97 96 {
98 97 fpa11->fType[getFn(opcode)] = typeDouble;
99 98 fpa11->fpreg[getFn(opcode)].fDouble =
100   - int32_to_float64(readRegister(getRd(opcode)));
  99 + int32_to_float64(readRegister(getRd(opcode)), &fpa11->fp_status);
101 100 }
102 101 break;
103 102  
... ... @@ -105,7 +104,7 @@ unsigned int PerformFLT(const unsigned int opcode)
105 104 {
106 105 fpa11->fType[getFn(opcode)] = typeExtended;
107 106 fpa11->fpreg[getFn(opcode)].fExtended =
108   - int32_to_floatx80(readRegister(getRd(opcode)));
  107 + int32_to_floatx80(readRegister(getRd(opcode)), &fpa11->fp_status);
109 108 }
110 109 break;
111 110  
... ... @@ -128,7 +127,7 @@ unsigned int PerformFIX(const unsigned int opcode)
128 127 case typeSingle:
129 128 {
130 129 writeRegister(getRd(opcode),
131   - float32_to_int32(fpa11->fpreg[Fn].fSingle));
  130 + float32_to_int32(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status));
132 131 }
133 132 break;
134 133  
... ... @@ -136,14 +135,14 @@ unsigned int PerformFIX(const unsigned int opcode)
136 135 {
137 136 //printf("F%d is 0x%llx\n",Fn,fpa11->fpreg[Fn].fDouble);
138 137 writeRegister(getRd(opcode),
139   - float64_to_int32(fpa11->fpreg[Fn].fDouble));
  138 + float64_to_int32(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status));
140 139 }
141 140 break;
142 141  
143 142 case typeExtended:
144 143 {
145 144 writeRegister(getRd(opcode),
146   - floatx80_to_int32(fpa11->fpreg[Fn].fExtended));
  145 + floatx80_to_int32(fpa11->fpreg[Fn].fExtended, &fpa11->fp_status));
147 146 }
148 147 break;
149 148  
... ... @@ -157,22 +156,23 @@ unsigned int PerformFIX(const unsigned int opcode)
157 156 static unsigned int __inline__
158 157 PerformComparisonOperation(floatx80 Fn, floatx80 Fm)
159 158 {
  159 + FPA11 *fpa11 = GET_FPA11();
160 160 unsigned int flags = 0;
161 161  
162 162 /* test for less than condition */
163   - if (floatx80_lt(Fn,Fm))
  163 + if (floatx80_lt(Fn,Fm, &fpa11->fp_status))
164 164 {
165 165 flags |= CC_NEGATIVE;
166 166 }
167 167  
168 168 /* test for equal condition */
169   - if (floatx80_eq(Fn,Fm))
  169 + if (floatx80_eq(Fn,Fm, &fpa11->fp_status))
170 170 {
171 171 flags |= CC_ZERO;
172 172 }
173 173  
174 174 /* test for greater than or equal condition */
175   - if (floatx80_lt(Fm,Fn))
  175 + if (floatx80_lt(Fm,Fn, &fpa11->fp_status))
176 176 {
177 177 flags |= CC_CARRY;
178 178 }
... ... @@ -208,14 +208,14 @@ static unsigned int PerformComparison(const unsigned int opcode)
208 208 //printk("single.\n");
209 209 if (float32_is_nan(fpa11->fpreg[Fn].fSingle))
210 210 goto unordered;
211   - rFn = float32_to_floatx80(fpa11->fpreg[Fn].fSingle);
  211 + rFn = float32_to_floatx80(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status);
212 212 break;
213 213  
214 214 case typeDouble:
215 215 //printk("double.\n");
216 216 if (float64_is_nan(fpa11->fpreg[Fn].fDouble))
217 217 goto unordered;
218   - rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble);
  218 + rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status);
219 219 break;
220 220  
221 221 case typeExtended:
... ... @@ -244,14 +244,14 @@ static unsigned int PerformComparison(const unsigned int opcode)
244 244 //printk("single.\n");
245 245 if (float32_is_nan(fpa11->fpreg[Fm].fSingle))
246 246 goto unordered;
247   - rFm = float32_to_floatx80(fpa11->fpreg[Fm].fSingle);
  247 + rFm = float32_to_floatx80(fpa11->fpreg[Fm].fSingle, &fpa11->fp_status);
248 248 break;
249 249  
250 250 case typeDouble:
251 251 //printk("double.\n");
252 252 if (float64_is_nan(fpa11->fpreg[Fm].fDouble))
253 253 goto unordered;
254   - rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble);
  254 + rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble, &fpa11->fp_status);
255 255 break;
256 256  
257 257 case typeExtended:
... ... @@ -283,7 +283,7 @@ static unsigned int PerformComparison(const unsigned int opcode)
283 283  
284 284 if (BIT_AC & readFPSR()) flags |= CC_CARRY;
285 285  
286   - if (e_flag) float_raise(float_flag_invalid);
  286 + if (e_flag) float_raise(float_flag_invalid, &fpa11->fp_status);
287 287  
288 288 writeConditionCodes(flags);
289 289 return 1;
... ...
target-arm/nwfpe/fpopcode.c
  View file @2049521
... ... @@ -27,14 +27,14 @@
27 27 //#include "fpmodule.inl"
28 28  
29 29 const floatx80 floatx80Constant[] = {
30   - { 0x0000, 0x0000000000000000ULL}, /* extended 0.0 */
31   - { 0x3fff, 0x8000000000000000ULL}, /* extended 1.0 */
32   - { 0x4000, 0x8000000000000000ULL}, /* extended 2.0 */
33   - { 0x4000, 0xc000000000000000ULL}, /* extended 3.0 */
34   - { 0x4001, 0x8000000000000000ULL}, /* extended 4.0 */
35   - { 0x4001, 0xa000000000000000ULL}, /* extended 5.0 */
36   - { 0x3ffe, 0x8000000000000000ULL}, /* extended 0.5 */
37   - { 0x4002, 0xa000000000000000ULL} /* extended 10.0 */
  30 + { 0x0000000000000000ULL, 0x0000}, /* extended 0.0 */
  31 + { 0x8000000000000000ULL, 0x3fff}, /* extended 1.0 */
  32 + { 0x8000000000000000ULL, 0x4000}, /* extended 2.0 */
  33 + { 0xc000000000000000ULL, 0x4000}, /* extended 3.0 */
  34 + { 0x8000000000000000ULL, 0x4001}, /* extended 4.0 */
  35 + { 0xa000000000000000ULL, 0x4001}, /* extended 5.0 */
  36 + { 0x8000000000000000ULL, 0x3ffe}, /* extended 0.5 */
  37 + { 0xa000000000000000ULL, 0x4002} /* extended 10.0 */
38 38 };
39 39  
40 40 const float64 float64Constant[] = {
... ...
target-arm/nwfpe/milieu.h deleted 100644 → 0
  View file @158142c
1   -
2   -/*
3   -===============================================================================
4   -
5   -This C header file is part of the SoftFloat IEC/IEEE Floating-point
6   -Arithmetic Package, Release 2.
7   -
8   -Written by John R. Hauser. This work was made possible in part by the
9   -International Computer Science Institute, located at Suite 600, 1947 Center
10   -Street, Berkeley, California 94704. Funding was partially provided by the
11   -National Science Foundation under grant MIP-9311980. The original version
12   -of this code was written as part of a project to build a fixed-point vector
13   -processor in collaboration with the University of California at Berkeley,
14   -overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15   -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16   -arithmetic/softfloat.html'.
17   -
18   -THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19   -has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20   -TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21   -PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22   -AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23   -
24   -Derivative works are acceptable, even for commercial purposes, so long as
25   -(1) they include prominent notice that the work is derivative, and (2) they
26   -include prominent notice akin to these three paragraphs for those parts of
27   -this code that are retained.
28   -
29   -===============================================================================
30   -*/
31   -
32   -/*
33   --------------------------------------------------------------------------------
34   -Include common integer types and flags.
35   --------------------------------------------------------------------------------
36   -*/
37   -#include "ARM-gcc.h"
38   -
39   -/*
40   --------------------------------------------------------------------------------
41   -Symbolic Boolean literals.
42   --------------------------------------------------------------------------------
43   -*/
44   -enum {
45   - FALSE = 0,
46   - TRUE = 1
47   -};
48   -
target-arm/nwfpe/single_cpdo.c
  View file @2049521
... ... @@ -76,30 +76,30 @@ unsigned int SingleCPDO(const unsigned int opcode)
76 76 {
77 77 /* dyadic opcodes */
78 78 case ADF_CODE:
79   - fpa11->fpreg[Fd].fSingle = float32_add(rFn,rFm);
  79 + fpa11->fpreg[Fd].fSingle = float32_add(rFn,rFm, &fpa11->fp_status);
80 80 break;
81 81  
82 82 case MUF_CODE:
83 83 case FML_CODE:
84   - fpa11->fpreg[Fd].fSingle = float32_mul(rFn,rFm);
  84 + fpa11->fpreg[Fd].fSingle = float32_mul(rFn,rFm, &fpa11->fp_status);
85 85 break;
86 86  
87 87 case SUF_CODE:
88   - fpa11->fpreg[Fd].fSingle = float32_sub(rFn,rFm);
  88 + fpa11->fpreg[Fd].fSingle = float32_sub(rFn,rFm, &fpa11->fp_status);
89 89 break;
90 90  
91 91 case RSF_CODE:
92   - fpa11->fpreg[Fd].fSingle = float32_sub(rFm,rFn);
  92 + fpa11->fpreg[Fd].fSingle = float32_sub(rFm,rFn, &fpa11->fp_status);
93 93 break;
94 94  
95 95 case DVF_CODE:
96 96 case FDV_CODE:
97   - fpa11->fpreg[Fd].fSingle = float32_div(rFn,rFm);
  97 + fpa11->fpreg[Fd].fSingle = float32_div(rFn,rFm, &fpa11->fp_status);
98 98 break;
99 99  
100 100 case RDF_CODE:
101 101 case FRD_CODE:
102   - fpa11->fpreg[Fd].fSingle = float32_div(rFm,rFn);
  102 + fpa11->fpreg[Fd].fSingle = float32_div(rFm,rFn, &fpa11->fp_status);
103 103 break;
104 104  
105 105 #if 0
... ... @@ -113,7 +113,7 @@ unsigned int SingleCPDO(const unsigned int opcode)
113 113 #endif
114 114  
115 115 case RMF_CODE:
116   - fpa11->fpreg[Fd].fSingle = float32_rem(rFn,rFm);
  116 + fpa11->fpreg[Fd].fSingle = float32_rem(rFn,rFm, &fpa11->fp_status);
117 117 break;
118 118  
119 119 #if 0
... ... @@ -139,11 +139,11 @@ unsigned int SingleCPDO(const unsigned int opcode)
139 139  
140 140 case RND_CODE:
141 141 case URD_CODE:
142   - fpa11->fpreg[Fd].fSingle = float32_round_to_int(rFm);
  142 + fpa11->fpreg[Fd].fSingle = float32_round_to_int(rFm, &fpa11->fp_status);
143 143 break;
144 144  
145 145 case SQT_CODE:
146   - fpa11->fpreg[Fd].fSingle = float32_sqrt(rFm);
  146 + fpa11->fpreg[Fd].fSingle = float32_sqrt(rFm, &fpa11->fp_status);
147 147 break;
148 148  
149 149 #if 0
... ...
target-arm/nwfpe/softfloat-macros deleted 100644 → 0
  View file @158142c
1   -
2   -/*
3   -===============================================================================
4   -
5   -This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
6   -Arithmetic Package, Release 2.
7   -
8   -Written by John R. Hauser. This work was made possible in part by the
9   -International Computer Science Institute, located at Suite 600, 1947 Center
10   -Street, Berkeley, California 94704. Funding was partially provided by the
11   -National Science Foundation under grant MIP-9311980. The original version
12   -of this code was written as part of a project to build a fixed-point vector
13   -processor in collaboration with the University of California at Berkeley,
14   -overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15   -is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16   -arithmetic/softfloat.html'.
17   -
18   -THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19   -has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20   -TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21   -PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22   -AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23   -
24   -Derivative works are acceptable, even for commercial purposes, so long as
25   -(1) they include prominent notice that the work is derivative, and (2) they
26   -include prominent notice akin to these three paragraphs for those parts of
27   -this code that are retained.
28   -
29   -===============================================================================
30   -*/
31   -
32   -/*
33   --------------------------------------------------------------------------------
34   -Shifts `a' right by the number of bits given in `count'. If any nonzero
35   -bits are shifted off, they are ``jammed'' into the least significant bit of
36   -the result by setting the least significant bit to 1. The value of `count'
37   -can be arbitrarily large; in particular, if `count' is greater than 32, the
38   -result will be either 0 or 1, depending on whether `a' is zero or nonzero.
39   -The result is stored in the location pointed to by `zPtr'.
40   --------------------------------------------------------------------------------
41   -*/
42   -INLINE void shift32RightJamming( bits32 a, int16 count, bits32 *zPtr )
43   -{
44   - bits32 z;
45   - if ( count == 0 ) {
46   - z = a;
47   - }
48   - else if ( count < 32 ) {
49   - z = ( a>>count ) | ( ( a<<( ( - count ) & 31 ) ) != 0 );
50   - }
51   - else {
52   - z = ( a != 0 );
53   - }
54   - *zPtr = z;
55   -}
56   -
57   -/*
58   --------------------------------------------------------------------------------
59   -Shifts `a' right by the number of bits given in `count'. If any nonzero
60   -bits are shifted off, they are ``jammed'' into the least significant bit of
61   -the result by setting the least significant bit to 1. The value of `count'
62   -can be arbitrarily large; in particular, if `count' is greater than 64, the
63   -result will be either 0 or 1, depending on whether `a' is zero or nonzero.
64   -The result is stored in the location pointed to by `zPtr'.
65   --------------------------------------------------------------------------------
66   -*/
67   -INLINE void shift64RightJamming( bits64 a, int16 count, bits64 *zPtr )
68   -{
69   - bits64 z;
70   -
71   -// __asm__("@shift64RightJamming -- start");
72   - if ( count == 0 ) {
73   - z = a;
74   - }
75   - else if ( count < 64 ) {
76   - z = ( a>>count ) | ( ( a<<( ( - count ) & 63 ) ) != 0 );
77   - }
78   - else {
79   - z = ( a != 0 );
80   - }
81   -// __asm__("@shift64RightJamming -- end");
82   - *zPtr = z;
83   -}
84   -
85   -/*
86   --------------------------------------------------------------------------------
87   -Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64
88   -_plus_ the number of bits given in `count'. The shifted result is at most
89   -64 nonzero bits; this is stored at the location pointed to by `z0Ptr'. The
90   -bits shifted off form a second 64-bit result as follows: The _last_ bit
91   -shifted off is the most-significant bit of the extra result, and the other
92   -63 bits of the extra result are all zero if and only if _all_but_the_last_
93   -bits shifted off were all zero. This extra result is stored in the location
94   -pointed to by `z1Ptr'. The value of `count' can be arbitrarily large.
95   - (This routine makes more sense if `a0' and `a1' are considered to form a
96   -fixed-point value with binary point between `a0' and `a1'. This fixed-point
97   -value is shifted right by the number of bits given in `count', and the
98   -integer part of the result is returned at the location pointed to by
99   -`z0Ptr'. The fractional part of the result may be slightly corrupted as
100   -described above, and is returned at the location pointed to by `z1Ptr'.)
101   --------------------------------------------------------------------------------
102   -*/
103   -INLINE void
104   - shift64ExtraRightJamming(
105   - bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
106   -{
107   - bits64 z0, z1;
108   - int8 negCount = ( - count ) & 63;
109   -
110   - if ( count == 0 ) {
111   - z1 = a1;
112   - z0 = a0;
113   - }
114   - else if ( count < 64 ) {
115   - z1 = ( a0<<negCount ) | ( a1 != 0 );
116   - z0 = a0>>count;
117   - }
118   - else {
119   - if ( count == 64 ) {
120   - z1 = a0 | ( a1 != 0 );
121   - }
122   - else {
123   - z1 = ( ( a0 | a1 ) != 0 );
124   - }
125   - z0 = 0;
126   - }
127   - *z1Ptr = z1;
128   - *z0Ptr = z0;
129   -
130   -}
131   -
132   -/*
133   --------------------------------------------------------------------------------
134   -Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
135   -number of bits given in `count'. Any bits shifted off are lost. The value
136   -of `count' can be arbitrarily large; in particular, if `count' is greater
137   -than 128, the result will be 0. The result is broken into two 64-bit pieces
138   -which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
139   --------------------------------------------------------------------------------
140   -*/
141   -INLINE void
142   - shift128Right(
143   - bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
144   -{
145   - bits64 z0, z1;
146   - int8 negCount = ( - count ) & 63;
147   -
148   - if ( count == 0 ) {
149   - z1 = a1;
150   - z0 = a0;
151   - }
152   - else if ( count < 64 ) {
153   - z1 = ( a0<<negCount ) | ( a1>>count );
154   - z0 = a0>>count;
155   - }
156   - else {
157   - z1 = ( count < 64 ) ? ( a0>>( count & 63 ) ) : 0;
158   - z0 = 0;
159   - }
160   - *z1Ptr = z1;
161   - *z0Ptr = z0;
162   -
163   -}
164   -
165   -/*
166   --------------------------------------------------------------------------------
167   -Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
168   -number of bits given in `count'. If any nonzero bits are shifted off, they
169   -are ``jammed'' into the least significant bit of the result by setting the
170   -least significant bit to 1. The value of `count' can be arbitrarily large;
171   -in particular, if `count' is greater than 128, the result will be either 0
172   -or 1, depending on whether the concatenation of `a0' and `a1' is zero or
173   -nonzero. The result is broken into two 64-bit pieces which are stored at
174   -the locations pointed to by `z0Ptr' and `z1Ptr'.
175   --------------------------------------------------------------------------------
176   -*/
177   -INLINE void
178   - shift128RightJamming(
179   - bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
180   -{
181   - bits64 z0, z1;
182   - int8 negCount = ( - count ) & 63;
183   -
184   - if ( count == 0 ) {
185   - z1 = a1;
186   - z0 = a0;
187   - }
188   - else if ( count < 64 ) {
189   - z1 = ( a0<<negCount ) | ( a1>>count ) | ( ( a1<<negCount ) != 0 );
190   - z0 = a0>>count;
191   - }
192   - else {
193   - if ( count == 64 ) {
194   - z1 = a0 | ( a1 != 0 );
195   - }
196   - else if ( count < 128 ) {
197   - z1 = ( a0>>( count & 63 ) ) | ( ( ( a0<<negCount ) | a1 ) != 0 );
198   - }
199   - else {
200   - z1 = ( ( a0 | a1 ) != 0 );
201   - }
202   - z0 = 0;
203   - }
204   - *z1Ptr = z1;
205   - *z0Ptr = z0;
206   -
207   -}
208   -
209   -/*
210   --------------------------------------------------------------------------------
211   -Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' right
212   -by 64 _plus_ the number of bits given in `count'. The shifted result is
213   -at most 128 nonzero bits; these are broken into two 64-bit pieces which are
214   -stored at the locations pointed to by `z0Ptr' and `z1Ptr'. The bits shifted
215   -off form a third 64-bit result as follows: The _last_ bit shifted off is
216   -the most-significant bit of the extra result, and the other 63 bits of the
217   -extra result are all zero if and only if _all_but_the_last_ bits shifted off
218   -were all zero. This extra result is stored in the location pointed to by
219   -`z2Ptr'. The value of `count' can be arbitrarily large.
220   - (This routine makes more sense if `a0', `a1', and `a2' are considered
221   -to form a fixed-point value with binary point between `a1' and `a2'. This
222   -fixed-point value is shifted right by the number of bits given in `count',
223   -and the integer part of the result is returned at the locations pointed to
224   -by `z0Ptr' and `z1Ptr'. The fractional part of the result may be slightly
225   -corrupted as described above, and is returned at the location pointed to by
226   -`z2Ptr'.)
227   --------------------------------------------------------------------------------
228   -*/
229   -INLINE void
230   - shift128ExtraRightJamming(
231   - bits64 a0,
232   - bits64 a1,
233   - bits64 a2,
234   - int16 count,
235   - bits64 *z0Ptr,
236   - bits64 *z1Ptr,
237   - bits64 *z2Ptr
238   - )
239   -{
240   - bits64 z0, z1, z2;
241   - int8 negCount = ( - count ) & 63;
242   -
243   - if ( count == 0 ) {
244   - z2 = a2;
245   - z1 = a1;
246   - z0 = a0;
247   - }
248   - else {
249   - if ( count < 64 ) {
250   - z2 = a1<<negCount;
251   - z1 = ( a0<<negCount ) | ( a1>>count );
252   - z0 = a0>>count;
253   - }
254   - else {
255   - if ( count == 64 ) {
256   - z2 = a1;
257   - z1 = a0;
258   - }
259   - else {
260   - a2 |= a1;
261   - if ( count < 128 ) {
262   - z2 = a0<<negCount;
263   - z1 = a0>>( count & 63 );
264   - }
265   - else {
266   - z2 = ( count == 128 ) ? a0 : ( a0 != 0 );
267   - z1 = 0;
268   - }
269   - }
270   - z0 = 0;
271   - }
272   - z2 |= ( a2 != 0 );
273   - }
274   - *z2Ptr = z2;
275   - *z1Ptr = z1;
276   - *z0Ptr = z0;
277   -
278   -}
279   -
280   -/*
281   --------------------------------------------------------------------------------
282   -Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the
283   -number of bits given in `count'. Any bits shifted off are lost. The value
284   -of `count' must be less than 64. The result is broken into two 64-bit
285   -pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
286   --------------------------------------------------------------------------------
287   -*/
288   -INLINE void
289   - shortShift128Left(
290   - bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
291   -{
292   -
293   - *z1Ptr = a1<<count;
294   - *z0Ptr =
295   - ( count == 0 ) ? a0 : ( a0<<count ) | ( a1>>( ( - count ) & 63 ) );
296   -
297   -}
298   -
299   -/*
300   --------------------------------------------------------------------------------
301   -Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' left
302   -by the number of bits given in `count'. Any bits shifted off are lost.
303   -The value of `count' must be less than 64. The result is broken into three
304   -64-bit pieces which are stored at the locations pointed to by `z0Ptr',
305   -`z1Ptr', and `z2Ptr'.
306   --------------------------------------------------------------------------------
307   -*/
308   -INLINE void
309   - shortShift192Left(
310   - bits64 a0,
311   - bits64 a1,
312   - bits64 a2,
313   - int16 count,
314   - bits64 *z0Ptr,
315   - bits64 *z1Ptr,
316   - bits64 *z2Ptr
317   - )
318   -{
319   - bits64 z0, z1, z2;
320   - int8 negCount;
321   -
322   - z2 = a2<<count;
323   - z1 = a1<<count;
324   - z0 = a0<<count;
325   - if ( 0 < count ) {
326   - negCount = ( ( - count ) & 63 );
327   - z1 |= a2>>negCount;
328   - z0 |= a1>>negCount;
329   - }
330   - *z2Ptr = z2;
331   - *z1Ptr = z1;
332   - *z0Ptr = z0;
333   -
334   -}
335   -
336   -/*
337   --------------------------------------------------------------------------------
338   -Adds the 128-bit value formed by concatenating `a0' and `a1' to the 128-bit
339   -value formed by concatenating `b0' and `b1'. Addition is modulo 2^128, so
340   -any carry out is lost. The result is broken into two 64-bit pieces which
341   -are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
342   --------------------------------------------------------------------------------
343   -*/
344   -INLINE void
345   - add128(
346   - bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
347   -{
348   - bits64 z1;
349   -
350   - z1 = a1 + b1;
351   - *z1Ptr = z1;
352   - *z0Ptr = a0 + b0 + ( z1 < a1 );
353   -
354   -}
355   -
356   -/*
357   --------------------------------------------------------------------------------
358   -Adds the 192-bit value formed by concatenating `a0', `a1', and `a2' to the
359   -192-bit value formed by concatenating `b0', `b1', and `b2'. Addition is
360   -modulo 2^192, so any carry out is lost. The result is broken into three
361   -64-bit pieces which are stored at the locations pointed to by `z0Ptr',
362   -`z1Ptr', and `z2Ptr'.
363   --------------------------------------------------------------------------------
364   -*/
365   -INLINE void
366   - add192(
367   - bits64 a0,
368   - bits64 a1,
369   - bits64 a2,
370   - bits64 b0,
371   - bits64 b1,
372   - bits64 b2,
373   - bits64 *z0Ptr,
374   - bits64 *z1Ptr,
375   - bits64 *z2Ptr
376   - )
377   -{
378   - bits64 z0, z1, z2;
379   - int8 carry0, carry1;
380   -
381   - z2 = a2 + b2;
382   - carry1 = ( z2 < a2 );
383   - z1 = a1 + b1;
384   - carry0 = ( z1 < a1 );
385   - z0 = a0 + b0;
386   - z1 += carry1;
387   - z0 += ( z1 < carry1 );
388   - z0 += carry0;
389   - *z2Ptr = z2;
390   - *z1Ptr = z1;
391   - *z0Ptr = z0;
392   -
393   -}
394   -
395   -/*
396   --------------------------------------------------------------------------------
397   -Subtracts the 128-bit value formed by concatenating `b0' and `b1' from the
398   -128-bit value formed by concatenating `a0' and `a1'. Subtraction is modulo
399   -2^128, so any borrow out (carry out) is lost. The result is broken into two
400   -64-bit pieces which are stored at the locations pointed to by `z0Ptr' and
401   -`z1Ptr'.
402   --------------------------------------------------------------------------------
403   -*/
404   -INLINE void
405   - sub128(
406   - bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
407   -{
408   -
409   - *z1Ptr = a1 - b1;
410   - *z0Ptr = a0 - b0 - ( a1 < b1 );
411   -
412   -}
413   -
414   -/*
415   --------------------------------------------------------------------------------
416   -Subtracts the 192-bit value formed by concatenating `b0', `b1', and `b2'
417   -from the 192-bit value formed by concatenating `a0', `a1', and `a2'.
418   -Subtraction is modulo 2^192, so any borrow out (carry out) is lost. The
419   -result is broken into three 64-bit pieces which are stored at the locations
420   -pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'.
421   --------------------------------------------------------------------------------
422   -*/
423   -INLINE void
424   - sub192(
425   - bits64 a0,
426   - bits64 a1,
427   - bits64 a2,
428   - bits64 b0,
429   - bits64 b1,
430   - bits64 b2,
431   - bits64 *z0Ptr,
432   - bits64 *z1Ptr,
433   - bits64 *z2Ptr
434   - )
435   -{
436   - bits64 z0, z1, z2;
437   - int8 borrow0, borrow1;
438   -
439   - z2 = a2 - b2;
440   - borrow1 = ( a2 < b2 );
441   - z1 = a1 - b1;
442   - borrow0 = ( a1 < b1 );
443   - z0 = a0 - b0;
444   - z0 -= ( z1 < borrow1 );
445   - z1 -= borrow1;
446   - z0 -= borrow0;
447   - *z2Ptr = z2;
448   - *z1Ptr = z1;
449   - *z0Ptr = z0;
450   -
451   -}
452   -
453   -/*
454   --------------------------------------------------------------------------------
455   -Multiplies `a' by `b' to obtain a 128-bit product. The product is broken
456   -into two 64-bit pieces which are stored at the locations pointed to by
457   -`z0Ptr' and `z1Ptr'.
458   --------------------------------------------------------------------------------
459   -*/
460   -INLINE void mul64To128( bits64 a, bits64 b, bits64 *z0Ptr, bits64 *z1Ptr )
461   -{
462   - bits32 aHigh, aLow, bHigh, bLow;
463   - bits64 z0, zMiddleA, zMiddleB, z1;
464   -
465   - aLow = a;
466   - aHigh = a>>32;
467   - bLow = b;
468   - bHigh = b>>32;
469   - z1 = ( (bits64) aLow ) * bLow;
470   - zMiddleA = ( (bits64) aLow ) * bHigh;
471   - zMiddleB = ( (bits64) aHigh ) * bLow;
472   - z0 = ( (bits64) aHigh ) * bHigh;
473   - zMiddleA += zMiddleB;
474   - z0 += ( ( (bits64) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 );
475   - zMiddleA <<= 32;
476   - z1 += zMiddleA;
477   - z0 += ( z1 < zMiddleA );
478   - *z1Ptr = z1;
479   - *z0Ptr = z0;
480   -
481   -}
482   -
483   -/*
484   --------------------------------------------------------------------------------
485   -Multiplies the 128-bit value formed by concatenating `a0' and `a1' by `b' to
486   -obtain a 192-bit product. The product is broken into three 64-bit pieces
487   -which are stored at the locations pointed to by `z0Ptr', `z1Ptr', and
488   -`z2Ptr'.
489   --------------------------------------------------------------------------------
490   -*/
491   -INLINE void
492   - mul128By64To192(
493   - bits64 a0,
494   - bits64 a1,
495   - bits64 b,
496   - bits64 *z0Ptr,
497   - bits64 *z1Ptr,
498   - bits64 *z2Ptr
499   - )
500   -{
501   - bits64 z0, z1, z2, more1;
502   -
503   - mul64To128( a1, b, &z1, &z2 );
504   - mul64To128( a0, b, &z0, &more1 );
505   - add128( z0, more1, 0, z1, &z0, &z1 );
506   - *z2Ptr = z2;
507   - *z1Ptr = z1;
508   - *z0Ptr = z0;
509   -
510   -}
511   -
512   -/*
513   --------------------------------------------------------------------------------
514   -Multiplies the 128-bit value formed by concatenating `a0' and `a1' to the
515   -128-bit value formed by concatenating `b0' and `b1' to obtain a 256-bit
516   -product. The product is broken into four 64-bit pieces which are stored at
517   -the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.
518   --------------------------------------------------------------------------------
519   -*/
520   -INLINE void
521   - mul128To256(
522   - bits64 a0,
523   - bits64 a1,
524   - bits64 b0,
525   - bits64 b1,
526   - bits64 *z0Ptr,
527   - bits64 *z1Ptr,
528   - bits64 *z2Ptr,
529   - bits64 *z3Ptr
530   - )
531   -{
532   - bits64 z0, z1, z2, z3;
533   - bits64 more1, more2;
534   -
535   - mul64To128( a1, b1, &z2, &z3 );
536   - mul64To128( a1, b0, &z1, &more2 );
537   - add128( z1, more2, 0, z2, &z1, &z2 );
538   - mul64To128( a0, b0, &z0, &more1 );
539   - add128( z0, more1, 0, z1, &z0, &z1 );
540   - mul64To128( a0, b1, &more1, &more2 );
541   - add128( more1, more2, 0, z2, &more1, &z2 );
542   - add128( z0, z1, 0, more1, &z0, &z1 );
543   - *z3Ptr = z3;
544   - *z2Ptr = z2;
545   - *z1Ptr = z1;
546   - *z0Ptr = z0;
547   -
548   -}
549   -
550   -/*
551   --------------------------------------------------------------------------------
552   -Returns an approximation to the 64-bit integer quotient obtained by dividing
553   -`b' into the 128-bit value formed by concatenating `a0' and `a1'. The
554   -divisor `b' must be at least 2^63. If q is the exact quotient truncated
555   -toward zero, the approximation returned lies between q and q + 2 inclusive.
556   -If the exact quotient q is larger than 64 bits, the maximum positive 64-bit
557   -unsigned integer is returned.
558   --------------------------------------------------------------------------------
559   -*/
560   -static bits64 estimateDiv128To64( bits64 a0, bits64 a1, bits64 b )
561   -{
562   - bits64 b0, b1;
563   - bits64 rem0, rem1, term0, term1;
564   - bits64 z;
565   - if ( b <= a0 ) return LIT64( 0xFFFFFFFFFFFFFFFF );
566   - b0 = b>>32;
567   - z = ( b0<<32 <= a0 ) ? LIT64( 0xFFFFFFFF00000000 ) : ( a0 / b0 )<<32;
568   - mul64To128( b, z, &term0, &term1 );
569   - sub128( a0, a1, term0, term1, &rem0, &rem1 );
570   - while ( ( (sbits64) rem0 ) < 0 ) {
571   - z -= LIT64( 0x100000000 );
572   - b1 = b<<32;
573   - add128( rem0, rem1, b0, b1, &rem0, &rem1 );
574   - }
575   - rem0 = ( rem0<<32 ) | ( rem1>>32 );
576   - z |= ( b0<<32 <= rem0 ) ? 0xFFFFFFFF : rem0 / b0;
577   - return z;
578   -
579   -}
580   -
581   -/*
582   --------------------------------------------------------------------------------
583   -Returns an approximation to the square root of the 32-bit significand given
584   -by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of
585   -`aExp' (the least significant bit) is 1, the integer returned approximates
586   -2^31*sqrt(`a'/2^31), where `a' is considered an integer. If bit 0 of `aExp'
587   -is 0, the integer returned approximates 2^31*sqrt(`a'/2^30). In either
588   -case, the approximation returned lies strictly within +/-2 of the exact
589   -value.
590   --------------------------------------------------------------------------------
591   -*/
592   -static bits32 estimateSqrt32( int16 aExp, bits32 a )
593   -{
594   - static const bits16 sqrtOddAdjustments[] = {
595   - 0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0,
596   - 0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67
597   - };
598   - static const bits16 sqrtEvenAdjustments[] = {
599   - 0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E,
600   - 0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002
601   - };
602   - int8 index;
603   - bits32 z;
604   -
605   - index = ( a>>27 ) & 15;
606   - if ( aExp & 1 ) {
607   - z = 0x4000 + ( a>>17 ) - sqrtOddAdjustments[ index ];
608   - z = ( ( a / z )<<14 ) + ( z<<15 );
609   - a >>= 1;
610   - }
611   - else {
612   - z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ index ];
613   - z = a / z + z;
614   - z = ( 0x20000 <= z ) ? 0xFFFF8000 : ( z<<15 );
615   - if ( z <= a ) return (bits32) ( ( (sbits32) a )>>1 );
616   - }
617   - return ( (bits32) ( ( ( (bits64) a )<<31 ) / z ) ) + ( z>>1 );
618   -
619   -}
620   -
621   -/*
622   --------------------------------------------------------------------------------
623   -Returns the number of leading 0 bits before the most-significant 1 bit
624   -of `a'. If `a' is zero, 32 is returned.
625   --------------------------------------------------------------------------------
626   -*/
627   -static int8 countLeadingZeros32( bits32 a )
628   -{
629   - static const int8 countLeadingZerosHigh[] = {
630   - 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
631   - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
632   - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
633   - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
634   - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
635   - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
636   - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
637   - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
638   - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
639   - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
640   - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
641   - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
642   - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
643   - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
644   - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
645   - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
646   - };
647   - int8 shiftCount;
648   -
649   - shiftCount = 0;
650   - if ( a < 0x10000 ) {
651   - shiftCount += 16;
652   - a <<= 16;
653   - }
654   - if ( a < 0x1000000 ) {
655   - shiftCount += 8;
656   - a <<= 8;
657   - }
658   - shiftCount += countLeadingZerosHigh[ a>>24 ];
659   - return shiftCount;
660   -
661   -}
662   -
663   -/*
664   --------------------------------------------------------------------------------
665   -Returns the number of leading 0 bits before the most-significant 1 bit
666   -of `a'. If `a' is zero, 64 is returned.
667   --------------------------------------------------------------------------------
668   -*/
669   -static int8 countLeadingZeros64( bits64 a )
670   -{
671   - int8 shiftCount;
672   -
673   - shiftCount = 0;
674   - if ( a < ( (bits64) 1 )<<32 ) {
675   - shiftCount += 32;
676   - }
677   - else {
678   - a >>= 32;
679   - }
680   - shiftCount += countLeadingZeros32( a );
681   - return shiftCount;
682   -
683   -}
684   -
685   -/*
686   --------------------------------------------------------------------------------
687   -Returns 1 if the 128-bit value formed by concatenating `a0' and `a1'
688   -is equal to the 128-bit value formed by concatenating `b0' and `b1'.
689   -Otherwise, returns 0.
690   --------------------------------------------------------------------------------
691   -*/
692   -INLINE flag eq128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
693   -{
694   -
695   - return ( a0 == b0 ) && ( a1 == b1 );
696   -
697   -}
698   -
699   -/*
700   --------------------------------------------------------------------------------
701   -Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
702   -than or equal to the 128-bit value formed by concatenating `b0' and `b1'.
703   -Otherwise, returns 0.
704   --------------------------------------------------------------------------------
705   -*/
706   -INLINE flag le128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
707   -{
708   -
709   - return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 <= b1 ) );
710   -
711   -}
712   -
713   -/*
714   --------------------------------------------------------------------------------
715   -Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
716   -than the 128-bit value formed by concatenating `b0' and `b1'. Otherwise,
717   -returns 0.
718   --------------------------------------------------------------------------------
719   -*/
720   -INLINE flag lt128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
721   -{
722   -
723   - return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 < b1 ) );
724   -
725   -}
726   -
727   -/*
728   --------------------------------------------------------------------------------
729   -Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is
730   -not equal to the 128-bit value formed by concatenating `b0' and `b1'.
731   -Otherwise, returns 0.
732   --------------------------------------------------------------------------------
733   -*/
734   -INLINE flag ne128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
735   -{
736   -
737   - return ( a0 != b0 ) || ( a1 != b1 );
738   -
739   -}
740   -
target-arm/nwfpe/softfloat-specialize deleted 100644 → 0
  View file @158142c
1   -
2   -/*
3   -===============================================================================
4   -
5   -This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
6   -Arithmetic Package, Release 2.
7   -
8   -Written by John R. Hauser. This work was made possible in part by the
9   -International Computer Science Institute, located at Suite 600, 1947 Center
10   -Street, Berkeley, California 94704. Funding was partially provided by the
11   -National Science Foundation under grant MIP-9311980. The original version
12   -of this code was written as part of a project to build a fixed-point vector
13   -processor in collaboration with the University of California at Berkeley,
14   -overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15   -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16   -arithmetic/softfloat.html'.
17   -
18   -THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19   -has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20   -TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21   -PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22   -AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23   -
24   -Derivative works are acceptable, even for commercial purposes, so long as
25   -(1) they include prominent notice that the work is derivative, and (2) they
26   -include prominent notice akin to these three paragraphs for those parts of
27   -this code that are retained.
28   -
29   -===============================================================================
30   -*/
31   -
32   -/*
33   --------------------------------------------------------------------------------
34   -Underflow tininess-detection mode, statically initialized to default value.
35   -(The declaration in `softfloat.h' must match the `int8' type here.)
36   --------------------------------------------------------------------------------
37   -*/
38   -int8 float_detect_tininess = float_tininess_after_rounding;
39   -
40   -/*
41   --------------------------------------------------------------------------------
42   -Raises the exceptions specified by `flags'. Floating-point traps can be
43   -defined here if desired. It is currently not possible for such a trap to
44   -substitute a result value. If traps are not implemented, this routine
45   -should be simply `float_exception_flags |= flags;'.
46   -
47   -ScottB: November 4, 1998
48   -Moved this function out of softfloat-specialize into fpmodule.c.
49   -This effectively isolates all the changes required for integrating with the
50   -Linux kernel into fpmodule.c. Porting to NetBSD should only require modifying
51   -fpmodule.c to integrate with the NetBSD kernel (I hope!).
52   --------------------------------------------------------------------------------
53   -*/
54   -void float_raise( int8 flags )
55   -{
56   - float_exception_flags |= flags;
57   -}
58   -
59   -/*
60   --------------------------------------------------------------------------------
61   -Internal canonical NaN format.
62   --------------------------------------------------------------------------------
63   -*/
64   -typedef struct {
65   - flag sign;
66   - bits64 high, low;
67   -} commonNaNT;
68   -
69   -/*
70   --------------------------------------------------------------------------------
71   -The pattern for a default generated single-precision NaN.
72   --------------------------------------------------------------------------------
73   -*/
74   -#define float32_default_nan 0xFFFFFFFF
75   -
76   -/*
77   --------------------------------------------------------------------------------
78   -Returns 1 if the single-precision floating-point value `a' is a NaN;
79   -otherwise returns 0.
80   --------------------------------------------------------------------------------
81   -*/
82   -flag float32_is_nan( float32 a )
83   -{
84   -
85   - return ( 0xFF000000 < (bits32) ( a<<1 ) );
86   -
87   -}
88   -
89   -/*
90   --------------------------------------------------------------------------------
91   -Returns 1 if the single-precision floating-point value `a' is a signaling
92   -NaN; otherwise returns 0.
93   --------------------------------------------------------------------------------
94   -*/
95   -flag float32_is_signaling_nan( float32 a )
96   -{
97   -
98   - return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
99   -
100   -}
101   -
102   -/*
103   --------------------------------------------------------------------------------
104   -Returns the result of converting the single-precision floating-point NaN
105   -`a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
106   -exception is raised.
107   --------------------------------------------------------------------------------
108   -*/
109   -static commonNaNT float32ToCommonNaN( float32 a )
110   -{
111   - commonNaNT z;
112   -
113   - if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
114   - z.sign = a>>31;
115   - z.low = 0;
116   - z.high = ( (bits64) a )<<41;
117   - return z;
118   -
119   -}
120   -
121   -/*
122   --------------------------------------------------------------------------------
123   -Returns the result of converting the canonical NaN `a' to the single-
124   -precision floating-point format.
125   --------------------------------------------------------------------------------
126   -*/
127   -static float32 commonNaNToFloat32( commonNaNT a )
128   -{
129   -
130   - return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 );
131   -
132   -}
133   -
134   -/*
135   --------------------------------------------------------------------------------
136   -Takes two single-precision floating-point values `a' and `b', one of which
137   -is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
138   -signaling NaN, the invalid exception is raised.
139   --------------------------------------------------------------------------------
140   -*/
141   -static float32 propagateFloat32NaN( float32 a, float32 b )
142   -{
143   - flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
144   -
145   - aIsNaN = float32_is_nan( a );
146   - aIsSignalingNaN = float32_is_signaling_nan( a );
147   - bIsNaN = float32_is_nan( b );
148   - bIsSignalingNaN = float32_is_signaling_nan( b );
149   - a |= 0x00400000;
150   - b |= 0x00400000;
151   - if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
152   - if ( aIsNaN ) {
153   - return ( aIsSignalingNaN & bIsNaN ) ? b : a;
154   - }
155   - else {
156   - return b;
157   - }
158   -
159   -}
160   -
161   -/*
162   --------------------------------------------------------------------------------
163   -The pattern for a default generated double-precision NaN.
164   --------------------------------------------------------------------------------
165   -*/
166   -#define float64_default_nan LIT64( 0xFFFFFFFFFFFFFFFF )
167   -
168   -/*
169   --------------------------------------------------------------------------------
170   -Returns 1 if the double-precision floating-point value `a' is a NaN;
171   -otherwise returns 0.
172   --------------------------------------------------------------------------------
173   -*/
174   -flag float64_is_nan( float64 a )
175   -{
176   -
177   - return ( LIT64( 0xFFE0000000000000 ) < (bits64) ( a<<1 ) );
178   -
179   -}
180   -
181   -/*
182   --------------------------------------------------------------------------------
183   -Returns 1 if the double-precision floating-point value `a' is a signaling
184   -NaN; otherwise returns 0.
185   --------------------------------------------------------------------------------
186   -*/
187   -flag float64_is_signaling_nan( float64 a )
188   -{
189   -
190   - return
191   - ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
192   - && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
193   -
194   -}
195   -
196   -/*
197   --------------------------------------------------------------------------------
198   -Returns the result of converting the double-precision floating-point NaN
199   -`a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
200   -exception is raised.
201   --------------------------------------------------------------------------------
202   -*/
203   -static commonNaNT float64ToCommonNaN( float64 a )
204   -{
205   - commonNaNT z;
206   -
207   - if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
208   - z.sign = a>>63;
209   - z.low = 0;
210   - z.high = a<<12;
211   - return z;
212   -
213   -}
214   -
215   -/*
216   --------------------------------------------------------------------------------
217   -Returns the result of converting the canonical NaN `a' to the double-
218   -precision floating-point format.
219   --------------------------------------------------------------------------------
220   -*/
221   -static float64 commonNaNToFloat64( commonNaNT a )
222   -{
223   -
224   - return
225   - ( ( (bits64) a.sign )<<63 )
226   - | LIT64( 0x7FF8000000000000 )
227   - | ( a.high>>12 );
228   -
229   -}
230   -
231   -/*
232   --------------------------------------------------------------------------------
233   -Takes two double-precision floating-point values `a' and `b', one of which
234   -is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
235   -signaling NaN, the invalid exception is raised.
236   --------------------------------------------------------------------------------
237   -*/
238   -static float64 propagateFloat64NaN( float64 a, float64 b )
239   -{
240   - flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
241   -
242   - aIsNaN = float64_is_nan( a );
243   - aIsSignalingNaN = float64_is_signaling_nan( a );
244   - bIsNaN = float64_is_nan( b );
245   - bIsSignalingNaN = float64_is_signaling_nan( b );
246   - a |= LIT64( 0x0008000000000000 );
247   - b |= LIT64( 0x0008000000000000 );
248   - if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
249   - if ( aIsNaN ) {
250   - return ( aIsSignalingNaN & bIsNaN ) ? b : a;
251   - }
252   - else {
253   - return b;
254   - }
255   -
256   -}
257   -
258   -#ifdef FLOATX80
259   -
260   -/*
261   --------------------------------------------------------------------------------
262   -The pattern for a default generated extended double-precision NaN. The
263   -`high' and `low' values hold the most- and least-significant bits,
264   -respectively.
265   --------------------------------------------------------------------------------
266   -*/
267   -#define floatx80_default_nan_high 0xFFFF
268   -#define floatx80_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF )
269   -
270   -/*
271   --------------------------------------------------------------------------------
272   -Returns 1 if the extended double-precision floating-point value `a' is a
273   -NaN; otherwise returns 0.
274   --------------------------------------------------------------------------------
275   -*/
276   -flag floatx80_is_nan( floatx80 a )
277   -{
278   -
279   - return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );
280   -
281   -}
282   -
283   -/*
284   --------------------------------------------------------------------------------
285   -Returns 1 if the extended double-precision floating-point value `a' is a
286   -signaling NaN; otherwise returns 0.
287   --------------------------------------------------------------------------------
288   -*/
289   -flag floatx80_is_signaling_nan( floatx80 a )
290   -{
291   - //register int lr;
292   - bits64 aLow;
293   -
294   - //__asm__("mov %0, lr" : : "g" (lr));
295   - //fp_printk("floatx80_is_signalling_nan() called from 0x%08x\n",lr);
296   - aLow = a.low & ~ LIT64( 0x4000000000000000 );
297   - return
298   - ( ( a.high & 0x7FFF ) == 0x7FFF )
299   - && (bits64) ( aLow<<1 )
300   - && ( a.low == aLow );
301   -
302   -}
303   -
304   -/*
305   --------------------------------------------------------------------------------
306   -Returns the result of converting the extended double-precision floating-
307   -point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the
308   -invalid exception is raised.
309   --------------------------------------------------------------------------------
310   -*/
311   -static commonNaNT floatx80ToCommonNaN( floatx80 a )
312   -{
313   - commonNaNT z;
314   -
315   - if ( floatx80_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
316   - z.sign = a.high>>15;
317   - z.low = 0;
318   - z.high = a.low<<1;
319   - return z;
320   -
321   -}
322   -
323   -/*
324   --------------------------------------------------------------------------------
325   -Returns the result of converting the canonical NaN `a' to the extended
326   -double-precision floating-point format.
327   --------------------------------------------------------------------------------
328   -*/
329   -static floatx80 commonNaNToFloatx80( commonNaNT a )
330   -{
331   - floatx80 z;
332   -
333   - z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );
334   - z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;
335   - return z;
336   -
337   -}
338   -
339   -/*
340   --------------------------------------------------------------------------------
341   -Takes two extended double-precision floating-point values `a' and `b', one
342   -of which is a NaN, and returns the appropriate NaN result. If either `a' or
343   -`b' is a signaling NaN, the invalid exception is raised.
344   --------------------------------------------------------------------------------
345   -*/
346   -static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b )
347   -{
348   - flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
349   -
350   - aIsNaN = floatx80_is_nan( a );
351   - aIsSignalingNaN = floatx80_is_signaling_nan( a );
352   - bIsNaN = floatx80_is_nan( b );
353   - bIsSignalingNaN = floatx80_is_signaling_nan( b );
354   - a.low |= LIT64( 0xC000000000000000 );
355   - b.low |= LIT64( 0xC000000000000000 );
356   - if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
357   - if ( aIsNaN ) {
358   - return ( aIsSignalingNaN & bIsNaN ) ? b : a;
359   - }
360   - else {
361   - return b;
362   - }
363   -
364   -}
365   -
366   -#endif