gwj / at91sam9263 · Commits

Commit 1e8864f75dc6af4e59a24832ea5c128ef1dbb782

Authored by aurel32
1 parent 3bf73a49

SH4: use TCG variables for gregs 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5102 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 202 additions and 200 deletions
target-sh4/translate.c
  View file @1e8864f
... ... @@ -57,18 +57,38 @@ enum {
57 57 BS_EXCP = 3, /* We reached an exception condition */
58 58 };
59 59  
60   -static TCGv cpu_env, cpu_T[2];
  60 +/* global register indexes */
  61 +static TCGv cpu_env;
  62 +static TCGv cpu_gregs[24];
  63 +
  64 +/* dyngen register indexes */
  65 +static TCGv cpu_T[2];
61 66  
62 67 #include "gen-icount.h"
63 68  
64 69 static void sh4_translate_init(void)
65 70 {
  71 + int i;
66 72 static int done_init = 0;
  73 + static const char * const gregnames[24] = {
  74 + "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
  75 + "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
  76 + "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
  77 + "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
  78 + "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
  79 + };
  80 +
67 81 if (done_init)
68 82 return;
  83 +
69 84 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
70   - cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
71   - cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
  85 + cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG1, "T0");
  86 + cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG2, "T1");
  87 +
  88 + for (i = 0; i < 24; i++)
  89 + cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  90 + offsetof(CPUState, gregs[i]),
  91 + gregnames[i]);
72 92  
73 93 /* register helpers */
74 94 #undef DEF_HELPER
... ... @@ -78,24 +98,6 @@ static void sh4_translate_init(void)
78 98 done_init = 1;
79 99 }
80 100  
81   -/* General purpose registers moves. */
82   -static inline void gen_movl_imm_rN(uint32_t arg, int reg)
83   -{
84   - TCGv tmp = tcg_const_i32(arg);
85   - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, gregs[reg]));
86   - tcg_temp_free(tmp);
87   -}
88   -
89   -static always_inline void gen_movl_T_rN (TCGv t, int reg)
90   -{
91   - tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
92   -}
93   -
94   -static always_inline void gen_movl_rN_T (TCGv t, int reg)
95   -{
96   - tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
97   -}
98   -
99 101 #ifdef CONFIG_USER_ONLY
100 102  
101 103 #define GEN_OP_LD(width, reg) \
... ... @@ -340,29 +342,29 @@ void _decode_opc(DisasContext * ctx)
340 342  
341 343 switch (ctx->opcode & 0xf000) {
342 344 case 0x1000: /* mov.l Rm,@(disp,Rn) */
343   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
344   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  345 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  346 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
345 347 gen_op_addl_imm_T1(B3_0 * 4);
346 348 gen_op_stl_T0_T1(ctx);
347 349 return;
348 350 case 0x5000: /* mov.l @(disp,Rm),Rn */
349   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  351 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
350 352 gen_op_addl_imm_T0(B3_0 * 4);
351 353 gen_op_ldl_T0_T0(ctx);
352   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  354 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
353 355 return;
354 356 case 0xe000: /* mov #imm,Rn */
355   - gen_movl_imm_rN(B7_0s, REG(B11_8));
  357 + tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], B7_0s);
356 358 return;
357 359 case 0x9000: /* mov.w @(disp,PC),Rn */
358 360 tcg_gen_movi_i32(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
359 361 gen_op_ldw_T0_T0(ctx);
360   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  362 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
361 363 return;
362 364 case 0xd000: /* mov.l @(disp,PC),Rn */
363 365 tcg_gen_movi_i32(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
364 366 gen_op_ldl_T0_T0(ctx);
365   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  367 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
366 368 return;
367 369 case 0x7000: /* add #imm,Rn */
368 370 gen_op_add_imm_rN(B7_0s, REG(B11_8));
... ... @@ -382,324 +384,324 @@ void _decode_opc(DisasContext * ctx)
382 384  
383 385 switch (ctx->opcode & 0xf00f) {
384 386 case 0x6003: /* mov Rm,Rn */
385   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
386   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  387 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  388 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
387 389 return;
388 390 case 0x2000: /* mov.b Rm,@Rn */
389   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
390   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  391 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  392 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
391 393 gen_op_stb_T0_T1(ctx);
392 394 return;
393 395 case 0x2001: /* mov.w Rm,@Rn */
394   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
395   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  396 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  397 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
396 398 gen_op_stw_T0_T1(ctx);
397 399 return;
398 400 case 0x2002: /* mov.l Rm,@Rn */
399   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
400   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  401 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  402 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
401 403 gen_op_stl_T0_T1(ctx);
402 404 return;
403 405 case 0x6000: /* mov.b @Rm,Rn */
404   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  406 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
405 407 gen_op_ldb_T0_T0(ctx);
406   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  408 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
407 409 return;
408 410 case 0x6001: /* mov.w @Rm,Rn */
409   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  411 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
410 412 gen_op_ldw_T0_T0(ctx);
411   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  413 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
412 414 return;
413 415 case 0x6002: /* mov.l @Rm,Rn */
414   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  416 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
415 417 gen_op_ldl_T0_T0(ctx);
416   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  418 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
417 419 return;
418 420 case 0x2004: /* mov.b Rm,@-Rn */
419   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  421 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
420 422 gen_op_dec1_rN(REG(B11_8)); /* modify register status */
421   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  423 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
422 424 gen_op_inc1_rN(REG(B11_8)); /* recover register status */
423 425 gen_op_stb_T0_T1(ctx); /* might cause re-execution */
424 426 gen_op_dec1_rN(REG(B11_8)); /* modify register status */
425 427 return;
426 428 case 0x2005: /* mov.w Rm,@-Rn */
427   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  429 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
428 430 gen_op_dec2_rN(REG(B11_8));
429   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  431 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
430 432 gen_op_inc2_rN(REG(B11_8));
431 433 gen_op_stw_T0_T1(ctx);
432 434 gen_op_dec2_rN(REG(B11_8));
433 435 return;
434 436 case 0x2006: /* mov.l Rm,@-Rn */
435   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  437 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
436 438 gen_op_dec4_rN(REG(B11_8));
437   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  439 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
438 440 gen_op_inc4_rN(REG(B11_8));
439 441 gen_op_stl_T0_T1(ctx);
440 442 gen_op_dec4_rN(REG(B11_8));
441 443 return;
442 444 case 0x6004: /* mov.b @Rm+,Rn */
443   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  445 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
444 446 gen_op_ldb_T0_T0(ctx);
445   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  447 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
446 448 if ( B11_8 != B7_4 )
447 449 gen_op_inc1_rN(REG(B7_4));
448 450 return;
449 451 case 0x6005: /* mov.w @Rm+,Rn */
450   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  452 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
451 453 gen_op_ldw_T0_T0(ctx);
452   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  454 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
453 455 if ( B11_8 != B7_4 )
454 456 gen_op_inc2_rN(REG(B7_4));
455 457 return;
456 458 case 0x6006: /* mov.l @Rm+,Rn */
457   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  459 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
458 460 gen_op_ldl_T0_T0(ctx);
459   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  461 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
460 462 if ( B11_8 != B7_4 )
461 463 gen_op_inc4_rN(REG(B7_4));
462 464 return;
463 465 case 0x0004: /* mov.b Rm,@(R0,Rn) */
464   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
465   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  466 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  467 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
466 468 gen_op_add_rN_T1(REG(0));
467 469 gen_op_stb_T0_T1(ctx);
468 470 return;
469 471 case 0x0005: /* mov.w Rm,@(R0,Rn) */
470   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
471   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  472 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  473 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
472 474 gen_op_add_rN_T1(REG(0));
473 475 gen_op_stw_T0_T1(ctx);
474 476 return;
475 477 case 0x0006: /* mov.l Rm,@(R0,Rn) */
476   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
477   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  478 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  479 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
478 480 gen_op_add_rN_T1(REG(0));
479 481 gen_op_stl_T0_T1(ctx);
480 482 return;
481 483 case 0x000c: /* mov.b @(R0,Rm),Rn */
482   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  484 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
483 485 gen_op_add_rN_T0(REG(0));
484 486 gen_op_ldb_T0_T0(ctx);
485   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  487 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
486 488 return;
487 489 case 0x000d: /* mov.w @(R0,Rm),Rn */
488   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  490 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
489 491 gen_op_add_rN_T0(REG(0));
490 492 gen_op_ldw_T0_T0(ctx);
491   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  493 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
492 494 return;
493 495 case 0x000e: /* mov.l @(R0,Rm),Rn */
494   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  496 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
495 497 gen_op_add_rN_T0(REG(0));
496 498 gen_op_ldl_T0_T0(ctx);
497   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  499 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
498 500 return;
499 501 case 0x6008: /* swap.b Rm,Rn */
500   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  502 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
501 503 gen_op_swapb_T0();
502   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  504 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
503 505 return;
504 506 case 0x6009: /* swap.w Rm,Rn */
505   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  507 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
506 508 gen_op_swapw_T0();
507   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  509 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
508 510 return;
509 511 case 0x200d: /* xtrct Rm,Rn */
510   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
511   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  512 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  513 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
512 514 gen_op_xtrct_T0_T1();
513   - gen_movl_T_rN(cpu_T[1], REG(B11_8));
  515 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
514 516 return;
515 517 case 0x300c: /* add Rm,Rn */
516   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  518 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
517 519 gen_op_add_T0_rN(REG(B11_8));
518 520 return;
519 521 case 0x300e: /* addc Rm,Rn */
520   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
521   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  522 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  523 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
522 524 gen_op_addc_T0_T1();
523   - gen_movl_T_rN(cpu_T[1], REG(B11_8));
  525 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
524 526 return;
525 527 case 0x300f: /* addv Rm,Rn */
526   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
527   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  528 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  529 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
528 530 gen_op_addv_T0_T1();
529   - gen_movl_T_rN(cpu_T[1], REG(B11_8));
  531 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
530 532 return;
531 533 case 0x2009: /* and Rm,Rn */
532   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  534 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
533 535 gen_op_and_T0_rN(REG(B11_8));
534 536 return;
535 537 case 0x3000: /* cmp/eq Rm,Rn */
536   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
537   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  538 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  539 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
538 540 gen_op_cmp_eq_T0_T1();
539 541 return;
540 542 case 0x3003: /* cmp/ge Rm,Rn */
541   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
542   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  543 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  544 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
543 545 gen_op_cmp_ge_T0_T1();
544 546 return;
545 547 case 0x3007: /* cmp/gt Rm,Rn */
546   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
547   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  548 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  549 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
548 550 gen_op_cmp_gt_T0_T1();
549 551 return;
550 552 case 0x3006: /* cmp/hi Rm,Rn */
551   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
552   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  553 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  554 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
553 555 gen_op_cmp_hi_T0_T1();
554 556 return;
555 557 case 0x3002: /* cmp/hs Rm,Rn */
556   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
557   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  558 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  559 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
558 560 gen_op_cmp_hs_T0_T1();
559 561 return;
560 562 case 0x200c: /* cmp/str Rm,Rn */
561   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
562   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  563 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  564 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
563 565 gen_op_cmp_str_T0_T1();
564 566 return;
565 567 case 0x2007: /* div0s Rm,Rn */
566   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
567   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  568 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  569 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
568 570 gen_op_div0s_T0_T1();
569 571 return;
570 572 case 0x3004: /* div1 Rm,Rn */
571   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
572   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  573 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  574 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
573 575 gen_op_div1_T0_T1();
574   - gen_movl_T_rN(cpu_T[1], REG(B11_8));
  576 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
575 577 return;
576 578 case 0x300d: /* dmuls.l Rm,Rn */
577   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
578   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  579 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  580 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
579 581 gen_op_dmulsl_T0_T1();
580 582 return;
581 583 case 0x3005: /* dmulu.l Rm,Rn */
582   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
583   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  584 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  585 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
584 586 gen_op_dmulul_T0_T1();
585 587 return;
586 588 case 0x600e: /* exts.b Rm,Rn */
587   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  589 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
588 590 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
589 591 tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
590   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  592 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
591 593 return;
592 594 case 0x600f: /* exts.w Rm,Rn */
593   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  595 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
594 596 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
595 597 tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
596   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  598 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
597 599 return;
598 600 case 0x600c: /* extu.b Rm,Rn */
599   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  601 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
600 602 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
601   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  603 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
602 604 return;
603 605 case 0x600d: /* extu.w Rm,Rn */
604   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  606 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
605 607 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
606   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  608 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
607 609 return;
608 610 case 0x000f: /* mac.l @Rm+,@Rn+ */
609   - gen_movl_rN_T(cpu_T[0], REG(B11_8));
  611 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
610 612 gen_op_ldl_T0_T0(ctx);
611 613 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
612   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  614 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
613 615 gen_op_ldl_T0_T0(ctx);
614 616 gen_op_macl_T0_T1();
615 617 gen_op_inc4_rN(REG(B11_8));
616 618 gen_op_inc4_rN(REG(B7_4));
617 619 return;
618 620 case 0x400f: /* mac.w @Rm+,@Rn+ */
619   - gen_movl_rN_T(cpu_T[0], REG(B11_8));
  621 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
620 622 gen_op_ldl_T0_T0(ctx);
621 623 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
622   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  624 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
623 625 gen_op_ldl_T0_T0(ctx);
624 626 gen_op_macw_T0_T1();
625 627 gen_op_inc2_rN(REG(B11_8));
626 628 gen_op_inc2_rN(REG(B7_4));
627 629 return;
628 630 case 0x0007: /* mul.l Rm,Rn */
629   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
630   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  631 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  632 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
631 633 gen_op_mull_T0_T1();
632 634 return;
633 635 case 0x200f: /* muls.w Rm,Rn */
634   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  636 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
635 637 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
636 638 tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
637   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  639 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
638 640 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
639 641 tcg_gen_ext16s_i32(cpu_T[1], cpu_T[1]);
640 642 gen_op_mulsw_T0_T1();
641 643 return;
642 644 case 0x200e: /* mulu.w Rm,Rn */
643   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  645 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
644 646 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
645   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  647 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
646 648 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
647 649 gen_op_muluw_T0_T1();
648 650 return;
649 651 case 0x600b: /* neg Rm,Rn */
650   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  652 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
651 653 gen_op_neg_T0();
652   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  654 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
653 655 return;
654 656 case 0x600a: /* negc Rm,Rn */
655   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  657 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
656 658 gen_op_negc_T0();
657   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  659 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
658 660 return;
659 661 case 0x6007: /* not Rm,Rn */
660   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  662 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
661 663 gen_op_not_T0();
662   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  664 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
663 665 return;
664 666 case 0x200b: /* or Rm,Rn */
665   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  667 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
666 668 gen_op_or_T0_rN(REG(B11_8));
667 669 return;
668 670 case 0x400c: /* shad Rm,Rn */
669   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
670   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  671 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  672 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
671 673 gen_op_shad_T0_T1();
672   - gen_movl_T_rN(cpu_T[1], REG(B11_8));
  674 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
673 675 return;
674 676 case 0x400d: /* shld Rm,Rn */
675   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
676   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  677 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  678 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
677 679 gen_op_shld_T0_T1();
678   - gen_movl_T_rN(cpu_T[1], REG(B11_8));
  680 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
679 681 return;
680 682 case 0x3008: /* sub Rm,Rn */
681   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  683 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
682 684 gen_op_sub_T0_rN(REG(B11_8));
683 685 return;
684 686 case 0x300a: /* subc Rm,Rn */
685   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
686   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  687 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  688 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
687 689 gen_op_subc_T0_T1();
688   - gen_movl_T_rN(cpu_T[1], REG(B11_8));
  690 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
689 691 return;
690 692 case 0x300b: /* subv Rm,Rn */
691   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
692   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  693 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  694 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
693 695 gen_op_subv_T0_T1();
694   - gen_movl_T_rN(cpu_T[1], REG(B11_8));
  696 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
695 697 return;
696 698 case 0x2008: /* tst Rm,Rn */
697   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
698   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  699 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
  700 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
699 701 gen_op_tst_T0_T1();
700 702 return;
701 703 case 0x200a: /* xor Rm,Rn */
702   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  704 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
703 705 gen_op_xor_T0_rN(REG(B11_8));
704 706 return;
705 707 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
... ... @@ -714,33 +716,33 @@ void _decode_opc(DisasContext * ctx)
714 716 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
715 717 if (ctx->fpscr & FPSCR_SZ) {
716 718 gen_op_fmov_drN_DT0(XREG(B7_4));
717   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  719 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
718 720 gen_op_stfq_DT0_T1(ctx);
719 721 } else {
720 722 gen_op_fmov_frN_FT0(FREG(B7_4));
721   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  723 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
722 724 gen_op_stfl_FT0_T1(ctx);
723 725 }
724 726 return;
725 727 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
726 728 if (ctx->fpscr & FPSCR_SZ) {
727   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  729 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
728 730 gen_op_ldfq_T0_DT0(ctx);
729 731 gen_op_fmov_DT0_drN(XREG(B11_8));
730 732 } else {
731   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  733 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
732 734 gen_op_ldfl_T0_FT0(ctx);
733 735 gen_op_fmov_FT0_frN(FREG(B11_8));
734 736 }
735 737 return;
736 738 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
737 739 if (ctx->fpscr & FPSCR_SZ) {
738   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  740 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
739 741 gen_op_ldfq_T0_DT0(ctx);
740 742 gen_op_fmov_DT0_drN(XREG(B11_8));
741 743 gen_op_inc8_rN(REG(B7_4));
742 744 } else {
743   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  745 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
744 746 gen_op_ldfl_T0_FT0(ctx);
745 747 gen_op_fmov_FT0_frN(FREG(B11_8));
746 748 gen_op_inc4_rN(REG(B7_4));
... ... @@ -750,14 +752,14 @@ void _decode_opc(DisasContext * ctx)
750 752 if (ctx->fpscr & FPSCR_SZ) {
751 753 gen_op_dec8_rN(REG(B11_8));
752 754 gen_op_fmov_drN_DT0(XREG(B7_4));
753   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  755 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
754 756 gen_op_inc8_rN(REG(B11_8));
755 757 gen_op_stfq_DT0_T1(ctx);
756 758 gen_op_dec8_rN(REG(B11_8));
757 759 } else {
758 760 gen_op_dec4_rN(REG(B11_8));
759 761 gen_op_fmov_frN_FT0(FREG(B7_4));
760   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  762 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
761 763 gen_op_inc4_rN(REG(B11_8));
762 764 gen_op_stfl_FT0_T1(ctx);
763 765 gen_op_dec4_rN(REG(B11_8));
... ... @@ -765,12 +767,12 @@ void _decode_opc(DisasContext * ctx)
765 767 return;
766 768 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
767 769 if (ctx->fpscr & FPSCR_SZ) {
768   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  770 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
769 771 gen_op_add_rN_T0(REG(0));
770 772 gen_op_ldfq_T0_DT0(ctx);
771 773 gen_op_fmov_DT0_drN(XREG(B11_8));
772 774 } else {
773   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  775 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
774 776 gen_op_add_rN_T0(REG(0));
775 777 gen_op_ldfl_T0_FT0(ctx);
776 778 gen_op_fmov_FT0_frN(FREG(B11_8));
... ... @@ -779,12 +781,12 @@ void _decode_opc(DisasContext * ctx)
779 781 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
780 782 if (ctx->fpscr & FPSCR_SZ) {
781 783 gen_op_fmov_drN_DT0(XREG(B7_4));
782   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  784 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
783 785 gen_op_add_rN_T1(REG(0));
784 786 gen_op_stfq_DT0_T1(ctx);
785 787 } else {
786 788 gen_op_fmov_frN_FT0(FREG(B7_4));
787   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  789 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
788 790 gen_op_add_rN_T1(REG(0));
789 791 gen_op_stfl_FT0_T1(ctx);
790 792 }
... ... @@ -841,7 +843,7 @@ void _decode_opc(DisasContext * ctx)
841 843 gen_op_and_imm_rN(B7_0, REG(0));
842 844 return;
843 845 case 0xcd00: /* and.b #imm,@(R0,GBR) */
844   - gen_movl_rN_T(cpu_T[0], REG(0));
  846 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
845 847 gen_op_addl_GBR_T0();
846 848 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
847 849 gen_op_ldub_T0_T0(ctx);
... ... @@ -871,81 +873,81 @@ void _decode_opc(DisasContext * ctx)
871 873 ctx->flags |= DELAY_SLOT_CONDITIONAL;
872 874 return;
873 875 case 0x8800: /* cmp/eq #imm,R0 */
874   - gen_movl_rN_T(cpu_T[0], REG(0));
  876 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
875 877 gen_op_cmp_eq_imm_T0(B7_0s);
876 878 return;
877 879 case 0xc400: /* mov.b @(disp,GBR),R0 */
878 880 gen_op_stc_gbr_T0();
879 881 gen_op_addl_imm_T0(B7_0);
880 882 gen_op_ldb_T0_T0(ctx);
881   - gen_movl_T_rN(cpu_T[0], REG(0));
  883 + tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
882 884 return;
883 885 case 0xc500: /* mov.w @(disp,GBR),R0 */
884 886 gen_op_stc_gbr_T0();
885 887 gen_op_addl_imm_T0(B7_0 * 2);
886 888 gen_op_ldw_T0_T0(ctx);
887   - gen_movl_T_rN(cpu_T[0], REG(0));
  889 + tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
888 890 return;
889 891 case 0xc600: /* mov.l @(disp,GBR),R0 */
890 892 gen_op_stc_gbr_T0();
891 893 gen_op_addl_imm_T0(B7_0 * 4);
892 894 gen_op_ldl_T0_T0(ctx);
893   - gen_movl_T_rN(cpu_T[0], REG(0));
  895 + tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
894 896 return;
895 897 case 0xc000: /* mov.b R0,@(disp,GBR) */
896 898 gen_op_stc_gbr_T0();
897 899 gen_op_addl_imm_T0(B7_0);
898 900 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
899   - gen_movl_rN_T(cpu_T[0], REG(0));
  901 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
900 902 gen_op_stb_T0_T1(ctx);
901 903 return;
902 904 case 0xc100: /* mov.w R0,@(disp,GBR) */
903 905 gen_op_stc_gbr_T0();
904 906 gen_op_addl_imm_T0(B7_0 * 2);
905 907 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
906   - gen_movl_rN_T(cpu_T[0], REG(0));
  908 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
907 909 gen_op_stw_T0_T1(ctx);
908 910 return;
909 911 case 0xc200: /* mov.l R0,@(disp,GBR) */
910 912 gen_op_stc_gbr_T0();
911 913 gen_op_addl_imm_T0(B7_0 * 4);
912 914 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
913   - gen_movl_rN_T(cpu_T[0], REG(0));
  915 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
914 916 gen_op_stl_T0_T1(ctx);
915 917 return;
916 918 case 0x8000: /* mov.b R0,@(disp,Rn) */
917   - gen_movl_rN_T(cpu_T[0], REG(0));
918   - gen_movl_rN_T(cpu_T[1], REG(B7_4));
  919 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
  920 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]);
919 921 gen_op_addl_imm_T1(B3_0);
920 922 gen_op_stb_T0_T1(ctx);
921 923 return;
922 924 case 0x8100: /* mov.w R0,@(disp,Rn) */
923   - gen_movl_rN_T(cpu_T[0], REG(0));
924   - gen_movl_rN_T(cpu_T[1], REG(B7_4));
  925 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
  926 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]);
925 927 gen_op_addl_imm_T1(B3_0 * 2);
926 928 gen_op_stw_T0_T1(ctx);
927 929 return;
928 930 case 0x8400: /* mov.b @(disp,Rn),R0 */
929   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  931 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
930 932 gen_op_addl_imm_T0(B3_0);
931 933 gen_op_ldb_T0_T0(ctx);
932   - gen_movl_T_rN(cpu_T[0], REG(0));
  934 + tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
933 935 return;
934 936 case 0x8500: /* mov.w @(disp,Rn),R0 */
935   - gen_movl_rN_T(cpu_T[0], REG(B7_4));
  937 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
936 938 gen_op_addl_imm_T0(B3_0 * 2);
937 939 gen_op_ldw_T0_T0(ctx);
938   - gen_movl_T_rN(cpu_T[0], REG(0));
  940 + tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
939 941 return;
940 942 case 0xc700: /* mova @(disp,PC),R0 */
941   - gen_movl_imm_rN(((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3,
942   - REG(0));
  943 + tcg_gen_movi_i32(cpu_gregs[REG(0)],
  944 + ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);
943 945 return;
944 946 case 0xcb00: /* or #imm,R0 */
945 947 gen_op_or_imm_rN(B7_0, REG(0));
946 948 return;
947 949 case 0xcf00: /* or.b #imm,@(R0,GBR) */
948   - gen_movl_rN_T(cpu_T[0], REG(0));
  950 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
949 951 gen_op_addl_GBR_T0();
950 952 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
951 953 gen_op_ldub_T0_T0(ctx);
... ... @@ -961,7 +963,7 @@ void _decode_opc(DisasContext * ctx)
961 963 gen_op_tst_imm_rN(B7_0, REG(0));
962 964 return;
963 965 case 0xcc00: /* tst.b #imm,@(R0,GBR) */
964   - gen_movl_rN_T(cpu_T[0], REG(0));
  966 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
965 967 gen_op_addl_GBR_T0();
966 968 gen_op_ldub_T0_T0(ctx);
967 969 gen_op_tst_imm_T0(B7_0);
... ... @@ -970,7 +972,7 @@ void _decode_opc(DisasContext * ctx)
970 972 gen_op_xor_imm_rN(B7_0, REG(0));
971 973 return;
972 974 case 0xce00: /* xor.b #imm,@(R0,GBR) */
973   - gen_movl_rN_T(cpu_T[0], REG(0));
  975 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
974 976 gen_op_addl_GBR_T0();
975 977 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
976 978 gen_op_ldub_T0_T0(ctx);
... ... @@ -981,23 +983,23 @@ void _decode_opc(DisasContext * ctx)
981 983  
982 984 switch (ctx->opcode & 0xf08f) {
983 985 case 0x408e: /* ldc Rm,Rn_BANK */
984   - gen_movl_rN_T(cpu_T[0], REG(B11_8));
985   - gen_movl_T_rN(cpu_T[0], ALTREG(B6_4));
  986 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
  987 + tcg_gen_mov_i32(cpu_gregs[ALTREG(B6_4)], cpu_T[0]);
986 988 return;
987 989 case 0x4087: /* ldc.l @Rm+,Rn_BANK */
988   - gen_movl_rN_T(cpu_T[0], REG(B11_8));
  990 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
989 991 gen_op_ldl_T0_T0(ctx);
990   - gen_movl_T_rN(cpu_T[0], ALTREG(B6_4));
  992 + tcg_gen_mov_i32(cpu_gregs[ALTREG(B6_4)], cpu_T[0]);
991 993 gen_op_inc4_rN(REG(B11_8));
992 994 return;
993 995 case 0x0082: /* stc Rm_BANK,Rn */
994   - gen_movl_rN_T(cpu_T[0], ALTREG(B6_4));
995   - gen_movl_T_rN(cpu_T[0], REG(B11_8));
  996 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]);
  997 + tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
996 998 return;
997 999 case 0x4083: /* stc.l Rm_BANK,@-Rn */
998 1000 gen_op_dec4_rN(REG(B11_8));
999   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
1000   - gen_movl_rN_T(cpu_T[0], ALTREG(B6_4));
  1001 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
  1002 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]);
1001 1003 gen_op_inc4_rN(REG(B11_8));
1002 1004 gen_op_stl_T0_T1(ctx);
1003 1005 gen_op_dec4_rN(REG(B11_8));
... ... @@ -1006,48 +1008,48 @@ void _decode_opc(DisasContext * ctx)
1006 1008  
1007 1009 switch (ctx->opcode & 0xf0ff) {
1008 1010 case 0x0023: /* braf Rn */
1009   - CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
  1011 + CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1010 1012 gen_op_braf_T0(ctx->pc + 4);
1011 1013 ctx->flags |= DELAY_SLOT;
1012 1014 ctx->delayed_pc = (uint32_t) - 1;
1013 1015 return;
1014 1016 case 0x0003: /* bsrf Rn */
1015   - CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
  1017 + CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1016 1018 gen_op_bsrf_T0(ctx->pc + 4);
1017 1019 ctx->flags |= DELAY_SLOT;
1018 1020 ctx->delayed_pc = (uint32_t) - 1;
1019 1021 return;
1020 1022 case 0x4015: /* cmp/pl Rn */
1021   - gen_movl_rN_T(cpu_T[0], REG(B11_8));
  1023 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1022 1024 gen_op_cmp_pl_T0();
1023 1025 return;
1024 1026 case 0x4011: /* cmp/pz Rn */
1025   - gen_movl_rN_T(cpu_T[0], REG(B11_8));
  1027 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1026 1028 gen_op_cmp_pz_T0();
1027 1029 return;
1028 1030 case 0x4010: /* dt Rn */
1029 1031 gen_op_dt_rN(REG(B11_8));
1030 1032 return;
1031 1033 case 0x402b: /* jmp @Rn */
1032   - CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
  1034 + CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1033 1035 gen_op_jmp_T0();
1034 1036 ctx->flags |= DELAY_SLOT;
1035 1037 ctx->delayed_pc = (uint32_t) - 1;
1036 1038 return;
1037 1039 case 0x400b: /* jsr @Rn */
1038   - CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
  1040 + CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1039 1041 gen_op_jsr_T0(ctx->pc + 4);
1040 1042 ctx->flags |= DELAY_SLOT;
1041 1043 ctx->delayed_pc = (uint32_t) - 1;
1042 1044 return;
1043 1045 #define LDST(reg,ldnum,ldpnum,ldop,stnum,stpnum,stop,extrald) \
1044 1046 case ldnum: \
1045   - gen_movl_rN_T (cpu_T[0], REG(B11_8)); \
  1047 + tcg_gen_mov_i32 (cpu_T[0], cpu_gregs[REG(B11_8)]); \
1046 1048 gen_op_##ldop##_T0_##reg (); \
1047 1049 extrald \
1048 1050 return; \
1049 1051 case ldpnum: \
1050   - gen_movl_rN_T (cpu_T[0], REG(B11_8)); \
  1052 + tcg_gen_mov_i32 (cpu_T[0], cpu_gregs[REG(B11_8)]); \
1051 1053 gen_op_ldl_T0_T0 (ctx); \
1052 1054 gen_op_inc4_rN (REG(B11_8)); \
1053 1055 gen_op_##ldop##_T0_##reg (); \
... ... @@ -1055,12 +1057,12 @@ void _decode_opc(DisasContext * ctx)
1055 1057 return; \
1056 1058 case stnum: \
1057 1059 gen_op_##stop##_##reg##_T0 (); \
1058   - gen_movl_T_rN (cpu_T[0], REG(B11_8)); \
  1060 + tcg_gen_mov_i32 (cpu_gregs[REG(B11_8)], cpu_T[0]); \
1059 1061 return; \
1060 1062 case stpnum: \
1061 1063 gen_op_##stop##_##reg##_T0 (); \
1062 1064 gen_op_dec4_rN (REG(B11_8)); \
1063   - gen_movl_rN_T (cpu_T[1], REG(B11_8)); \
  1065 + tcg_gen_mov_i32 (cpu_T[1], cpu_gregs[REG(B11_8)]); \
1064 1066 gen_op_inc4_rN (REG(B11_8)); \
1065 1067 gen_op_stl_T0_T1 (ctx); \
1066 1068 gen_op_dec4_rN (REG(B11_8)); \
... ... @@ -1079,23 +1081,23 @@ void _decode_opc(DisasContext * ctx)
1079 1081 LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->bstate =
1080 1082 BS_STOP;)
1081 1083 case 0x00c3: /* movca.l R0,@Rm */
1082   - gen_movl_rN_T(cpu_T[0], REG(0));
1083   - gen_movl_rN_T(cpu_T[1], REG(B11_8));
  1084 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
  1085 + tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
1084 1086 gen_op_stl_T0_T1(ctx);
1085 1087 return;
1086 1088 case 0x0029: /* movt Rn */
1087 1089 gen_op_movt_rN(REG(B11_8));
1088 1090 return;
1089 1091 case 0x0093: /* ocbi @Rn */
1090   - gen_movl_rN_T(cpu_T[0], REG(B11_8));
  1092 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1091 1093 gen_op_ldl_T0_T0(ctx);
1092 1094 return;
1093 1095 case 0x00a3: /* ocbp @Rn */
1094   - gen_movl_rN_T(cpu_T[0], REG(B11_8));
  1096 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1095 1097 gen_op_ldl_T0_T0(ctx);
1096 1098 return;
1097 1099 case 0x00b3: /* ocbwb @Rn */
1098   - gen_movl_rN_T(cpu_T[0], REG(B11_8));
  1100 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1099 1101 gen_op_ldl_T0_T0(ctx);
1100 1102 return;
1101 1103 case 0x0083: /* pref @Rn */
... ... @@ -1141,7 +1143,7 @@ void _decode_opc(DisasContext * ctx)
1141 1143 gen_op_shlr16_Rn(REG(B11_8));
1142 1144 return;
1143 1145 case 0x401b: /* tas.b @Rn */
1144   - gen_movl_rN_T(cpu_T[0], REG(B11_8));
  1146 + tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1145 1147 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
1146 1148 gen_op_ldub_T0_T0(ctx);
1147 1149 gen_op_cmp_eq_imm_T0(0);
... ...