gwj / at91sam9263 · Commits

Commit 1a3fd9c3da4e2d9434a14168306b2fa0abadce18

Authored by ths
1 parent e1bf387e

Remove remaining uses of T0 in the MIPS target. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4788 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 468 additions and 454 deletions
target-mips/cpu.h
  View file @1a3fd9c
@@ -140,9 +140,6 @@ struct CPUMIPSState { @@ -140,9 +140,6 @@ struct CPUMIPSState {
140 target_ulong gpr[MIPS_SHADOW_SET_MAX][32]; 140 target_ulong gpr[MIPS_SHADOW_SET_MAX][32];
141 /* Special registers */ 141 /* Special registers */
142 target_ulong PC[MIPS_TC_MAX]; 142 target_ulong PC[MIPS_TC_MAX];
143 -#if TARGET_LONG_BITS > HOST_LONG_BITS  
144 - target_ulong t0;  
145 -#endif  
146 /* temporary hack for FP globals */ 143 /* temporary hack for FP globals */
147 #ifndef USE_HOST_FLOAT_REGS 144 #ifndef USE_HOST_FLOAT_REGS
148 fpr_t ft0; 145 fpr_t ft0;
target-mips/exec.h
  View file @1a3fd9c
@@ -10,12 +10,6 @@ @@ -10,12 +10,6 @@
10 10
11 register struct CPUMIPSState *env asm(AREG0); 11 register struct CPUMIPSState *env asm(AREG0);
12 12
13 -#if TARGET_LONG_BITS > HOST_LONG_BITS  
14 -#define T0 (env->t0)  
15 -#else  
16 -register target_ulong T0 asm(AREG1);  
17 -#endif  
18 -  
19 #if defined (USE_HOST_FLOAT_REGS) 13 #if defined (USE_HOST_FLOAT_REGS)
20 #error "implement me." 14 #error "implement me."
21 #else 15 #else
target-mips/helper.h
  View file @1a3fd9c
@@ -43,40 +43,40 @@ DEF_HELPER(target_ulong, do_msachiu, (target_ulong t0, target_ulong t1)) @@ -43,40 +43,40 @@ DEF_HELPER(target_ulong, do_msachiu, (target_ulong t0, target_ulong t1))
43 43
44 /* CP0 helpers */ 44 /* CP0 helpers */
45 #ifndef CONFIG_USER_ONLY 45 #ifndef CONFIG_USER_ONLY
46 -DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (target_ulong t0))  
47 -DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (target_ulong t0))  
48 -DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (target_ulong t0))  
49 -DEF_HELPER(target_ulong, do_mfc0_random, (target_ulong t0))  
50 -DEF_HELPER(target_ulong, do_mfc0_tcstatus, (target_ulong t0))  
51 -DEF_HELPER(target_ulong, do_mftc0_tcstatus, (target_ulong t0))  
52 -DEF_HELPER(target_ulong, do_mfc0_tcbind, (target_ulong t0))  
53 -DEF_HELPER(target_ulong, do_mftc0_tcbind, (target_ulong t0))  
54 -DEF_HELPER(target_ulong, do_mfc0_tcrestart, (target_ulong t0))  
55 -DEF_HELPER(target_ulong, do_mftc0_tcrestart, (target_ulong t0))  
56 -DEF_HELPER(target_ulong, do_mfc0_tchalt, (target_ulong t0))  
57 -DEF_HELPER(target_ulong, do_mftc0_tchalt, (target_ulong t0))  
58 -DEF_HELPER(target_ulong, do_mfc0_tccontext, (target_ulong t0))  
59 -DEF_HELPER(target_ulong, do_mftc0_tccontext, (target_ulong t0))  
60 -DEF_HELPER(target_ulong, do_mfc0_tcschedule, (target_ulong t0))  
61 -DEF_HELPER(target_ulong, do_mftc0_tcschedule, (target_ulong t0))  
62 -DEF_HELPER(target_ulong, do_mfc0_tcschefback, (target_ulong t0))  
63 -DEF_HELPER(target_ulong, do_mftc0_tcschefback, (target_ulong t0))  
64 -DEF_HELPER(target_ulong, do_mfc0_count, (target_ulong t0))  
65 -DEF_HELPER(target_ulong, do_mftc0_entryhi, (target_ulong t0))  
66 -DEF_HELPER(target_ulong, do_mftc0_status, (target_ulong t0))  
67 -DEF_HELPER(target_ulong, do_mfc0_lladdr, (target_ulong t0))  
68 -DEF_HELPER(target_ulong, do_mfc0_watchlo, (target_ulong t0, uint32_t sel))  
69 -DEF_HELPER(target_ulong, do_mfc0_watchhi, (target_ulong t0, uint32_t sel))  
70 -DEF_HELPER(target_ulong, do_mfc0_debug, (target_ulong t0))  
71 -DEF_HELPER(target_ulong, do_mftc0_debug, (target_ulong t0)) 46 +DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (void))
  47 +DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (void))
  48 +DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (void))
  49 +DEF_HELPER(target_ulong, do_mfc0_random, (void))
  50 +DEF_HELPER(target_ulong, do_mfc0_tcstatus, (void))
  51 +DEF_HELPER(target_ulong, do_mftc0_tcstatus, (void))
  52 +DEF_HELPER(target_ulong, do_mfc0_tcbind, (void))
  53 +DEF_HELPER(target_ulong, do_mftc0_tcbind, (void))
  54 +DEF_HELPER(target_ulong, do_mfc0_tcrestart, (void))
  55 +DEF_HELPER(target_ulong, do_mftc0_tcrestart, (void))
  56 +DEF_HELPER(target_ulong, do_mfc0_tchalt, (void))
  57 +DEF_HELPER(target_ulong, do_mftc0_tchalt, (void))
  58 +DEF_HELPER(target_ulong, do_mfc0_tccontext, (void))
  59 +DEF_HELPER(target_ulong, do_mftc0_tccontext, (void))
  60 +DEF_HELPER(target_ulong, do_mfc0_tcschedule, (void))
  61 +DEF_HELPER(target_ulong, do_mftc0_tcschedule, (void))
  62 +DEF_HELPER(target_ulong, do_mfc0_tcschefback, (void))
  63 +DEF_HELPER(target_ulong, do_mftc0_tcschefback, (void))
  64 +DEF_HELPER(target_ulong, do_mfc0_count, (void))
  65 +DEF_HELPER(target_ulong, do_mftc0_entryhi, (void))
  66 +DEF_HELPER(target_ulong, do_mftc0_status, (void))
  67 +DEF_HELPER(target_ulong, do_mfc0_lladdr, (void))
  68 +DEF_HELPER(target_ulong, do_mfc0_watchlo, (uint32_t sel))
  69 +DEF_HELPER(target_ulong, do_mfc0_watchhi, (uint32_t sel))
  70 +DEF_HELPER(target_ulong, do_mfc0_debug, (void))
  71 +DEF_HELPER(target_ulong, do_mftc0_debug, (void))
72 #ifdef TARGET_MIPS64 72 #ifdef TARGET_MIPS64
73 -DEF_HELPER(target_ulong, do_dmfc0_tcrestart, (target_ulong t0))  
74 -DEF_HELPER(target_ulong, do_dmfc0_tchalt, (target_ulong t0))  
75 -DEF_HELPER(target_ulong, do_dmfc0_tccontext, (target_ulong t0))  
76 -DEF_HELPER(target_ulong, do_dmfc0_tcschedule, (target_ulong t0))  
77 -DEF_HELPER(target_ulong, do_dmfc0_tcschefback, (target_ulong t0))  
78 -DEF_HELPER(target_ulong, do_dmfc0_lladdr, (target_ulong t0))  
79 -DEF_HELPER(target_ulong, do_dmfc0_watchlo, (target_ulong t0, uint32_t sel)) 73 +DEF_HELPER(target_ulong, do_dmfc0_tcrestart, (void))
  74 +DEF_HELPER(target_ulong, do_dmfc0_tchalt, (void))
  75 +DEF_HELPER(target_ulong, do_dmfc0_tccontext, (void))
  76 +DEF_HELPER(target_ulong, do_dmfc0_tcschedule, (void))
  77 +DEF_HELPER(target_ulong, do_dmfc0_tcschefback, (void))
  78 +DEF_HELPER(target_ulong, do_dmfc0_lladdr, (void))
  79 +DEF_HELPER(target_ulong, do_dmfc0_watchlo, (uint32_t sel))
80 #endif /* TARGET_MIPS64 */ 80 #endif /* TARGET_MIPS64 */
81 81
82 DEF_HELPER(void, do_mtc0_index, (target_ulong t0)) 82 DEF_HELPER(void, do_mtc0_index, (target_ulong t0))
target-mips/op_helper.c
  View file @1a3fd9c
@@ -650,126 +650,127 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global) @@ -650,126 +650,127 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global)
650 #else 650 #else
651 651
652 /* CP0 helpers */ 652 /* CP0 helpers */
653 -target_ulong do_mfc0_mvpcontrol (target_ulong t0) 653 +target_ulong do_mfc0_mvpcontrol (void)
654 { 654 {
655 return env->mvp->CP0_MVPControl; 655 return env->mvp->CP0_MVPControl;
656 } 656 }
657 657
658 -target_ulong do_mfc0_mvpconf0 (target_ulong t0) 658 +target_ulong do_mfc0_mvpconf0 (void)
659 { 659 {
660 return env->mvp->CP0_MVPConf0; 660 return env->mvp->CP0_MVPConf0;
661 } 661 }
662 662
663 -target_ulong do_mfc0_mvpconf1 (target_ulong t0) 663 +target_ulong do_mfc0_mvpconf1 (void)
664 { 664 {
665 return env->mvp->CP0_MVPConf1; 665 return env->mvp->CP0_MVPConf1;
666 } 666 }
667 667
668 -target_ulong do_mfc0_random (target_ulong t0) 668 +target_ulong do_mfc0_random (void)
669 { 669 {
670 return (int32_t)cpu_mips_get_random(env); 670 return (int32_t)cpu_mips_get_random(env);
671 } 671 }
672 672
673 -target_ulong do_mfc0_tcstatus (target_ulong t0) 673 +target_ulong do_mfc0_tcstatus (void)
674 { 674 {
675 return env->CP0_TCStatus[env->current_tc]; 675 return env->CP0_TCStatus[env->current_tc];
676 } 676 }
677 677
678 -target_ulong do_mftc0_tcstatus(target_ulong t0) 678 +target_ulong do_mftc0_tcstatus(void)
679 { 679 {
680 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 680 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
681 681
682 return env->CP0_TCStatus[other_tc]; 682 return env->CP0_TCStatus[other_tc];
683 } 683 }
684 684
685 -target_ulong do_mfc0_tcbind (target_ulong t0) 685 +target_ulong do_mfc0_tcbind (void)
686 { 686 {
687 return env->CP0_TCBind[env->current_tc]; 687 return env->CP0_TCBind[env->current_tc];
688 } 688 }
689 689
690 -target_ulong do_mftc0_tcbind(target_ulong t0) 690 +target_ulong do_mftc0_tcbind(void)
691 { 691 {
692 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 692 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
693 693
694 return env->CP0_TCBind[other_tc]; 694 return env->CP0_TCBind[other_tc];
695 } 695 }
696 696
697 -target_ulong do_mfc0_tcrestart (target_ulong t0) 697 +target_ulong do_mfc0_tcrestart (void)
698 { 698 {
699 return env->PC[env->current_tc]; 699 return env->PC[env->current_tc];
700 } 700 }
701 701
702 -target_ulong do_mftc0_tcrestart(target_ulong t0) 702 +target_ulong do_mftc0_tcrestart(void)
703 { 703 {
704 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 704 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
705 705
706 return env->PC[other_tc]; 706 return env->PC[other_tc];
707 } 707 }
708 708
709 -target_ulong do_mfc0_tchalt (target_ulong t0) 709 +target_ulong do_mfc0_tchalt (void)
710 { 710 {
711 return env->CP0_TCHalt[env->current_tc]; 711 return env->CP0_TCHalt[env->current_tc];
712 } 712 }
713 713
714 -target_ulong do_mftc0_tchalt(target_ulong t0) 714 +target_ulong do_mftc0_tchalt(void)
715 { 715 {
716 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 716 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
717 717
718 return env->CP0_TCHalt[other_tc]; 718 return env->CP0_TCHalt[other_tc];
719 } 719 }
720 720
721 -target_ulong do_mfc0_tccontext (target_ulong t0) 721 +target_ulong do_mfc0_tccontext (void)
722 { 722 {
723 return env->CP0_TCContext[env->current_tc]; 723 return env->CP0_TCContext[env->current_tc];
724 } 724 }
725 725
726 -target_ulong do_mftc0_tccontext(target_ulong t0) 726 +target_ulong do_mftc0_tccontext(void)
727 { 727 {
728 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 728 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
729 729
730 return env->CP0_TCContext[other_tc]; 730 return env->CP0_TCContext[other_tc];
731 } 731 }
732 732
733 -target_ulong do_mfc0_tcschedule (target_ulong t0) 733 +target_ulong do_mfc0_tcschedule (void)
734 { 734 {
735 return env->CP0_TCSchedule[env->current_tc]; 735 return env->CP0_TCSchedule[env->current_tc];
736 } 736 }
737 737
738 -target_ulong do_mftc0_tcschedule(target_ulong t0) 738 +target_ulong do_mftc0_tcschedule(void)
739 { 739 {
740 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 740 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
741 741
742 return env->CP0_TCSchedule[other_tc]; 742 return env->CP0_TCSchedule[other_tc];
743 } 743 }
744 744
745 -target_ulong do_mfc0_tcschefback (target_ulong t0) 745 +target_ulong do_mfc0_tcschefback (void)
746 { 746 {
747 return env->CP0_TCScheFBack[env->current_tc]; 747 return env->CP0_TCScheFBack[env->current_tc];
748 } 748 }
749 749
750 -target_ulong do_mftc0_tcschefback(target_ulong t0) 750 +target_ulong do_mftc0_tcschefback(void)
751 { 751 {
752 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 752 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
753 753
754 return env->CP0_TCScheFBack[other_tc]; 754 return env->CP0_TCScheFBack[other_tc];
755 } 755 }
756 756
757 -target_ulong do_mfc0_count (target_ulong t0) 757 +target_ulong do_mfc0_count (void)
758 { 758 {
759 return (int32_t)cpu_mips_get_count(env); 759 return (int32_t)cpu_mips_get_count(env);
760 } 760 }
761 761
762 -target_ulong do_mftc0_entryhi(target_ulong t0) 762 +target_ulong do_mftc0_entryhi(void)
763 { 763 {
764 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 764 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
765 765
766 return (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff); 766 return (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
767 } 767 }
768 768
769 -target_ulong do_mftc0_status(target_ulong t0) 769 +target_ulong do_mftc0_status(void)
770 { 770 {
771 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 771 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
772 uint32_t tcstatus = env->CP0_TCStatus[other_tc]; 772 uint32_t tcstatus = env->CP0_TCStatus[other_tc];
  773 + target_ulong t0;
773 774
774 t0 = env->CP0_Status & ~0xf1000018; 775 t0 = env->CP0_Status & ~0xf1000018;
775 t0 |= tcstatus & (0xf << CP0TCSt_TCU0); 776 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
@@ -779,31 +780,31 @@ target_ulong do_mftc0_status(target_ulong t0) @@ -779,31 +780,31 @@ target_ulong do_mftc0_status(target_ulong t0)
779 return t0; 780 return t0;
780 } 781 }
781 782
782 -target_ulong do_mfc0_lladdr (target_ulong t0) 783 +target_ulong do_mfc0_lladdr (void)
783 { 784 {
784 return (int32_t)env->CP0_LLAddr >> 4; 785 return (int32_t)env->CP0_LLAddr >> 4;
785 } 786 }
786 787
787 -target_ulong do_mfc0_watchlo (target_ulong t0, uint32_t sel) 788 +target_ulong do_mfc0_watchlo (uint32_t sel)
788 { 789 {
789 return (int32_t)env->CP0_WatchLo[sel]; 790 return (int32_t)env->CP0_WatchLo[sel];
790 } 791 }
791 792
792 -target_ulong do_mfc0_watchhi (target_ulong t0, uint32_t sel) 793 +target_ulong do_mfc0_watchhi (uint32_t sel)
793 { 794 {
794 return env->CP0_WatchHi[sel]; 795 return env->CP0_WatchHi[sel];
795 } 796 }
796 797
797 -target_ulong do_mfc0_debug (target_ulong t0) 798 +target_ulong do_mfc0_debug (void)
798 { 799 {
799 - t0 = env->CP0_Debug; 800 + target_ulong t0 = env->CP0_Debug;
800 if (env->hflags & MIPS_HFLAG_DM) 801 if (env->hflags & MIPS_HFLAG_DM)
801 t0 |= 1 << CP0DB_DM; 802 t0 |= 1 << CP0DB_DM;
802 803
803 return t0; 804 return t0;
804 } 805 }
805 806
806 -target_ulong do_mftc0_debug(target_ulong t0) 807 +target_ulong do_mftc0_debug(void)
807 { 808 {
808 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 809 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
809 810
@@ -814,37 +815,37 @@ target_ulong do_mftc0_debug(target_ulong t0) @@ -814,37 +815,37 @@ target_ulong do_mftc0_debug(target_ulong t0)
814 } 815 }
815 816
816 #if defined(TARGET_MIPS64) 817 #if defined(TARGET_MIPS64)
817 -target_ulong do_dmfc0_tcrestart (target_ulong t0) 818 +target_ulong do_dmfc0_tcrestart (void)
818 { 819 {
819 return env->PC[env->current_tc]; 820 return env->PC[env->current_tc];
820 } 821 }
821 822
822 -target_ulong do_dmfc0_tchalt (target_ulong t0) 823 +target_ulong do_dmfc0_tchalt (void)
823 { 824 {
824 return env->CP0_TCHalt[env->current_tc]; 825 return env->CP0_TCHalt[env->current_tc];
825 } 826 }
826 827
827 -target_ulong do_dmfc0_tccontext (target_ulong t0) 828 +target_ulong do_dmfc0_tccontext (void)
828 { 829 {
829 return env->CP0_TCContext[env->current_tc]; 830 return env->CP0_TCContext[env->current_tc];
830 } 831 }
831 832
832 -target_ulong do_dmfc0_tcschedule (target_ulong t0) 833 +target_ulong do_dmfc0_tcschedule (void)
833 { 834 {
834 return env->CP0_TCSchedule[env->current_tc]; 835 return env->CP0_TCSchedule[env->current_tc];
835 } 836 }
836 837
837 -target_ulong do_dmfc0_tcschefback (target_ulong t0) 838 +target_ulong do_dmfc0_tcschefback (void)
838 { 839 {
839 return env->CP0_TCScheFBack[env->current_tc]; 840 return env->CP0_TCScheFBack[env->current_tc];
840 } 841 }
841 842
842 -target_ulong do_dmfc0_lladdr (target_ulong t0) 843 +target_ulong do_dmfc0_lladdr (void)
843 { 844 {
844 return env->CP0_LLAddr >> 4; 845 return env->CP0_LLAddr >> 4;
845 } 846 }
846 847
847 -target_ulong do_dmfc0_watchlo (target_ulong t0, uint32_t sel) 848 +target_ulong do_dmfc0_watchlo (uint32_t sel)
848 { 849 {
849 return env->CP0_WatchLo[sel]; 850 return env->CP0_WatchLo[sel];
850 } 851 }
target-mips/translate.c
  View file @1a3fd9c
@@ -423,7 +423,7 @@ enum { @@ -423,7 +423,7 @@ enum {
423 }; 423 };
424 424
425 /* global register indices */ 425 /* global register indices */
426 -static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu, cpu_T[1]; 426 +static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu;
427 427
428 /* FPU TNs, global for now. */ 428 /* FPU TNs, global for now. */
429 static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3]; 429 static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3];
@@ -2856,7 +2856,7 @@ static inline void gen_mtc0_store64 (TCGv t, target_ulong off) @@ -2856,7 +2856,7 @@ static inline void gen_mtc0_store64 (TCGv t, target_ulong off)
2856 tcg_gen_st_tl(t, cpu_env, off); 2856 tcg_gen_st_tl(t, cpu_env, off);
2857 } 2857 }
2858 2858
2859 -static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) 2859 +static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
2860 { 2860 {
2861 const char *rn = "invalid"; 2861 const char *rn = "invalid";
2862 2862
@@ -2867,22 +2867,22 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2867,22 +2867,22 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2867 case 0: 2867 case 0:
2868 switch (sel) { 2868 switch (sel) {
2869 case 0: 2869 case 0:
2870 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Index)); 2870 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
2871 rn = "Index"; 2871 rn = "Index";
2872 break; 2872 break;
2873 case 1: 2873 case 1:
2874 check_insn(env, ctx, ASE_MT); 2874 check_insn(env, ctx, ASE_MT);
2875 - tcg_gen_helper_1_1(do_mfc0_mvpcontrol, cpu_T[0], cpu_T[0]); 2875 + tcg_gen_helper_1_0(do_mfc0_mvpcontrol, t0);
2876 rn = "MVPControl"; 2876 rn = "MVPControl";
2877 break; 2877 break;
2878 case 2: 2878 case 2:
2879 check_insn(env, ctx, ASE_MT); 2879 check_insn(env, ctx, ASE_MT);
2880 - tcg_gen_helper_1_1(do_mfc0_mvpconf0, cpu_T[0], cpu_T[0]); 2880 + tcg_gen_helper_1_0(do_mfc0_mvpconf0, t0);
2881 rn = "MVPConf0"; 2881 rn = "MVPConf0";
2882 break; 2882 break;
2883 case 3: 2883 case 3:
2884 check_insn(env, ctx, ASE_MT); 2884 check_insn(env, ctx, ASE_MT);
2885 - tcg_gen_helper_1_1(do_mfc0_mvpconf1, cpu_T[0], cpu_T[0]); 2885 + tcg_gen_helper_1_0(do_mfc0_mvpconf1, t0);
2886 rn = "MVPConf1"; 2886 rn = "MVPConf1";
2887 break; 2887 break;
2888 default: 2888 default:
@@ -2892,42 +2892,42 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2892,42 +2892,42 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2892 case 1: 2892 case 1:
2893 switch (sel) { 2893 switch (sel) {
2894 case 0: 2894 case 0:
2895 - tcg_gen_helper_1_1(do_mfc0_random, cpu_T[0], cpu_T[0]); 2895 + tcg_gen_helper_1_0(do_mfc0_random, t0);
2896 rn = "Random"; 2896 rn = "Random";
2897 break; 2897 break;
2898 case 1: 2898 case 1:
2899 check_insn(env, ctx, ASE_MT); 2899 check_insn(env, ctx, ASE_MT);
2900 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEControl)); 2900 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
2901 rn = "VPEControl"; 2901 rn = "VPEControl";
2902 break; 2902 break;
2903 case 2: 2903 case 2:
2904 check_insn(env, ctx, ASE_MT); 2904 check_insn(env, ctx, ASE_MT);
2905 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf0)); 2905 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
2906 rn = "VPEConf0"; 2906 rn = "VPEConf0";
2907 break; 2907 break;
2908 case 3: 2908 case 3:
2909 check_insn(env, ctx, ASE_MT); 2909 check_insn(env, ctx, ASE_MT);
2910 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf1)); 2910 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
2911 rn = "VPEConf1"; 2911 rn = "VPEConf1";
2912 break; 2912 break;
2913 case 4: 2913 case 4:
2914 check_insn(env, ctx, ASE_MT); 2914 check_insn(env, ctx, ASE_MT);
2915 - gen_mfc0_load64(cpu_T[0], offsetof(CPUState, CP0_YQMask)); 2915 + gen_mfc0_load64(t0, offsetof(CPUState, CP0_YQMask));
2916 rn = "YQMask"; 2916 rn = "YQMask";
2917 break; 2917 break;
2918 case 5: 2918 case 5:
2919 check_insn(env, ctx, ASE_MT); 2919 check_insn(env, ctx, ASE_MT);
2920 - gen_mfc0_load64(cpu_T[0], offsetof(CPUState, CP0_VPESchedule)); 2920 + gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPESchedule));
2921 rn = "VPESchedule"; 2921 rn = "VPESchedule";
2922 break; 2922 break;
2923 case 6: 2923 case 6:
2924 check_insn(env, ctx, ASE_MT); 2924 check_insn(env, ctx, ASE_MT);
2925 - gen_mfc0_load64(cpu_T[0], offsetof(CPUState, CP0_VPEScheFBack)); 2925 + gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPEScheFBack));
2926 rn = "VPEScheFBack"; 2926 rn = "VPEScheFBack";
2927 break; 2927 break;
2928 case 7: 2928 case 7:
2929 check_insn(env, ctx, ASE_MT); 2929 check_insn(env, ctx, ASE_MT);
2930 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEOpt)); 2930 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
2931 rn = "VPEOpt"; 2931 rn = "VPEOpt";
2932 break; 2932 break;
2933 default: 2933 default:
@@ -2937,43 +2937,43 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2937,43 +2937,43 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2937 case 2: 2937 case 2:
2938 switch (sel) { 2938 switch (sel) {
2939 case 0: 2939 case 0:
2940 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0));  
2941 - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); 2940 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
  2941 + tcg_gen_ext32s_tl(t0, t0);
2942 rn = "EntryLo0"; 2942 rn = "EntryLo0";
2943 break; 2943 break;
2944 case 1: 2944 case 1:
2945 check_insn(env, ctx, ASE_MT); 2945 check_insn(env, ctx, ASE_MT);
2946 - tcg_gen_helper_1_1(do_mfc0_tcstatus, cpu_T[0], cpu_T[0]); 2946 + tcg_gen_helper_1_0(do_mfc0_tcstatus, t0);
2947 rn = "TCStatus"; 2947 rn = "TCStatus";
2948 break; 2948 break;
2949 case 2: 2949 case 2:
2950 check_insn(env, ctx, ASE_MT); 2950 check_insn(env, ctx, ASE_MT);
2951 - tcg_gen_helper_1_1(do_mfc0_tcbind, cpu_T[0], cpu_T[0]); 2951 + tcg_gen_helper_1_0(do_mfc0_tcbind, t0);
2952 rn = "TCBind"; 2952 rn = "TCBind";
2953 break; 2953 break;
2954 case 3: 2954 case 3:
2955 check_insn(env, ctx, ASE_MT); 2955 check_insn(env, ctx, ASE_MT);
2956 - tcg_gen_helper_1_1(do_mfc0_tcrestart, cpu_T[0], cpu_T[0]); 2956 + tcg_gen_helper_1_0(do_mfc0_tcrestart, t0);
2957 rn = "TCRestart"; 2957 rn = "TCRestart";
2958 break; 2958 break;
2959 case 4: 2959 case 4:
2960 check_insn(env, ctx, ASE_MT); 2960 check_insn(env, ctx, ASE_MT);
2961 - tcg_gen_helper_1_1(do_mfc0_tchalt, cpu_T[0], cpu_T[0]); 2961 + tcg_gen_helper_1_0(do_mfc0_tchalt, t0);
2962 rn = "TCHalt"; 2962 rn = "TCHalt";
2963 break; 2963 break;
2964 case 5: 2964 case 5:
2965 check_insn(env, ctx, ASE_MT); 2965 check_insn(env, ctx, ASE_MT);
2966 - tcg_gen_helper_1_1(do_mfc0_tccontext, cpu_T[0], cpu_T[0]); 2966 + tcg_gen_helper_1_0(do_mfc0_tccontext, t0);
2967 rn = "TCContext"; 2967 rn = "TCContext";
2968 break; 2968 break;
2969 case 6: 2969 case 6:
2970 check_insn(env, ctx, ASE_MT); 2970 check_insn(env, ctx, ASE_MT);
2971 - tcg_gen_helper_1_1(do_mfc0_tcschedule, cpu_T[0], cpu_T[0]); 2971 + tcg_gen_helper_1_0(do_mfc0_tcschedule, t0);
2972 rn = "TCSchedule"; 2972 rn = "TCSchedule";
2973 break; 2973 break;
2974 case 7: 2974 case 7:
2975 check_insn(env, ctx, ASE_MT); 2975 check_insn(env, ctx, ASE_MT);
2976 - tcg_gen_helper_1_1(do_mfc0_tcschefback, cpu_T[0], cpu_T[0]); 2976 + tcg_gen_helper_1_0(do_mfc0_tcschefback, t0);
2977 rn = "TCScheFBack"; 2977 rn = "TCScheFBack";
2978 break; 2978 break;
2979 default: 2979 default:
@@ -2983,8 +2983,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2983,8 +2983,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2983 case 3: 2983 case 3:
2984 switch (sel) { 2984 switch (sel) {
2985 case 0: 2985 case 0:
2986 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1));  
2987 - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); 2986 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
  2987 + tcg_gen_ext32s_tl(t0, t0);
2988 rn = "EntryLo1"; 2988 rn = "EntryLo1";
2989 break; 2989 break;
2990 default: 2990 default:
@@ -2994,12 +2994,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2994,12 +2994,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2994 case 4: 2994 case 4:
2995 switch (sel) { 2995 switch (sel) {
2996 case 0: 2996 case 0:
2997 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context));  
2998 - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); 2997 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
  2998 + tcg_gen_ext32s_tl(t0, t0);
2999 rn = "Context"; 2999 rn = "Context";
3000 break; 3000 break;
3001 case 1: 3001 case 1:
3002 -// tcg_gen_helper_1_1(do_mfc0_contextconfig, cpu_T[0], cpu_T[0]); /* SmartMIPS ASE */ 3002 +// tcg_gen_helper_1_0(do_mfc0_contextconfig, t0); /* SmartMIPS ASE */
3003 rn = "ContextConfig"; 3003 rn = "ContextConfig";
3004 // break; 3004 // break;
3005 default: 3005 default:
@@ -3009,12 +3009,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3009,12 +3009,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3009 case 5: 3009 case 5:
3010 switch (sel) { 3010 switch (sel) {
3011 case 0: 3011 case 0:
3012 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageMask)); 3012 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
3013 rn = "PageMask"; 3013 rn = "PageMask";
3014 break; 3014 break;
3015 case 1: 3015 case 1:
3016 check_insn(env, ctx, ISA_MIPS32R2); 3016 check_insn(env, ctx, ISA_MIPS32R2);
3017 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageGrain)); 3017 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
3018 rn = "PageGrain"; 3018 rn = "PageGrain";
3019 break; 3019 break;
3020 default: 3020 default:
@@ -3024,32 +3024,32 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3024,32 +3024,32 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3024 case 6: 3024 case 6:
3025 switch (sel) { 3025 switch (sel) {
3026 case 0: 3026 case 0:
3027 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Wired)); 3027 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
3028 rn = "Wired"; 3028 rn = "Wired";
3029 break; 3029 break;
3030 case 1: 3030 case 1:
3031 check_insn(env, ctx, ISA_MIPS32R2); 3031 check_insn(env, ctx, ISA_MIPS32R2);
3032 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf0)); 3032 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
3033 rn = "SRSConf0"; 3033 rn = "SRSConf0";
3034 break; 3034 break;
3035 case 2: 3035 case 2:
3036 check_insn(env, ctx, ISA_MIPS32R2); 3036 check_insn(env, ctx, ISA_MIPS32R2);
3037 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf1)); 3037 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
3038 rn = "SRSConf1"; 3038 rn = "SRSConf1";
3039 break; 3039 break;
3040 case 3: 3040 case 3:
3041 check_insn(env, ctx, ISA_MIPS32R2); 3041 check_insn(env, ctx, ISA_MIPS32R2);
3042 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf2)); 3042 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
3043 rn = "SRSConf2"; 3043 rn = "SRSConf2";
3044 break; 3044 break;
3045 case 4: 3045 case 4:
3046 check_insn(env, ctx, ISA_MIPS32R2); 3046 check_insn(env, ctx, ISA_MIPS32R2);
3047 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf3)); 3047 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
3048 rn = "SRSConf3"; 3048 rn = "SRSConf3";
3049 break; 3049 break;
3050 case 5: 3050 case 5:
3051 check_insn(env, ctx, ISA_MIPS32R2); 3051 check_insn(env, ctx, ISA_MIPS32R2);
3052 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf4)); 3052 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
3053 rn = "SRSConf4"; 3053 rn = "SRSConf4";
3054 break; 3054 break;
3055 default: 3055 default:
@@ -3060,7 +3060,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3060,7 +3060,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3060 switch (sel) { 3060 switch (sel) {
3061 case 0: 3061 case 0:
3062 check_insn(env, ctx, ISA_MIPS32R2); 3062 check_insn(env, ctx, ISA_MIPS32R2);
3063 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_HWREna)); 3063 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
3064 rn = "HWREna"; 3064 rn = "HWREna";
3065 break; 3065 break;
3066 default: 3066 default:
@@ -3070,8 +3070,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3070,8 +3070,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3070 case 8: 3070 case 8:
3071 switch (sel) { 3071 switch (sel) {
3072 case 0: 3072 case 0:
3073 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr));  
3074 - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); 3073 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
  3074 + tcg_gen_ext32s_tl(t0, t0);
3075 rn = "BadVAddr"; 3075 rn = "BadVAddr";
3076 break; 3076 break;
3077 default: 3077 default:
@@ -3081,7 +3081,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3081,7 +3081,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3081 case 9: 3081 case 9:
3082 switch (sel) { 3082 switch (sel) {
3083 case 0: 3083 case 0:
3084 - tcg_gen_helper_1_1(do_mfc0_count, cpu_T[0], cpu_T[0]); 3084 + tcg_gen_helper_1_0(do_mfc0_count, t0);
3085 rn = "Count"; 3085 rn = "Count";
3086 break; 3086 break;
3087 /* 6,7 are implementation dependent */ 3087 /* 6,7 are implementation dependent */
@@ -3092,8 +3092,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3092,8 +3092,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3092 case 10: 3092 case 10:
3093 switch (sel) { 3093 switch (sel) {
3094 case 0: 3094 case 0:
3095 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi));  
3096 - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); 3095 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
  3096 + tcg_gen_ext32s_tl(t0, t0);
3097 rn = "EntryHi"; 3097 rn = "EntryHi";
3098 break; 3098 break;
3099 default: 3099 default:
@@ -3103,7 +3103,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3103,7 +3103,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3103 case 11: 3103 case 11:
3104 switch (sel) { 3104 switch (sel) {
3105 case 0: 3105 case 0:
3106 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Compare)); 3106 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
3107 rn = "Compare"; 3107 rn = "Compare";
3108 break; 3108 break;
3109 /* 6,7 are implementation dependent */ 3109 /* 6,7 are implementation dependent */
@@ -3114,22 +3114,22 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3114,22 +3114,22 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3114 case 12: 3114 case 12:
3115 switch (sel) { 3115 switch (sel) {
3116 case 0: 3116 case 0:
3117 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Status)); 3117 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
3118 rn = "Status"; 3118 rn = "Status";
3119 break; 3119 break;
3120 case 1: 3120 case 1:
3121 check_insn(env, ctx, ISA_MIPS32R2); 3121 check_insn(env, ctx, ISA_MIPS32R2);
3122 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_IntCtl)); 3122 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
3123 rn = "IntCtl"; 3123 rn = "IntCtl";
3124 break; 3124 break;
3125 case 2: 3125 case 2:
3126 check_insn(env, ctx, ISA_MIPS32R2); 3126 check_insn(env, ctx, ISA_MIPS32R2);
3127 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSCtl)); 3127 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
3128 rn = "SRSCtl"; 3128 rn = "SRSCtl";
3129 break; 3129 break;
3130 case 3: 3130 case 3:
3131 check_insn(env, ctx, ISA_MIPS32R2); 3131 check_insn(env, ctx, ISA_MIPS32R2);
3132 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSMap)); 3132 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
3133 rn = "SRSMap"; 3133 rn = "SRSMap";
3134 break; 3134 break;
3135 default: 3135 default:
@@ -3139,7 +3139,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3139,7 +3139,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3139 case 13: 3139 case 13:
3140 switch (sel) { 3140 switch (sel) {
3141 case 0: 3141 case 0:
3142 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Cause)); 3142 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
3143 rn = "Cause"; 3143 rn = "Cause";
3144 break; 3144 break;
3145 default: 3145 default:
@@ -3149,8 +3149,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3149,8 +3149,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3149 case 14: 3149 case 14:
3150 switch (sel) { 3150 switch (sel) {
3151 case 0: 3151 case 0:
3152 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));  
3153 - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); 3152 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
  3153 + tcg_gen_ext32s_tl(t0, t0);
3154 rn = "EPC"; 3154 rn = "EPC";
3155 break; 3155 break;
3156 default: 3156 default:
@@ -3160,12 +3160,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3160,12 +3160,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3160 case 15: 3160 case 15:
3161 switch (sel) { 3161 switch (sel) {
3162 case 0: 3162 case 0:
3163 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PRid)); 3163 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
3164 rn = "PRid"; 3164 rn = "PRid";
3165 break; 3165 break;
3166 case 1: 3166 case 1:
3167 check_insn(env, ctx, ISA_MIPS32R2); 3167 check_insn(env, ctx, ISA_MIPS32R2);
3168 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_EBase)); 3168 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
3169 rn = "EBase"; 3169 rn = "EBase";
3170 break; 3170 break;
3171 default: 3171 default:
@@ -3175,29 +3175,29 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3175,29 +3175,29 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3175 case 16: 3175 case 16:
3176 switch (sel) { 3176 switch (sel) {
3177 case 0: 3177 case 0:
3178 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config0)); 3178 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
3179 rn = "Config"; 3179 rn = "Config";
3180 break; 3180 break;
3181 case 1: 3181 case 1:
3182 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config1)); 3182 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
3183 rn = "Config1"; 3183 rn = "Config1";
3184 break; 3184 break;
3185 case 2: 3185 case 2:
3186 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config2)); 3186 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
3187 rn = "Config2"; 3187 rn = "Config2";
3188 break; 3188 break;
3189 case 3: 3189 case 3:
3190 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config3)); 3190 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
3191 rn = "Config3"; 3191 rn = "Config3";
3192 break; 3192 break;
3193 /* 4,5 are reserved */ 3193 /* 4,5 are reserved */
3194 /* 6,7 are implementation dependent */ 3194 /* 6,7 are implementation dependent */
3195 case 6: 3195 case 6:
3196 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config6)); 3196 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
3197 rn = "Config6"; 3197 rn = "Config6";
3198 break; 3198 break;
3199 case 7: 3199 case 7:
3200 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config7)); 3200 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
3201 rn = "Config7"; 3201 rn = "Config7";
3202 break; 3202 break;
3203 default: 3203 default:
@@ -3207,7 +3207,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3207,7 +3207,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3207 case 17: 3207 case 17:
3208 switch (sel) { 3208 switch (sel) {
3209 case 0: 3209 case 0:
3210 - tcg_gen_helper_1_1(do_mfc0_lladdr, cpu_T[0], cpu_T[0]); 3210 + tcg_gen_helper_1_0(do_mfc0_lladdr, t0);
3211 rn = "LLAddr"; 3211 rn = "LLAddr";
3212 break; 3212 break;
3213 default: 3213 default:
@@ -3217,7 +3217,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3217,7 +3217,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3217 case 18: 3217 case 18:
3218 switch (sel) { 3218 switch (sel) {
3219 case 0 ... 7: 3219 case 0 ... 7:
3220 - tcg_gen_helper_1_1i(do_mfc0_watchlo, cpu_T[0], cpu_T[0], sel); 3220 + tcg_gen_helper_1_i(do_mfc0_watchlo, t0, sel);
3221 rn = "WatchLo"; 3221 rn = "WatchLo";
3222 break; 3222 break;
3223 default: 3223 default:
@@ -3227,7 +3227,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3227,7 +3227,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3227 case 19: 3227 case 19:
3228 switch (sel) { 3228 switch (sel) {
3229 case 0 ...7: 3229 case 0 ...7:
3230 - tcg_gen_helper_1_1i(do_mfc0_watchhi, cpu_T[0], cpu_T[0], sel); 3230 + tcg_gen_helper_1_i(do_mfc0_watchhi, t0, sel);
3231 rn = "WatchHi"; 3231 rn = "WatchHi";
3232 break; 3232 break;
3233 default: 3233 default:
@@ -3239,8 +3239,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3239,8 +3239,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3239 case 0: 3239 case 0:
3240 #if defined(TARGET_MIPS64) 3240 #if defined(TARGET_MIPS64)
3241 check_insn(env, ctx, ISA_MIPS3); 3241 check_insn(env, ctx, ISA_MIPS3);
3242 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext));  
3243 - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); 3242 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
  3243 + tcg_gen_ext32s_tl(t0, t0);
3244 rn = "XContext"; 3244 rn = "XContext";
3245 break; 3245 break;
3246 #endif 3246 #endif
@@ -3252,7 +3252,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3252,7 +3252,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3252 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 3252 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3253 switch (sel) { 3253 switch (sel) {
3254 case 0: 3254 case 0:
3255 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Framemask)); 3255 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
3256 rn = "Framemask"; 3256 rn = "Framemask";
3257 break; 3257 break;
3258 default: 3258 default:
@@ -3266,23 +3266,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3266,23 +3266,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3266 case 23: 3266 case 23:
3267 switch (sel) { 3267 switch (sel) {
3268 case 0: 3268 case 0:
3269 - tcg_gen_helper_1_1(do_mfc0_debug, cpu_T[0], cpu_T[0]); /* EJTAG support */ 3269 + tcg_gen_helper_1_0(do_mfc0_debug, t0); /* EJTAG support */
3270 rn = "Debug"; 3270 rn = "Debug";
3271 break; 3271 break;
3272 case 1: 3272 case 1:
3273 -// tcg_gen_helper_1_1(do_mfc0_tracecontrol, cpu_T[0], cpu_T[0]); /* PDtrace support */ 3273 +// tcg_gen_helper_1_0(do_mfc0_tracecontrol, t0); /* PDtrace support */
3274 rn = "TraceControl"; 3274 rn = "TraceControl";
3275 // break; 3275 // break;
3276 case 2: 3276 case 2:
3277 -// tcg_gen_helper_1_1(do_mfc0_tracecontrol2, cpu_T[0], cpu_T[0]); /* PDtrace support */ 3277 +// tcg_gen_helper_1_0(do_mfc0_tracecontrol2, t0); /* PDtrace support */
3278 rn = "TraceControl2"; 3278 rn = "TraceControl2";
3279 // break; 3279 // break;
3280 case 3: 3280 case 3:
3281 -// tcg_gen_helper_1_1(do_mfc0_usertracedata, cpu_T[0], cpu_T[0]); /* PDtrace support */ 3281 +// tcg_gen_helper_1_0(do_mfc0_usertracedata, t0); /* PDtrace support */
3282 rn = "UserTraceData"; 3282 rn = "UserTraceData";
3283 // break; 3283 // break;
3284 case 4: 3284 case 4:
3285 -// tcg_gen_helper_1_1(do_mfc0_tracebpc, cpu_T[0], cpu_T[0]); /* PDtrace support */ 3285 +// tcg_gen_helper_1_0(do_mfc0_tracebpc, t0); /* PDtrace support */
3286 rn = "TraceBPC"; 3286 rn = "TraceBPC";
3287 // break; 3287 // break;
3288 default: 3288 default:
@@ -3293,8 +3293,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3293,8 +3293,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3293 switch (sel) { 3293 switch (sel) {
3294 case 0: 3294 case 0:
3295 /* EJTAG support */ 3295 /* EJTAG support */
3296 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));  
3297 - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); 3296 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
  3297 + tcg_gen_ext32s_tl(t0, t0);
3298 rn = "DEPC"; 3298 rn = "DEPC";
3299 break; 3299 break;
3300 default: 3300 default:
@@ -3304,35 +3304,35 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3304,35 +3304,35 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3304 case 25: 3304 case 25:
3305 switch (sel) { 3305 switch (sel) {
3306 case 0: 3306 case 0:
3307 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Performance0)); 3307 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
3308 rn = "Performance0"; 3308 rn = "Performance0";
3309 break; 3309 break;
3310 case 1: 3310 case 1:
3311 -// tcg_gen_helper_1_1(do_mfc0_performance1, cpu_T[0], cpu_T[0]); 3311 +// tcg_gen_helper_1_0(do_mfc0_performance1, t0);
3312 rn = "Performance1"; 3312 rn = "Performance1";
3313 // break; 3313 // break;
3314 case 2: 3314 case 2:
3315 -// tcg_gen_helper_1_1(do_mfc0_performance2, cpu_T[0], cpu_T[0]); 3315 +// tcg_gen_helper_1_0(do_mfc0_performance2, t0);
3316 rn = "Performance2"; 3316 rn = "Performance2";
3317 // break; 3317 // break;
3318 case 3: 3318 case 3:
3319 -// tcg_gen_helper_1_1(do_mfc0_performance3, cpu_T[0], cpu_T[0]); 3319 +// tcg_gen_helper_1_0(do_mfc0_performance3, t0);
3320 rn = "Performance3"; 3320 rn = "Performance3";
3321 // break; 3321 // break;
3322 case 4: 3322 case 4:
3323 -// tcg_gen_helper_1_1(do_mfc0_performance4, cpu_T[0], cpu_T[0]); 3323 +// tcg_gen_helper_1_0(do_mfc0_performance4, t0);
3324 rn = "Performance4"; 3324 rn = "Performance4";
3325 // break; 3325 // break;
3326 case 5: 3326 case 5:
3327 -// tcg_gen_helper_1_1(do_mfc0_performance5, cpu_T[0], cpu_T[0]); 3327 +// tcg_gen_helper_1_0(do_mfc0_performance5, t0);
3328 rn = "Performance5"; 3328 rn = "Performance5";
3329 // break; 3329 // break;
3330 case 6: 3330 case 6:
3331 -// tcg_gen_helper_1_1(do_mfc0_performance6, cpu_T[0], cpu_T[0]); 3331 +// tcg_gen_helper_1_0(do_mfc0_performance6, t0);
3332 rn = "Performance6"; 3332 rn = "Performance6";
3333 // break; 3333 // break;
3334 case 7: 3334 case 7:
3335 -// tcg_gen_helper_1_1(do_mfc0_performance7, cpu_T[0], cpu_T[0]); 3335 +// tcg_gen_helper_1_0(do_mfc0_performance7, t0);
3336 rn = "Performance7"; 3336 rn = "Performance7";
3337 // break; 3337 // break;
3338 default: 3338 default:
@@ -3358,14 +3358,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3358,14 +3358,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3358 case 2: 3358 case 2:
3359 case 4: 3359 case 4:
3360 case 6: 3360 case 6:
3361 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagLo)); 3361 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
3362 rn = "TagLo"; 3362 rn = "TagLo";
3363 break; 3363 break;
3364 case 1: 3364 case 1:
3365 case 3: 3365 case 3:
3366 case 5: 3366 case 5:
3367 case 7: 3367 case 7:
3368 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataLo)); 3368 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
3369 rn = "DataLo"; 3369 rn = "DataLo";
3370 break; 3370 break;
3371 default: 3371 default:
@@ -3378,14 +3378,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3378,14 +3378,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3378 case 2: 3378 case 2:
3379 case 4: 3379 case 4:
3380 case 6: 3380 case 6:
3381 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagHi)); 3381 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
3382 rn = "TagHi"; 3382 rn = "TagHi";
3383 break; 3383 break;
3384 case 1: 3384 case 1:
3385 case 3: 3385 case 3:
3386 case 5: 3386 case 5:
3387 case 7: 3387 case 7:
3388 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataHi)); 3388 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
3389 rn = "DataHi"; 3389 rn = "DataHi";
3390 break; 3390 break;
3391 default: 3391 default:
@@ -3395,8 +3395,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3395,8 +3395,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3395 case 30: 3395 case 30:
3396 switch (sel) { 3396 switch (sel) {
3397 case 0: 3397 case 0:
3398 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));  
3399 - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); 3398 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
  3399 + tcg_gen_ext32s_tl(t0, t0);
3400 rn = "ErrorEPC"; 3400 rn = "ErrorEPC";
3401 break; 3401 break;
3402 default: 3402 default:
@@ -3407,7 +3407,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3407,7 +3407,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3407 switch (sel) { 3407 switch (sel) {
3408 case 0: 3408 case 0:
3409 /* EJTAG support */ 3409 /* EJTAG support */
3410 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DESAVE)); 3410 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
3411 rn = "DESAVE"; 3411 rn = "DESAVE";
3412 break; 3412 break;
3413 default: 3413 default:
@@ -3435,7 +3435,7 @@ die: @@ -3435,7 +3435,7 @@ die:
3435 generate_exception(ctx, EXCP_RI); 3435 generate_exception(ctx, EXCP_RI);
3436 } 3436 }
3437 3437
3438 -static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) 3438 +static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
3439 { 3439 {
3440 const char *rn = "invalid"; 3440 const char *rn = "invalid";
3441 3441
@@ -3446,12 +3446,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3446,12 +3446,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3446 case 0: 3446 case 0:
3447 switch (sel) { 3447 switch (sel) {
3448 case 0: 3448 case 0:
3449 - tcg_gen_helper_0_1(do_mtc0_index, cpu_T[0]); 3449 + tcg_gen_helper_0_1(do_mtc0_index, t0);
3450 rn = "Index"; 3450 rn = "Index";
3451 break; 3451 break;
3452 case 1: 3452 case 1:
3453 check_insn(env, ctx, ASE_MT); 3453 check_insn(env, ctx, ASE_MT);
3454 - tcg_gen_helper_0_1(do_mtc0_mvpcontrol, cpu_T[0]); 3454 + tcg_gen_helper_0_1(do_mtc0_mvpcontrol, t0);
3455 rn = "MVPControl"; 3455 rn = "MVPControl";
3456 break; 3456 break;
3457 case 2: 3457 case 2:
@@ -3476,37 +3476,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3476,37 +3476,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3476 break; 3476 break;
3477 case 1: 3477 case 1:
3478 check_insn(env, ctx, ASE_MT); 3478 check_insn(env, ctx, ASE_MT);
3479 - tcg_gen_helper_0_1(do_mtc0_vpecontrol, cpu_T[0]); 3479 + tcg_gen_helper_0_1(do_mtc0_vpecontrol, t0);
3480 rn = "VPEControl"; 3480 rn = "VPEControl";
3481 break; 3481 break;
3482 case 2: 3482 case 2:
3483 check_insn(env, ctx, ASE_MT); 3483 check_insn(env, ctx, ASE_MT);
3484 - tcg_gen_helper_0_1(do_mtc0_vpeconf0, cpu_T[0]); 3484 + tcg_gen_helper_0_1(do_mtc0_vpeconf0, t0);
3485 rn = "VPEConf0"; 3485 rn = "VPEConf0";
3486 break; 3486 break;
3487 case 3: 3487 case 3:
3488 check_insn(env, ctx, ASE_MT); 3488 check_insn(env, ctx, ASE_MT);
3489 - tcg_gen_helper_0_1(do_mtc0_vpeconf1, cpu_T[0]); 3489 + tcg_gen_helper_0_1(do_mtc0_vpeconf1, t0);
3490 rn = "VPEConf1"; 3490 rn = "VPEConf1";
3491 break; 3491 break;
3492 case 4: 3492 case 4:
3493 check_insn(env, ctx, ASE_MT); 3493 check_insn(env, ctx, ASE_MT);
3494 - tcg_gen_helper_0_1(do_mtc0_yqmask, cpu_T[0]); 3494 + tcg_gen_helper_0_1(do_mtc0_yqmask, t0);
3495 rn = "YQMask"; 3495 rn = "YQMask";
3496 break; 3496 break;
3497 case 5: 3497 case 5:
3498 check_insn(env, ctx, ASE_MT); 3498 check_insn(env, ctx, ASE_MT);
3499 - gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_VPESchedule)); 3499 + gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPESchedule));
3500 rn = "VPESchedule"; 3500 rn = "VPESchedule";
3501 break; 3501 break;
3502 case 6: 3502 case 6:
3503 check_insn(env, ctx, ASE_MT); 3503 check_insn(env, ctx, ASE_MT);
3504 - gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_VPEScheFBack)); 3504 + gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPEScheFBack));
3505 rn = "VPEScheFBack"; 3505 rn = "VPEScheFBack";
3506 break; 3506 break;
3507 case 7: 3507 case 7:
3508 check_insn(env, ctx, ASE_MT); 3508 check_insn(env, ctx, ASE_MT);
3509 - tcg_gen_helper_0_1(do_mtc0_vpeopt, cpu_T[0]); 3509 + tcg_gen_helper_0_1(do_mtc0_vpeopt, t0);
3510 rn = "VPEOpt"; 3510 rn = "VPEOpt";
3511 break; 3511 break;
3512 default: 3512 default:
@@ -3516,42 +3516,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3516,42 +3516,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3516 case 2: 3516 case 2:
3517 switch (sel) { 3517 switch (sel) {
3518 case 0: 3518 case 0:
3519 - tcg_gen_helper_0_1(do_mtc0_entrylo0, cpu_T[0]); 3519 + tcg_gen_helper_0_1(do_mtc0_entrylo0, t0);
3520 rn = "EntryLo0"; 3520 rn = "EntryLo0";
3521 break; 3521 break;
3522 case 1: 3522 case 1:
3523 check_insn(env, ctx, ASE_MT); 3523 check_insn(env, ctx, ASE_MT);
3524 - tcg_gen_helper_0_1(do_mtc0_tcstatus, cpu_T[0]); 3524 + tcg_gen_helper_0_1(do_mtc0_tcstatus, t0);
3525 rn = "TCStatus"; 3525 rn = "TCStatus";
3526 break; 3526 break;
3527 case 2: 3527 case 2:
3528 check_insn(env, ctx, ASE_MT); 3528 check_insn(env, ctx, ASE_MT);
3529 - tcg_gen_helper_0_1(do_mtc0_tcbind, cpu_T[0]); 3529 + tcg_gen_helper_0_1(do_mtc0_tcbind, t0);
3530 rn = "TCBind"; 3530 rn = "TCBind";
3531 break; 3531 break;
3532 case 3: 3532 case 3:
3533 check_insn(env, ctx, ASE_MT); 3533 check_insn(env, ctx, ASE_MT);
3534 - tcg_gen_helper_0_1(do_mtc0_tcrestart, cpu_T[0]); 3534 + tcg_gen_helper_0_1(do_mtc0_tcrestart, t0);
3535 rn = "TCRestart"; 3535 rn = "TCRestart";
3536 break; 3536 break;
3537 case 4: 3537 case 4:
3538 check_insn(env, ctx, ASE_MT); 3538 check_insn(env, ctx, ASE_MT);
3539 - tcg_gen_helper_0_1(do_mtc0_tchalt, cpu_T[0]); 3539 + tcg_gen_helper_0_1(do_mtc0_tchalt, t0);
3540 rn = "TCHalt"; 3540 rn = "TCHalt";
3541 break; 3541 break;
3542 case 5: 3542 case 5:
3543 check_insn(env, ctx, ASE_MT); 3543 check_insn(env, ctx, ASE_MT);
3544 - tcg_gen_helper_0_1(do_mtc0_tccontext, cpu_T[0]); 3544 + tcg_gen_helper_0_1(do_mtc0_tccontext, t0);
3545 rn = "TCContext"; 3545 rn = "TCContext";
3546 break; 3546 break;
3547 case 6: 3547 case 6:
3548 check_insn(env, ctx, ASE_MT); 3548 check_insn(env, ctx, ASE_MT);
3549 - tcg_gen_helper_0_1(do_mtc0_tcschedule, cpu_T[0]); 3549 + tcg_gen_helper_0_1(do_mtc0_tcschedule, t0);
3550 rn = "TCSchedule"; 3550 rn = "TCSchedule";
3551 break; 3551 break;
3552 case 7: 3552 case 7:
3553 check_insn(env, ctx, ASE_MT); 3553 check_insn(env, ctx, ASE_MT);
3554 - tcg_gen_helper_0_1(do_mtc0_tcschefback, cpu_T[0]); 3554 + tcg_gen_helper_0_1(do_mtc0_tcschefback, t0);
3555 rn = "TCScheFBack"; 3555 rn = "TCScheFBack";
3556 break; 3556 break;
3557 default: 3557 default:
@@ -3561,7 +3561,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3561,7 +3561,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3561 case 3: 3561 case 3:
3562 switch (sel) { 3562 switch (sel) {
3563 case 0: 3563 case 0:
3564 - tcg_gen_helper_0_1(do_mtc0_entrylo1, cpu_T[0]); 3564 + tcg_gen_helper_0_1(do_mtc0_entrylo1, t0);
3565 rn = "EntryLo1"; 3565 rn = "EntryLo1";
3566 break; 3566 break;
3567 default: 3567 default:
@@ -3571,11 +3571,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3571,11 +3571,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3571 case 4: 3571 case 4:
3572 switch (sel) { 3572 switch (sel) {
3573 case 0: 3573 case 0:
3574 - tcg_gen_helper_0_1(do_mtc0_context, cpu_T[0]); 3574 + tcg_gen_helper_0_1(do_mtc0_context, t0);
3575 rn = "Context"; 3575 rn = "Context";
3576 break; 3576 break;
3577 case 1: 3577 case 1:
3578 -// tcg_gen_helper_0_1(do_mtc0_contextconfig, cpu_T[0]); /* SmartMIPS ASE */ 3578 +// tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
3579 rn = "ContextConfig"; 3579 rn = "ContextConfig";
3580 // break; 3580 // break;
3581 default: 3581 default:
@@ -3585,12 +3585,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3585,12 +3585,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3585 case 5: 3585 case 5:
3586 switch (sel) { 3586 switch (sel) {
3587 case 0: 3587 case 0:
3588 - tcg_gen_helper_0_1(do_mtc0_pagemask, cpu_T[0]); 3588 + tcg_gen_helper_0_1(do_mtc0_pagemask, t0);
3589 rn = "PageMask"; 3589 rn = "PageMask";
3590 break; 3590 break;
3591 case 1: 3591 case 1:
3592 check_insn(env, ctx, ISA_MIPS32R2); 3592 check_insn(env, ctx, ISA_MIPS32R2);
3593 - tcg_gen_helper_0_1(do_mtc0_pagegrain, cpu_T[0]); 3593 + tcg_gen_helper_0_1(do_mtc0_pagegrain, t0);
3594 rn = "PageGrain"; 3594 rn = "PageGrain";
3595 break; 3595 break;
3596 default: 3596 default:
@@ -3600,32 +3600,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3600,32 +3600,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3600 case 6: 3600 case 6:
3601 switch (sel) { 3601 switch (sel) {
3602 case 0: 3602 case 0:
3603 - tcg_gen_helper_0_1(do_mtc0_wired, cpu_T[0]); 3603 + tcg_gen_helper_0_1(do_mtc0_wired, t0);
3604 rn = "Wired"; 3604 rn = "Wired";
3605 break; 3605 break;
3606 case 1: 3606 case 1:
3607 check_insn(env, ctx, ISA_MIPS32R2); 3607 check_insn(env, ctx, ISA_MIPS32R2);
3608 - tcg_gen_helper_0_1(do_mtc0_srsconf0, cpu_T[0]); 3608 + tcg_gen_helper_0_1(do_mtc0_srsconf0, t0);
3609 rn = "SRSConf0"; 3609 rn = "SRSConf0";
3610 break; 3610 break;
3611 case 2: 3611 case 2:
3612 check_insn(env, ctx, ISA_MIPS32R2); 3612 check_insn(env, ctx, ISA_MIPS32R2);
3613 - tcg_gen_helper_0_1(do_mtc0_srsconf1, cpu_T[0]); 3613 + tcg_gen_helper_0_1(do_mtc0_srsconf1, t0);
3614 rn = "SRSConf1"; 3614 rn = "SRSConf1";
3615 break; 3615 break;
3616 case 3: 3616 case 3:
3617 check_insn(env, ctx, ISA_MIPS32R2); 3617 check_insn(env, ctx, ISA_MIPS32R2);
3618 - tcg_gen_helper_0_1(do_mtc0_srsconf2, cpu_T[0]); 3618 + tcg_gen_helper_0_1(do_mtc0_srsconf2, t0);
3619 rn = "SRSConf2"; 3619 rn = "SRSConf2";
3620 break; 3620 break;
3621 case 4: 3621 case 4:
3622 check_insn(env, ctx, ISA_MIPS32R2); 3622 check_insn(env, ctx, ISA_MIPS32R2);
3623 - tcg_gen_helper_0_1(do_mtc0_srsconf3, cpu_T[0]); 3623 + tcg_gen_helper_0_1(do_mtc0_srsconf3, t0);
3624 rn = "SRSConf3"; 3624 rn = "SRSConf3";
3625 break; 3625 break;
3626 case 5: 3626 case 5:
3627 check_insn(env, ctx, ISA_MIPS32R2); 3627 check_insn(env, ctx, ISA_MIPS32R2);
3628 - tcg_gen_helper_0_1(do_mtc0_srsconf4, cpu_T[0]); 3628 + tcg_gen_helper_0_1(do_mtc0_srsconf4, t0);
3629 rn = "SRSConf4"; 3629 rn = "SRSConf4";
3630 break; 3630 break;
3631 default: 3631 default:
@@ -3636,7 +3636,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3636,7 +3636,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3636 switch (sel) { 3636 switch (sel) {
3637 case 0: 3637 case 0:
3638 check_insn(env, ctx, ISA_MIPS32R2); 3638 check_insn(env, ctx, ISA_MIPS32R2);
3639 - tcg_gen_helper_0_1(do_mtc0_hwrena, cpu_T[0]); 3639 + tcg_gen_helper_0_1(do_mtc0_hwrena, t0);
3640 rn = "HWREna"; 3640 rn = "HWREna";
3641 break; 3641 break;
3642 default: 3642 default:
@@ -3650,7 +3650,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3650,7 +3650,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3650 case 9: 3650 case 9:
3651 switch (sel) { 3651 switch (sel) {
3652 case 0: 3652 case 0:
3653 - tcg_gen_helper_0_1(do_mtc0_count, cpu_T[0]); 3653 + tcg_gen_helper_0_1(do_mtc0_count, t0);
3654 rn = "Count"; 3654 rn = "Count";
3655 break; 3655 break;
3656 /* 6,7 are implementation dependent */ 3656 /* 6,7 are implementation dependent */
@@ -3663,7 +3663,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3663,7 +3663,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3663 case 10: 3663 case 10:
3664 switch (sel) { 3664 switch (sel) {
3665 case 0: 3665 case 0:
3666 - tcg_gen_helper_0_1(do_mtc0_entryhi, cpu_T[0]); 3666 + tcg_gen_helper_0_1(do_mtc0_entryhi, t0);
3667 rn = "EntryHi"; 3667 rn = "EntryHi";
3668 break; 3668 break;
3669 default: 3669 default:
@@ -3673,7 +3673,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3673,7 +3673,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3673 case 11: 3673 case 11:
3674 switch (sel) { 3674 switch (sel) {
3675 case 0: 3675 case 0:
3676 - tcg_gen_helper_0_1(do_mtc0_compare, cpu_T[0]); 3676 + tcg_gen_helper_0_1(do_mtc0_compare, t0);
3677 rn = "Compare"; 3677 rn = "Compare";
3678 break; 3678 break;
3679 /* 6,7 are implementation dependent */ 3679 /* 6,7 are implementation dependent */
@@ -3686,7 +3686,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3686,7 +3686,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3686 case 12: 3686 case 12:
3687 switch (sel) { 3687 switch (sel) {
3688 case 0: 3688 case 0:
3689 - tcg_gen_helper_0_1(do_mtc0_status, cpu_T[0]); 3689 + tcg_gen_helper_0_1(do_mtc0_status, t0);
3690 /* BS_STOP isn't good enough here, hflags may have changed. */ 3690 /* BS_STOP isn't good enough here, hflags may have changed. */
3691 gen_save_pc(ctx->pc + 4); 3691 gen_save_pc(ctx->pc + 4);
3692 ctx->bstate = BS_EXCP; 3692 ctx->bstate = BS_EXCP;
@@ -3694,21 +3694,21 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3694,21 +3694,21 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3694 break; 3694 break;
3695 case 1: 3695 case 1:
3696 check_insn(env, ctx, ISA_MIPS32R2); 3696 check_insn(env, ctx, ISA_MIPS32R2);
3697 - tcg_gen_helper_0_1(do_mtc0_intctl, cpu_T[0]); 3697 + tcg_gen_helper_0_1(do_mtc0_intctl, t0);
3698 /* Stop translation as we may have switched the execution mode */ 3698 /* Stop translation as we may have switched the execution mode */
3699 ctx->bstate = BS_STOP; 3699 ctx->bstate = BS_STOP;
3700 rn = "IntCtl"; 3700 rn = "IntCtl";
3701 break; 3701 break;
3702 case 2: 3702 case 2:
3703 check_insn(env, ctx, ISA_MIPS32R2); 3703 check_insn(env, ctx, ISA_MIPS32R2);
3704 - tcg_gen_helper_0_1(do_mtc0_srsctl, cpu_T[0]); 3704 + tcg_gen_helper_0_1(do_mtc0_srsctl, t0);
3705 /* Stop translation as we may have switched the execution mode */ 3705 /* Stop translation as we may have switched the execution mode */
3706 ctx->bstate = BS_STOP; 3706 ctx->bstate = BS_STOP;
3707 rn = "SRSCtl"; 3707 rn = "SRSCtl";
3708 break; 3708 break;
3709 case 3: 3709 case 3:
3710 check_insn(env, ctx, ISA_MIPS32R2); 3710 check_insn(env, ctx, ISA_MIPS32R2);
3711 - gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_SRSMap)); 3711 + gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
3712 /* Stop translation as we may have switched the execution mode */ 3712 /* Stop translation as we may have switched the execution mode */
3713 ctx->bstate = BS_STOP; 3713 ctx->bstate = BS_STOP;
3714 rn = "SRSMap"; 3714 rn = "SRSMap";
@@ -3720,7 +3720,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3720,7 +3720,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3720 case 13: 3720 case 13:
3721 switch (sel) { 3721 switch (sel) {
3722 case 0: 3722 case 0:
3723 - tcg_gen_helper_0_1(do_mtc0_cause, cpu_T[0]); 3723 + tcg_gen_helper_0_1(do_mtc0_cause, t0);
3724 rn = "Cause"; 3724 rn = "Cause";
3725 break; 3725 break;
3726 default: 3726 default:
@@ -3732,7 +3732,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3732,7 +3732,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3732 case 14: 3732 case 14:
3733 switch (sel) { 3733 switch (sel) {
3734 case 0: 3734 case 0:
3735 - gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_EPC)); 3735 + gen_mtc0_store64(t0, offsetof(CPUState, CP0_EPC));
3736 rn = "EPC"; 3736 rn = "EPC";
3737 break; 3737 break;
3738 default: 3738 default:
@@ -3747,7 +3747,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3747,7 +3747,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3747 break; 3747 break;
3748 case 1: 3748 case 1:
3749 check_insn(env, ctx, ISA_MIPS32R2); 3749 check_insn(env, ctx, ISA_MIPS32R2);
3750 - tcg_gen_helper_0_1(do_mtc0_ebase, cpu_T[0]); 3750 + tcg_gen_helper_0_1(do_mtc0_ebase, t0);
3751 rn = "EBase"; 3751 rn = "EBase";
3752 break; 3752 break;
3753 default: 3753 default:
@@ -3757,7 +3757,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3757,7 +3757,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3757 case 16: 3757 case 16:
3758 switch (sel) { 3758 switch (sel) {
3759 case 0: 3759 case 0:
3760 - tcg_gen_helper_0_1(do_mtc0_config0, cpu_T[0]); 3760 + tcg_gen_helper_0_1(do_mtc0_config0, t0);
3761 rn = "Config"; 3761 rn = "Config";
3762 /* Stop translation as we may have switched the execution mode */ 3762 /* Stop translation as we may have switched the execution mode */
3763 ctx->bstate = BS_STOP; 3763 ctx->bstate = BS_STOP;
@@ -3767,7 +3767,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3767,7 +3767,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3767 rn = "Config1"; 3767 rn = "Config1";
3768 break; 3768 break;
3769 case 2: 3769 case 2:
3770 - tcg_gen_helper_0_1(do_mtc0_config2, cpu_T[0]); 3770 + tcg_gen_helper_0_1(do_mtc0_config2, t0);
3771 rn = "Config2"; 3771 rn = "Config2";
3772 /* Stop translation as we may have switched the execution mode */ 3772 /* Stop translation as we may have switched the execution mode */
3773 ctx->bstate = BS_STOP; 3773 ctx->bstate = BS_STOP;
@@ -3804,7 +3804,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3804,7 +3804,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3804 case 18: 3804 case 18:
3805 switch (sel) { 3805 switch (sel) {
3806 case 0 ... 7: 3806 case 0 ... 7:
3807 - tcg_gen_helper_0_1i(do_mtc0_watchlo, cpu_T[0], sel); 3807 + tcg_gen_helper_0_1i(do_mtc0_watchlo, t0, sel);
3808 rn = "WatchLo"; 3808 rn = "WatchLo";
3809 break; 3809 break;
3810 default: 3810 default:
@@ -3814,7 +3814,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3814,7 +3814,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3814 case 19: 3814 case 19:
3815 switch (sel) { 3815 switch (sel) {
3816 case 0 ... 7: 3816 case 0 ... 7:
3817 - tcg_gen_helper_0_1i(do_mtc0_watchhi, cpu_T[0], sel); 3817 + tcg_gen_helper_0_1i(do_mtc0_watchhi, t0, sel);
3818 rn = "WatchHi"; 3818 rn = "WatchHi";
3819 break; 3819 break;
3820 default: 3820 default:
@@ -3826,7 +3826,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3826,7 +3826,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3826 case 0: 3826 case 0:
3827 #if defined(TARGET_MIPS64) 3827 #if defined(TARGET_MIPS64)
3828 check_insn(env, ctx, ISA_MIPS3); 3828 check_insn(env, ctx, ISA_MIPS3);
3829 - tcg_gen_helper_0_1(do_mtc0_xcontext, cpu_T[0]); 3829 + tcg_gen_helper_0_1(do_mtc0_xcontext, t0);
3830 rn = "XContext"; 3830 rn = "XContext";
3831 break; 3831 break;
3832 #endif 3832 #endif
@@ -3838,7 +3838,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3838,7 +3838,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3838 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 3838 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3839 switch (sel) { 3839 switch (sel) {
3840 case 0: 3840 case 0:
3841 - tcg_gen_helper_0_1(do_mtc0_framemask, cpu_T[0]); 3841 + tcg_gen_helper_0_1(do_mtc0_framemask, t0);
3842 rn = "Framemask"; 3842 rn = "Framemask";
3843 break; 3843 break;
3844 default: 3844 default:
@@ -3852,20 +3852,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3852,20 +3852,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3852 case 23: 3852 case 23:
3853 switch (sel) { 3853 switch (sel) {
3854 case 0: 3854 case 0:
3855 - tcg_gen_helper_0_1(do_mtc0_debug, cpu_T[0]); /* EJTAG support */ 3855 + tcg_gen_helper_0_1(do_mtc0_debug, t0); /* EJTAG support */
3856 /* BS_STOP isn't good enough here, hflags may have changed. */ 3856 /* BS_STOP isn't good enough here, hflags may have changed. */
3857 gen_save_pc(ctx->pc + 4); 3857 gen_save_pc(ctx->pc + 4);
3858 ctx->bstate = BS_EXCP; 3858 ctx->bstate = BS_EXCP;
3859 rn = "Debug"; 3859 rn = "Debug";
3860 break; 3860 break;
3861 case 1: 3861 case 1:
3862 -// tcg_gen_helper_0_1(do_mtc0_tracecontrol, cpu_T[0]); /* PDtrace support */ 3862 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
3863 rn = "TraceControl"; 3863 rn = "TraceControl";
3864 /* Stop translation as we may have switched the execution mode */ 3864 /* Stop translation as we may have switched the execution mode */
3865 ctx->bstate = BS_STOP; 3865 ctx->bstate = BS_STOP;
3866 // break; 3866 // break;
3867 case 2: 3867 case 2:
3868 -// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, cpu_T[0]); /* PDtrace support */ 3868 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
3869 rn = "TraceControl2"; 3869 rn = "TraceControl2";
3870 /* Stop translation as we may have switched the execution mode */ 3870 /* Stop translation as we may have switched the execution mode */
3871 ctx->bstate = BS_STOP; 3871 ctx->bstate = BS_STOP;
@@ -3873,13 +3873,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3873,13 +3873,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3873 case 3: 3873 case 3:
3874 /* Stop translation as we may have switched the execution mode */ 3874 /* Stop translation as we may have switched the execution mode */
3875 ctx->bstate = BS_STOP; 3875 ctx->bstate = BS_STOP;
3876 -// tcg_gen_helper_0_1(do_mtc0_usertracedata, cpu_T[0]); /* PDtrace support */ 3876 +// tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
3877 rn = "UserTraceData"; 3877 rn = "UserTraceData";
3878 /* Stop translation as we may have switched the execution mode */ 3878 /* Stop translation as we may have switched the execution mode */
3879 ctx->bstate = BS_STOP; 3879 ctx->bstate = BS_STOP;
3880 // break; 3880 // break;
3881 case 4: 3881 case 4:
3882 -// tcg_gen_helper_0_1(do_mtc0_tracebpc, cpu_T[0]); /* PDtrace support */ 3882 +// tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
3883 /* Stop translation as we may have switched the execution mode */ 3883 /* Stop translation as we may have switched the execution mode */
3884 ctx->bstate = BS_STOP; 3884 ctx->bstate = BS_STOP;
3885 rn = "TraceBPC"; 3885 rn = "TraceBPC";
@@ -3892,7 +3892,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3892,7 +3892,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3892 switch (sel) { 3892 switch (sel) {
3893 case 0: 3893 case 0:
3894 /* EJTAG support */ 3894 /* EJTAG support */
3895 - gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_DEPC)); 3895 + gen_mtc0_store64(t0, offsetof(CPUState, CP0_DEPC));
3896 rn = "DEPC"; 3896 rn = "DEPC";
3897 break; 3897 break;
3898 default: 3898 default:
@@ -3902,35 +3902,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3902,35 +3902,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3902 case 25: 3902 case 25:
3903 switch (sel) { 3903 switch (sel) {
3904 case 0: 3904 case 0:
3905 - tcg_gen_helper_0_1(do_mtc0_performance0, cpu_T[0]); 3905 + tcg_gen_helper_0_1(do_mtc0_performance0, t0);
3906 rn = "Performance0"; 3906 rn = "Performance0";
3907 break; 3907 break;
3908 case 1: 3908 case 1:
3909 -// tcg_gen_helper_0_1(do_mtc0_performance1, cpu_T[0]); 3909 +// tcg_gen_helper_0_1(do_mtc0_performance1, t0);
3910 rn = "Performance1"; 3910 rn = "Performance1";
3911 // break; 3911 // break;
3912 case 2: 3912 case 2:
3913 -// tcg_gen_helper_0_1(do_mtc0_performance2, cpu_T[0]); 3913 +// tcg_gen_helper_0_1(do_mtc0_performance2, t0);
3914 rn = "Performance2"; 3914 rn = "Performance2";
3915 // break; 3915 // break;
3916 case 3: 3916 case 3:
3917 -// tcg_gen_helper_0_1(do_mtc0_performance3, cpu_T[0]); 3917 +// tcg_gen_helper_0_1(do_mtc0_performance3, t0);
3918 rn = "Performance3"; 3918 rn = "Performance3";
3919 // break; 3919 // break;
3920 case 4: 3920 case 4:
3921 -// tcg_gen_helper_0_1(do_mtc0_performance4, cpu_T[0]); 3921 +// tcg_gen_helper_0_1(do_mtc0_performance4, t0);
3922 rn = "Performance4"; 3922 rn = "Performance4";
3923 // break; 3923 // break;
3924 case 5: 3924 case 5:
3925 -// tcg_gen_helper_0_1(do_mtc0_performance5, cpu_T[0]); 3925 +// tcg_gen_helper_0_1(do_mtc0_performance5, t0);
3926 rn = "Performance5"; 3926 rn = "Performance5";
3927 // break; 3927 // break;
3928 case 6: 3928 case 6:
3929 -// tcg_gen_helper_0_1(do_mtc0_performance6, cpu_T[0]); 3929 +// tcg_gen_helper_0_1(do_mtc0_performance6, t0);
3930 rn = "Performance6"; 3930 rn = "Performance6";
3931 // break; 3931 // break;
3932 case 7: 3932 case 7:
3933 -// tcg_gen_helper_0_1(do_mtc0_performance7, cpu_T[0]); 3933 +// tcg_gen_helper_0_1(do_mtc0_performance7, t0);
3934 rn = "Performance7"; 3934 rn = "Performance7";
3935 // break; 3935 // break;
3936 default: 3936 default:
@@ -3957,14 +3957,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3957,14 +3957,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3957 case 2: 3957 case 2:
3958 case 4: 3958 case 4:
3959 case 6: 3959 case 6:
3960 - tcg_gen_helper_0_1(do_mtc0_taglo, cpu_T[0]); 3960 + tcg_gen_helper_0_1(do_mtc0_taglo, t0);
3961 rn = "TagLo"; 3961 rn = "TagLo";
3962 break; 3962 break;
3963 case 1: 3963 case 1:
3964 case 3: 3964 case 3:
3965 case 5: 3965 case 5:
3966 case 7: 3966 case 7:
3967 - tcg_gen_helper_0_1(do_mtc0_datalo, cpu_T[0]); 3967 + tcg_gen_helper_0_1(do_mtc0_datalo, t0);
3968 rn = "DataLo"; 3968 rn = "DataLo";
3969 break; 3969 break;
3970 default: 3970 default:
@@ -3977,14 +3977,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3977,14 +3977,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3977 case 2: 3977 case 2:
3978 case 4: 3978 case 4:
3979 case 6: 3979 case 6:
3980 - tcg_gen_helper_0_1(do_mtc0_taghi, cpu_T[0]); 3980 + tcg_gen_helper_0_1(do_mtc0_taghi, t0);
3981 rn = "TagHi"; 3981 rn = "TagHi";
3982 break; 3982 break;
3983 case 1: 3983 case 1:
3984 case 3: 3984 case 3:
3985 case 5: 3985 case 5:
3986 case 7: 3986 case 7:
3987 - tcg_gen_helper_0_1(do_mtc0_datahi, cpu_T[0]); 3987 + tcg_gen_helper_0_1(do_mtc0_datahi, t0);
3988 rn = "DataHi"; 3988 rn = "DataHi";
3989 break; 3989 break;
3990 default: 3990 default:
@@ -3995,7 +3995,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3995,7 +3995,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3995 case 30: 3995 case 30:
3996 switch (sel) { 3996 switch (sel) {
3997 case 0: 3997 case 0:
3998 - gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_ErrorEPC)); 3998 + gen_mtc0_store64(t0, offsetof(CPUState, CP0_ErrorEPC));
3999 rn = "ErrorEPC"; 3999 rn = "ErrorEPC";
4000 break; 4000 break;
4001 default: 4001 default:
@@ -4006,7 +4006,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4006,7 +4006,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4006 switch (sel) { 4006 switch (sel) {
4007 case 0: 4007 case 0:
4008 /* EJTAG support */ 4008 /* EJTAG support */
4009 - gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_DESAVE)); 4009 + gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
4010 rn = "DESAVE"; 4010 rn = "DESAVE";
4011 break; 4011 break;
4012 default: 4012 default:
@@ -4037,7 +4037,7 @@ die: @@ -4037,7 +4037,7 @@ die:
4037 } 4037 }
4038 4038
4039 #if defined(TARGET_MIPS64) 4039 #if defined(TARGET_MIPS64)
4040 -static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) 4040 +static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
4041 { 4041 {
4042 const char *rn = "invalid"; 4042 const char *rn = "invalid";
4043 4043
@@ -4048,22 +4048,22 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4048,22 +4048,22 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4048 case 0: 4048 case 0:
4049 switch (sel) { 4049 switch (sel) {
4050 case 0: 4050 case 0:
4051 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Index)); 4051 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
4052 rn = "Index"; 4052 rn = "Index";
4053 break; 4053 break;
4054 case 1: 4054 case 1:
4055 check_insn(env, ctx, ASE_MT); 4055 check_insn(env, ctx, ASE_MT);
4056 - tcg_gen_helper_1_1(do_mfc0_mvpcontrol, cpu_T[0], cpu_T[0]); 4056 + tcg_gen_helper_1_0(do_mfc0_mvpcontrol, t0);
4057 rn = "MVPControl"; 4057 rn = "MVPControl";
4058 break; 4058 break;
4059 case 2: 4059 case 2:
4060 check_insn(env, ctx, ASE_MT); 4060 check_insn(env, ctx, ASE_MT);
4061 - tcg_gen_helper_1_1(do_mfc0_mvpconf0, cpu_T[0], cpu_T[0]); 4061 + tcg_gen_helper_1_0(do_mfc0_mvpconf0, t0);
4062 rn = "MVPConf0"; 4062 rn = "MVPConf0";
4063 break; 4063 break;
4064 case 3: 4064 case 3:
4065 check_insn(env, ctx, ASE_MT); 4065 check_insn(env, ctx, ASE_MT);
4066 - tcg_gen_helper_1_1(do_mfc0_mvpconf1, cpu_T[0], cpu_T[0]); 4066 + tcg_gen_helper_1_0(do_mfc0_mvpconf1, t0);
4067 rn = "MVPConf1"; 4067 rn = "MVPConf1";
4068 break; 4068 break;
4069 default: 4069 default:
@@ -4073,42 +4073,42 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4073,42 +4073,42 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4073 case 1: 4073 case 1:
4074 switch (sel) { 4074 switch (sel) {
4075 case 0: 4075 case 0:
4076 - tcg_gen_helper_1_1(do_mfc0_random, cpu_T[0], cpu_T[0]); 4076 + tcg_gen_helper_1_0(do_mfc0_random, t0);
4077 rn = "Random"; 4077 rn = "Random";
4078 break; 4078 break;
4079 case 1: 4079 case 1:
4080 check_insn(env, ctx, ASE_MT); 4080 check_insn(env, ctx, ASE_MT);
4081 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEControl)); 4081 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
4082 rn = "VPEControl"; 4082 rn = "VPEControl";
4083 break; 4083 break;
4084 case 2: 4084 case 2:
4085 check_insn(env, ctx, ASE_MT); 4085 check_insn(env, ctx, ASE_MT);
4086 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf0)); 4086 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
4087 rn = "VPEConf0"; 4087 rn = "VPEConf0";
4088 break; 4088 break;
4089 case 3: 4089 case 3:
4090 check_insn(env, ctx, ASE_MT); 4090 check_insn(env, ctx, ASE_MT);
4091 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf1)); 4091 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
4092 rn = "VPEConf1"; 4092 rn = "VPEConf1";
4093 break; 4093 break;
4094 case 4: 4094 case 4:
4095 check_insn(env, ctx, ASE_MT); 4095 check_insn(env, ctx, ASE_MT);
4096 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_YQMask)); 4096 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_YQMask));
4097 rn = "YQMask"; 4097 rn = "YQMask";
4098 break; 4098 break;
4099 case 5: 4099 case 5:
4100 check_insn(env, ctx, ASE_MT); 4100 check_insn(env, ctx, ASE_MT);
4101 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule)); 4101 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4102 rn = "VPESchedule"; 4102 rn = "VPESchedule";
4103 break; 4103 break;
4104 case 6: 4104 case 6:
4105 check_insn(env, ctx, ASE_MT); 4105 check_insn(env, ctx, ASE_MT);
4106 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack)); 4106 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4107 rn = "VPEScheFBack"; 4107 rn = "VPEScheFBack";
4108 break; 4108 break;
4109 case 7: 4109 case 7:
4110 check_insn(env, ctx, ASE_MT); 4110 check_insn(env, ctx, ASE_MT);
4111 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEOpt)); 4111 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
4112 rn = "VPEOpt"; 4112 rn = "VPEOpt";
4113 break; 4113 break;
4114 default: 4114 default:
@@ -4118,42 +4118,42 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4118,42 +4118,42 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4118 case 2: 4118 case 2:
4119 switch (sel) { 4119 switch (sel) {
4120 case 0: 4120 case 0:
4121 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0)); 4121 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
4122 rn = "EntryLo0"; 4122 rn = "EntryLo0";
4123 break; 4123 break;
4124 case 1: 4124 case 1:
4125 check_insn(env, ctx, ASE_MT); 4125 check_insn(env, ctx, ASE_MT);
4126 - tcg_gen_helper_1_1(do_mfc0_tcstatus, cpu_T[0], cpu_T[0]); 4126 + tcg_gen_helper_1_0(do_mfc0_tcstatus, t0);
4127 rn = "TCStatus"; 4127 rn = "TCStatus";
4128 break; 4128 break;
4129 case 2: 4129 case 2:
4130 check_insn(env, ctx, ASE_MT); 4130 check_insn(env, ctx, ASE_MT);
4131 - tcg_gen_helper_1_1(do_mfc0_tcbind, cpu_T[0], cpu_T[0]); 4131 + tcg_gen_helper_1_0(do_mfc0_tcbind, t0);
4132 rn = "TCBind"; 4132 rn = "TCBind";
4133 break; 4133 break;
4134 case 3: 4134 case 3:
4135 check_insn(env, ctx, ASE_MT); 4135 check_insn(env, ctx, ASE_MT);
4136 - tcg_gen_helper_1_1(do_dmfc0_tcrestart, cpu_T[0], cpu_T[0]); 4136 + tcg_gen_helper_1_0(do_dmfc0_tcrestart, t0);
4137 rn = "TCRestart"; 4137 rn = "TCRestart";
4138 break; 4138 break;
4139 case 4: 4139 case 4:
4140 check_insn(env, ctx, ASE_MT); 4140 check_insn(env, ctx, ASE_MT);
4141 - tcg_gen_helper_1_1(do_dmfc0_tchalt, cpu_T[0], cpu_T[0]); 4141 + tcg_gen_helper_1_0(do_dmfc0_tchalt, t0);
4142 rn = "TCHalt"; 4142 rn = "TCHalt";
4143 break; 4143 break;
4144 case 5: 4144 case 5:
4145 check_insn(env, ctx, ASE_MT); 4145 check_insn(env, ctx, ASE_MT);
4146 - tcg_gen_helper_1_1(do_dmfc0_tccontext, cpu_T[0], cpu_T[0]); 4146 + tcg_gen_helper_1_0(do_dmfc0_tccontext, t0);
4147 rn = "TCContext"; 4147 rn = "TCContext";
4148 break; 4148 break;
4149 case 6: 4149 case 6:
4150 check_insn(env, ctx, ASE_MT); 4150 check_insn(env, ctx, ASE_MT);
4151 - tcg_gen_helper_1_1(do_dmfc0_tcschedule, cpu_T[0], cpu_T[0]); 4151 + tcg_gen_helper_1_0(do_dmfc0_tcschedule, t0);
4152 rn = "TCSchedule"; 4152 rn = "TCSchedule";
4153 break; 4153 break;
4154 case 7: 4154 case 7:
4155 check_insn(env, ctx, ASE_MT); 4155 check_insn(env, ctx, ASE_MT);
4156 - tcg_gen_helper_1_1(do_dmfc0_tcschefback, cpu_T[0], cpu_T[0]); 4156 + tcg_gen_helper_1_0(do_dmfc0_tcschefback, t0);
4157 rn = "TCScheFBack"; 4157 rn = "TCScheFBack";
4158 break; 4158 break;
4159 default: 4159 default:
@@ -4163,7 +4163,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4163,7 +4163,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4163 case 3: 4163 case 3:
4164 switch (sel) { 4164 switch (sel) {
4165 case 0: 4165 case 0:
4166 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1)); 4166 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
4167 rn = "EntryLo1"; 4167 rn = "EntryLo1";
4168 break; 4168 break;
4169 default: 4169 default:
@@ -4173,11 +4173,11 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4173,11 +4173,11 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4173 case 4: 4173 case 4:
4174 switch (sel) { 4174 switch (sel) {
4175 case 0: 4175 case 0:
4176 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context)); 4176 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
4177 rn = "Context"; 4177 rn = "Context";
4178 break; 4178 break;
4179 case 1: 4179 case 1:
4180 -// tcg_gen_helper_1_1(do_dmfc0_contextconfig, cpu_T[0], cpu_T[0]); /* SmartMIPS ASE */ 4180 +// tcg_gen_helper_1_0(do_dmfc0_contextconfig, t0); /* SmartMIPS ASE */
4181 rn = "ContextConfig"; 4181 rn = "ContextConfig";
4182 // break; 4182 // break;
4183 default: 4183 default:
@@ -4187,12 +4187,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4187,12 +4187,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4187 case 5: 4187 case 5:
4188 switch (sel) { 4188 switch (sel) {
4189 case 0: 4189 case 0:
4190 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageMask)); 4190 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
4191 rn = "PageMask"; 4191 rn = "PageMask";
4192 break; 4192 break;
4193 case 1: 4193 case 1:
4194 check_insn(env, ctx, ISA_MIPS32R2); 4194 check_insn(env, ctx, ISA_MIPS32R2);
4195 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageGrain)); 4195 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
4196 rn = "PageGrain"; 4196 rn = "PageGrain";
4197 break; 4197 break;
4198 default: 4198 default:
@@ -4202,32 +4202,32 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4202,32 +4202,32 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4202 case 6: 4202 case 6:
4203 switch (sel) { 4203 switch (sel) {
4204 case 0: 4204 case 0:
4205 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Wired)); 4205 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
4206 rn = "Wired"; 4206 rn = "Wired";
4207 break; 4207 break;
4208 case 1: 4208 case 1:
4209 check_insn(env, ctx, ISA_MIPS32R2); 4209 check_insn(env, ctx, ISA_MIPS32R2);
4210 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf0)); 4210 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
4211 rn = "SRSConf0"; 4211 rn = "SRSConf0";
4212 break; 4212 break;
4213 case 2: 4213 case 2:
4214 check_insn(env, ctx, ISA_MIPS32R2); 4214 check_insn(env, ctx, ISA_MIPS32R2);
4215 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf1)); 4215 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
4216 rn = "SRSConf1"; 4216 rn = "SRSConf1";
4217 break; 4217 break;
4218 case 3: 4218 case 3:
4219 check_insn(env, ctx, ISA_MIPS32R2); 4219 check_insn(env, ctx, ISA_MIPS32R2);
4220 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf2)); 4220 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
4221 rn = "SRSConf2"; 4221 rn = "SRSConf2";
4222 break; 4222 break;
4223 case 4: 4223 case 4:
4224 check_insn(env, ctx, ISA_MIPS32R2); 4224 check_insn(env, ctx, ISA_MIPS32R2);
4225 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf3)); 4225 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
4226 rn = "SRSConf3"; 4226 rn = "SRSConf3";
4227 break; 4227 break;
4228 case 5: 4228 case 5:
4229 check_insn(env, ctx, ISA_MIPS32R2); 4229 check_insn(env, ctx, ISA_MIPS32R2);
4230 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf4)); 4230 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
4231 rn = "SRSConf4"; 4231 rn = "SRSConf4";
4232 break; 4232 break;
4233 default: 4233 default:
@@ -4238,7 +4238,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4238,7 +4238,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4238 switch (sel) { 4238 switch (sel) {
4239 case 0: 4239 case 0:
4240 check_insn(env, ctx, ISA_MIPS32R2); 4240 check_insn(env, ctx, ISA_MIPS32R2);
4241 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_HWREna)); 4241 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
4242 rn = "HWREna"; 4242 rn = "HWREna";
4243 break; 4243 break;
4244 default: 4244 default:
@@ -4248,7 +4248,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4248,7 +4248,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4248 case 8: 4248 case 8:
4249 switch (sel) { 4249 switch (sel) {
4250 case 0: 4250 case 0:
4251 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr)); 4251 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
4252 rn = "BadVAddr"; 4252 rn = "BadVAddr";
4253 break; 4253 break;
4254 default: 4254 default:
@@ -4258,7 +4258,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4258,7 +4258,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4258 case 9: 4258 case 9:
4259 switch (sel) { 4259 switch (sel) {
4260 case 0: 4260 case 0:
4261 - tcg_gen_helper_1_1(do_mfc0_count, cpu_T[0], cpu_T[0]); 4261 + tcg_gen_helper_1_0(do_mfc0_count, t0);
4262 rn = "Count"; 4262 rn = "Count";
4263 break; 4263 break;
4264 /* 6,7 are implementation dependent */ 4264 /* 6,7 are implementation dependent */
@@ -4269,7 +4269,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4269,7 +4269,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4269 case 10: 4269 case 10:
4270 switch (sel) { 4270 switch (sel) {
4271 case 0: 4271 case 0:
4272 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi)); 4272 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
4273 rn = "EntryHi"; 4273 rn = "EntryHi";
4274 break; 4274 break;
4275 default: 4275 default:
@@ -4279,7 +4279,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4279,7 +4279,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4279 case 11: 4279 case 11:
4280 switch (sel) { 4280 switch (sel) {
4281 case 0: 4281 case 0:
4282 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Compare)); 4282 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
4283 rn = "Compare"; 4283 rn = "Compare";
4284 break; 4284 break;
4285 /* 6,7 are implementation dependent */ 4285 /* 6,7 are implementation dependent */
@@ -4290,22 +4290,22 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4290,22 +4290,22 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4290 case 12: 4290 case 12:
4291 switch (sel) { 4291 switch (sel) {
4292 case 0: 4292 case 0:
4293 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Status)); 4293 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
4294 rn = "Status"; 4294 rn = "Status";
4295 break; 4295 break;
4296 case 1: 4296 case 1:
4297 check_insn(env, ctx, ISA_MIPS32R2); 4297 check_insn(env, ctx, ISA_MIPS32R2);
4298 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_IntCtl)); 4298 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
4299 rn = "IntCtl"; 4299 rn = "IntCtl";
4300 break; 4300 break;
4301 case 2: 4301 case 2:
4302 check_insn(env, ctx, ISA_MIPS32R2); 4302 check_insn(env, ctx, ISA_MIPS32R2);
4303 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSCtl)); 4303 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
4304 rn = "SRSCtl"; 4304 rn = "SRSCtl";
4305 break; 4305 break;
4306 case 3: 4306 case 3:
4307 check_insn(env, ctx, ISA_MIPS32R2); 4307 check_insn(env, ctx, ISA_MIPS32R2);
4308 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSMap)); 4308 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
4309 rn = "SRSMap"; 4309 rn = "SRSMap";
4310 break; 4310 break;
4311 default: 4311 default:
@@ -4315,7 +4315,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4315,7 +4315,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4315 case 13: 4315 case 13:
4316 switch (sel) { 4316 switch (sel) {
4317 case 0: 4317 case 0:
4318 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Cause)); 4318 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
4319 rn = "Cause"; 4319 rn = "Cause";
4320 break; 4320 break;
4321 default: 4321 default:
@@ -4325,7 +4325,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4325,7 +4325,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4325 case 14: 4325 case 14:
4326 switch (sel) { 4326 switch (sel) {
4327 case 0: 4327 case 0:
4328 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC)); 4328 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
4329 rn = "EPC"; 4329 rn = "EPC";
4330 break; 4330 break;
4331 default: 4331 default:
@@ -4335,12 +4335,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4335,12 +4335,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4335 case 15: 4335 case 15:
4336 switch (sel) { 4336 switch (sel) {
4337 case 0: 4337 case 0:
4338 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PRid)); 4338 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
4339 rn = "PRid"; 4339 rn = "PRid";
4340 break; 4340 break;
4341 case 1: 4341 case 1:
4342 check_insn(env, ctx, ISA_MIPS32R2); 4342 check_insn(env, ctx, ISA_MIPS32R2);
4343 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_EBase)); 4343 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
4344 rn = "EBase"; 4344 rn = "EBase";
4345 break; 4345 break;
4346 default: 4346 default:
@@ -4350,28 +4350,28 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4350,28 +4350,28 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4350 case 16: 4350 case 16:
4351 switch (sel) { 4351 switch (sel) {
4352 case 0: 4352 case 0:
4353 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config0)); 4353 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
4354 rn = "Config"; 4354 rn = "Config";
4355 break; 4355 break;
4356 case 1: 4356 case 1:
4357 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config1)); 4357 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
4358 rn = "Config1"; 4358 rn = "Config1";
4359 break; 4359 break;
4360 case 2: 4360 case 2:
4361 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config2)); 4361 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
4362 rn = "Config2"; 4362 rn = "Config2";
4363 break; 4363 break;
4364 case 3: 4364 case 3:
4365 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config3)); 4365 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
4366 rn = "Config3"; 4366 rn = "Config3";
4367 break; 4367 break;
4368 /* 6,7 are implementation dependent */ 4368 /* 6,7 are implementation dependent */
4369 case 6: 4369 case 6:
4370 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config6)); 4370 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
4371 rn = "Config6"; 4371 rn = "Config6";
4372 break; 4372 break;
4373 case 7: 4373 case 7:
4374 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config7)); 4374 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
4375 rn = "Config7"; 4375 rn = "Config7";
4376 break; 4376 break;
4377 default: 4377 default:
@@ -4381,7 +4381,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4381,7 +4381,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4381 case 17: 4381 case 17:
4382 switch (sel) { 4382 switch (sel) {
4383 case 0: 4383 case 0:
4384 - tcg_gen_helper_1_1(do_dmfc0_lladdr, cpu_T[0], cpu_T[0]); 4384 + tcg_gen_helper_1_0(do_dmfc0_lladdr, t0);
4385 rn = "LLAddr"; 4385 rn = "LLAddr";
4386 break; 4386 break;
4387 default: 4387 default:
@@ -4391,7 +4391,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4391,7 +4391,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4391 case 18: 4391 case 18:
4392 switch (sel) { 4392 switch (sel) {
4393 case 0 ... 7: 4393 case 0 ... 7:
4394 - tcg_gen_helper_1_1i(do_dmfc0_watchlo, cpu_T[0], cpu_T[0], sel); 4394 + tcg_gen_helper_1_i(do_dmfc0_watchlo, t0, sel);
4395 rn = "WatchLo"; 4395 rn = "WatchLo";
4396 break; 4396 break;
4397 default: 4397 default:
@@ -4401,7 +4401,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4401,7 +4401,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4401 case 19: 4401 case 19:
4402 switch (sel) { 4402 switch (sel) {
4403 case 0 ... 7: 4403 case 0 ... 7:
4404 - tcg_gen_helper_1_1i(do_mfc0_watchhi, cpu_T[0], cpu_T[0], sel); 4404 + tcg_gen_helper_1_i(do_mfc0_watchhi, t0, sel);
4405 rn = "WatchHi"; 4405 rn = "WatchHi";
4406 break; 4406 break;
4407 default: 4407 default:
@@ -4412,7 +4412,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4412,7 +4412,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4412 switch (sel) { 4412 switch (sel) {
4413 case 0: 4413 case 0:
4414 check_insn(env, ctx, ISA_MIPS3); 4414 check_insn(env, ctx, ISA_MIPS3);
4415 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext)); 4415 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
4416 rn = "XContext"; 4416 rn = "XContext";
4417 break; 4417 break;
4418 default: 4418 default:
@@ -4423,7 +4423,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4423,7 +4423,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4423 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 4423 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4424 switch (sel) { 4424 switch (sel) {
4425 case 0: 4425 case 0:
4426 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Framemask)); 4426 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
4427 rn = "Framemask"; 4427 rn = "Framemask";
4428 break; 4428 break;
4429 default: 4429 default:
@@ -4437,23 +4437,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4437,23 +4437,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4437 case 23: 4437 case 23:
4438 switch (sel) { 4438 switch (sel) {
4439 case 0: 4439 case 0:
4440 - tcg_gen_helper_1_1(do_mfc0_debug, cpu_T[0], cpu_T[0]); /* EJTAG support */ 4440 + tcg_gen_helper_1_0(do_mfc0_debug, t0); /* EJTAG support */
4441 rn = "Debug"; 4441 rn = "Debug";
4442 break; 4442 break;
4443 case 1: 4443 case 1:
4444 -// tcg_gen_helper_1_1(do_dmfc0_tracecontrol, cpu_T[0], cpu_T[0]); /* PDtrace support */ 4444 +// tcg_gen_helper_1_0(do_dmfc0_tracecontrol, t0); /* PDtrace support */
4445 rn = "TraceControl"; 4445 rn = "TraceControl";
4446 // break; 4446 // break;
4447 case 2: 4447 case 2:
4448 -// tcg_gen_helper_1_1(do_dmfc0_tracecontrol2, cpu_T[0], cpu_T[0]); /* PDtrace support */ 4448 +// tcg_gen_helper_1_0(do_dmfc0_tracecontrol2, t0); /* PDtrace support */
4449 rn = "TraceControl2"; 4449 rn = "TraceControl2";
4450 // break; 4450 // break;
4451 case 3: 4451 case 3:
4452 -// tcg_gen_helper_1_1(do_dmfc0_usertracedata, cpu_T[0], cpu_T[0]); /* PDtrace support */ 4452 +// tcg_gen_helper_1_0(do_dmfc0_usertracedata, t0); /* PDtrace support */
4453 rn = "UserTraceData"; 4453 rn = "UserTraceData";
4454 // break; 4454 // break;
4455 case 4: 4455 case 4:
4456 -// tcg_gen_helper_1_1(do_dmfc0_tracebpc, cpu_T[0], cpu_T[0]); /* PDtrace support */ 4456 +// tcg_gen_helper_1_0(do_dmfc0_tracebpc, t0); /* PDtrace support */
4457 rn = "TraceBPC"; 4457 rn = "TraceBPC";
4458 // break; 4458 // break;
4459 default: 4459 default:
@@ -4464,7 +4464,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4464,7 +4464,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4464 switch (sel) { 4464 switch (sel) {
4465 case 0: 4465 case 0:
4466 /* EJTAG support */ 4466 /* EJTAG support */
4467 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC)); 4467 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
4468 rn = "DEPC"; 4468 rn = "DEPC";
4469 break; 4469 break;
4470 default: 4470 default:
@@ -4474,35 +4474,35 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4474,35 +4474,35 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4474 case 25: 4474 case 25:
4475 switch (sel) { 4475 switch (sel) {
4476 case 0: 4476 case 0:
4477 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Performance0)); 4477 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
4478 rn = "Performance0"; 4478 rn = "Performance0";
4479 break; 4479 break;
4480 case 1: 4480 case 1:
4481 -// tcg_gen_helper_1_1(do_dmfc0_performance1, cpu_T[0], cpu_T[0]); 4481 +// tcg_gen_helper_1_0(do_dmfc0_performance1, t0);
4482 rn = "Performance1"; 4482 rn = "Performance1";
4483 // break; 4483 // break;
4484 case 2: 4484 case 2:
4485 -// tcg_gen_helper_1_1(do_dmfc0_performance2, cpu_T[0], cpu_T[0]); 4485 +// tcg_gen_helper_1_0(do_dmfc0_performance2, t0);
4486 rn = "Performance2"; 4486 rn = "Performance2";
4487 // break; 4487 // break;
4488 case 3: 4488 case 3:
4489 -// tcg_gen_helper_1_1(do_dmfc0_performance3, cpu_T[0], cpu_T[0]); 4489 +// tcg_gen_helper_1_0(do_dmfc0_performance3, t0);
4490 rn = "Performance3"; 4490 rn = "Performance3";
4491 // break; 4491 // break;
4492 case 4: 4492 case 4:
4493 -// tcg_gen_helper_1_1(do_dmfc0_performance4, cpu_T[0], cpu_T[0]); 4493 +// tcg_gen_helper_1_0(do_dmfc0_performance4, t0);
4494 rn = "Performance4"; 4494 rn = "Performance4";
4495 // break; 4495 // break;
4496 case 5: 4496 case 5:
4497 -// tcg_gen_helper_1_1(do_dmfc0_performance5, cpu_T[0], cpu_T[0]); 4497 +// tcg_gen_helper_1_0(do_dmfc0_performance5, t0);
4498 rn = "Performance5"; 4498 rn = "Performance5";
4499 // break; 4499 // break;
4500 case 6: 4500 case 6:
4501 -// tcg_gen_helper_1_1(do_dmfc0_performance6, cpu_T[0], cpu_T[0]); 4501 +// tcg_gen_helper_1_0(do_dmfc0_performance6, t0);
4502 rn = "Performance6"; 4502 rn = "Performance6";
4503 // break; 4503 // break;
4504 case 7: 4504 case 7:
4505 -// tcg_gen_helper_1_1(do_dmfc0_performance7, cpu_T[0], cpu_T[0]); 4505 +// tcg_gen_helper_1_0(do_dmfc0_performance7, t0);
4506 rn = "Performance7"; 4506 rn = "Performance7";
4507 // break; 4507 // break;
4508 default: 4508 default:
@@ -4528,14 +4528,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4528,14 +4528,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4528 case 2: 4528 case 2:
4529 case 4: 4529 case 4:
4530 case 6: 4530 case 6:
4531 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagLo)); 4531 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
4532 rn = "TagLo"; 4532 rn = "TagLo";
4533 break; 4533 break;
4534 case 1: 4534 case 1:
4535 case 3: 4535 case 3:
4536 case 5: 4536 case 5:
4537 case 7: 4537 case 7:
4538 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataLo)); 4538 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
4539 rn = "DataLo"; 4539 rn = "DataLo";
4540 break; 4540 break;
4541 default: 4541 default:
@@ -4548,14 +4548,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4548,14 +4548,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4548 case 2: 4548 case 2:
4549 case 4: 4549 case 4:
4550 case 6: 4550 case 6:
4551 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagHi)); 4551 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
4552 rn = "TagHi"; 4552 rn = "TagHi";
4553 break; 4553 break;
4554 case 1: 4554 case 1:
4555 case 3: 4555 case 3:
4556 case 5: 4556 case 5:
4557 case 7: 4557 case 7:
4558 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataHi)); 4558 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
4559 rn = "DataHi"; 4559 rn = "DataHi";
4560 break; 4560 break;
4561 default: 4561 default:
@@ -4565,7 +4565,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4565,7 +4565,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4565 case 30: 4565 case 30:
4566 switch (sel) { 4566 switch (sel) {
4567 case 0: 4567 case 0:
4568 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC)); 4568 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4569 rn = "ErrorEPC"; 4569 rn = "ErrorEPC";
4570 break; 4570 break;
4571 default: 4571 default:
@@ -4576,7 +4576,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4576,7 +4576,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4576 switch (sel) { 4576 switch (sel) {
4577 case 0: 4577 case 0:
4578 /* EJTAG support */ 4578 /* EJTAG support */
4579 - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DESAVE)); 4579 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
4580 rn = "DESAVE"; 4580 rn = "DESAVE";
4581 break; 4581 break;
4582 default: 4582 default:
@@ -4604,7 +4604,7 @@ die: @@ -4604,7 +4604,7 @@ die:
4604 generate_exception(ctx, EXCP_RI); 4604 generate_exception(ctx, EXCP_RI);
4605 } 4605 }
4606 4606
4607 -static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) 4607 +static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
4608 { 4608 {
4609 const char *rn = "invalid"; 4609 const char *rn = "invalid";
4610 4610
@@ -4615,12 +4615,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4615,12 +4615,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4615 case 0: 4615 case 0:
4616 switch (sel) { 4616 switch (sel) {
4617 case 0: 4617 case 0:
4618 - tcg_gen_helper_0_1(do_mtc0_index, cpu_T[0]); 4618 + tcg_gen_helper_0_1(do_mtc0_index, t0);
4619 rn = "Index"; 4619 rn = "Index";
4620 break; 4620 break;
4621 case 1: 4621 case 1:
4622 check_insn(env, ctx, ASE_MT); 4622 check_insn(env, ctx, ASE_MT);
4623 - tcg_gen_helper_0_1(do_mtc0_mvpcontrol, cpu_T[0]); 4623 + tcg_gen_helper_0_1(do_mtc0_mvpcontrol, t0);
4624 rn = "MVPControl"; 4624 rn = "MVPControl";
4625 break; 4625 break;
4626 case 2: 4626 case 2:
@@ -4645,37 +4645,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4645,37 +4645,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4645 break; 4645 break;
4646 case 1: 4646 case 1:
4647 check_insn(env, ctx, ASE_MT); 4647 check_insn(env, ctx, ASE_MT);
4648 - tcg_gen_helper_0_1(do_mtc0_vpecontrol, cpu_T[0]); 4648 + tcg_gen_helper_0_1(do_mtc0_vpecontrol, t0);
4649 rn = "VPEControl"; 4649 rn = "VPEControl";
4650 break; 4650 break;
4651 case 2: 4651 case 2:
4652 check_insn(env, ctx, ASE_MT); 4652 check_insn(env, ctx, ASE_MT);
4653 - tcg_gen_helper_0_1(do_mtc0_vpeconf0, cpu_T[0]); 4653 + tcg_gen_helper_0_1(do_mtc0_vpeconf0, t0);
4654 rn = "VPEConf0"; 4654 rn = "VPEConf0";
4655 break; 4655 break;
4656 case 3: 4656 case 3:
4657 check_insn(env, ctx, ASE_MT); 4657 check_insn(env, ctx, ASE_MT);
4658 - tcg_gen_helper_0_1(do_mtc0_vpeconf1, cpu_T[0]); 4658 + tcg_gen_helper_0_1(do_mtc0_vpeconf1, t0);
4659 rn = "VPEConf1"; 4659 rn = "VPEConf1";
4660 break; 4660 break;
4661 case 4: 4661 case 4:
4662 check_insn(env, ctx, ASE_MT); 4662 check_insn(env, ctx, ASE_MT);
4663 - tcg_gen_helper_0_1(do_mtc0_yqmask, cpu_T[0]); 4663 + tcg_gen_helper_0_1(do_mtc0_yqmask, t0);
4664 rn = "YQMask"; 4664 rn = "YQMask";
4665 break; 4665 break;
4666 case 5: 4666 case 5:
4667 check_insn(env, ctx, ASE_MT); 4667 check_insn(env, ctx, ASE_MT);
4668 - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule)); 4668 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4669 rn = "VPESchedule"; 4669 rn = "VPESchedule";
4670 break; 4670 break;
4671 case 6: 4671 case 6:
4672 check_insn(env, ctx, ASE_MT); 4672 check_insn(env, ctx, ASE_MT);
4673 - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack)); 4673 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4674 rn = "VPEScheFBack"; 4674 rn = "VPEScheFBack";
4675 break; 4675 break;
4676 case 7: 4676 case 7:
4677 check_insn(env, ctx, ASE_MT); 4677 check_insn(env, ctx, ASE_MT);
4678 - tcg_gen_helper_0_1(do_mtc0_vpeopt, cpu_T[0]); 4678 + tcg_gen_helper_0_1(do_mtc0_vpeopt, t0);
4679 rn = "VPEOpt"; 4679 rn = "VPEOpt";
4680 break; 4680 break;
4681 default: 4681 default:
@@ -4685,42 +4685,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4685,42 +4685,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4685 case 2: 4685 case 2:
4686 switch (sel) { 4686 switch (sel) {
4687 case 0: 4687 case 0:
4688 - tcg_gen_helper_0_1(do_mtc0_entrylo0, cpu_T[0]); 4688 + tcg_gen_helper_0_1(do_mtc0_entrylo0, t0);
4689 rn = "EntryLo0"; 4689 rn = "EntryLo0";
4690 break; 4690 break;
4691 case 1: 4691 case 1:
4692 check_insn(env, ctx, ASE_MT); 4692 check_insn(env, ctx, ASE_MT);
4693 - tcg_gen_helper_0_1(do_mtc0_tcstatus, cpu_T[0]); 4693 + tcg_gen_helper_0_1(do_mtc0_tcstatus, t0);
4694 rn = "TCStatus"; 4694 rn = "TCStatus";
4695 break; 4695 break;
4696 case 2: 4696 case 2:
4697 check_insn(env, ctx, ASE_MT); 4697 check_insn(env, ctx, ASE_MT);
4698 - tcg_gen_helper_0_1(do_mtc0_tcbind, cpu_T[0]); 4698 + tcg_gen_helper_0_1(do_mtc0_tcbind, t0);
4699 rn = "TCBind"; 4699 rn = "TCBind";
4700 break; 4700 break;
4701 case 3: 4701 case 3:
4702 check_insn(env, ctx, ASE_MT); 4702 check_insn(env, ctx, ASE_MT);
4703 - tcg_gen_helper_0_1(do_mtc0_tcrestart, cpu_T[0]); 4703 + tcg_gen_helper_0_1(do_mtc0_tcrestart, t0);
4704 rn = "TCRestart"; 4704 rn = "TCRestart";
4705 break; 4705 break;
4706 case 4: 4706 case 4:
4707 check_insn(env, ctx, ASE_MT); 4707 check_insn(env, ctx, ASE_MT);
4708 - tcg_gen_helper_0_1(do_mtc0_tchalt, cpu_T[0]); 4708 + tcg_gen_helper_0_1(do_mtc0_tchalt, t0);
4709 rn = "TCHalt"; 4709 rn = "TCHalt";
4710 break; 4710 break;
4711 case 5: 4711 case 5:
4712 check_insn(env, ctx, ASE_MT); 4712 check_insn(env, ctx, ASE_MT);
4713 - tcg_gen_helper_0_1(do_mtc0_tccontext, cpu_T[0]); 4713 + tcg_gen_helper_0_1(do_mtc0_tccontext, t0);
4714 rn = "TCContext"; 4714 rn = "TCContext";
4715 break; 4715 break;
4716 case 6: 4716 case 6:
4717 check_insn(env, ctx, ASE_MT); 4717 check_insn(env, ctx, ASE_MT);
4718 - tcg_gen_helper_0_1(do_mtc0_tcschedule, cpu_T[0]); 4718 + tcg_gen_helper_0_1(do_mtc0_tcschedule, t0);
4719 rn = "TCSchedule"; 4719 rn = "TCSchedule";
4720 break; 4720 break;
4721 case 7: 4721 case 7:
4722 check_insn(env, ctx, ASE_MT); 4722 check_insn(env, ctx, ASE_MT);
4723 - tcg_gen_helper_0_1(do_mtc0_tcschefback, cpu_T[0]); 4723 + tcg_gen_helper_0_1(do_mtc0_tcschefback, t0);
4724 rn = "TCScheFBack"; 4724 rn = "TCScheFBack";
4725 break; 4725 break;
4726 default: 4726 default:
@@ -4730,7 +4730,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4730,7 +4730,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4730 case 3: 4730 case 3:
4731 switch (sel) { 4731 switch (sel) {
4732 case 0: 4732 case 0:
4733 - tcg_gen_helper_0_1(do_mtc0_entrylo1, cpu_T[0]); 4733 + tcg_gen_helper_0_1(do_mtc0_entrylo1, t0);
4734 rn = "EntryLo1"; 4734 rn = "EntryLo1";
4735 break; 4735 break;
4736 default: 4736 default:
@@ -4740,11 +4740,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4740,11 +4740,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4740 case 4: 4740 case 4:
4741 switch (sel) { 4741 switch (sel) {
4742 case 0: 4742 case 0:
4743 - tcg_gen_helper_0_1(do_mtc0_context, cpu_T[0]); 4743 + tcg_gen_helper_0_1(do_mtc0_context, t0);
4744 rn = "Context"; 4744 rn = "Context";
4745 break; 4745 break;
4746 case 1: 4746 case 1:
4747 -// tcg_gen_helper_0_1(do_mtc0_contextconfig, cpu_T[0]); /* SmartMIPS ASE */ 4747 +// tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
4748 rn = "ContextConfig"; 4748 rn = "ContextConfig";
4749 // break; 4749 // break;
4750 default: 4750 default:
@@ -4754,12 +4754,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4754,12 +4754,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4754 case 5: 4754 case 5:
4755 switch (sel) { 4755 switch (sel) {
4756 case 0: 4756 case 0:
4757 - tcg_gen_helper_0_1(do_mtc0_pagemask, cpu_T[0]); 4757 + tcg_gen_helper_0_1(do_mtc0_pagemask, t0);
4758 rn = "PageMask"; 4758 rn = "PageMask";
4759 break; 4759 break;
4760 case 1: 4760 case 1:
4761 check_insn(env, ctx, ISA_MIPS32R2); 4761 check_insn(env, ctx, ISA_MIPS32R2);
4762 - tcg_gen_helper_0_1(do_mtc0_pagegrain, cpu_T[0]); 4762 + tcg_gen_helper_0_1(do_mtc0_pagegrain, t0);
4763 rn = "PageGrain"; 4763 rn = "PageGrain";
4764 break; 4764 break;
4765 default: 4765 default:
@@ -4769,32 +4769,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4769,32 +4769,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4769 case 6: 4769 case 6:
4770 switch (sel) { 4770 switch (sel) {
4771 case 0: 4771 case 0:
4772 - tcg_gen_helper_0_1(do_mtc0_wired, cpu_T[0]); 4772 + tcg_gen_helper_0_1(do_mtc0_wired, t0);
4773 rn = "Wired"; 4773 rn = "Wired";
4774 break; 4774 break;
4775 case 1: 4775 case 1:
4776 check_insn(env, ctx, ISA_MIPS32R2); 4776 check_insn(env, ctx, ISA_MIPS32R2);
4777 - tcg_gen_helper_0_1(do_mtc0_srsconf0, cpu_T[0]); 4777 + tcg_gen_helper_0_1(do_mtc0_srsconf0, t0);
4778 rn = "SRSConf0"; 4778 rn = "SRSConf0";
4779 break; 4779 break;
4780 case 2: 4780 case 2:
4781 check_insn(env, ctx, ISA_MIPS32R2); 4781 check_insn(env, ctx, ISA_MIPS32R2);
4782 - tcg_gen_helper_0_1(do_mtc0_srsconf1, cpu_T[0]); 4782 + tcg_gen_helper_0_1(do_mtc0_srsconf1, t0);
4783 rn = "SRSConf1"; 4783 rn = "SRSConf1";
4784 break; 4784 break;
4785 case 3: 4785 case 3:
4786 check_insn(env, ctx, ISA_MIPS32R2); 4786 check_insn(env, ctx, ISA_MIPS32R2);
4787 - tcg_gen_helper_0_1(do_mtc0_srsconf2, cpu_T[0]); 4787 + tcg_gen_helper_0_1(do_mtc0_srsconf2, t0);
4788 rn = "SRSConf2"; 4788 rn = "SRSConf2";
4789 break; 4789 break;
4790 case 4: 4790 case 4:
4791 check_insn(env, ctx, ISA_MIPS32R2); 4791 check_insn(env, ctx, ISA_MIPS32R2);
4792 - tcg_gen_helper_0_1(do_mtc0_srsconf3, cpu_T[0]); 4792 + tcg_gen_helper_0_1(do_mtc0_srsconf3, t0);
4793 rn = "SRSConf3"; 4793 rn = "SRSConf3";
4794 break; 4794 break;
4795 case 5: 4795 case 5:
4796 check_insn(env, ctx, ISA_MIPS32R2); 4796 check_insn(env, ctx, ISA_MIPS32R2);
4797 - tcg_gen_helper_0_1(do_mtc0_srsconf4, cpu_T[0]); 4797 + tcg_gen_helper_0_1(do_mtc0_srsconf4, t0);
4798 rn = "SRSConf4"; 4798 rn = "SRSConf4";
4799 break; 4799 break;
4800 default: 4800 default:
@@ -4805,7 +4805,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4805,7 +4805,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4805 switch (sel) { 4805 switch (sel) {
4806 case 0: 4806 case 0:
4807 check_insn(env, ctx, ISA_MIPS32R2); 4807 check_insn(env, ctx, ISA_MIPS32R2);
4808 - tcg_gen_helper_0_1(do_mtc0_hwrena, cpu_T[0]); 4808 + tcg_gen_helper_0_1(do_mtc0_hwrena, t0);
4809 rn = "HWREna"; 4809 rn = "HWREna";
4810 break; 4810 break;
4811 default: 4811 default:
@@ -4819,7 +4819,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4819,7 +4819,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4819 case 9: 4819 case 9:
4820 switch (sel) { 4820 switch (sel) {
4821 case 0: 4821 case 0:
4822 - tcg_gen_helper_0_1(do_mtc0_count, cpu_T[0]); 4822 + tcg_gen_helper_0_1(do_mtc0_count, t0);
4823 rn = "Count"; 4823 rn = "Count";
4824 break; 4824 break;
4825 /* 6,7 are implementation dependent */ 4825 /* 6,7 are implementation dependent */
@@ -4832,7 +4832,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4832,7 +4832,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4832 case 10: 4832 case 10:
4833 switch (sel) { 4833 switch (sel) {
4834 case 0: 4834 case 0:
4835 - tcg_gen_helper_0_1(do_mtc0_entryhi, cpu_T[0]); 4835 + tcg_gen_helper_0_1(do_mtc0_entryhi, t0);
4836 rn = "EntryHi"; 4836 rn = "EntryHi";
4837 break; 4837 break;
4838 default: 4838 default:
@@ -4842,7 +4842,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4842,7 +4842,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4842 case 11: 4842 case 11:
4843 switch (sel) { 4843 switch (sel) {
4844 case 0: 4844 case 0:
4845 - tcg_gen_helper_0_1(do_mtc0_compare, cpu_T[0]); 4845 + tcg_gen_helper_0_1(do_mtc0_compare, t0);
4846 rn = "Compare"; 4846 rn = "Compare";
4847 break; 4847 break;
4848 /* 6,7 are implementation dependent */ 4848 /* 6,7 are implementation dependent */
@@ -4855,7 +4855,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4855,7 +4855,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4855 case 12: 4855 case 12:
4856 switch (sel) { 4856 switch (sel) {
4857 case 0: 4857 case 0:
4858 - tcg_gen_helper_0_1(do_mtc0_status, cpu_T[0]); 4858 + tcg_gen_helper_0_1(do_mtc0_status, t0);
4859 /* BS_STOP isn't good enough here, hflags may have changed. */ 4859 /* BS_STOP isn't good enough here, hflags may have changed. */
4860 gen_save_pc(ctx->pc + 4); 4860 gen_save_pc(ctx->pc + 4);
4861 ctx->bstate = BS_EXCP; 4861 ctx->bstate = BS_EXCP;
@@ -4863,21 +4863,21 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4863,21 +4863,21 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4863 break; 4863 break;
4864 case 1: 4864 case 1:
4865 check_insn(env, ctx, ISA_MIPS32R2); 4865 check_insn(env, ctx, ISA_MIPS32R2);
4866 - tcg_gen_helper_0_1(do_mtc0_intctl, cpu_T[0]); 4866 + tcg_gen_helper_0_1(do_mtc0_intctl, t0);
4867 /* Stop translation as we may have switched the execution mode */ 4867 /* Stop translation as we may have switched the execution mode */
4868 ctx->bstate = BS_STOP; 4868 ctx->bstate = BS_STOP;
4869 rn = "IntCtl"; 4869 rn = "IntCtl";
4870 break; 4870 break;
4871 case 2: 4871 case 2:
4872 check_insn(env, ctx, ISA_MIPS32R2); 4872 check_insn(env, ctx, ISA_MIPS32R2);
4873 - tcg_gen_helper_0_1(do_mtc0_srsctl, cpu_T[0]); 4873 + tcg_gen_helper_0_1(do_mtc0_srsctl, t0);
4874 /* Stop translation as we may have switched the execution mode */ 4874 /* Stop translation as we may have switched the execution mode */
4875 ctx->bstate = BS_STOP; 4875 ctx->bstate = BS_STOP;
4876 rn = "SRSCtl"; 4876 rn = "SRSCtl";
4877 break; 4877 break;
4878 case 3: 4878 case 3:
4879 check_insn(env, ctx, ISA_MIPS32R2); 4879 check_insn(env, ctx, ISA_MIPS32R2);
4880 - gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_SRSMap)); 4880 + gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
4881 /* Stop translation as we may have switched the execution mode */ 4881 /* Stop translation as we may have switched the execution mode */
4882 ctx->bstate = BS_STOP; 4882 ctx->bstate = BS_STOP;
4883 rn = "SRSMap"; 4883 rn = "SRSMap";
@@ -4889,7 +4889,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4889,7 +4889,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4889 case 13: 4889 case 13:
4890 switch (sel) { 4890 switch (sel) {
4891 case 0: 4891 case 0:
4892 - tcg_gen_helper_0_1(do_mtc0_cause, cpu_T[0]); 4892 + tcg_gen_helper_0_1(do_mtc0_cause, t0);
4893 rn = "Cause"; 4893 rn = "Cause";
4894 break; 4894 break;
4895 default: 4895 default:
@@ -4901,7 +4901,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4901,7 +4901,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4901 case 14: 4901 case 14:
4902 switch (sel) { 4902 switch (sel) {
4903 case 0: 4903 case 0:
4904 - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC)); 4904 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
4905 rn = "EPC"; 4905 rn = "EPC";
4906 break; 4906 break;
4907 default: 4907 default:
@@ -4916,7 +4916,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4916,7 +4916,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4916 break; 4916 break;
4917 case 1: 4917 case 1:
4918 check_insn(env, ctx, ISA_MIPS32R2); 4918 check_insn(env, ctx, ISA_MIPS32R2);
4919 - tcg_gen_helper_0_1(do_mtc0_ebase, cpu_T[0]); 4919 + tcg_gen_helper_0_1(do_mtc0_ebase, t0);
4920 rn = "EBase"; 4920 rn = "EBase";
4921 break; 4921 break;
4922 default: 4922 default:
@@ -4926,7 +4926,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4926,7 +4926,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4926 case 16: 4926 case 16:
4927 switch (sel) { 4927 switch (sel) {
4928 case 0: 4928 case 0:
4929 - tcg_gen_helper_0_1(do_mtc0_config0, cpu_T[0]); 4929 + tcg_gen_helper_0_1(do_mtc0_config0, t0);
4930 rn = "Config"; 4930 rn = "Config";
4931 /* Stop translation as we may have switched the execution mode */ 4931 /* Stop translation as we may have switched the execution mode */
4932 ctx->bstate = BS_STOP; 4932 ctx->bstate = BS_STOP;
@@ -4936,7 +4936,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4936,7 +4936,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4936 rn = "Config1"; 4936 rn = "Config1";
4937 break; 4937 break;
4938 case 2: 4938 case 2:
4939 - tcg_gen_helper_0_1(do_mtc0_config2, cpu_T[0]); 4939 + tcg_gen_helper_0_1(do_mtc0_config2, t0);
4940 rn = "Config2"; 4940 rn = "Config2";
4941 /* Stop translation as we may have switched the execution mode */ 4941 /* Stop translation as we may have switched the execution mode */
4942 ctx->bstate = BS_STOP; 4942 ctx->bstate = BS_STOP;
@@ -4964,7 +4964,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4964,7 +4964,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4964 case 18: 4964 case 18:
4965 switch (sel) { 4965 switch (sel) {
4966 case 0 ... 7: 4966 case 0 ... 7:
4967 - tcg_gen_helper_0_1i(do_mtc0_watchlo, cpu_T[0], sel); 4967 + tcg_gen_helper_0_1i(do_mtc0_watchlo, t0, sel);
4968 rn = "WatchLo"; 4968 rn = "WatchLo";
4969 break; 4969 break;
4970 default: 4970 default:
@@ -4974,7 +4974,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4974,7 +4974,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4974 case 19: 4974 case 19:
4975 switch (sel) { 4975 switch (sel) {
4976 case 0 ... 7: 4976 case 0 ... 7:
4977 - tcg_gen_helper_0_1i(do_mtc0_watchhi, cpu_T[0], sel); 4977 + tcg_gen_helper_0_1i(do_mtc0_watchhi, t0, sel);
4978 rn = "WatchHi"; 4978 rn = "WatchHi";
4979 break; 4979 break;
4980 default: 4980 default:
@@ -4985,7 +4985,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4985,7 +4985,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4985 switch (sel) { 4985 switch (sel) {
4986 case 0: 4986 case 0:
4987 check_insn(env, ctx, ISA_MIPS3); 4987 check_insn(env, ctx, ISA_MIPS3);
4988 - tcg_gen_helper_0_1(do_mtc0_xcontext, cpu_T[0]); 4988 + tcg_gen_helper_0_1(do_mtc0_xcontext, t0);
4989 rn = "XContext"; 4989 rn = "XContext";
4990 break; 4990 break;
4991 default: 4991 default:
@@ -4996,7 +4996,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4996,7 +4996,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4996 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 4996 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4997 switch (sel) { 4997 switch (sel) {
4998 case 0: 4998 case 0:
4999 - tcg_gen_helper_0_1(do_mtc0_framemask, cpu_T[0]); 4999 + tcg_gen_helper_0_1(do_mtc0_framemask, t0);
5000 rn = "Framemask"; 5000 rn = "Framemask";
5001 break; 5001 break;
5002 default: 5002 default:
@@ -5010,32 +5010,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -5010,32 +5010,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5010 case 23: 5010 case 23:
5011 switch (sel) { 5011 switch (sel) {
5012 case 0: 5012 case 0:
5013 - tcg_gen_helper_0_1(do_mtc0_debug, cpu_T[0]); /* EJTAG support */ 5013 + tcg_gen_helper_0_1(do_mtc0_debug, t0); /* EJTAG support */
5014 /* BS_STOP isn't good enough here, hflags may have changed. */ 5014 /* BS_STOP isn't good enough here, hflags may have changed. */
5015 gen_save_pc(ctx->pc + 4); 5015 gen_save_pc(ctx->pc + 4);
5016 ctx->bstate = BS_EXCP; 5016 ctx->bstate = BS_EXCP;
5017 rn = "Debug"; 5017 rn = "Debug";
5018 break; 5018 break;
5019 case 1: 5019 case 1:
5020 -// tcg_gen_helper_0_1(do_mtc0_tracecontrol, cpu_T[0]); /* PDtrace support */ 5020 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
5021 /* Stop translation as we may have switched the execution mode */ 5021 /* Stop translation as we may have switched the execution mode */
5022 ctx->bstate = BS_STOP; 5022 ctx->bstate = BS_STOP;
5023 rn = "TraceControl"; 5023 rn = "TraceControl";
5024 // break; 5024 // break;
5025 case 2: 5025 case 2:
5026 -// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, cpu_T[0]); /* PDtrace support */ 5026 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
5027 /* Stop translation as we may have switched the execution mode */ 5027 /* Stop translation as we may have switched the execution mode */
5028 ctx->bstate = BS_STOP; 5028 ctx->bstate = BS_STOP;
5029 rn = "TraceControl2"; 5029 rn = "TraceControl2";
5030 // break; 5030 // break;
5031 case 3: 5031 case 3:
5032 -// tcg_gen_helper_0_1(do_mtc0_usertracedata, cpu_T[0]); /* PDtrace support */ 5032 +// tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
5033 /* Stop translation as we may have switched the execution mode */ 5033 /* Stop translation as we may have switched the execution mode */
5034 ctx->bstate = BS_STOP; 5034 ctx->bstate = BS_STOP;
5035 rn = "UserTraceData"; 5035 rn = "UserTraceData";
5036 // break; 5036 // break;
5037 case 4: 5037 case 4:
5038 -// tcg_gen_helper_0_1(do_mtc0_tracebpc, cpu_T[0]); /* PDtrace support */ 5038 +// tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
5039 /* Stop translation as we may have switched the execution mode */ 5039 /* Stop translation as we may have switched the execution mode */
5040 ctx->bstate = BS_STOP; 5040 ctx->bstate = BS_STOP;
5041 rn = "TraceBPC"; 5041 rn = "TraceBPC";
@@ -5048,7 +5048,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -5048,7 +5048,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5048 switch (sel) { 5048 switch (sel) {
5049 case 0: 5049 case 0:
5050 /* EJTAG support */ 5050 /* EJTAG support */
5051 - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC)); 5051 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
5052 rn = "DEPC"; 5052 rn = "DEPC";
5053 break; 5053 break;
5054 default: 5054 default:
@@ -5058,35 +5058,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -5058,35 +5058,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5058 case 25: 5058 case 25:
5059 switch (sel) { 5059 switch (sel) {
5060 case 0: 5060 case 0:
5061 - tcg_gen_helper_0_1(do_mtc0_performance0, cpu_T[0]); 5061 + tcg_gen_helper_0_1(do_mtc0_performance0, t0);
5062 rn = "Performance0"; 5062 rn = "Performance0";
5063 break; 5063 break;
5064 case 1: 5064 case 1:
5065 -// tcg_gen_helper_0_1(do_mtc0_performance1, cpu_T[0]); 5065 +// tcg_gen_helper_0_1(do_mtc0_performance1, t0);
5066 rn = "Performance1"; 5066 rn = "Performance1";
5067 // break; 5067 // break;
5068 case 2: 5068 case 2:
5069 -// tcg_gen_helper_0_1(do_mtc0_performance2, cpu_T[0]); 5069 +// tcg_gen_helper_0_1(do_mtc0_performance2, t0);
5070 rn = "Performance2"; 5070 rn = "Performance2";
5071 // break; 5071 // break;
5072 case 3: 5072 case 3:
5073 -// tcg_gen_helper_0_1(do_mtc0_performance3, cpu_T[0]); 5073 +// tcg_gen_helper_0_1(do_mtc0_performance3, t0);
5074 rn = "Performance3"; 5074 rn = "Performance3";
5075 // break; 5075 // break;
5076 case 4: 5076 case 4:
5077 -// tcg_gen_helper_0_1(do_mtc0_performance4, cpu_T[0]); 5077 +// tcg_gen_helper_0_1(do_mtc0_performance4, t0);
5078 rn = "Performance4"; 5078 rn = "Performance4";
5079 // break; 5079 // break;
5080 case 5: 5080 case 5:
5081 -// tcg_gen_helper_0_1(do_mtc0_performance5, cpu_T[0]); 5081 +// tcg_gen_helper_0_1(do_mtc0_performance5, t0);
5082 rn = "Performance5"; 5082 rn = "Performance5";
5083 // break; 5083 // break;
5084 case 6: 5084 case 6:
5085 -// tcg_gen_helper_0_1(do_mtc0_performance6, cpu_T[0]); 5085 +// tcg_gen_helper_0_1(do_mtc0_performance6, t0);
5086 rn = "Performance6"; 5086 rn = "Performance6";
5087 // break; 5087 // break;
5088 case 7: 5088 case 7:
5089 -// tcg_gen_helper_0_1(do_mtc0_performance7, cpu_T[0]); 5089 +// tcg_gen_helper_0_1(do_mtc0_performance7, t0);
5090 rn = "Performance7"; 5090 rn = "Performance7";
5091 // break; 5091 // break;
5092 default: 5092 default:
@@ -5113,14 +5113,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -5113,14 +5113,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5113 case 2: 5113 case 2:
5114 case 4: 5114 case 4:
5115 case 6: 5115 case 6:
5116 - tcg_gen_helper_0_1(do_mtc0_taglo, cpu_T[0]); 5116 + tcg_gen_helper_0_1(do_mtc0_taglo, t0);
5117 rn = "TagLo"; 5117 rn = "TagLo";
5118 break; 5118 break;
5119 case 1: 5119 case 1:
5120 case 3: 5120 case 3:
5121 case 5: 5121 case 5:
5122 case 7: 5122 case 7:
5123 - tcg_gen_helper_0_1(do_mtc0_datalo, cpu_T[0]); 5123 + tcg_gen_helper_0_1(do_mtc0_datalo, t0);
5124 rn = "DataLo"; 5124 rn = "DataLo";
5125 break; 5125 break;
5126 default: 5126 default:
@@ -5133,14 +5133,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -5133,14 +5133,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5133 case 2: 5133 case 2:
5134 case 4: 5134 case 4:
5135 case 6: 5135 case 6:
5136 - tcg_gen_helper_0_1(do_mtc0_taghi, cpu_T[0]); 5136 + tcg_gen_helper_0_1(do_mtc0_taghi, t0);
5137 rn = "TagHi"; 5137 rn = "TagHi";
5138 break; 5138 break;
5139 case 1: 5139 case 1:
5140 case 3: 5140 case 3:
5141 case 5: 5141 case 5:
5142 case 7: 5142 case 7:
5143 - tcg_gen_helper_0_1(do_mtc0_datahi, cpu_T[0]); 5143 + tcg_gen_helper_0_1(do_mtc0_datahi, t0);
5144 rn = "DataHi"; 5144 rn = "DataHi";
5145 break; 5145 break;
5146 default: 5146 default:
@@ -5151,7 +5151,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -5151,7 +5151,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5151 case 30: 5151 case 30:
5152 switch (sel) { 5152 switch (sel) {
5153 case 0: 5153 case 0:
5154 - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC)); 5154 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
5155 rn = "ErrorEPC"; 5155 rn = "ErrorEPC";
5156 break; 5156 break;
5157 default: 5157 default:
@@ -5162,7 +5162,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -5162,7 +5162,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5162 switch (sel) { 5162 switch (sel) {
5163 case 0: 5163 case 0:
5164 /* EJTAG support */ 5164 /* EJTAG support */
5165 - gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_DESAVE)); 5165 + gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
5166 rn = "DESAVE"; 5166 rn = "DESAVE";
5167 break; 5167 break;
5168 default: 5168 default:
@@ -5180,9 +5180,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -5180,9 +5180,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5180 rn, reg, sel); 5180 rn, reg, sel);
5181 } 5181 }
5182 #endif 5182 #endif
  5183 + tcg_temp_free(t0);
5183 return; 5184 return;
5184 5185
5185 die: 5186 die:
  5187 + tcg_temp_free(t0);
5186 #if defined MIPS_DEBUG_DISAS 5188 #if defined MIPS_DEBUG_DISAS
5187 if (loglevel & CPU_LOG_TB_IN_ASM) { 5189 if (loglevel & CPU_LOG_TB_IN_ASM) {
5188 fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n", 5190 fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
@@ -5197,121 +5199,122 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd, @@ -5197,121 +5199,122 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5197 int u, int sel, int h) 5199 int u, int sel, int h)
5198 { 5200 {
5199 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 5201 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  5202 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5200 5203
5201 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && 5204 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5202 ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) != 5205 ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) !=
5203 (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE)))) 5206 (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE))))
5204 - tcg_gen_movi_tl(cpu_T[0], -1); 5207 + tcg_gen_movi_tl(t0, -1);
5205 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > 5208 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
5206 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) 5209 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
5207 - tcg_gen_movi_tl(cpu_T[0], -1); 5210 + tcg_gen_movi_tl(t0, -1);
5208 else if (u == 0) { 5211 else if (u == 0) {
5209 switch (rt) { 5212 switch (rt) {
5210 case 2: 5213 case 2:
5211 switch (sel) { 5214 switch (sel) {
5212 case 1: 5215 case 1:
5213 - tcg_gen_helper_1_1(do_mftc0_tcstatus, cpu_T[0], cpu_T[0]); 5216 + tcg_gen_helper_1_1(do_mftc0_tcstatus, t0, t0);
5214 break; 5217 break;
5215 case 2: 5218 case 2:
5216 - tcg_gen_helper_1_1(do_mftc0_tcbind, cpu_T[0], cpu_T[0]); 5219 + tcg_gen_helper_1_1(do_mftc0_tcbind, t0, t0);
5217 break; 5220 break;
5218 case 3: 5221 case 3:
5219 - tcg_gen_helper_1_1(do_mftc0_tcrestart, cpu_T[0], cpu_T[0]); 5222 + tcg_gen_helper_1_1(do_mftc0_tcrestart, t0, t0);
5220 break; 5223 break;
5221 case 4: 5224 case 4:
5222 - tcg_gen_helper_1_1(do_mftc0_tchalt, cpu_T[0], cpu_T[0]); 5225 + tcg_gen_helper_1_1(do_mftc0_tchalt, t0, t0);
5223 break; 5226 break;
5224 case 5: 5227 case 5:
5225 - tcg_gen_helper_1_1(do_mftc0_tccontext, cpu_T[0], cpu_T[0]); 5228 + tcg_gen_helper_1_1(do_mftc0_tccontext, t0, t0);
5226 break; 5229 break;
5227 case 6: 5230 case 6:
5228 - tcg_gen_helper_1_1(do_mftc0_tcschedule, cpu_T[0], cpu_T[0]); 5231 + tcg_gen_helper_1_1(do_mftc0_tcschedule, t0, t0);
5229 break; 5232 break;
5230 case 7: 5233 case 7:
5231 - tcg_gen_helper_1_1(do_mftc0_tcschefback, cpu_T[0], cpu_T[0]); 5234 + tcg_gen_helper_1_1(do_mftc0_tcschefback, t0, t0);
5232 break; 5235 break;
5233 default: 5236 default:
5234 - gen_mfc0(env, ctx, rt, sel); 5237 + gen_mfc0(env, ctx, t0, rt, sel);
5235 break; 5238 break;
5236 } 5239 }
5237 break; 5240 break;
5238 case 10: 5241 case 10:
5239 switch (sel) { 5242 switch (sel) {
5240 case 0: 5243 case 0:
5241 - tcg_gen_helper_1_1(do_mftc0_entryhi, cpu_T[0], cpu_T[0]); 5244 + tcg_gen_helper_1_1(do_mftc0_entryhi, t0, t0);
5242 break; 5245 break;
5243 default: 5246 default:
5244 - gen_mfc0(env, ctx, rt, sel); 5247 + gen_mfc0(env, ctx, t0, rt, sel);
5245 break; 5248 break;
5246 } 5249 }
5247 case 12: 5250 case 12:
5248 switch (sel) { 5251 switch (sel) {
5249 case 0: 5252 case 0:
5250 - tcg_gen_helper_1_1(do_mftc0_status, cpu_T[0], cpu_T[0]); 5253 + tcg_gen_helper_1_1(do_mftc0_status, t0, t0);
5251 break; 5254 break;
5252 default: 5255 default:
5253 - gen_mfc0(env, ctx, rt, sel); 5256 + gen_mfc0(env, ctx, t0, rt, sel);
5254 break; 5257 break;
5255 } 5258 }
5256 case 23: 5259 case 23:
5257 switch (sel) { 5260 switch (sel) {
5258 case 0: 5261 case 0:
5259 - tcg_gen_helper_1_1(do_mftc0_debug, cpu_T[0], cpu_T[0]); 5262 + tcg_gen_helper_1_1(do_mftc0_debug, t0, t0);
5260 break; 5263 break;
5261 default: 5264 default:
5262 - gen_mfc0(env, ctx, rt, sel); 5265 + gen_mfc0(env, ctx, t0, rt, sel);
5263 break; 5266 break;
5264 } 5267 }
5265 break; 5268 break;
5266 default: 5269 default:
5267 - gen_mfc0(env, ctx, rt, sel); 5270 + gen_mfc0(env, ctx, t0, rt, sel);
5268 } 5271 }
5269 } else switch (sel) { 5272 } else switch (sel) {
5270 /* GPR registers. */ 5273 /* GPR registers. */
5271 case 0: 5274 case 0:
5272 - tcg_gen_helper_1_1i(do_mftgpr, cpu_T[0], cpu_T[0], rt); 5275 + tcg_gen_helper_1_1i(do_mftgpr, t0, t0, rt);
5273 break; 5276 break;
5274 /* Auxiliary CPU registers */ 5277 /* Auxiliary CPU registers */
5275 case 1: 5278 case 1:
5276 switch (rt) { 5279 switch (rt) {
5277 case 0: 5280 case 0:
5278 - tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 0); 5281 + tcg_gen_helper_1_1i(do_mftlo, t0, t0, 0);
5279 break; 5282 break;
5280 case 1: 5283 case 1:
5281 - tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 0); 5284 + tcg_gen_helper_1_1i(do_mfthi, t0, t0, 0);
5282 break; 5285 break;
5283 case 2: 5286 case 2:
5284 - tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 0); 5287 + tcg_gen_helper_1_1i(do_mftacx, t0, t0, 0);
5285 break; 5288 break;
5286 case 4: 5289 case 4:
5287 - tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 1); 5290 + tcg_gen_helper_1_1i(do_mftlo, t0, t0, 1);
5288 break; 5291 break;
5289 case 5: 5292 case 5:
5290 - tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 1); 5293 + tcg_gen_helper_1_1i(do_mfthi, t0, t0, 1);
5291 break; 5294 break;
5292 case 6: 5295 case 6:
5293 - tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 1); 5296 + tcg_gen_helper_1_1i(do_mftacx, t0, t0, 1);
5294 break; 5297 break;
5295 case 8: 5298 case 8:
5296 - tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 2); 5299 + tcg_gen_helper_1_1i(do_mftlo, t0, t0, 2);
5297 break; 5300 break;
5298 case 9: 5301 case 9:
5299 - tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 2); 5302 + tcg_gen_helper_1_1i(do_mfthi, t0, t0, 2);
5300 break; 5303 break;
5301 case 10: 5304 case 10:
5302 - tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 2); 5305 + tcg_gen_helper_1_1i(do_mftacx, t0, t0, 2);
5303 break; 5306 break;
5304 case 12: 5307 case 12:
5305 - tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 3); 5308 + tcg_gen_helper_1_1i(do_mftlo, t0, t0, 3);
5306 break; 5309 break;
5307 case 13: 5310 case 13:
5308 - tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 3); 5311 + tcg_gen_helper_1_1i(do_mfthi, t0, t0, 3);
5309 break; 5312 break;
5310 case 14: 5313 case 14:
5311 - tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 3); 5314 + tcg_gen_helper_1_1i(do_mftacx, t0, t0, 3);
5312 break; 5315 break;
5313 case 16: 5316 case 16:
5314 - tcg_gen_helper_1_1(do_mftdsp, cpu_T[0], cpu_T[0]); 5317 + tcg_gen_helper_1_1(do_mftdsp, t0, t0);
5315 break; 5318 break;
5316 default: 5319 default:
5317 goto die; 5320 goto die;
@@ -5322,15 +5325,15 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd, @@ -5322,15 +5325,15 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5322 /* XXX: For now we support only a single FPU context. */ 5325 /* XXX: For now we support only a single FPU context. */
5323 if (h == 0) { 5326 if (h == 0) {
5324 gen_load_fpr32(fpu32_T[0], rt); 5327 gen_load_fpr32(fpu32_T[0], rt);
5325 - tcg_gen_ext_i32_tl(cpu_T[0], fpu32_T[0]); 5328 + tcg_gen_ext_i32_tl(t0, fpu32_T[0]);
5326 } else { 5329 } else {
5327 gen_load_fpr32h(fpu32h_T[0], rt); 5330 gen_load_fpr32h(fpu32h_T[0], rt);
5328 - tcg_gen_ext_i32_tl(cpu_T[0], fpu32h_T[0]); 5331 + tcg_gen_ext_i32_tl(t0, fpu32h_T[0]);
5329 } 5332 }
5330 break; 5333 break;
5331 case 3: 5334 case 3:
5332 /* XXX: For now we support only a single FPU context. */ 5335 /* XXX: For now we support only a single FPU context. */
5333 - tcg_gen_helper_1_1i(do_cfc1, cpu_T[0], cpu_T[0], rt); 5336 + tcg_gen_helper_1_1i(do_cfc1, t0, t0, rt);
5334 break; 5337 break;
5335 /* COP2: Not implemented. */ 5338 /* COP2: Not implemented. */
5336 case 4: 5339 case 4:
@@ -5345,10 +5348,12 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd, @@ -5345,10 +5348,12 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5345 rt, u, sel, h); 5348 rt, u, sel, h);
5346 } 5349 }
5347 #endif 5350 #endif
5348 - gen_store_gpr(cpu_T[0], rd); 5351 + gen_store_gpr(t0, rd);
  5352 + tcg_temp_free(t0);
5349 return; 5353 return;
5350 5354
5351 die: 5355 die:
  5356 + tcg_temp_free(t0);
5352 #if defined MIPS_DEBUG_DISAS 5357 #if defined MIPS_DEBUG_DISAS
5353 if (loglevel & CPU_LOG_TB_IN_ASM) { 5358 if (loglevel & CPU_LOG_TB_IN_ASM) {
5354 fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n", 5359 fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",
@@ -5362,8 +5367,9 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt, @@ -5362,8 +5367,9 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5362 int u, int sel, int h) 5367 int u, int sel, int h)
5363 { 5368 {
5364 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 5369 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  5370 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5365 5371
5366 - gen_load_gpr(cpu_T[0], rt); 5372 + gen_load_gpr(t0, rt);
5367 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && 5373 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5368 ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) != 5374 ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) !=
5369 (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE)))) 5375 (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE))))
@@ -5376,108 +5382,108 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt, @@ -5376,108 +5382,108 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5376 case 2: 5382 case 2:
5377 switch (sel) { 5383 switch (sel) {
5378 case 1: 5384 case 1:
5379 - tcg_gen_helper_0_1(do_mttc0_tcstatus, cpu_T[0]); 5385 + tcg_gen_helper_0_1(do_mttc0_tcstatus, t0);
5380 break; 5386 break;
5381 case 2: 5387 case 2:
5382 - tcg_gen_helper_0_1(do_mttc0_tcbind, cpu_T[0]); 5388 + tcg_gen_helper_0_1(do_mttc0_tcbind, t0);
5383 break; 5389 break;
5384 case 3: 5390 case 3:
5385 - tcg_gen_helper_0_1(do_mttc0_tcrestart, cpu_T[0]); 5391 + tcg_gen_helper_0_1(do_mttc0_tcrestart, t0);
5386 break; 5392 break;
5387 case 4: 5393 case 4:
5388 - tcg_gen_helper_0_1(do_mttc0_tchalt, cpu_T[0]); 5394 + tcg_gen_helper_0_1(do_mttc0_tchalt, t0);
5389 break; 5395 break;
5390 case 5: 5396 case 5:
5391 - tcg_gen_helper_0_1(do_mttc0_tccontext, cpu_T[0]); 5397 + tcg_gen_helper_0_1(do_mttc0_tccontext, t0);
5392 break; 5398 break;
5393 case 6: 5399 case 6:
5394 - tcg_gen_helper_0_1(do_mttc0_tcschedule, cpu_T[0]); 5400 + tcg_gen_helper_0_1(do_mttc0_tcschedule, t0);
5395 break; 5401 break;
5396 case 7: 5402 case 7:
5397 - tcg_gen_helper_0_1(do_mttc0_tcschefback, cpu_T[0]); 5403 + tcg_gen_helper_0_1(do_mttc0_tcschefback, t0);
5398 break; 5404 break;
5399 default: 5405 default:
5400 - gen_mtc0(env, ctx, rd, sel); 5406 + gen_mtc0(env, ctx, t0, rd, sel);
5401 break; 5407 break;
5402 } 5408 }
5403 break; 5409 break;
5404 case 10: 5410 case 10:
5405 switch (sel) { 5411 switch (sel) {
5406 case 0: 5412 case 0:
5407 - tcg_gen_helper_0_1(do_mttc0_entryhi, cpu_T[0]); 5413 + tcg_gen_helper_0_1(do_mttc0_entryhi, t0);
5408 break; 5414 break;
5409 default: 5415 default:
5410 - gen_mtc0(env, ctx, rd, sel); 5416 + gen_mtc0(env, ctx, t0, rd, sel);
5411 break; 5417 break;
5412 } 5418 }
5413 case 12: 5419 case 12:
5414 switch (sel) { 5420 switch (sel) {
5415 case 0: 5421 case 0:
5416 - tcg_gen_helper_0_1(do_mttc0_status, cpu_T[0]); 5422 + tcg_gen_helper_0_1(do_mttc0_status, t0);
5417 break; 5423 break;
5418 default: 5424 default:
5419 - gen_mtc0(env, ctx, rd, sel); 5425 + gen_mtc0(env, ctx, t0, rd, sel);
5420 break; 5426 break;
5421 } 5427 }
5422 case 23: 5428 case 23:
5423 switch (sel) { 5429 switch (sel) {
5424 case 0: 5430 case 0:
5425 - tcg_gen_helper_0_1(do_mttc0_debug, cpu_T[0]); 5431 + tcg_gen_helper_0_1(do_mttc0_debug, t0);
5426 break; 5432 break;
5427 default: 5433 default:
5428 - gen_mtc0(env, ctx, rd, sel); 5434 + gen_mtc0(env, ctx, t0, rd, sel);
5429 break; 5435 break;
5430 } 5436 }
5431 break; 5437 break;
5432 default: 5438 default:
5433 - gen_mtc0(env, ctx, rd, sel); 5439 + gen_mtc0(env, ctx, t0, rd, sel);
5434 } 5440 }
5435 } else switch (sel) { 5441 } else switch (sel) {
5436 /* GPR registers. */ 5442 /* GPR registers. */
5437 case 0: 5443 case 0:
5438 - tcg_gen_helper_0_1i(do_mttgpr, cpu_T[0], rd); 5444 + tcg_gen_helper_0_1i(do_mttgpr, t0, rd);
5439 break; 5445 break;
5440 /* Auxiliary CPU registers */ 5446 /* Auxiliary CPU registers */
5441 case 1: 5447 case 1:
5442 switch (rd) { 5448 switch (rd) {
5443 case 0: 5449 case 0:
5444 - tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 0); 5450 + tcg_gen_helper_0_1i(do_mttlo, t0, 0);
5445 break; 5451 break;
5446 case 1: 5452 case 1:
5447 - tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 0); 5453 + tcg_gen_helper_0_1i(do_mtthi, t0, 0);
5448 break; 5454 break;
5449 case 2: 5455 case 2:
5450 - tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 0); 5456 + tcg_gen_helper_0_1i(do_mttacx, t0, 0);
5451 break; 5457 break;
5452 case 4: 5458 case 4:
5453 - tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 1); 5459 + tcg_gen_helper_0_1i(do_mttlo, t0, 1);
5454 break; 5460 break;
5455 case 5: 5461 case 5:
5456 - tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 1); 5462 + tcg_gen_helper_0_1i(do_mtthi, t0, 1);
5457 break; 5463 break;
5458 case 6: 5464 case 6:
5459 - tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 1); 5465 + tcg_gen_helper_0_1i(do_mttacx, t0, 1);
5460 break; 5466 break;
5461 case 8: 5467 case 8:
5462 - tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 2); 5468 + tcg_gen_helper_0_1i(do_mttlo, t0, 2);
5463 break; 5469 break;
5464 case 9: 5470 case 9:
5465 - tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 2); 5471 + tcg_gen_helper_0_1i(do_mtthi, t0, 2);
5466 break; 5472 break;
5467 case 10: 5473 case 10:
5468 - tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 2); 5474 + tcg_gen_helper_0_1i(do_mttacx, t0, 2);
5469 break; 5475 break;
5470 case 12: 5476 case 12:
5471 - tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 3); 5477 + tcg_gen_helper_0_1i(do_mttlo, t0, 3);
5472 break; 5478 break;
5473 case 13: 5479 case 13:
5474 - tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 3); 5480 + tcg_gen_helper_0_1i(do_mtthi, t0, 3);
5475 break; 5481 break;
5476 case 14: 5482 case 14:
5477 - tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 3); 5483 + tcg_gen_helper_0_1i(do_mttacx, t0, 3);
5478 break; 5484 break;
5479 case 16: 5485 case 16:
5480 - tcg_gen_helper_0_1(do_mttdsp, cpu_T[0]); 5486 + tcg_gen_helper_0_1(do_mttdsp, t0);
5481 break; 5487 break;
5482 default: 5488 default:
5483 goto die; 5489 goto die;
@@ -5487,16 +5493,16 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt, @@ -5487,16 +5493,16 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5487 case 2: 5493 case 2:
5488 /* XXX: For now we support only a single FPU context. */ 5494 /* XXX: For now we support only a single FPU context. */
5489 if (h == 0) { 5495 if (h == 0) {
5490 - tcg_gen_trunc_tl_i32(fpu32_T[0], cpu_T[0]); 5496 + tcg_gen_trunc_tl_i32(fpu32_T[0], t0);
5491 gen_store_fpr32(fpu32_T[0], rd); 5497 gen_store_fpr32(fpu32_T[0], rd);
5492 } else { 5498 } else {
5493 - tcg_gen_trunc_tl_i32(fpu32h_T[0], cpu_T[0]); 5499 + tcg_gen_trunc_tl_i32(fpu32h_T[0], t0);
5494 gen_store_fpr32h(fpu32h_T[0], rd); 5500 gen_store_fpr32h(fpu32h_T[0], rd);
5495 } 5501 }
5496 break; 5502 break;
5497 case 3: 5503 case 3:
5498 /* XXX: For now we support only a single FPU context. */ 5504 /* XXX: For now we support only a single FPU context. */
5499 - tcg_gen_helper_0_1i(do_ctc1, cpu_T[0], rd); 5505 + tcg_gen_helper_0_1i(do_ctc1, t0, rd);
5500 break; 5506 break;
5501 /* COP2: Not implemented. */ 5507 /* COP2: Not implemented. */
5502 case 4: 5508 case 4:
@@ -5511,9 +5517,11 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt, @@ -5511,9 +5517,11 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5511 rd, u, sel, h); 5517 rd, u, sel, h);
5512 } 5518 }
5513 #endif 5519 #endif
  5520 + tcg_temp_free(t0);
5514 return; 5521 return;
5515 5522
5516 die: 5523 die:
  5524 + tcg_temp_free(t0);
5517 #if defined MIPS_DEBUG_DISAS 5525 #if defined MIPS_DEBUG_DISAS
5518 if (loglevel & CPU_LOG_TB_IN_ASM) { 5526 if (loglevel & CPU_LOG_TB_IN_ASM) {
5519 fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n", 5527 fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",
@@ -5533,14 +5541,24 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5533,14 +5541,24 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5533 /* Treat as NOP. */ 5541 /* Treat as NOP. */
5534 return; 5542 return;
5535 } 5543 }
5536 - gen_mfc0(env, ctx, rd, ctx->opcode & 0x7);  
5537 - gen_store_gpr(cpu_T[0], rt); 5544 + {
  5545 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  5546 +
  5547 + gen_mfc0(env, ctx, t0, rd, ctx->opcode & 0x7);
  5548 + gen_store_gpr(t0, rt);
  5549 + tcg_temp_free(t0);
  5550 + }
5538 opn = "mfc0"; 5551 opn = "mfc0";
5539 break; 5552 break;
5540 case OPC_MTC0: 5553 case OPC_MTC0:
5541 - gen_load_gpr(cpu_T[0], rt);  
5542 - save_cpu_state(ctx, 1);  
5543 - gen_mtc0(env, ctx, rd, ctx->opcode & 0x7); 5554 + {
  5555 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  5556 +
  5557 + gen_load_gpr(t0, rt);
  5558 + save_cpu_state(ctx, 1);
  5559 + gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
  5560 + tcg_temp_free(t0);
  5561 + }
5544 opn = "mtc0"; 5562 opn = "mtc0";
5545 break; 5563 break;
5546 #if defined(TARGET_MIPS64) 5564 #if defined(TARGET_MIPS64)
@@ -5550,15 +5568,25 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5550,15 +5568,25 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5550 /* Treat as NOP. */ 5568 /* Treat as NOP. */
5551 return; 5569 return;
5552 } 5570 }
5553 - gen_dmfc0(env, ctx, rd, ctx->opcode & 0x7);  
5554 - gen_store_gpr(cpu_T[0], rt); 5571 + {
  5572 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  5573 +
  5574 + gen_dmfc0(env, ctx, t0, rd, ctx->opcode & 0x7);
  5575 + gen_store_gpr(t0, rt);
  5576 + tcg_temp_free(t0);
  5577 + }
5555 opn = "dmfc0"; 5578 opn = "dmfc0";
5556 break; 5579 break;
5557 case OPC_DMTC0: 5580 case OPC_DMTC0:
5558 check_insn(env, ctx, ISA_MIPS3); 5581 check_insn(env, ctx, ISA_MIPS3);
5559 - gen_load_gpr(cpu_T[0], rt);  
5560 - save_cpu_state(ctx, 1);  
5561 - gen_dmtc0(env, ctx, rd, ctx->opcode & 0x7); 5582 + {
  5583 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  5584 +
  5585 + gen_load_gpr(t0, rt);
  5586 + save_cpu_state(ctx, 1);
  5587 + gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
  5588 + tcg_temp_free(t0);
  5589 + }
5562 opn = "dmtc0"; 5590 opn = "dmtc0";
5563 break; 5591 break;
5564 #endif 5592 #endif
@@ -8069,12 +8097,6 @@ static void mips_tcg_init(void) @@ -8069,12 +8097,6 @@ static void mips_tcg_init(void)
8069 TCG_AREG0, 8097 TCG_AREG0,
8070 offsetof(CPUState, fpu), 8098 offsetof(CPUState, fpu),
8071 "current_fpu"); 8099 "current_fpu");
8072 -#if TARGET_LONG_BITS > HOST_LONG_BITS  
8073 - cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,  
8074 - TCG_AREG0, offsetof(CPUState, t0), "T0");  
8075 -#else  
8076 - cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");  
8077 -#endif  
8078 8100
8079 /* register helpers */ 8101 /* register helpers */
8080 #undef DEF_HELPER 8102 #undef DEF_HELPER