gwj / at91sam9263 · Commits

Commit 1a3fd9c3da4e2d9434a14168306b2fa0abadce18

Authored by ths
1 parent e1bf387e

Remove remaining uses of T0 in the MIPS target. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4788 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 5 changed files with 468 additions and 454 deletions
target-mips/cpu.h
  View file @1a3fd9c
... ... @@ -140,9 +140,6 @@ struct CPUMIPSState {
140 140 target_ulong gpr[MIPS_SHADOW_SET_MAX][32];
141 141 /* Special registers */
142 142 target_ulong PC[MIPS_TC_MAX];
143   -#if TARGET_LONG_BITS > HOST_LONG_BITS
144   - target_ulong t0;
145   -#endif
146 143 /* temporary hack for FP globals */
147 144 #ifndef USE_HOST_FLOAT_REGS
148 145 fpr_t ft0;
... ...
target-mips/exec.h
  View file @1a3fd9c
... ... @@ -10,12 +10,6 @@
10 10  
11 11 register struct CPUMIPSState *env asm(AREG0);
12 12  
13   -#if TARGET_LONG_BITS > HOST_LONG_BITS
14   -#define T0 (env->t0)
15   -#else
16   -register target_ulong T0 asm(AREG1);
17   -#endif
18   -
19 13 #if defined (USE_HOST_FLOAT_REGS)
20 14 #error "implement me."
21 15 #else
... ...
target-mips/helper.h
  View file @1a3fd9c
... ... @@ -43,40 +43,40 @@ DEF_HELPER(target_ulong, do_msachiu, (target_ulong t0, target_ulong t1))
43 43  
44 44 /* CP0 helpers */
45 45 #ifndef CONFIG_USER_ONLY
46   -DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (target_ulong t0))
47   -DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (target_ulong t0))
48   -DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (target_ulong t0))
49   -DEF_HELPER(target_ulong, do_mfc0_random, (target_ulong t0))
50   -DEF_HELPER(target_ulong, do_mfc0_tcstatus, (target_ulong t0))
51   -DEF_HELPER(target_ulong, do_mftc0_tcstatus, (target_ulong t0))
52   -DEF_HELPER(target_ulong, do_mfc0_tcbind, (target_ulong t0))
53   -DEF_HELPER(target_ulong, do_mftc0_tcbind, (target_ulong t0))
54   -DEF_HELPER(target_ulong, do_mfc0_tcrestart, (target_ulong t0))
55   -DEF_HELPER(target_ulong, do_mftc0_tcrestart, (target_ulong t0))
56   -DEF_HELPER(target_ulong, do_mfc0_tchalt, (target_ulong t0))
57   -DEF_HELPER(target_ulong, do_mftc0_tchalt, (target_ulong t0))
58   -DEF_HELPER(target_ulong, do_mfc0_tccontext, (target_ulong t0))
59   -DEF_HELPER(target_ulong, do_mftc0_tccontext, (target_ulong t0))
60   -DEF_HELPER(target_ulong, do_mfc0_tcschedule, (target_ulong t0))
61   -DEF_HELPER(target_ulong, do_mftc0_tcschedule, (target_ulong t0))
62   -DEF_HELPER(target_ulong, do_mfc0_tcschefback, (target_ulong t0))
63   -DEF_HELPER(target_ulong, do_mftc0_tcschefback, (target_ulong t0))
64   -DEF_HELPER(target_ulong, do_mfc0_count, (target_ulong t0))
65   -DEF_HELPER(target_ulong, do_mftc0_entryhi, (target_ulong t0))
66   -DEF_HELPER(target_ulong, do_mftc0_status, (target_ulong t0))
67   -DEF_HELPER(target_ulong, do_mfc0_lladdr, (target_ulong t0))
68   -DEF_HELPER(target_ulong, do_mfc0_watchlo, (target_ulong t0, uint32_t sel))
69   -DEF_HELPER(target_ulong, do_mfc0_watchhi, (target_ulong t0, uint32_t sel))
70   -DEF_HELPER(target_ulong, do_mfc0_debug, (target_ulong t0))
71   -DEF_HELPER(target_ulong, do_mftc0_debug, (target_ulong t0))
  46 +DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (void))
  47 +DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (void))
  48 +DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (void))
  49 +DEF_HELPER(target_ulong, do_mfc0_random, (void))
  50 +DEF_HELPER(target_ulong, do_mfc0_tcstatus, (void))
  51 +DEF_HELPER(target_ulong, do_mftc0_tcstatus, (void))
  52 +DEF_HELPER(target_ulong, do_mfc0_tcbind, (void))
  53 +DEF_HELPER(target_ulong, do_mftc0_tcbind, (void))
  54 +DEF_HELPER(target_ulong, do_mfc0_tcrestart, (void))
  55 +DEF_HELPER(target_ulong, do_mftc0_tcrestart, (void))
  56 +DEF_HELPER(target_ulong, do_mfc0_tchalt, (void))
  57 +DEF_HELPER(target_ulong, do_mftc0_tchalt, (void))
  58 +DEF_HELPER(target_ulong, do_mfc0_tccontext, (void))
  59 +DEF_HELPER(target_ulong, do_mftc0_tccontext, (void))
  60 +DEF_HELPER(target_ulong, do_mfc0_tcschedule, (void))
  61 +DEF_HELPER(target_ulong, do_mftc0_tcschedule, (void))
  62 +DEF_HELPER(target_ulong, do_mfc0_tcschefback, (void))
  63 +DEF_HELPER(target_ulong, do_mftc0_tcschefback, (void))
  64 +DEF_HELPER(target_ulong, do_mfc0_count, (void))
  65 +DEF_HELPER(target_ulong, do_mftc0_entryhi, (void))
  66 +DEF_HELPER(target_ulong, do_mftc0_status, (void))
  67 +DEF_HELPER(target_ulong, do_mfc0_lladdr, (void))
  68 +DEF_HELPER(target_ulong, do_mfc0_watchlo, (uint32_t sel))
  69 +DEF_HELPER(target_ulong, do_mfc0_watchhi, (uint32_t sel))
  70 +DEF_HELPER(target_ulong, do_mfc0_debug, (void))
  71 +DEF_HELPER(target_ulong, do_mftc0_debug, (void))
72 72 #ifdef TARGET_MIPS64
73   -DEF_HELPER(target_ulong, do_dmfc0_tcrestart, (target_ulong t0))
74   -DEF_HELPER(target_ulong, do_dmfc0_tchalt, (target_ulong t0))
75   -DEF_HELPER(target_ulong, do_dmfc0_tccontext, (target_ulong t0))
76   -DEF_HELPER(target_ulong, do_dmfc0_tcschedule, (target_ulong t0))
77   -DEF_HELPER(target_ulong, do_dmfc0_tcschefback, (target_ulong t0))
78   -DEF_HELPER(target_ulong, do_dmfc0_lladdr, (target_ulong t0))
79   -DEF_HELPER(target_ulong, do_dmfc0_watchlo, (target_ulong t0, uint32_t sel))
  73 +DEF_HELPER(target_ulong, do_dmfc0_tcrestart, (void))
  74 +DEF_HELPER(target_ulong, do_dmfc0_tchalt, (void))
  75 +DEF_HELPER(target_ulong, do_dmfc0_tccontext, (void))
  76 +DEF_HELPER(target_ulong, do_dmfc0_tcschedule, (void))
  77 +DEF_HELPER(target_ulong, do_dmfc0_tcschefback, (void))
  78 +DEF_HELPER(target_ulong, do_dmfc0_lladdr, (void))
  79 +DEF_HELPER(target_ulong, do_dmfc0_watchlo, (uint32_t sel))
80 80 #endif /* TARGET_MIPS64 */
81 81  
82 82 DEF_HELPER(void, do_mtc0_index, (target_ulong t0))
... ...
target-mips/op_helper.c
  View file @1a3fd9c
... ... @@ -650,126 +650,127 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global)
650 650 #else
651 651  
652 652 /* CP0 helpers */
653   -target_ulong do_mfc0_mvpcontrol (target_ulong t0)
  653 +target_ulong do_mfc0_mvpcontrol (void)
654 654 {
655 655 return env->mvp->CP0_MVPControl;
656 656 }
657 657  
658   -target_ulong do_mfc0_mvpconf0 (target_ulong t0)
  658 +target_ulong do_mfc0_mvpconf0 (void)
659 659 {
660 660 return env->mvp->CP0_MVPConf0;
661 661 }
662 662  
663   -target_ulong do_mfc0_mvpconf1 (target_ulong t0)
  663 +target_ulong do_mfc0_mvpconf1 (void)
664 664 {
665 665 return env->mvp->CP0_MVPConf1;
666 666 }
667 667  
668   -target_ulong do_mfc0_random (target_ulong t0)
  668 +target_ulong do_mfc0_random (void)
669 669 {
670 670 return (int32_t)cpu_mips_get_random(env);
671 671 }
672 672  
673   -target_ulong do_mfc0_tcstatus (target_ulong t0)
  673 +target_ulong do_mfc0_tcstatus (void)
674 674 {
675 675 return env->CP0_TCStatus[env->current_tc];
676 676 }
677 677  
678   -target_ulong do_mftc0_tcstatus(target_ulong t0)
  678 +target_ulong do_mftc0_tcstatus(void)
679 679 {
680 680 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
681 681  
682 682 return env->CP0_TCStatus[other_tc];
683 683 }
684 684  
685   -target_ulong do_mfc0_tcbind (target_ulong t0)
  685 +target_ulong do_mfc0_tcbind (void)
686 686 {
687 687 return env->CP0_TCBind[env->current_tc];
688 688 }
689 689  
690   -target_ulong do_mftc0_tcbind(target_ulong t0)
  690 +target_ulong do_mftc0_tcbind(void)
691 691 {
692 692 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
693 693  
694 694 return env->CP0_TCBind[other_tc];
695 695 }
696 696  
697   -target_ulong do_mfc0_tcrestart (target_ulong t0)
  697 +target_ulong do_mfc0_tcrestart (void)
698 698 {
699 699 return env->PC[env->current_tc];
700 700 }
701 701  
702   -target_ulong do_mftc0_tcrestart(target_ulong t0)
  702 +target_ulong do_mftc0_tcrestart(void)
703 703 {
704 704 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
705 705  
706 706 return env->PC[other_tc];
707 707 }
708 708  
709   -target_ulong do_mfc0_tchalt (target_ulong t0)
  709 +target_ulong do_mfc0_tchalt (void)
710 710 {
711 711 return env->CP0_TCHalt[env->current_tc];
712 712 }
713 713  
714   -target_ulong do_mftc0_tchalt(target_ulong t0)
  714 +target_ulong do_mftc0_tchalt(void)
715 715 {
716 716 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
717 717  
718 718 return env->CP0_TCHalt[other_tc];
719 719 }
720 720  
721   -target_ulong do_mfc0_tccontext (target_ulong t0)
  721 +target_ulong do_mfc0_tccontext (void)
722 722 {
723 723 return env->CP0_TCContext[env->current_tc];
724 724 }
725 725  
726   -target_ulong do_mftc0_tccontext(target_ulong t0)
  726 +target_ulong do_mftc0_tccontext(void)
727 727 {
728 728 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
729 729  
730 730 return env->CP0_TCContext[other_tc];
731 731 }
732 732  
733   -target_ulong do_mfc0_tcschedule (target_ulong t0)
  733 +target_ulong do_mfc0_tcschedule (void)
734 734 {
735 735 return env->CP0_TCSchedule[env->current_tc];
736 736 }
737 737  
738   -target_ulong do_mftc0_tcschedule(target_ulong t0)
  738 +target_ulong do_mftc0_tcschedule(void)
739 739 {
740 740 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
741 741  
742 742 return env->CP0_TCSchedule[other_tc];
743 743 }
744 744  
745   -target_ulong do_mfc0_tcschefback (target_ulong t0)
  745 +target_ulong do_mfc0_tcschefback (void)
746 746 {
747 747 return env->CP0_TCScheFBack[env->current_tc];
748 748 }
749 749  
750   -target_ulong do_mftc0_tcschefback(target_ulong t0)
  750 +target_ulong do_mftc0_tcschefback(void)
751 751 {
752 752 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
753 753  
754 754 return env->CP0_TCScheFBack[other_tc];
755 755 }
756 756  
757   -target_ulong do_mfc0_count (target_ulong t0)
  757 +target_ulong do_mfc0_count (void)
758 758 {
759 759 return (int32_t)cpu_mips_get_count(env);
760 760 }
761 761  
762   -target_ulong do_mftc0_entryhi(target_ulong t0)
  762 +target_ulong do_mftc0_entryhi(void)
763 763 {
764 764 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
765 765  
766 766 return (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
767 767 }
768 768  
769   -target_ulong do_mftc0_status(target_ulong t0)
  769 +target_ulong do_mftc0_status(void)
770 770 {
771 771 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
772 772 uint32_t tcstatus = env->CP0_TCStatus[other_tc];
  773 + target_ulong t0;
773 774  
774 775 t0 = env->CP0_Status & ~0xf1000018;
775 776 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
... ... @@ -779,31 +780,31 @@ target_ulong do_mftc0_status(target_ulong t0)
779 780 return t0;
780 781 }
781 782  
782   -target_ulong do_mfc0_lladdr (target_ulong t0)
  783 +target_ulong do_mfc0_lladdr (void)
783 784 {
784 785 return (int32_t)env->CP0_LLAddr >> 4;
785 786 }
786 787  
787   -target_ulong do_mfc0_watchlo (target_ulong t0, uint32_t sel)
  788 +target_ulong do_mfc0_watchlo (uint32_t sel)
788 789 {
789 790 return (int32_t)env->CP0_WatchLo[sel];
790 791 }
791 792  
792   -target_ulong do_mfc0_watchhi (target_ulong t0, uint32_t sel)
  793 +target_ulong do_mfc0_watchhi (uint32_t sel)
793 794 {
794 795 return env->CP0_WatchHi[sel];
795 796 }
796 797  
797   -target_ulong do_mfc0_debug (target_ulong t0)
  798 +target_ulong do_mfc0_debug (void)
798 799 {
799   - t0 = env->CP0_Debug;
  800 + target_ulong t0 = env->CP0_Debug;
800 801 if (env->hflags & MIPS_HFLAG_DM)
801 802 t0 |= 1 << CP0DB_DM;
802 803  
803 804 return t0;
804 805 }
805 806  
806   -target_ulong do_mftc0_debug(target_ulong t0)
  807 +target_ulong do_mftc0_debug(void)
807 808 {
808 809 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
809 810  
... ... @@ -814,37 +815,37 @@ target_ulong do_mftc0_debug(target_ulong t0)
814 815 }
815 816  
816 817 #if defined(TARGET_MIPS64)
817   -target_ulong do_dmfc0_tcrestart (target_ulong t0)
  818 +target_ulong do_dmfc0_tcrestart (void)
818 819 {
819 820 return env->PC[env->current_tc];
820 821 }
821 822  
822   -target_ulong do_dmfc0_tchalt (target_ulong t0)
  823 +target_ulong do_dmfc0_tchalt (void)
823 824 {
824 825 return env->CP0_TCHalt[env->current_tc];
825 826 }
826 827  
827   -target_ulong do_dmfc0_tccontext (target_ulong t0)
  828 +target_ulong do_dmfc0_tccontext (void)
828 829 {
829 830 return env->CP0_TCContext[env->current_tc];
830 831 }
831 832  
832   -target_ulong do_dmfc0_tcschedule (target_ulong t0)
  833 +target_ulong do_dmfc0_tcschedule (void)
833 834 {
834 835 return env->CP0_TCSchedule[env->current_tc];
835 836 }
836 837  
837   -target_ulong do_dmfc0_tcschefback (target_ulong t0)
  838 +target_ulong do_dmfc0_tcschefback (void)
838 839 {
839 840 return env->CP0_TCScheFBack[env->current_tc];
840 841 }
841 842  
842   -target_ulong do_dmfc0_lladdr (target_ulong t0)
  843 +target_ulong do_dmfc0_lladdr (void)
843 844 {
844 845 return env->CP0_LLAddr >> 4;
845 846 }
846 847  
847   -target_ulong do_dmfc0_watchlo (target_ulong t0, uint32_t sel)
  848 +target_ulong do_dmfc0_watchlo (uint32_t sel)
848 849 {
849 850 return env->CP0_WatchLo[sel];
850 851 }
... ...
target-mips/translate.c
  View file @1a3fd9c
... ... @@ -423,7 +423,7 @@ enum {
423 423 };
424 424  
425 425 /* global register indices */
426   -static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu, cpu_T[1];
  426 +static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu;
427 427  
428 428 /* FPU TNs, global for now. */
429 429 static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3];
... ... @@ -2856,7 +2856,7 @@ static inline void gen_mtc0_store64 (TCGv t, target_ulong off)
2856 2856 tcg_gen_st_tl(t, cpu_env, off);
2857 2857 }
2858 2858  
2859   -static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
  2859 +static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
2860 2860 {
2861 2861 const char *rn = "invalid";
2862 2862  
... ... @@ -2867,22 +2867,22 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2867 2867 case 0:
2868 2868 switch (sel) {
2869 2869 case 0:
2870   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Index));
  2870 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
2871 2871 rn = "Index";
2872 2872 break;
2873 2873 case 1:
2874 2874 check_insn(env, ctx, ASE_MT);
2875   - tcg_gen_helper_1_1(do_mfc0_mvpcontrol, cpu_T[0], cpu_T[0]);
  2875 + tcg_gen_helper_1_0(do_mfc0_mvpcontrol, t0);
2876 2876 rn = "MVPControl";
2877 2877 break;
2878 2878 case 2:
2879 2879 check_insn(env, ctx, ASE_MT);
2880   - tcg_gen_helper_1_1(do_mfc0_mvpconf0, cpu_T[0], cpu_T[0]);
  2880 + tcg_gen_helper_1_0(do_mfc0_mvpconf0, t0);
2881 2881 rn = "MVPConf0";
2882 2882 break;
2883 2883 case 3:
2884 2884 check_insn(env, ctx, ASE_MT);
2885   - tcg_gen_helper_1_1(do_mfc0_mvpconf1, cpu_T[0], cpu_T[0]);
  2885 + tcg_gen_helper_1_0(do_mfc0_mvpconf1, t0);
2886 2886 rn = "MVPConf1";
2887 2887 break;
2888 2888 default:
... ... @@ -2892,42 +2892,42 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2892 2892 case 1:
2893 2893 switch (sel) {
2894 2894 case 0:
2895   - tcg_gen_helper_1_1(do_mfc0_random, cpu_T[0], cpu_T[0]);
  2895 + tcg_gen_helper_1_0(do_mfc0_random, t0);
2896 2896 rn = "Random";
2897 2897 break;
2898 2898 case 1:
2899 2899 check_insn(env, ctx, ASE_MT);
2900   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEControl));
  2900 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
2901 2901 rn = "VPEControl";
2902 2902 break;
2903 2903 case 2:
2904 2904 check_insn(env, ctx, ASE_MT);
2905   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf0));
  2905 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
2906 2906 rn = "VPEConf0";
2907 2907 break;
2908 2908 case 3:
2909 2909 check_insn(env, ctx, ASE_MT);
2910   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf1));
  2910 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
2911 2911 rn = "VPEConf1";
2912 2912 break;
2913 2913 case 4:
2914 2914 check_insn(env, ctx, ASE_MT);
2915   - gen_mfc0_load64(cpu_T[0], offsetof(CPUState, CP0_YQMask));
  2915 + gen_mfc0_load64(t0, offsetof(CPUState, CP0_YQMask));
2916 2916 rn = "YQMask";
2917 2917 break;
2918 2918 case 5:
2919 2919 check_insn(env, ctx, ASE_MT);
2920   - gen_mfc0_load64(cpu_T[0], offsetof(CPUState, CP0_VPESchedule));
  2920 + gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPESchedule));
2921 2921 rn = "VPESchedule";
2922 2922 break;
2923 2923 case 6:
2924 2924 check_insn(env, ctx, ASE_MT);
2925   - gen_mfc0_load64(cpu_T[0], offsetof(CPUState, CP0_VPEScheFBack));
  2925 + gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPEScheFBack));
2926 2926 rn = "VPEScheFBack";
2927 2927 break;
2928 2928 case 7:
2929 2929 check_insn(env, ctx, ASE_MT);
2930   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEOpt));
  2930 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
2931 2931 rn = "VPEOpt";
2932 2932 break;
2933 2933 default:
... ... @@ -2937,43 +2937,43 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2937 2937 case 2:
2938 2938 switch (sel) {
2939 2939 case 0:
2940   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0));
2941   - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  2940 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
  2941 + tcg_gen_ext32s_tl(t0, t0);
2942 2942 rn = "EntryLo0";
2943 2943 break;
2944 2944 case 1:
2945 2945 check_insn(env, ctx, ASE_MT);
2946   - tcg_gen_helper_1_1(do_mfc0_tcstatus, cpu_T[0], cpu_T[0]);
  2946 + tcg_gen_helper_1_0(do_mfc0_tcstatus, t0);
2947 2947 rn = "TCStatus";
2948 2948 break;
2949 2949 case 2:
2950 2950 check_insn(env, ctx, ASE_MT);
2951   - tcg_gen_helper_1_1(do_mfc0_tcbind, cpu_T[0], cpu_T[0]);
  2951 + tcg_gen_helper_1_0(do_mfc0_tcbind, t0);
2952 2952 rn = "TCBind";
2953 2953 break;
2954 2954 case 3:
2955 2955 check_insn(env, ctx, ASE_MT);
2956   - tcg_gen_helper_1_1(do_mfc0_tcrestart, cpu_T[0], cpu_T[0]);
  2956 + tcg_gen_helper_1_0(do_mfc0_tcrestart, t0);
2957 2957 rn = "TCRestart";
2958 2958 break;
2959 2959 case 4:
2960 2960 check_insn(env, ctx, ASE_MT);
2961   - tcg_gen_helper_1_1(do_mfc0_tchalt, cpu_T[0], cpu_T[0]);
  2961 + tcg_gen_helper_1_0(do_mfc0_tchalt, t0);
2962 2962 rn = "TCHalt";
2963 2963 break;
2964 2964 case 5:
2965 2965 check_insn(env, ctx, ASE_MT);
2966   - tcg_gen_helper_1_1(do_mfc0_tccontext, cpu_T[0], cpu_T[0]);
  2966 + tcg_gen_helper_1_0(do_mfc0_tccontext, t0);
2967 2967 rn = "TCContext";
2968 2968 break;
2969 2969 case 6:
2970 2970 check_insn(env, ctx, ASE_MT);
2971   - tcg_gen_helper_1_1(do_mfc0_tcschedule, cpu_T[0], cpu_T[0]);
  2971 + tcg_gen_helper_1_0(do_mfc0_tcschedule, t0);
2972 2972 rn = "TCSchedule";
2973 2973 break;
2974 2974 case 7:
2975 2975 check_insn(env, ctx, ASE_MT);
2976   - tcg_gen_helper_1_1(do_mfc0_tcschefback, cpu_T[0], cpu_T[0]);
  2976 + tcg_gen_helper_1_0(do_mfc0_tcschefback, t0);
2977 2977 rn = "TCScheFBack";
2978 2978 break;
2979 2979 default:
... ... @@ -2983,8 +2983,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2983 2983 case 3:
2984 2984 switch (sel) {
2985 2985 case 0:
2986   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1));
2987   - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  2986 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
  2987 + tcg_gen_ext32s_tl(t0, t0);
2988 2988 rn = "EntryLo1";
2989 2989 break;
2990 2990 default:
... ... @@ -2994,12 +2994,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2994 2994 case 4:
2995 2995 switch (sel) {
2996 2996 case 0:
2997   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context));
2998   - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  2997 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
  2998 + tcg_gen_ext32s_tl(t0, t0);
2999 2999 rn = "Context";
3000 3000 break;
3001 3001 case 1:
3002   -// tcg_gen_helper_1_1(do_mfc0_contextconfig, cpu_T[0], cpu_T[0]); /* SmartMIPS ASE */
  3002 +// tcg_gen_helper_1_0(do_mfc0_contextconfig, t0); /* SmartMIPS ASE */
3003 3003 rn = "ContextConfig";
3004 3004 // break;
3005 3005 default:
... ... @@ -3009,12 +3009,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3009 3009 case 5:
3010 3010 switch (sel) {
3011 3011 case 0:
3012   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageMask));
  3012 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
3013 3013 rn = "PageMask";
3014 3014 break;
3015 3015 case 1:
3016 3016 check_insn(env, ctx, ISA_MIPS32R2);
3017   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageGrain));
  3017 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
3018 3018 rn = "PageGrain";
3019 3019 break;
3020 3020 default:
... ... @@ -3024,32 +3024,32 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3024 3024 case 6:
3025 3025 switch (sel) {
3026 3026 case 0:
3027   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Wired));
  3027 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
3028 3028 rn = "Wired";
3029 3029 break;
3030 3030 case 1:
3031 3031 check_insn(env, ctx, ISA_MIPS32R2);
3032   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf0));
  3032 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
3033 3033 rn = "SRSConf0";
3034 3034 break;
3035 3035 case 2:
3036 3036 check_insn(env, ctx, ISA_MIPS32R2);
3037   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf1));
  3037 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
3038 3038 rn = "SRSConf1";
3039 3039 break;
3040 3040 case 3:
3041 3041 check_insn(env, ctx, ISA_MIPS32R2);
3042   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf2));
  3042 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
3043 3043 rn = "SRSConf2";
3044 3044 break;
3045 3045 case 4:
3046 3046 check_insn(env, ctx, ISA_MIPS32R2);
3047   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf3));
  3047 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
3048 3048 rn = "SRSConf3";
3049 3049 break;
3050 3050 case 5:
3051 3051 check_insn(env, ctx, ISA_MIPS32R2);
3052   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf4));
  3052 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
3053 3053 rn = "SRSConf4";
3054 3054 break;
3055 3055 default:
... ... @@ -3060,7 +3060,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3060 3060 switch (sel) {
3061 3061 case 0:
3062 3062 check_insn(env, ctx, ISA_MIPS32R2);
3063   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_HWREna));
  3063 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
3064 3064 rn = "HWREna";
3065 3065 break;
3066 3066 default:
... ... @@ -3070,8 +3070,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3070 3070 case 8:
3071 3071 switch (sel) {
3072 3072 case 0:
3073   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr));
3074   - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  3073 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
  3074 + tcg_gen_ext32s_tl(t0, t0);
3075 3075 rn = "BadVAddr";
3076 3076 break;
3077 3077 default:
... ... @@ -3081,7 +3081,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3081 3081 case 9:
3082 3082 switch (sel) {
3083 3083 case 0:
3084   - tcg_gen_helper_1_1(do_mfc0_count, cpu_T[0], cpu_T[0]);
  3084 + tcg_gen_helper_1_0(do_mfc0_count, t0);
3085 3085 rn = "Count";
3086 3086 break;
3087 3087 /* 6,7 are implementation dependent */
... ... @@ -3092,8 +3092,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3092 3092 case 10:
3093 3093 switch (sel) {
3094 3094 case 0:
3095   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi));
3096   - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  3095 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
  3096 + tcg_gen_ext32s_tl(t0, t0);
3097 3097 rn = "EntryHi";
3098 3098 break;
3099 3099 default:
... ... @@ -3103,7 +3103,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3103 3103 case 11:
3104 3104 switch (sel) {
3105 3105 case 0:
3106   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Compare));
  3106 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
3107 3107 rn = "Compare";
3108 3108 break;
3109 3109 /* 6,7 are implementation dependent */
... ... @@ -3114,22 +3114,22 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3114 3114 case 12:
3115 3115 switch (sel) {
3116 3116 case 0:
3117   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Status));
  3117 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
3118 3118 rn = "Status";
3119 3119 break;
3120 3120 case 1:
3121 3121 check_insn(env, ctx, ISA_MIPS32R2);
3122   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_IntCtl));
  3122 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
3123 3123 rn = "IntCtl";
3124 3124 break;
3125 3125 case 2:
3126 3126 check_insn(env, ctx, ISA_MIPS32R2);
3127   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSCtl));
  3127 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
3128 3128 rn = "SRSCtl";
3129 3129 break;
3130 3130 case 3:
3131 3131 check_insn(env, ctx, ISA_MIPS32R2);
3132   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSMap));
  3132 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
3133 3133 rn = "SRSMap";
3134 3134 break;
3135 3135 default:
... ... @@ -3139,7 +3139,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3139 3139 case 13:
3140 3140 switch (sel) {
3141 3141 case 0:
3142   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Cause));
  3142 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
3143 3143 rn = "Cause";
3144 3144 break;
3145 3145 default:
... ... @@ -3149,8 +3149,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3149 3149 case 14:
3150 3150 switch (sel) {
3151 3151 case 0:
3152   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
3153   - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  3152 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
  3153 + tcg_gen_ext32s_tl(t0, t0);
3154 3154 rn = "EPC";
3155 3155 break;
3156 3156 default:
... ... @@ -3160,12 +3160,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3160 3160 case 15:
3161 3161 switch (sel) {
3162 3162 case 0:
3163   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PRid));
  3163 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
3164 3164 rn = "PRid";
3165 3165 break;
3166 3166 case 1:
3167 3167 check_insn(env, ctx, ISA_MIPS32R2);
3168   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_EBase));
  3168 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
3169 3169 rn = "EBase";
3170 3170 break;
3171 3171 default:
... ... @@ -3175,29 +3175,29 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3175 3175 case 16:
3176 3176 switch (sel) {
3177 3177 case 0:
3178   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config0));
  3178 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
3179 3179 rn = "Config";
3180 3180 break;
3181 3181 case 1:
3182   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config1));
  3182 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
3183 3183 rn = "Config1";
3184 3184 break;
3185 3185 case 2:
3186   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config2));
  3186 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
3187 3187 rn = "Config2";
3188 3188 break;
3189 3189 case 3:
3190   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config3));
  3190 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
3191 3191 rn = "Config3";
3192 3192 break;
3193 3193 /* 4,5 are reserved */
3194 3194 /* 6,7 are implementation dependent */
3195 3195 case 6:
3196   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config6));
  3196 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
3197 3197 rn = "Config6";
3198 3198 break;
3199 3199 case 7:
3200   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config7));
  3200 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
3201 3201 rn = "Config7";
3202 3202 break;
3203 3203 default:
... ... @@ -3207,7 +3207,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3207 3207 case 17:
3208 3208 switch (sel) {
3209 3209 case 0:
3210   - tcg_gen_helper_1_1(do_mfc0_lladdr, cpu_T[0], cpu_T[0]);
  3210 + tcg_gen_helper_1_0(do_mfc0_lladdr, t0);
3211 3211 rn = "LLAddr";
3212 3212 break;
3213 3213 default:
... ... @@ -3217,7 +3217,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3217 3217 case 18:
3218 3218 switch (sel) {
3219 3219 case 0 ... 7:
3220   - tcg_gen_helper_1_1i(do_mfc0_watchlo, cpu_T[0], cpu_T[0], sel);
  3220 + tcg_gen_helper_1_i(do_mfc0_watchlo, t0, sel);
3221 3221 rn = "WatchLo";
3222 3222 break;
3223 3223 default:
... ... @@ -3227,7 +3227,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3227 3227 case 19:
3228 3228 switch (sel) {
3229 3229 case 0 ...7:
3230   - tcg_gen_helper_1_1i(do_mfc0_watchhi, cpu_T[0], cpu_T[0], sel);
  3230 + tcg_gen_helper_1_i(do_mfc0_watchhi, t0, sel);
3231 3231 rn = "WatchHi";
3232 3232 break;
3233 3233 default:
... ... @@ -3239,8 +3239,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3239 3239 case 0:
3240 3240 #if defined(TARGET_MIPS64)
3241 3241 check_insn(env, ctx, ISA_MIPS3);
3242   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext));
3243   - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  3242 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
  3243 + tcg_gen_ext32s_tl(t0, t0);
3244 3244 rn = "XContext";
3245 3245 break;
3246 3246 #endif
... ... @@ -3252,7 +3252,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3252 3252 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3253 3253 switch (sel) {
3254 3254 case 0:
3255   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Framemask));
  3255 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
3256 3256 rn = "Framemask";
3257 3257 break;
3258 3258 default:
... ... @@ -3266,23 +3266,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3266 3266 case 23:
3267 3267 switch (sel) {
3268 3268 case 0:
3269   - tcg_gen_helper_1_1(do_mfc0_debug, cpu_T[0], cpu_T[0]); /* EJTAG support */
  3269 + tcg_gen_helper_1_0(do_mfc0_debug, t0); /* EJTAG support */
3270 3270 rn = "Debug";
3271 3271 break;
3272 3272 case 1:
3273   -// tcg_gen_helper_1_1(do_mfc0_tracecontrol, cpu_T[0], cpu_T[0]); /* PDtrace support */
  3273 +// tcg_gen_helper_1_0(do_mfc0_tracecontrol, t0); /* PDtrace support */
3274 3274 rn = "TraceControl";
3275 3275 // break;
3276 3276 case 2:
3277   -// tcg_gen_helper_1_1(do_mfc0_tracecontrol2, cpu_T[0], cpu_T[0]); /* PDtrace support */
  3277 +// tcg_gen_helper_1_0(do_mfc0_tracecontrol2, t0); /* PDtrace support */
3278 3278 rn = "TraceControl2";
3279 3279 // break;
3280 3280 case 3:
3281   -// tcg_gen_helper_1_1(do_mfc0_usertracedata, cpu_T[0], cpu_T[0]); /* PDtrace support */
  3281 +// tcg_gen_helper_1_0(do_mfc0_usertracedata, t0); /* PDtrace support */
3282 3282 rn = "UserTraceData";
3283 3283 // break;
3284 3284 case 4:
3285   -// tcg_gen_helper_1_1(do_mfc0_tracebpc, cpu_T[0], cpu_T[0]); /* PDtrace support */
  3285 +// tcg_gen_helper_1_0(do_mfc0_tracebpc, t0); /* PDtrace support */
3286 3286 rn = "TraceBPC";
3287 3287 // break;
3288 3288 default:
... ... @@ -3293,8 +3293,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3293 3293 switch (sel) {
3294 3294 case 0:
3295 3295 /* EJTAG support */
3296   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
3297   - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  3296 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
  3297 + tcg_gen_ext32s_tl(t0, t0);
3298 3298 rn = "DEPC";
3299 3299 break;
3300 3300 default:
... ... @@ -3304,35 +3304,35 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3304 3304 case 25:
3305 3305 switch (sel) {
3306 3306 case 0:
3307   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Performance0));
  3307 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
3308 3308 rn = "Performance0";
3309 3309 break;
3310 3310 case 1:
3311   -// tcg_gen_helper_1_1(do_mfc0_performance1, cpu_T[0], cpu_T[0]);
  3311 +// tcg_gen_helper_1_0(do_mfc0_performance1, t0);
3312 3312 rn = "Performance1";
3313 3313 // break;
3314 3314 case 2:
3315   -// tcg_gen_helper_1_1(do_mfc0_performance2, cpu_T[0], cpu_T[0]);
  3315 +// tcg_gen_helper_1_0(do_mfc0_performance2, t0);
3316 3316 rn = "Performance2";
3317 3317 // break;
3318 3318 case 3:
3319   -// tcg_gen_helper_1_1(do_mfc0_performance3, cpu_T[0], cpu_T[0]);
  3319 +// tcg_gen_helper_1_0(do_mfc0_performance3, t0);
3320 3320 rn = "Performance3";
3321 3321 // break;
3322 3322 case 4:
3323   -// tcg_gen_helper_1_1(do_mfc0_performance4, cpu_T[0], cpu_T[0]);
  3323 +// tcg_gen_helper_1_0(do_mfc0_performance4, t0);
3324 3324 rn = "Performance4";
3325 3325 // break;
3326 3326 case 5:
3327   -// tcg_gen_helper_1_1(do_mfc0_performance5, cpu_T[0], cpu_T[0]);
  3327 +// tcg_gen_helper_1_0(do_mfc0_performance5, t0);
3328 3328 rn = "Performance5";
3329 3329 // break;
3330 3330 case 6:
3331   -// tcg_gen_helper_1_1(do_mfc0_performance6, cpu_T[0], cpu_T[0]);
  3331 +// tcg_gen_helper_1_0(do_mfc0_performance6, t0);
3332 3332 rn = "Performance6";
3333 3333 // break;
3334 3334 case 7:
3335   -// tcg_gen_helper_1_1(do_mfc0_performance7, cpu_T[0], cpu_T[0]);
  3335 +// tcg_gen_helper_1_0(do_mfc0_performance7, t0);
3336 3336 rn = "Performance7";
3337 3337 // break;
3338 3338 default:
... ... @@ -3358,14 +3358,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3358 3358 case 2:
3359 3359 case 4:
3360 3360 case 6:
3361   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagLo));
  3361 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
3362 3362 rn = "TagLo";
3363 3363 break;
3364 3364 case 1:
3365 3365 case 3:
3366 3366 case 5:
3367 3367 case 7:
3368   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataLo));
  3368 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
3369 3369 rn = "DataLo";
3370 3370 break;
3371 3371 default:
... ... @@ -3378,14 +3378,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3378 3378 case 2:
3379 3379 case 4:
3380 3380 case 6:
3381   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagHi));
  3381 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
3382 3382 rn = "TagHi";
3383 3383 break;
3384 3384 case 1:
3385 3385 case 3:
3386 3386 case 5:
3387 3387 case 7:
3388   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataHi));
  3388 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
3389 3389 rn = "DataHi";
3390 3390 break;
3391 3391 default:
... ... @@ -3395,8 +3395,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3395 3395 case 30:
3396 3396 switch (sel) {
3397 3397 case 0:
3398   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
3399   - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
  3398 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
  3399 + tcg_gen_ext32s_tl(t0, t0);
3400 3400 rn = "ErrorEPC";
3401 3401 break;
3402 3402 default:
... ... @@ -3407,7 +3407,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3407 3407 switch (sel) {
3408 3408 case 0:
3409 3409 /* EJTAG support */
3410   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DESAVE));
  3410 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
3411 3411 rn = "DESAVE";
3412 3412 break;
3413 3413 default:
... ... @@ -3435,7 +3435,7 @@ die:
3435 3435 generate_exception(ctx, EXCP_RI);
3436 3436 }
3437 3437  
3438   -static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
  3438 +static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
3439 3439 {
3440 3440 const char *rn = "invalid";
3441 3441  
... ... @@ -3446,12 +3446,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3446 3446 case 0:
3447 3447 switch (sel) {
3448 3448 case 0:
3449   - tcg_gen_helper_0_1(do_mtc0_index, cpu_T[0]);
  3449 + tcg_gen_helper_0_1(do_mtc0_index, t0);
3450 3450 rn = "Index";
3451 3451 break;
3452 3452 case 1:
3453 3453 check_insn(env, ctx, ASE_MT);
3454   - tcg_gen_helper_0_1(do_mtc0_mvpcontrol, cpu_T[0]);
  3454 + tcg_gen_helper_0_1(do_mtc0_mvpcontrol, t0);
3455 3455 rn = "MVPControl";
3456 3456 break;
3457 3457 case 2:
... ... @@ -3476,37 +3476,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3476 3476 break;
3477 3477 case 1:
3478 3478 check_insn(env, ctx, ASE_MT);
3479   - tcg_gen_helper_0_1(do_mtc0_vpecontrol, cpu_T[0]);
  3479 + tcg_gen_helper_0_1(do_mtc0_vpecontrol, t0);
3480 3480 rn = "VPEControl";
3481 3481 break;
3482 3482 case 2:
3483 3483 check_insn(env, ctx, ASE_MT);
3484   - tcg_gen_helper_0_1(do_mtc0_vpeconf0, cpu_T[0]);
  3484 + tcg_gen_helper_0_1(do_mtc0_vpeconf0, t0);
3485 3485 rn = "VPEConf0";
3486 3486 break;
3487 3487 case 3:
3488 3488 check_insn(env, ctx, ASE_MT);
3489   - tcg_gen_helper_0_1(do_mtc0_vpeconf1, cpu_T[0]);
  3489 + tcg_gen_helper_0_1(do_mtc0_vpeconf1, t0);
3490 3490 rn = "VPEConf1";
3491 3491 break;
3492 3492 case 4:
3493 3493 check_insn(env, ctx, ASE_MT);
3494   - tcg_gen_helper_0_1(do_mtc0_yqmask, cpu_T[0]);
  3494 + tcg_gen_helper_0_1(do_mtc0_yqmask, t0);
3495 3495 rn = "YQMask";
3496 3496 break;
3497 3497 case 5:
3498 3498 check_insn(env, ctx, ASE_MT);
3499   - gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_VPESchedule));
  3499 + gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPESchedule));
3500 3500 rn = "VPESchedule";
3501 3501 break;
3502 3502 case 6:
3503 3503 check_insn(env, ctx, ASE_MT);
3504   - gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_VPEScheFBack));
  3504 + gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPEScheFBack));
3505 3505 rn = "VPEScheFBack";
3506 3506 break;
3507 3507 case 7:
3508 3508 check_insn(env, ctx, ASE_MT);
3509   - tcg_gen_helper_0_1(do_mtc0_vpeopt, cpu_T[0]);
  3509 + tcg_gen_helper_0_1(do_mtc0_vpeopt, t0);
3510 3510 rn = "VPEOpt";
3511 3511 break;
3512 3512 default:
... ... @@ -3516,42 +3516,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3516 3516 case 2:
3517 3517 switch (sel) {
3518 3518 case 0:
3519   - tcg_gen_helper_0_1(do_mtc0_entrylo0, cpu_T[0]);
  3519 + tcg_gen_helper_0_1(do_mtc0_entrylo0, t0);
3520 3520 rn = "EntryLo0";
3521 3521 break;
3522 3522 case 1:
3523 3523 check_insn(env, ctx, ASE_MT);
3524   - tcg_gen_helper_0_1(do_mtc0_tcstatus, cpu_T[0]);
  3524 + tcg_gen_helper_0_1(do_mtc0_tcstatus, t0);
3525 3525 rn = "TCStatus";
3526 3526 break;
3527 3527 case 2:
3528 3528 check_insn(env, ctx, ASE_MT);
3529   - tcg_gen_helper_0_1(do_mtc0_tcbind, cpu_T[0]);
  3529 + tcg_gen_helper_0_1(do_mtc0_tcbind, t0);
3530 3530 rn = "TCBind";
3531 3531 break;
3532 3532 case 3:
3533 3533 check_insn(env, ctx, ASE_MT);
3534   - tcg_gen_helper_0_1(do_mtc0_tcrestart, cpu_T[0]);
  3534 + tcg_gen_helper_0_1(do_mtc0_tcrestart, t0);
3535 3535 rn = "TCRestart";
3536 3536 break;
3537 3537 case 4:
3538 3538 check_insn(env, ctx, ASE_MT);
3539   - tcg_gen_helper_0_1(do_mtc0_tchalt, cpu_T[0]);
  3539 + tcg_gen_helper_0_1(do_mtc0_tchalt, t0);
3540 3540 rn = "TCHalt";
3541 3541 break;
3542 3542 case 5:
3543 3543 check_insn(env, ctx, ASE_MT);
3544   - tcg_gen_helper_0_1(do_mtc0_tccontext, cpu_T[0]);
  3544 + tcg_gen_helper_0_1(do_mtc0_tccontext, t0);
3545 3545 rn = "TCContext";
3546 3546 break;
3547 3547 case 6:
3548 3548 check_insn(env, ctx, ASE_MT);
3549   - tcg_gen_helper_0_1(do_mtc0_tcschedule, cpu_T[0]);
  3549 + tcg_gen_helper_0_1(do_mtc0_tcschedule, t0);
3550 3550 rn = "TCSchedule";
3551 3551 break;
3552 3552 case 7:
3553 3553 check_insn(env, ctx, ASE_MT);
3554   - tcg_gen_helper_0_1(do_mtc0_tcschefback, cpu_T[0]);
  3554 + tcg_gen_helper_0_1(do_mtc0_tcschefback, t0);
3555 3555 rn = "TCScheFBack";
3556 3556 break;
3557 3557 default:
... ... @@ -3561,7 +3561,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3561 3561 case 3:
3562 3562 switch (sel) {
3563 3563 case 0:
3564   - tcg_gen_helper_0_1(do_mtc0_entrylo1, cpu_T[0]);
  3564 + tcg_gen_helper_0_1(do_mtc0_entrylo1, t0);
3565 3565 rn = "EntryLo1";
3566 3566 break;
3567 3567 default:
... ... @@ -3571,11 +3571,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3571 3571 case 4:
3572 3572 switch (sel) {
3573 3573 case 0:
3574   - tcg_gen_helper_0_1(do_mtc0_context, cpu_T[0]);
  3574 + tcg_gen_helper_0_1(do_mtc0_context, t0);
3575 3575 rn = "Context";
3576 3576 break;
3577 3577 case 1:
3578   -// tcg_gen_helper_0_1(do_mtc0_contextconfig, cpu_T[0]); /* SmartMIPS ASE */
  3578 +// tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
3579 3579 rn = "ContextConfig";
3580 3580 // break;
3581 3581 default:
... ... @@ -3585,12 +3585,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3585 3585 case 5:
3586 3586 switch (sel) {
3587 3587 case 0:
3588   - tcg_gen_helper_0_1(do_mtc0_pagemask, cpu_T[0]);
  3588 + tcg_gen_helper_0_1(do_mtc0_pagemask, t0);
3589 3589 rn = "PageMask";
3590 3590 break;
3591 3591 case 1:
3592 3592 check_insn(env, ctx, ISA_MIPS32R2);
3593   - tcg_gen_helper_0_1(do_mtc0_pagegrain, cpu_T[0]);
  3593 + tcg_gen_helper_0_1(do_mtc0_pagegrain, t0);
3594 3594 rn = "PageGrain";
3595 3595 break;
3596 3596 default:
... ... @@ -3600,32 +3600,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3600 3600 case 6:
3601 3601 switch (sel) {
3602 3602 case 0:
3603   - tcg_gen_helper_0_1(do_mtc0_wired, cpu_T[0]);
  3603 + tcg_gen_helper_0_1(do_mtc0_wired, t0);
3604 3604 rn = "Wired";
3605 3605 break;
3606 3606 case 1:
3607 3607 check_insn(env, ctx, ISA_MIPS32R2);
3608   - tcg_gen_helper_0_1(do_mtc0_srsconf0, cpu_T[0]);
  3608 + tcg_gen_helper_0_1(do_mtc0_srsconf0, t0);
3609 3609 rn = "SRSConf0";
3610 3610 break;
3611 3611 case 2:
3612 3612 check_insn(env, ctx, ISA_MIPS32R2);
3613   - tcg_gen_helper_0_1(do_mtc0_srsconf1, cpu_T[0]);
  3613 + tcg_gen_helper_0_1(do_mtc0_srsconf1, t0);
3614 3614 rn = "SRSConf1";
3615 3615 break;
3616 3616 case 3:
3617 3617 check_insn(env, ctx, ISA_MIPS32R2);
3618   - tcg_gen_helper_0_1(do_mtc0_srsconf2, cpu_T[0]);
  3618 + tcg_gen_helper_0_1(do_mtc0_srsconf2, t0);
3619 3619 rn = "SRSConf2";
3620 3620 break;
3621 3621 case 4:
3622 3622 check_insn(env, ctx, ISA_MIPS32R2);
3623   - tcg_gen_helper_0_1(do_mtc0_srsconf3, cpu_T[0]);
  3623 + tcg_gen_helper_0_1(do_mtc0_srsconf3, t0);
3624 3624 rn = "SRSConf3";
3625 3625 break;
3626 3626 case 5:
3627 3627 check_insn(env, ctx, ISA_MIPS32R2);
3628   - tcg_gen_helper_0_1(do_mtc0_srsconf4, cpu_T[0]);
  3628 + tcg_gen_helper_0_1(do_mtc0_srsconf4, t0);
3629 3629 rn = "SRSConf4";
3630 3630 break;
3631 3631 default:
... ... @@ -3636,7 +3636,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3636 3636 switch (sel) {
3637 3637 case 0:
3638 3638 check_insn(env, ctx, ISA_MIPS32R2);
3639   - tcg_gen_helper_0_1(do_mtc0_hwrena, cpu_T[0]);
  3639 + tcg_gen_helper_0_1(do_mtc0_hwrena, t0);
3640 3640 rn = "HWREna";
3641 3641 break;
3642 3642 default:
... ... @@ -3650,7 +3650,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3650 3650 case 9:
3651 3651 switch (sel) {
3652 3652 case 0:
3653   - tcg_gen_helper_0_1(do_mtc0_count, cpu_T[0]);
  3653 + tcg_gen_helper_0_1(do_mtc0_count, t0);
3654 3654 rn = "Count";
3655 3655 break;
3656 3656 /* 6,7 are implementation dependent */
... ... @@ -3663,7 +3663,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3663 3663 case 10:
3664 3664 switch (sel) {
3665 3665 case 0:
3666   - tcg_gen_helper_0_1(do_mtc0_entryhi, cpu_T[0]);
  3666 + tcg_gen_helper_0_1(do_mtc0_entryhi, t0);
3667 3667 rn = "EntryHi";
3668 3668 break;
3669 3669 default:
... ... @@ -3673,7 +3673,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3673 3673 case 11:
3674 3674 switch (sel) {
3675 3675 case 0:
3676   - tcg_gen_helper_0_1(do_mtc0_compare, cpu_T[0]);
  3676 + tcg_gen_helper_0_1(do_mtc0_compare, t0);
3677 3677 rn = "Compare";
3678 3678 break;
3679 3679 /* 6,7 are implementation dependent */
... ... @@ -3686,7 +3686,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3686 3686 case 12:
3687 3687 switch (sel) {
3688 3688 case 0:
3689   - tcg_gen_helper_0_1(do_mtc0_status, cpu_T[0]);
  3689 + tcg_gen_helper_0_1(do_mtc0_status, t0);
3690 3690 /* BS_STOP isn't good enough here, hflags may have changed. */
3691 3691 gen_save_pc(ctx->pc + 4);
3692 3692 ctx->bstate = BS_EXCP;
... ... @@ -3694,21 +3694,21 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3694 3694 break;
3695 3695 case 1:
3696 3696 check_insn(env, ctx, ISA_MIPS32R2);
3697   - tcg_gen_helper_0_1(do_mtc0_intctl, cpu_T[0]);
  3697 + tcg_gen_helper_0_1(do_mtc0_intctl, t0);
3698 3698 /* Stop translation as we may have switched the execution mode */
3699 3699 ctx->bstate = BS_STOP;
3700 3700 rn = "IntCtl";
3701 3701 break;
3702 3702 case 2:
3703 3703 check_insn(env, ctx, ISA_MIPS32R2);
3704   - tcg_gen_helper_0_1(do_mtc0_srsctl, cpu_T[0]);
  3704 + tcg_gen_helper_0_1(do_mtc0_srsctl, t0);
3705 3705 /* Stop translation as we may have switched the execution mode */
3706 3706 ctx->bstate = BS_STOP;
3707 3707 rn = "SRSCtl";
3708 3708 break;
3709 3709 case 3:
3710 3710 check_insn(env, ctx, ISA_MIPS32R2);
3711   - gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_SRSMap));
  3711 + gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
3712 3712 /* Stop translation as we may have switched the execution mode */
3713 3713 ctx->bstate = BS_STOP;
3714 3714 rn = "SRSMap";
... ... @@ -3720,7 +3720,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3720 3720 case 13:
3721 3721 switch (sel) {
3722 3722 case 0:
3723   - tcg_gen_helper_0_1(do_mtc0_cause, cpu_T[0]);
  3723 + tcg_gen_helper_0_1(do_mtc0_cause, t0);
3724 3724 rn = "Cause";
3725 3725 break;
3726 3726 default:
... ... @@ -3732,7 +3732,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3732 3732 case 14:
3733 3733 switch (sel) {
3734 3734 case 0:
3735   - gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_EPC));
  3735 + gen_mtc0_store64(t0, offsetof(CPUState, CP0_EPC));
3736 3736 rn = "EPC";
3737 3737 break;
3738 3738 default:
... ... @@ -3747,7 +3747,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3747 3747 break;
3748 3748 case 1:
3749 3749 check_insn(env, ctx, ISA_MIPS32R2);
3750   - tcg_gen_helper_0_1(do_mtc0_ebase, cpu_T[0]);
  3750 + tcg_gen_helper_0_1(do_mtc0_ebase, t0);
3751 3751 rn = "EBase";
3752 3752 break;
3753 3753 default:
... ... @@ -3757,7 +3757,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3757 3757 case 16:
3758 3758 switch (sel) {
3759 3759 case 0:
3760   - tcg_gen_helper_0_1(do_mtc0_config0, cpu_T[0]);
  3760 + tcg_gen_helper_0_1(do_mtc0_config0, t0);
3761 3761 rn = "Config";
3762 3762 /* Stop translation as we may have switched the execution mode */
3763 3763 ctx->bstate = BS_STOP;
... ... @@ -3767,7 +3767,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3767 3767 rn = "Config1";
3768 3768 break;
3769 3769 case 2:
3770   - tcg_gen_helper_0_1(do_mtc0_config2, cpu_T[0]);
  3770 + tcg_gen_helper_0_1(do_mtc0_config2, t0);
3771 3771 rn = "Config2";
3772 3772 /* Stop translation as we may have switched the execution mode */
3773 3773 ctx->bstate = BS_STOP;
... ... @@ -3804,7 +3804,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3804 3804 case 18:
3805 3805 switch (sel) {
3806 3806 case 0 ... 7:
3807   - tcg_gen_helper_0_1i(do_mtc0_watchlo, cpu_T[0], sel);
  3807 + tcg_gen_helper_0_1i(do_mtc0_watchlo, t0, sel);
3808 3808 rn = "WatchLo";
3809 3809 break;
3810 3810 default:
... ... @@ -3814,7 +3814,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3814 3814 case 19:
3815 3815 switch (sel) {
3816 3816 case 0 ... 7:
3817   - tcg_gen_helper_0_1i(do_mtc0_watchhi, cpu_T[0], sel);
  3817 + tcg_gen_helper_0_1i(do_mtc0_watchhi, t0, sel);
3818 3818 rn = "WatchHi";
3819 3819 break;
3820 3820 default:
... ... @@ -3826,7 +3826,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3826 3826 case 0:
3827 3827 #if defined(TARGET_MIPS64)
3828 3828 check_insn(env, ctx, ISA_MIPS3);
3829   - tcg_gen_helper_0_1(do_mtc0_xcontext, cpu_T[0]);
  3829 + tcg_gen_helper_0_1(do_mtc0_xcontext, t0);
3830 3830 rn = "XContext";
3831 3831 break;
3832 3832 #endif
... ... @@ -3838,7 +3838,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3838 3838 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3839 3839 switch (sel) {
3840 3840 case 0:
3841   - tcg_gen_helper_0_1(do_mtc0_framemask, cpu_T[0]);
  3841 + tcg_gen_helper_0_1(do_mtc0_framemask, t0);
3842 3842 rn = "Framemask";
3843 3843 break;
3844 3844 default:
... ... @@ -3852,20 +3852,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3852 3852 case 23:
3853 3853 switch (sel) {
3854 3854 case 0:
3855   - tcg_gen_helper_0_1(do_mtc0_debug, cpu_T[0]); /* EJTAG support */
  3855 + tcg_gen_helper_0_1(do_mtc0_debug, t0); /* EJTAG support */
3856 3856 /* BS_STOP isn't good enough here, hflags may have changed. */
3857 3857 gen_save_pc(ctx->pc + 4);
3858 3858 ctx->bstate = BS_EXCP;
3859 3859 rn = "Debug";
3860 3860 break;
3861 3861 case 1:
3862   -// tcg_gen_helper_0_1(do_mtc0_tracecontrol, cpu_T[0]); /* PDtrace support */
  3862 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
3863 3863 rn = "TraceControl";
3864 3864 /* Stop translation as we may have switched the execution mode */
3865 3865 ctx->bstate = BS_STOP;
3866 3866 // break;
3867 3867 case 2:
3868   -// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, cpu_T[0]); /* PDtrace support */
  3868 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
3869 3869 rn = "TraceControl2";
3870 3870 /* Stop translation as we may have switched the execution mode */
3871 3871 ctx->bstate = BS_STOP;
... ... @@ -3873,13 +3873,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3873 3873 case 3:
3874 3874 /* Stop translation as we may have switched the execution mode */
3875 3875 ctx->bstate = BS_STOP;
3876   -// tcg_gen_helper_0_1(do_mtc0_usertracedata, cpu_T[0]); /* PDtrace support */
  3876 +// tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
3877 3877 rn = "UserTraceData";
3878 3878 /* Stop translation as we may have switched the execution mode */
3879 3879 ctx->bstate = BS_STOP;
3880 3880 // break;
3881 3881 case 4:
3882   -// tcg_gen_helper_0_1(do_mtc0_tracebpc, cpu_T[0]); /* PDtrace support */
  3882 +// tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
3883 3883 /* Stop translation as we may have switched the execution mode */
3884 3884 ctx->bstate = BS_STOP;
3885 3885 rn = "TraceBPC";
... ... @@ -3892,7 +3892,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3892 3892 switch (sel) {
3893 3893 case 0:
3894 3894 /* EJTAG support */
3895   - gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_DEPC));
  3895 + gen_mtc0_store64(t0, offsetof(CPUState, CP0_DEPC));
3896 3896 rn = "DEPC";
3897 3897 break;
3898 3898 default:
... ... @@ -3902,35 +3902,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3902 3902 case 25:
3903 3903 switch (sel) {
3904 3904 case 0:
3905   - tcg_gen_helper_0_1(do_mtc0_performance0, cpu_T[0]);
  3905 + tcg_gen_helper_0_1(do_mtc0_performance0, t0);
3906 3906 rn = "Performance0";
3907 3907 break;
3908 3908 case 1:
3909   -// tcg_gen_helper_0_1(do_mtc0_performance1, cpu_T[0]);
  3909 +// tcg_gen_helper_0_1(do_mtc0_performance1, t0);
3910 3910 rn = "Performance1";
3911 3911 // break;
3912 3912 case 2:
3913   -// tcg_gen_helper_0_1(do_mtc0_performance2, cpu_T[0]);
  3913 +// tcg_gen_helper_0_1(do_mtc0_performance2, t0);
3914 3914 rn = "Performance2";
3915 3915 // break;
3916 3916 case 3:
3917   -// tcg_gen_helper_0_1(do_mtc0_performance3, cpu_T[0]);
  3917 +// tcg_gen_helper_0_1(do_mtc0_performance3, t0);
3918 3918 rn = "Performance3";
3919 3919 // break;
3920 3920 case 4:
3921   -// tcg_gen_helper_0_1(do_mtc0_performance4, cpu_T[0]);
  3921 +// tcg_gen_helper_0_1(do_mtc0_performance4, t0);
3922 3922 rn = "Performance4";
3923 3923 // break;
3924 3924 case 5:
3925   -// tcg_gen_helper_0_1(do_mtc0_performance5, cpu_T[0]);
  3925 +// tcg_gen_helper_0_1(do_mtc0_performance5, t0);
3926 3926 rn = "Performance5";
3927 3927 // break;
3928 3928 case 6:
3929   -// tcg_gen_helper_0_1(do_mtc0_performance6, cpu_T[0]);
  3929 +// tcg_gen_helper_0_1(do_mtc0_performance6, t0);
3930 3930 rn = "Performance6";
3931 3931 // break;
3932 3932 case 7:
3933   -// tcg_gen_helper_0_1(do_mtc0_performance7, cpu_T[0]);
  3933 +// tcg_gen_helper_0_1(do_mtc0_performance7, t0);
3934 3934 rn = "Performance7";
3935 3935 // break;
3936 3936 default:
... ... @@ -3957,14 +3957,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3957 3957 case 2:
3958 3958 case 4:
3959 3959 case 6:
3960   - tcg_gen_helper_0_1(do_mtc0_taglo, cpu_T[0]);
  3960 + tcg_gen_helper_0_1(do_mtc0_taglo, t0);
3961 3961 rn = "TagLo";
3962 3962 break;
3963 3963 case 1:
3964 3964 case 3:
3965 3965 case 5:
3966 3966 case 7:
3967   - tcg_gen_helper_0_1(do_mtc0_datalo, cpu_T[0]);
  3967 + tcg_gen_helper_0_1(do_mtc0_datalo, t0);
3968 3968 rn = "DataLo";
3969 3969 break;
3970 3970 default:
... ... @@ -3977,14 +3977,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3977 3977 case 2:
3978 3978 case 4:
3979 3979 case 6:
3980   - tcg_gen_helper_0_1(do_mtc0_taghi, cpu_T[0]);
  3980 + tcg_gen_helper_0_1(do_mtc0_taghi, t0);
3981 3981 rn = "TagHi";
3982 3982 break;
3983 3983 case 1:
3984 3984 case 3:
3985 3985 case 5:
3986 3986 case 7:
3987   - tcg_gen_helper_0_1(do_mtc0_datahi, cpu_T[0]);
  3987 + tcg_gen_helper_0_1(do_mtc0_datahi, t0);
3988 3988 rn = "DataHi";
3989 3989 break;
3990 3990 default:
... ... @@ -3995,7 +3995,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3995 3995 case 30:
3996 3996 switch (sel) {
3997 3997 case 0:
3998   - gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_ErrorEPC));
  3998 + gen_mtc0_store64(t0, offsetof(CPUState, CP0_ErrorEPC));
3999 3999 rn = "ErrorEPC";
4000 4000 break;
4001 4001 default:
... ... @@ -4006,7 +4006,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4006 4006 switch (sel) {
4007 4007 case 0:
4008 4008 /* EJTAG support */
4009   - gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_DESAVE));
  4009 + gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
4010 4010 rn = "DESAVE";
4011 4011 break;
4012 4012 default:
... ... @@ -4037,7 +4037,7 @@ die:
4037 4037 }
4038 4038  
4039 4039 #if defined(TARGET_MIPS64)
4040   -static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
  4040 +static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
4041 4041 {
4042 4042 const char *rn = "invalid";
4043 4043  
... ... @@ -4048,22 +4048,22 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4048 4048 case 0:
4049 4049 switch (sel) {
4050 4050 case 0:
4051   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Index));
  4051 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
4052 4052 rn = "Index";
4053 4053 break;
4054 4054 case 1:
4055 4055 check_insn(env, ctx, ASE_MT);
4056   - tcg_gen_helper_1_1(do_mfc0_mvpcontrol, cpu_T[0], cpu_T[0]);
  4056 + tcg_gen_helper_1_0(do_mfc0_mvpcontrol, t0);
4057 4057 rn = "MVPControl";
4058 4058 break;
4059 4059 case 2:
4060 4060 check_insn(env, ctx, ASE_MT);
4061   - tcg_gen_helper_1_1(do_mfc0_mvpconf0, cpu_T[0], cpu_T[0]);
  4061 + tcg_gen_helper_1_0(do_mfc0_mvpconf0, t0);
4062 4062 rn = "MVPConf0";
4063 4063 break;
4064 4064 case 3:
4065 4065 check_insn(env, ctx, ASE_MT);
4066   - tcg_gen_helper_1_1(do_mfc0_mvpconf1, cpu_T[0], cpu_T[0]);
  4066 + tcg_gen_helper_1_0(do_mfc0_mvpconf1, t0);
4067 4067 rn = "MVPConf1";
4068 4068 break;
4069 4069 default:
... ... @@ -4073,42 +4073,42 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4073 4073 case 1:
4074 4074 switch (sel) {
4075 4075 case 0:
4076   - tcg_gen_helper_1_1(do_mfc0_random, cpu_T[0], cpu_T[0]);
  4076 + tcg_gen_helper_1_0(do_mfc0_random, t0);
4077 4077 rn = "Random";
4078 4078 break;
4079 4079 case 1:
4080 4080 check_insn(env, ctx, ASE_MT);
4081   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEControl));
  4081 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
4082 4082 rn = "VPEControl";
4083 4083 break;
4084 4084 case 2:
4085 4085 check_insn(env, ctx, ASE_MT);
4086   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf0));
  4086 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
4087 4087 rn = "VPEConf0";
4088 4088 break;
4089 4089 case 3:
4090 4090 check_insn(env, ctx, ASE_MT);
4091   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf1));
  4091 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
4092 4092 rn = "VPEConf1";
4093 4093 break;
4094 4094 case 4:
4095 4095 check_insn(env, ctx, ASE_MT);
4096   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_YQMask));
  4096 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_YQMask));
4097 4097 rn = "YQMask";
4098 4098 break;
4099 4099 case 5:
4100 4100 check_insn(env, ctx, ASE_MT);
4101   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule));
  4101 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4102 4102 rn = "VPESchedule";
4103 4103 break;
4104 4104 case 6:
4105 4105 check_insn(env, ctx, ASE_MT);
4106   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
  4106 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4107 4107 rn = "VPEScheFBack";
4108 4108 break;
4109 4109 case 7:
4110 4110 check_insn(env, ctx, ASE_MT);
4111   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEOpt));
  4111 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
4112 4112 rn = "VPEOpt";
4113 4113 break;
4114 4114 default:
... ... @@ -4118,42 +4118,42 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4118 4118 case 2:
4119 4119 switch (sel) {
4120 4120 case 0:
4121   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0));
  4121 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
4122 4122 rn = "EntryLo0";
4123 4123 break;
4124 4124 case 1:
4125 4125 check_insn(env, ctx, ASE_MT);
4126   - tcg_gen_helper_1_1(do_mfc0_tcstatus, cpu_T[0], cpu_T[0]);
  4126 + tcg_gen_helper_1_0(do_mfc0_tcstatus, t0);
4127 4127 rn = "TCStatus";
4128 4128 break;
4129 4129 case 2:
4130 4130 check_insn(env, ctx, ASE_MT);
4131   - tcg_gen_helper_1_1(do_mfc0_tcbind, cpu_T[0], cpu_T[0]);
  4131 + tcg_gen_helper_1_0(do_mfc0_tcbind, t0);
4132 4132 rn = "TCBind";
4133 4133 break;
4134 4134 case 3:
4135 4135 check_insn(env, ctx, ASE_MT);
4136   - tcg_gen_helper_1_1(do_dmfc0_tcrestart, cpu_T[0], cpu_T[0]);
  4136 + tcg_gen_helper_1_0(do_dmfc0_tcrestart, t0);
4137 4137 rn = "TCRestart";
4138 4138 break;
4139 4139 case 4:
4140 4140 check_insn(env, ctx, ASE_MT);
4141   - tcg_gen_helper_1_1(do_dmfc0_tchalt, cpu_T[0], cpu_T[0]);
  4141 + tcg_gen_helper_1_0(do_dmfc0_tchalt, t0);
4142 4142 rn = "TCHalt";
4143 4143 break;
4144 4144 case 5:
4145 4145 check_insn(env, ctx, ASE_MT);
4146   - tcg_gen_helper_1_1(do_dmfc0_tccontext, cpu_T[0], cpu_T[0]);
  4146 + tcg_gen_helper_1_0(do_dmfc0_tccontext, t0);
4147 4147 rn = "TCContext";
4148 4148 break;
4149 4149 case 6:
4150 4150 check_insn(env, ctx, ASE_MT);
4151   - tcg_gen_helper_1_1(do_dmfc0_tcschedule, cpu_T[0], cpu_T[0]);
  4151 + tcg_gen_helper_1_0(do_dmfc0_tcschedule, t0);
4152 4152 rn = "TCSchedule";
4153 4153 break;
4154 4154 case 7:
4155 4155 check_insn(env, ctx, ASE_MT);
4156   - tcg_gen_helper_1_1(do_dmfc0_tcschefback, cpu_T[0], cpu_T[0]);
  4156 + tcg_gen_helper_1_0(do_dmfc0_tcschefback, t0);
4157 4157 rn = "TCScheFBack";
4158 4158 break;
4159 4159 default:
... ... @@ -4163,7 +4163,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4163 4163 case 3:
4164 4164 switch (sel) {
4165 4165 case 0:
4166   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1));
  4166 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
4167 4167 rn = "EntryLo1";
4168 4168 break;
4169 4169 default:
... ... @@ -4173,11 +4173,11 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4173 4173 case 4:
4174 4174 switch (sel) {
4175 4175 case 0:
4176   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context));
  4176 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
4177 4177 rn = "Context";
4178 4178 break;
4179 4179 case 1:
4180   -// tcg_gen_helper_1_1(do_dmfc0_contextconfig, cpu_T[0], cpu_T[0]); /* SmartMIPS ASE */
  4180 +// tcg_gen_helper_1_0(do_dmfc0_contextconfig, t0); /* SmartMIPS ASE */
4181 4181 rn = "ContextConfig";
4182 4182 // break;
4183 4183 default:
... ... @@ -4187,12 +4187,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4187 4187 case 5:
4188 4188 switch (sel) {
4189 4189 case 0:
4190   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageMask));
  4190 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
4191 4191 rn = "PageMask";
4192 4192 break;
4193 4193 case 1:
4194 4194 check_insn(env, ctx, ISA_MIPS32R2);
4195   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageGrain));
  4195 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
4196 4196 rn = "PageGrain";
4197 4197 break;
4198 4198 default:
... ... @@ -4202,32 +4202,32 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4202 4202 case 6:
4203 4203 switch (sel) {
4204 4204 case 0:
4205   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Wired));
  4205 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
4206 4206 rn = "Wired";
4207 4207 break;
4208 4208 case 1:
4209 4209 check_insn(env, ctx, ISA_MIPS32R2);
4210   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf0));
  4210 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
4211 4211 rn = "SRSConf0";
4212 4212 break;
4213 4213 case 2:
4214 4214 check_insn(env, ctx, ISA_MIPS32R2);
4215   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf1));
  4215 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
4216 4216 rn = "SRSConf1";
4217 4217 break;
4218 4218 case 3:
4219 4219 check_insn(env, ctx, ISA_MIPS32R2);
4220   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf2));
  4220 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
4221 4221 rn = "SRSConf2";
4222 4222 break;
4223 4223 case 4:
4224 4224 check_insn(env, ctx, ISA_MIPS32R2);
4225   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf3));
  4225 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
4226 4226 rn = "SRSConf3";
4227 4227 break;
4228 4228 case 5:
4229 4229 check_insn(env, ctx, ISA_MIPS32R2);
4230   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf4));
  4230 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
4231 4231 rn = "SRSConf4";
4232 4232 break;
4233 4233 default:
... ... @@ -4238,7 +4238,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4238 4238 switch (sel) {
4239 4239 case 0:
4240 4240 check_insn(env, ctx, ISA_MIPS32R2);
4241   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_HWREna));
  4241 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
4242 4242 rn = "HWREna";
4243 4243 break;
4244 4244 default:
... ... @@ -4248,7 +4248,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4248 4248 case 8:
4249 4249 switch (sel) {
4250 4250 case 0:
4251   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr));
  4251 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
4252 4252 rn = "BadVAddr";
4253 4253 break;
4254 4254 default:
... ... @@ -4258,7 +4258,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4258 4258 case 9:
4259 4259 switch (sel) {
4260 4260 case 0:
4261   - tcg_gen_helper_1_1(do_mfc0_count, cpu_T[0], cpu_T[0]);
  4261 + tcg_gen_helper_1_0(do_mfc0_count, t0);
4262 4262 rn = "Count";
4263 4263 break;
4264 4264 /* 6,7 are implementation dependent */
... ... @@ -4269,7 +4269,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4269 4269 case 10:
4270 4270 switch (sel) {
4271 4271 case 0:
4272   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi));
  4272 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
4273 4273 rn = "EntryHi";
4274 4274 break;
4275 4275 default:
... ... @@ -4279,7 +4279,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4279 4279 case 11:
4280 4280 switch (sel) {
4281 4281 case 0:
4282   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Compare));
  4282 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
4283 4283 rn = "Compare";
4284 4284 break;
4285 4285 /* 6,7 are implementation dependent */
... ... @@ -4290,22 +4290,22 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4290 4290 case 12:
4291 4291 switch (sel) {
4292 4292 case 0:
4293   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Status));
  4293 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
4294 4294 rn = "Status";
4295 4295 break;
4296 4296 case 1:
4297 4297 check_insn(env, ctx, ISA_MIPS32R2);
4298   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_IntCtl));
  4298 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
4299 4299 rn = "IntCtl";
4300 4300 break;
4301 4301 case 2:
4302 4302 check_insn(env, ctx, ISA_MIPS32R2);
4303   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSCtl));
  4303 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
4304 4304 rn = "SRSCtl";
4305 4305 break;
4306 4306 case 3:
4307 4307 check_insn(env, ctx, ISA_MIPS32R2);
4308   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSMap));
  4308 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
4309 4309 rn = "SRSMap";
4310 4310 break;
4311 4311 default:
... ... @@ -4315,7 +4315,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4315 4315 case 13:
4316 4316 switch (sel) {
4317 4317 case 0:
4318   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Cause));
  4318 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
4319 4319 rn = "Cause";
4320 4320 break;
4321 4321 default:
... ... @@ -4325,7 +4325,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4325 4325 case 14:
4326 4326 switch (sel) {
4327 4327 case 0:
4328   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
  4328 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
4329 4329 rn = "EPC";
4330 4330 break;
4331 4331 default:
... ... @@ -4335,12 +4335,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4335 4335 case 15:
4336 4336 switch (sel) {
4337 4337 case 0:
4338   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PRid));
  4338 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
4339 4339 rn = "PRid";
4340 4340 break;
4341 4341 case 1:
4342 4342 check_insn(env, ctx, ISA_MIPS32R2);
4343   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_EBase));
  4343 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
4344 4344 rn = "EBase";
4345 4345 break;
4346 4346 default:
... ... @@ -4350,28 +4350,28 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4350 4350 case 16:
4351 4351 switch (sel) {
4352 4352 case 0:
4353   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config0));
  4353 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
4354 4354 rn = "Config";
4355 4355 break;
4356 4356 case 1:
4357   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config1));
  4357 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
4358 4358 rn = "Config1";
4359 4359 break;
4360 4360 case 2:
4361   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config2));
  4361 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
4362 4362 rn = "Config2";
4363 4363 break;
4364 4364 case 3:
4365   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config3));
  4365 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
4366 4366 rn = "Config3";
4367 4367 break;
4368 4368 /* 6,7 are implementation dependent */
4369 4369 case 6:
4370   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config6));
  4370 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
4371 4371 rn = "Config6";
4372 4372 break;
4373 4373 case 7:
4374   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config7));
  4374 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
4375 4375 rn = "Config7";
4376 4376 break;
4377 4377 default:
... ... @@ -4381,7 +4381,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4381 4381 case 17:
4382 4382 switch (sel) {
4383 4383 case 0:
4384   - tcg_gen_helper_1_1(do_dmfc0_lladdr, cpu_T[0], cpu_T[0]);
  4384 + tcg_gen_helper_1_0(do_dmfc0_lladdr, t0);
4385 4385 rn = "LLAddr";
4386 4386 break;
4387 4387 default:
... ... @@ -4391,7 +4391,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4391 4391 case 18:
4392 4392 switch (sel) {
4393 4393 case 0 ... 7:
4394   - tcg_gen_helper_1_1i(do_dmfc0_watchlo, cpu_T[0], cpu_T[0], sel);
  4394 + tcg_gen_helper_1_i(do_dmfc0_watchlo, t0, sel);
4395 4395 rn = "WatchLo";
4396 4396 break;
4397 4397 default:
... ... @@ -4401,7 +4401,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4401 4401 case 19:
4402 4402 switch (sel) {
4403 4403 case 0 ... 7:
4404   - tcg_gen_helper_1_1i(do_mfc0_watchhi, cpu_T[0], cpu_T[0], sel);
  4404 + tcg_gen_helper_1_i(do_mfc0_watchhi, t0, sel);
4405 4405 rn = "WatchHi";
4406 4406 break;
4407 4407 default:
... ... @@ -4412,7 +4412,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4412 4412 switch (sel) {
4413 4413 case 0:
4414 4414 check_insn(env, ctx, ISA_MIPS3);
4415   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext));
  4415 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
4416 4416 rn = "XContext";
4417 4417 break;
4418 4418 default:
... ... @@ -4423,7 +4423,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4423 4423 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4424 4424 switch (sel) {
4425 4425 case 0:
4426   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Framemask));
  4426 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
4427 4427 rn = "Framemask";
4428 4428 break;
4429 4429 default:
... ... @@ -4437,23 +4437,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4437 4437 case 23:
4438 4438 switch (sel) {
4439 4439 case 0:
4440   - tcg_gen_helper_1_1(do_mfc0_debug, cpu_T[0], cpu_T[0]); /* EJTAG support */
  4440 + tcg_gen_helper_1_0(do_mfc0_debug, t0); /* EJTAG support */
4441 4441 rn = "Debug";
4442 4442 break;
4443 4443 case 1:
4444   -// tcg_gen_helper_1_1(do_dmfc0_tracecontrol, cpu_T[0], cpu_T[0]); /* PDtrace support */
  4444 +// tcg_gen_helper_1_0(do_dmfc0_tracecontrol, t0); /* PDtrace support */
4445 4445 rn = "TraceControl";
4446 4446 // break;
4447 4447 case 2:
4448   -// tcg_gen_helper_1_1(do_dmfc0_tracecontrol2, cpu_T[0], cpu_T[0]); /* PDtrace support */
  4448 +// tcg_gen_helper_1_0(do_dmfc0_tracecontrol2, t0); /* PDtrace support */
4449 4449 rn = "TraceControl2";
4450 4450 // break;
4451 4451 case 3:
4452   -// tcg_gen_helper_1_1(do_dmfc0_usertracedata, cpu_T[0], cpu_T[0]); /* PDtrace support */
  4452 +// tcg_gen_helper_1_0(do_dmfc0_usertracedata, t0); /* PDtrace support */
4453 4453 rn = "UserTraceData";
4454 4454 // break;
4455 4455 case 4:
4456   -// tcg_gen_helper_1_1(do_dmfc0_tracebpc, cpu_T[0], cpu_T[0]); /* PDtrace support */
  4456 +// tcg_gen_helper_1_0(do_dmfc0_tracebpc, t0); /* PDtrace support */
4457 4457 rn = "TraceBPC";
4458 4458 // break;
4459 4459 default:
... ... @@ -4464,7 +4464,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4464 4464 switch (sel) {
4465 4465 case 0:
4466 4466 /* EJTAG support */
4467   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
  4467 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
4468 4468 rn = "DEPC";
4469 4469 break;
4470 4470 default:
... ... @@ -4474,35 +4474,35 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4474 4474 case 25:
4475 4475 switch (sel) {
4476 4476 case 0:
4477   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Performance0));
  4477 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
4478 4478 rn = "Performance0";
4479 4479 break;
4480 4480 case 1:
4481   -// tcg_gen_helper_1_1(do_dmfc0_performance1, cpu_T[0], cpu_T[0]);
  4481 +// tcg_gen_helper_1_0(do_dmfc0_performance1, t0);
4482 4482 rn = "Performance1";
4483 4483 // break;
4484 4484 case 2:
4485   -// tcg_gen_helper_1_1(do_dmfc0_performance2, cpu_T[0], cpu_T[0]);
  4485 +// tcg_gen_helper_1_0(do_dmfc0_performance2, t0);
4486 4486 rn = "Performance2";
4487 4487 // break;
4488 4488 case 3:
4489   -// tcg_gen_helper_1_1(do_dmfc0_performance3, cpu_T[0], cpu_T[0]);
  4489 +// tcg_gen_helper_1_0(do_dmfc0_performance3, t0);
4490 4490 rn = "Performance3";
4491 4491 // break;
4492 4492 case 4:
4493   -// tcg_gen_helper_1_1(do_dmfc0_performance4, cpu_T[0], cpu_T[0]);
  4493 +// tcg_gen_helper_1_0(do_dmfc0_performance4, t0);
4494 4494 rn = "Performance4";
4495 4495 // break;
4496 4496 case 5:
4497   -// tcg_gen_helper_1_1(do_dmfc0_performance5, cpu_T[0], cpu_T[0]);
  4497 +// tcg_gen_helper_1_0(do_dmfc0_performance5, t0);
4498 4498 rn = "Performance5";
4499 4499 // break;
4500 4500 case 6:
4501   -// tcg_gen_helper_1_1(do_dmfc0_performance6, cpu_T[0], cpu_T[0]);
  4501 +// tcg_gen_helper_1_0(do_dmfc0_performance6, t0);
4502 4502 rn = "Performance6";
4503 4503 // break;
4504 4504 case 7:
4505   -// tcg_gen_helper_1_1(do_dmfc0_performance7, cpu_T[0], cpu_T[0]);
  4505 +// tcg_gen_helper_1_0(do_dmfc0_performance7, t0);
4506 4506 rn = "Performance7";
4507 4507 // break;
4508 4508 default:
... ... @@ -4528,14 +4528,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4528 4528 case 2:
4529 4529 case 4:
4530 4530 case 6:
4531   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagLo));
  4531 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
4532 4532 rn = "TagLo";
4533 4533 break;
4534 4534 case 1:
4535 4535 case 3:
4536 4536 case 5:
4537 4537 case 7:
4538   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataLo));
  4538 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
4539 4539 rn = "DataLo";
4540 4540 break;
4541 4541 default:
... ... @@ -4548,14 +4548,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4548 4548 case 2:
4549 4549 case 4:
4550 4550 case 6:
4551   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagHi));
  4551 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
4552 4552 rn = "TagHi";
4553 4553 break;
4554 4554 case 1:
4555 4555 case 3:
4556 4556 case 5:
4557 4557 case 7:
4558   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataHi));
  4558 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
4559 4559 rn = "DataHi";
4560 4560 break;
4561 4561 default:
... ... @@ -4565,7 +4565,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4565 4565 case 30:
4566 4566 switch (sel) {
4567 4567 case 0:
4568   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
  4568 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4569 4569 rn = "ErrorEPC";
4570 4570 break;
4571 4571 default:
... ... @@ -4576,7 +4576,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4576 4576 switch (sel) {
4577 4577 case 0:
4578 4578 /* EJTAG support */
4579   - gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DESAVE));
  4579 + gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
4580 4580 rn = "DESAVE";
4581 4581 break;
4582 4582 default:
... ... @@ -4604,7 +4604,7 @@ die:
4604 4604 generate_exception(ctx, EXCP_RI);
4605 4605 }
4606 4606  
4607   -static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
  4607 +static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
4608 4608 {
4609 4609 const char *rn = "invalid";
4610 4610  
... ... @@ -4615,12 +4615,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4615 4615 case 0:
4616 4616 switch (sel) {
4617 4617 case 0:
4618   - tcg_gen_helper_0_1(do_mtc0_index, cpu_T[0]);
  4618 + tcg_gen_helper_0_1(do_mtc0_index, t0);
4619 4619 rn = "Index";
4620 4620 break;
4621 4621 case 1:
4622 4622 check_insn(env, ctx, ASE_MT);
4623   - tcg_gen_helper_0_1(do_mtc0_mvpcontrol, cpu_T[0]);
  4623 + tcg_gen_helper_0_1(do_mtc0_mvpcontrol, t0);
4624 4624 rn = "MVPControl";
4625 4625 break;
4626 4626 case 2:
... ... @@ -4645,37 +4645,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4645 4645 break;
4646 4646 case 1:
4647 4647 check_insn(env, ctx, ASE_MT);
4648   - tcg_gen_helper_0_1(do_mtc0_vpecontrol, cpu_T[0]);
  4648 + tcg_gen_helper_0_1(do_mtc0_vpecontrol, t0);
4649 4649 rn = "VPEControl";
4650 4650 break;
4651 4651 case 2:
4652 4652 check_insn(env, ctx, ASE_MT);
4653   - tcg_gen_helper_0_1(do_mtc0_vpeconf0, cpu_T[0]);
  4653 + tcg_gen_helper_0_1(do_mtc0_vpeconf0, t0);
4654 4654 rn = "VPEConf0";
4655 4655 break;
4656 4656 case 3:
4657 4657 check_insn(env, ctx, ASE_MT);
4658   - tcg_gen_helper_0_1(do_mtc0_vpeconf1, cpu_T[0]);
  4658 + tcg_gen_helper_0_1(do_mtc0_vpeconf1, t0);
4659 4659 rn = "VPEConf1";
4660 4660 break;
4661 4661 case 4:
4662 4662 check_insn(env, ctx, ASE_MT);
4663   - tcg_gen_helper_0_1(do_mtc0_yqmask, cpu_T[0]);
  4663 + tcg_gen_helper_0_1(do_mtc0_yqmask, t0);
4664 4664 rn = "YQMask";
4665 4665 break;
4666 4666 case 5:
4667 4667 check_insn(env, ctx, ASE_MT);
4668   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule));
  4668 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4669 4669 rn = "VPESchedule";
4670 4670 break;
4671 4671 case 6:
4672 4672 check_insn(env, ctx, ASE_MT);
4673   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
  4673 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4674 4674 rn = "VPEScheFBack";
4675 4675 break;
4676 4676 case 7:
4677 4677 check_insn(env, ctx, ASE_MT);
4678   - tcg_gen_helper_0_1(do_mtc0_vpeopt, cpu_T[0]);
  4678 + tcg_gen_helper_0_1(do_mtc0_vpeopt, t0);
4679 4679 rn = "VPEOpt";
4680 4680 break;
4681 4681 default:
... ... @@ -4685,42 +4685,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4685 4685 case 2:
4686 4686 switch (sel) {
4687 4687 case 0:
4688   - tcg_gen_helper_0_1(do_mtc0_entrylo0, cpu_T[0]);
  4688 + tcg_gen_helper_0_1(do_mtc0_entrylo0, t0);
4689 4689 rn = "EntryLo0";
4690 4690 break;
4691 4691 case 1:
4692 4692 check_insn(env, ctx, ASE_MT);
4693   - tcg_gen_helper_0_1(do_mtc0_tcstatus, cpu_T[0]);
  4693 + tcg_gen_helper_0_1(do_mtc0_tcstatus, t0);
4694 4694 rn = "TCStatus";
4695 4695 break;
4696 4696 case 2:
4697 4697 check_insn(env, ctx, ASE_MT);
4698   - tcg_gen_helper_0_1(do_mtc0_tcbind, cpu_T[0]);
  4698 + tcg_gen_helper_0_1(do_mtc0_tcbind, t0);
4699 4699 rn = "TCBind";
4700 4700 break;
4701 4701 case 3:
4702 4702 check_insn(env, ctx, ASE_MT);
4703   - tcg_gen_helper_0_1(do_mtc0_tcrestart, cpu_T[0]);
  4703 + tcg_gen_helper_0_1(do_mtc0_tcrestart, t0);
4704 4704 rn = "TCRestart";
4705 4705 break;
4706 4706 case 4:
4707 4707 check_insn(env, ctx, ASE_MT);
4708   - tcg_gen_helper_0_1(do_mtc0_tchalt, cpu_T[0]);
  4708 + tcg_gen_helper_0_1(do_mtc0_tchalt, t0);
4709 4709 rn = "TCHalt";
4710 4710 break;
4711 4711 case 5:
4712 4712 check_insn(env, ctx, ASE_MT);
4713   - tcg_gen_helper_0_1(do_mtc0_tccontext, cpu_T[0]);
  4713 + tcg_gen_helper_0_1(do_mtc0_tccontext, t0);
4714 4714 rn = "TCContext";
4715 4715 break;
4716 4716 case 6:
4717 4717 check_insn(env, ctx, ASE_MT);
4718   - tcg_gen_helper_0_1(do_mtc0_tcschedule, cpu_T[0]);
  4718 + tcg_gen_helper_0_1(do_mtc0_tcschedule, t0);
4719 4719 rn = "TCSchedule";
4720 4720 break;
4721 4721 case 7:
4722 4722 check_insn(env, ctx, ASE_MT);
4723   - tcg_gen_helper_0_1(do_mtc0_tcschefback, cpu_T[0]);
  4723 + tcg_gen_helper_0_1(do_mtc0_tcschefback, t0);
4724 4724 rn = "TCScheFBack";
4725 4725 break;
4726 4726 default:
... ... @@ -4730,7 +4730,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4730 4730 case 3:
4731 4731 switch (sel) {
4732 4732 case 0:
4733   - tcg_gen_helper_0_1(do_mtc0_entrylo1, cpu_T[0]);
  4733 + tcg_gen_helper_0_1(do_mtc0_entrylo1, t0);
4734 4734 rn = "EntryLo1";
4735 4735 break;
4736 4736 default:
... ... @@ -4740,11 +4740,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4740 4740 case 4:
4741 4741 switch (sel) {
4742 4742 case 0:
4743   - tcg_gen_helper_0_1(do_mtc0_context, cpu_T[0]);
  4743 + tcg_gen_helper_0_1(do_mtc0_context, t0);
4744 4744 rn = "Context";
4745 4745 break;
4746 4746 case 1:
4747   -// tcg_gen_helper_0_1(do_mtc0_contextconfig, cpu_T[0]); /* SmartMIPS ASE */
  4747 +// tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
4748 4748 rn = "ContextConfig";
4749 4749 // break;
4750 4750 default:
... ... @@ -4754,12 +4754,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4754 4754 case 5:
4755 4755 switch (sel) {
4756 4756 case 0:
4757   - tcg_gen_helper_0_1(do_mtc0_pagemask, cpu_T[0]);
  4757 + tcg_gen_helper_0_1(do_mtc0_pagemask, t0);
4758 4758 rn = "PageMask";
4759 4759 break;
4760 4760 case 1:
4761 4761 check_insn(env, ctx, ISA_MIPS32R2);
4762   - tcg_gen_helper_0_1(do_mtc0_pagegrain, cpu_T[0]);
  4762 + tcg_gen_helper_0_1(do_mtc0_pagegrain, t0);
4763 4763 rn = "PageGrain";
4764 4764 break;
4765 4765 default:
... ... @@ -4769,32 +4769,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4769 4769 case 6:
4770 4770 switch (sel) {
4771 4771 case 0:
4772   - tcg_gen_helper_0_1(do_mtc0_wired, cpu_T[0]);
  4772 + tcg_gen_helper_0_1(do_mtc0_wired, t0);
4773 4773 rn = "Wired";
4774 4774 break;
4775 4775 case 1:
4776 4776 check_insn(env, ctx, ISA_MIPS32R2);
4777   - tcg_gen_helper_0_1(do_mtc0_srsconf0, cpu_T[0]);
  4777 + tcg_gen_helper_0_1(do_mtc0_srsconf0, t0);
4778 4778 rn = "SRSConf0";
4779 4779 break;
4780 4780 case 2:
4781 4781 check_insn(env, ctx, ISA_MIPS32R2);
4782   - tcg_gen_helper_0_1(do_mtc0_srsconf1, cpu_T[0]);
  4782 + tcg_gen_helper_0_1(do_mtc0_srsconf1, t0);
4783 4783 rn = "SRSConf1";
4784 4784 break;
4785 4785 case 3:
4786 4786 check_insn(env, ctx, ISA_MIPS32R2);
4787   - tcg_gen_helper_0_1(do_mtc0_srsconf2, cpu_T[0]);
  4787 + tcg_gen_helper_0_1(do_mtc0_srsconf2, t0);
4788 4788 rn = "SRSConf2";
4789 4789 break;
4790 4790 case 4:
4791 4791 check_insn(env, ctx, ISA_MIPS32R2);
4792   - tcg_gen_helper_0_1(do_mtc0_srsconf3, cpu_T[0]);
  4792 + tcg_gen_helper_0_1(do_mtc0_srsconf3, t0);
4793 4793 rn = "SRSConf3";
4794 4794 break;
4795 4795 case 5:
4796 4796 check_insn(env, ctx, ISA_MIPS32R2);
4797   - tcg_gen_helper_0_1(do_mtc0_srsconf4, cpu_T[0]);
  4797 + tcg_gen_helper_0_1(do_mtc0_srsconf4, t0);
4798 4798 rn = "SRSConf4";
4799 4799 break;
4800 4800 default:
... ... @@ -4805,7 +4805,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4805 4805 switch (sel) {
4806 4806 case 0:
4807 4807 check_insn(env, ctx, ISA_MIPS32R2);
4808   - tcg_gen_helper_0_1(do_mtc0_hwrena, cpu_T[0]);
  4808 + tcg_gen_helper_0_1(do_mtc0_hwrena, t0);
4809 4809 rn = "HWREna";
4810 4810 break;
4811 4811 default:
... ... @@ -4819,7 +4819,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4819 4819 case 9:
4820 4820 switch (sel) {
4821 4821 case 0:
4822   - tcg_gen_helper_0_1(do_mtc0_count, cpu_T[0]);
  4822 + tcg_gen_helper_0_1(do_mtc0_count, t0);
4823 4823 rn = "Count";
4824 4824 break;
4825 4825 /* 6,7 are implementation dependent */
... ... @@ -4832,7 +4832,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4832 4832 case 10:
4833 4833 switch (sel) {
4834 4834 case 0:
4835   - tcg_gen_helper_0_1(do_mtc0_entryhi, cpu_T[0]);
  4835 + tcg_gen_helper_0_1(do_mtc0_entryhi, t0);
4836 4836 rn = "EntryHi";
4837 4837 break;
4838 4838 default:
... ... @@ -4842,7 +4842,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4842 4842 case 11:
4843 4843 switch (sel) {
4844 4844 case 0:
4845   - tcg_gen_helper_0_1(do_mtc0_compare, cpu_T[0]);
  4845 + tcg_gen_helper_0_1(do_mtc0_compare, t0);
4846 4846 rn = "Compare";
4847 4847 break;
4848 4848 /* 6,7 are implementation dependent */
... ... @@ -4855,7 +4855,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4855 4855 case 12:
4856 4856 switch (sel) {
4857 4857 case 0:
4858   - tcg_gen_helper_0_1(do_mtc0_status, cpu_T[0]);
  4858 + tcg_gen_helper_0_1(do_mtc0_status, t0);
4859 4859 /* BS_STOP isn't good enough here, hflags may have changed. */
4860 4860 gen_save_pc(ctx->pc + 4);
4861 4861 ctx->bstate = BS_EXCP;
... ... @@ -4863,21 +4863,21 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4863 4863 break;
4864 4864 case 1:
4865 4865 check_insn(env, ctx, ISA_MIPS32R2);
4866   - tcg_gen_helper_0_1(do_mtc0_intctl, cpu_T[0]);
  4866 + tcg_gen_helper_0_1(do_mtc0_intctl, t0);
4867 4867 /* Stop translation as we may have switched the execution mode */
4868 4868 ctx->bstate = BS_STOP;
4869 4869 rn = "IntCtl";
4870 4870 break;
4871 4871 case 2:
4872 4872 check_insn(env, ctx, ISA_MIPS32R2);
4873   - tcg_gen_helper_0_1(do_mtc0_srsctl, cpu_T[0]);
  4873 + tcg_gen_helper_0_1(do_mtc0_srsctl, t0);
4874 4874 /* Stop translation as we may have switched the execution mode */
4875 4875 ctx->bstate = BS_STOP;
4876 4876 rn = "SRSCtl";
4877 4877 break;
4878 4878 case 3:
4879 4879 check_insn(env, ctx, ISA_MIPS32R2);
4880   - gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_SRSMap));
  4880 + gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
4881 4881 /* Stop translation as we may have switched the execution mode */
4882 4882 ctx->bstate = BS_STOP;
4883 4883 rn = "SRSMap";
... ... @@ -4889,7 +4889,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4889 4889 case 13:
4890 4890 switch (sel) {
4891 4891 case 0:
4892   - tcg_gen_helper_0_1(do_mtc0_cause, cpu_T[0]);
  4892 + tcg_gen_helper_0_1(do_mtc0_cause, t0);
4893 4893 rn = "Cause";
4894 4894 break;
4895 4895 default:
... ... @@ -4901,7 +4901,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4901 4901 case 14:
4902 4902 switch (sel) {
4903 4903 case 0:
4904   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
  4904 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
4905 4905 rn = "EPC";
4906 4906 break;
4907 4907 default:
... ... @@ -4916,7 +4916,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4916 4916 break;
4917 4917 case 1:
4918 4918 check_insn(env, ctx, ISA_MIPS32R2);
4919   - tcg_gen_helper_0_1(do_mtc0_ebase, cpu_T[0]);
  4919 + tcg_gen_helper_0_1(do_mtc0_ebase, t0);
4920 4920 rn = "EBase";
4921 4921 break;
4922 4922 default:
... ... @@ -4926,7 +4926,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4926 4926 case 16:
4927 4927 switch (sel) {
4928 4928 case 0:
4929   - tcg_gen_helper_0_1(do_mtc0_config0, cpu_T[0]);
  4929 + tcg_gen_helper_0_1(do_mtc0_config0, t0);
4930 4930 rn = "Config";
4931 4931 /* Stop translation as we may have switched the execution mode */
4932 4932 ctx->bstate = BS_STOP;
... ... @@ -4936,7 +4936,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4936 4936 rn = "Config1";
4937 4937 break;
4938 4938 case 2:
4939   - tcg_gen_helper_0_1(do_mtc0_config2, cpu_T[0]);
  4939 + tcg_gen_helper_0_1(do_mtc0_config2, t0);
4940 4940 rn = "Config2";
4941 4941 /* Stop translation as we may have switched the execution mode */
4942 4942 ctx->bstate = BS_STOP;
... ... @@ -4964,7 +4964,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4964 4964 case 18:
4965 4965 switch (sel) {
4966 4966 case 0 ... 7:
4967   - tcg_gen_helper_0_1i(do_mtc0_watchlo, cpu_T[0], sel);
  4967 + tcg_gen_helper_0_1i(do_mtc0_watchlo, t0, sel);
4968 4968 rn = "WatchLo";
4969 4969 break;
4970 4970 default:
... ... @@ -4974,7 +4974,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4974 4974 case 19:
4975 4975 switch (sel) {
4976 4976 case 0 ... 7:
4977   - tcg_gen_helper_0_1i(do_mtc0_watchhi, cpu_T[0], sel);
  4977 + tcg_gen_helper_0_1i(do_mtc0_watchhi, t0, sel);
4978 4978 rn = "WatchHi";
4979 4979 break;
4980 4980 default:
... ... @@ -4985,7 +4985,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4985 4985 switch (sel) {
4986 4986 case 0:
4987 4987 check_insn(env, ctx, ISA_MIPS3);
4988   - tcg_gen_helper_0_1(do_mtc0_xcontext, cpu_T[0]);
  4988 + tcg_gen_helper_0_1(do_mtc0_xcontext, t0);
4989 4989 rn = "XContext";
4990 4990 break;
4991 4991 default:
... ... @@ -4996,7 +4996,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4996 4996 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4997 4997 switch (sel) {
4998 4998 case 0:
4999   - tcg_gen_helper_0_1(do_mtc0_framemask, cpu_T[0]);
  4999 + tcg_gen_helper_0_1(do_mtc0_framemask, t0);
5000 5000 rn = "Framemask";
5001 5001 break;
5002 5002 default:
... ... @@ -5010,32 +5010,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5010 5010 case 23:
5011 5011 switch (sel) {
5012 5012 case 0:
5013   - tcg_gen_helper_0_1(do_mtc0_debug, cpu_T[0]); /* EJTAG support */
  5013 + tcg_gen_helper_0_1(do_mtc0_debug, t0); /* EJTAG support */
5014 5014 /* BS_STOP isn't good enough here, hflags may have changed. */
5015 5015 gen_save_pc(ctx->pc + 4);
5016 5016 ctx->bstate = BS_EXCP;
5017 5017 rn = "Debug";
5018 5018 break;
5019 5019 case 1:
5020   -// tcg_gen_helper_0_1(do_mtc0_tracecontrol, cpu_T[0]); /* PDtrace support */
  5020 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
5021 5021 /* Stop translation as we may have switched the execution mode */
5022 5022 ctx->bstate = BS_STOP;
5023 5023 rn = "TraceControl";
5024 5024 // break;
5025 5025 case 2:
5026   -// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, cpu_T[0]); /* PDtrace support */
  5026 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
5027 5027 /* Stop translation as we may have switched the execution mode */
5028 5028 ctx->bstate = BS_STOP;
5029 5029 rn = "TraceControl2";
5030 5030 // break;
5031 5031 case 3:
5032   -// tcg_gen_helper_0_1(do_mtc0_usertracedata, cpu_T[0]); /* PDtrace support */
  5032 +// tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
5033 5033 /* Stop translation as we may have switched the execution mode */
5034 5034 ctx->bstate = BS_STOP;
5035 5035 rn = "UserTraceData";
5036 5036 // break;
5037 5037 case 4:
5038   -// tcg_gen_helper_0_1(do_mtc0_tracebpc, cpu_T[0]); /* PDtrace support */
  5038 +// tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
5039 5039 /* Stop translation as we may have switched the execution mode */
5040 5040 ctx->bstate = BS_STOP;
5041 5041 rn = "TraceBPC";
... ... @@ -5048,7 +5048,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5048 5048 switch (sel) {
5049 5049 case 0:
5050 5050 /* EJTAG support */
5051   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
  5051 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
5052 5052 rn = "DEPC";
5053 5053 break;
5054 5054 default:
... ... @@ -5058,35 +5058,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5058 5058 case 25:
5059 5059 switch (sel) {
5060 5060 case 0:
5061   - tcg_gen_helper_0_1(do_mtc0_performance0, cpu_T[0]);
  5061 + tcg_gen_helper_0_1(do_mtc0_performance0, t0);
5062 5062 rn = "Performance0";
5063 5063 break;
5064 5064 case 1:
5065   -// tcg_gen_helper_0_1(do_mtc0_performance1, cpu_T[0]);
  5065 +// tcg_gen_helper_0_1(do_mtc0_performance1, t0);
5066 5066 rn = "Performance1";
5067 5067 // break;
5068 5068 case 2:
5069   -// tcg_gen_helper_0_1(do_mtc0_performance2, cpu_T[0]);
  5069 +// tcg_gen_helper_0_1(do_mtc0_performance2, t0);
5070 5070 rn = "Performance2";
5071 5071 // break;
5072 5072 case 3:
5073   -// tcg_gen_helper_0_1(do_mtc0_performance3, cpu_T[0]);
  5073 +// tcg_gen_helper_0_1(do_mtc0_performance3, t0);
5074 5074 rn = "Performance3";
5075 5075 // break;
5076 5076 case 4:
5077   -// tcg_gen_helper_0_1(do_mtc0_performance4, cpu_T[0]);
  5077 +// tcg_gen_helper_0_1(do_mtc0_performance4, t0);
5078 5078 rn = "Performance4";
5079 5079 // break;
5080 5080 case 5:
5081   -// tcg_gen_helper_0_1(do_mtc0_performance5, cpu_T[0]);
  5081 +// tcg_gen_helper_0_1(do_mtc0_performance5, t0);
5082 5082 rn = "Performance5";
5083 5083 // break;
5084 5084 case 6:
5085   -// tcg_gen_helper_0_1(do_mtc0_performance6, cpu_T[0]);
  5085 +// tcg_gen_helper_0_1(do_mtc0_performance6, t0);
5086 5086 rn = "Performance6";
5087 5087 // break;
5088 5088 case 7:
5089   -// tcg_gen_helper_0_1(do_mtc0_performance7, cpu_T[0]);
  5089 +// tcg_gen_helper_0_1(do_mtc0_performance7, t0);
5090 5090 rn = "Performance7";
5091 5091 // break;
5092 5092 default:
... ... @@ -5113,14 +5113,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5113 5113 case 2:
5114 5114 case 4:
5115 5115 case 6:
5116   - tcg_gen_helper_0_1(do_mtc0_taglo, cpu_T[0]);
  5116 + tcg_gen_helper_0_1(do_mtc0_taglo, t0);
5117 5117 rn = "TagLo";
5118 5118 break;
5119 5119 case 1:
5120 5120 case 3:
5121 5121 case 5:
5122 5122 case 7:
5123   - tcg_gen_helper_0_1(do_mtc0_datalo, cpu_T[0]);
  5123 + tcg_gen_helper_0_1(do_mtc0_datalo, t0);
5124 5124 rn = "DataLo";
5125 5125 break;
5126 5126 default:
... ... @@ -5133,14 +5133,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5133 5133 case 2:
5134 5134 case 4:
5135 5135 case 6:
5136   - tcg_gen_helper_0_1(do_mtc0_taghi, cpu_T[0]);
  5136 + tcg_gen_helper_0_1(do_mtc0_taghi, t0);
5137 5137 rn = "TagHi";
5138 5138 break;
5139 5139 case 1:
5140 5140 case 3:
5141 5141 case 5:
5142 5142 case 7:
5143   - tcg_gen_helper_0_1(do_mtc0_datahi, cpu_T[0]);
  5143 + tcg_gen_helper_0_1(do_mtc0_datahi, t0);
5144 5144 rn = "DataHi";
5145 5145 break;
5146 5146 default:
... ... @@ -5151,7 +5151,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5151 5151 case 30:
5152 5152 switch (sel) {
5153 5153 case 0:
5154   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
  5154 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
5155 5155 rn = "ErrorEPC";
5156 5156 break;
5157 5157 default:
... ... @@ -5162,7 +5162,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5162 5162 switch (sel) {
5163 5163 case 0:
5164 5164 /* EJTAG support */
5165   - gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_DESAVE));
  5165 + gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
5166 5166 rn = "DESAVE";
5167 5167 break;
5168 5168 default:
... ... @@ -5180,9 +5180,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5180 5180 rn, reg, sel);
5181 5181 }
5182 5182 #endif
  5183 + tcg_temp_free(t0);
5183 5184 return;
5184 5185  
5185 5186 die:
  5187 + tcg_temp_free(t0);
5186 5188 #if defined MIPS_DEBUG_DISAS
5187 5189 if (loglevel & CPU_LOG_TB_IN_ASM) {
5188 5190 fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
... ... @@ -5197,121 +5199,122 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5197 5199 int u, int sel, int h)
5198 5200 {
5199 5201 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  5202 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5200 5203  
5201 5204 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5202 5205 ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) !=
5203 5206 (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE))))
5204   - tcg_gen_movi_tl(cpu_T[0], -1);
  5207 + tcg_gen_movi_tl(t0, -1);
5205 5208 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
5206 5209 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
5207   - tcg_gen_movi_tl(cpu_T[0], -1);
  5210 + tcg_gen_movi_tl(t0, -1);
5208 5211 else if (u == 0) {
5209 5212 switch (rt) {
5210 5213 case 2:
5211 5214 switch (sel) {
5212 5215 case 1:
5213   - tcg_gen_helper_1_1(do_mftc0_tcstatus, cpu_T[0], cpu_T[0]);
  5216 + tcg_gen_helper_1_1(do_mftc0_tcstatus, t0, t0);
5214 5217 break;
5215 5218 case 2:
5216   - tcg_gen_helper_1_1(do_mftc0_tcbind, cpu_T[0], cpu_T[0]);
  5219 + tcg_gen_helper_1_1(do_mftc0_tcbind, t0, t0);
5217 5220 break;
5218 5221 case 3:
5219   - tcg_gen_helper_1_1(do_mftc0_tcrestart, cpu_T[0], cpu_T[0]);
  5222 + tcg_gen_helper_1_1(do_mftc0_tcrestart, t0, t0);
5220 5223 break;
5221 5224 case 4:
5222   - tcg_gen_helper_1_1(do_mftc0_tchalt, cpu_T[0], cpu_T[0]);
  5225 + tcg_gen_helper_1_1(do_mftc0_tchalt, t0, t0);
5223 5226 break;
5224 5227 case 5:
5225   - tcg_gen_helper_1_1(do_mftc0_tccontext, cpu_T[0], cpu_T[0]);
  5228 + tcg_gen_helper_1_1(do_mftc0_tccontext, t0, t0);
5226 5229 break;
5227 5230 case 6:
5228   - tcg_gen_helper_1_1(do_mftc0_tcschedule, cpu_T[0], cpu_T[0]);
  5231 + tcg_gen_helper_1_1(do_mftc0_tcschedule, t0, t0);
5229 5232 break;
5230 5233 case 7:
5231   - tcg_gen_helper_1_1(do_mftc0_tcschefback, cpu_T[0], cpu_T[0]);
  5234 + tcg_gen_helper_1_1(do_mftc0_tcschefback, t0, t0);
5232 5235 break;
5233 5236 default:
5234   - gen_mfc0(env, ctx, rt, sel);
  5237 + gen_mfc0(env, ctx, t0, rt, sel);
5235 5238 break;
5236 5239 }
5237 5240 break;
5238 5241 case 10:
5239 5242 switch (sel) {
5240 5243 case 0:
5241   - tcg_gen_helper_1_1(do_mftc0_entryhi, cpu_T[0], cpu_T[0]);
  5244 + tcg_gen_helper_1_1(do_mftc0_entryhi, t0, t0);
5242 5245 break;
5243 5246 default:
5244   - gen_mfc0(env, ctx, rt, sel);
  5247 + gen_mfc0(env, ctx, t0, rt, sel);
5245 5248 break;
5246 5249 }
5247 5250 case 12:
5248 5251 switch (sel) {
5249 5252 case 0:
5250   - tcg_gen_helper_1_1(do_mftc0_status, cpu_T[0], cpu_T[0]);
  5253 + tcg_gen_helper_1_1(do_mftc0_status, t0, t0);
5251 5254 break;
5252 5255 default:
5253   - gen_mfc0(env, ctx, rt, sel);
  5256 + gen_mfc0(env, ctx, t0, rt, sel);
5254 5257 break;
5255 5258 }
5256 5259 case 23:
5257 5260 switch (sel) {
5258 5261 case 0:
5259   - tcg_gen_helper_1_1(do_mftc0_debug, cpu_T[0], cpu_T[0]);
  5262 + tcg_gen_helper_1_1(do_mftc0_debug, t0, t0);
5260 5263 break;
5261 5264 default:
5262   - gen_mfc0(env, ctx, rt, sel);
  5265 + gen_mfc0(env, ctx, t0, rt, sel);
5263 5266 break;
5264 5267 }
5265 5268 break;
5266 5269 default:
5267   - gen_mfc0(env, ctx, rt, sel);
  5270 + gen_mfc0(env, ctx, t0, rt, sel);
5268 5271 }
5269 5272 } else switch (sel) {
5270 5273 /* GPR registers. */
5271 5274 case 0:
5272   - tcg_gen_helper_1_1i(do_mftgpr, cpu_T[0], cpu_T[0], rt);
  5275 + tcg_gen_helper_1_1i(do_mftgpr, t0, t0, rt);
5273 5276 break;
5274 5277 /* Auxiliary CPU registers */
5275 5278 case 1:
5276 5279 switch (rt) {
5277 5280 case 0:
5278   - tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 0);
  5281 + tcg_gen_helper_1_1i(do_mftlo, t0, t0, 0);
5279 5282 break;
5280 5283 case 1:
5281   - tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 0);
  5284 + tcg_gen_helper_1_1i(do_mfthi, t0, t0, 0);
5282 5285 break;
5283 5286 case 2:
5284   - tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 0);
  5287 + tcg_gen_helper_1_1i(do_mftacx, t0, t0, 0);
5285 5288 break;
5286 5289 case 4:
5287   - tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 1);
  5290 + tcg_gen_helper_1_1i(do_mftlo, t0, t0, 1);
5288 5291 break;
5289 5292 case 5:
5290   - tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 1);
  5293 + tcg_gen_helper_1_1i(do_mfthi, t0, t0, 1);
5291 5294 break;
5292 5295 case 6:
5293   - tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 1);
  5296 + tcg_gen_helper_1_1i(do_mftacx, t0, t0, 1);
5294 5297 break;
5295 5298 case 8:
5296   - tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 2);
  5299 + tcg_gen_helper_1_1i(do_mftlo, t0, t0, 2);
5297 5300 break;
5298 5301 case 9:
5299   - tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 2);
  5302 + tcg_gen_helper_1_1i(do_mfthi, t0, t0, 2);
5300 5303 break;
5301 5304 case 10:
5302   - tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 2);
  5305 + tcg_gen_helper_1_1i(do_mftacx, t0, t0, 2);
5303 5306 break;
5304 5307 case 12:
5305   - tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 3);
  5308 + tcg_gen_helper_1_1i(do_mftlo, t0, t0, 3);
5306 5309 break;
5307 5310 case 13:
5308   - tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 3);
  5311 + tcg_gen_helper_1_1i(do_mfthi, t0, t0, 3);
5309 5312 break;
5310 5313 case 14:
5311   - tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 3);
  5314 + tcg_gen_helper_1_1i(do_mftacx, t0, t0, 3);
5312 5315 break;
5313 5316 case 16:
5314   - tcg_gen_helper_1_1(do_mftdsp, cpu_T[0], cpu_T[0]);
  5317 + tcg_gen_helper_1_1(do_mftdsp, t0, t0);
5315 5318 break;
5316 5319 default:
5317 5320 goto die;
... ... @@ -5322,15 +5325,15 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5322 5325 /* XXX: For now we support only a single FPU context. */
5323 5326 if (h == 0) {
5324 5327 gen_load_fpr32(fpu32_T[0], rt);
5325   - tcg_gen_ext_i32_tl(cpu_T[0], fpu32_T[0]);
  5328 + tcg_gen_ext_i32_tl(t0, fpu32_T[0]);
5326 5329 } else {
5327 5330 gen_load_fpr32h(fpu32h_T[0], rt);
5328   - tcg_gen_ext_i32_tl(cpu_T[0], fpu32h_T[0]);
  5331 + tcg_gen_ext_i32_tl(t0, fpu32h_T[0]);
5329 5332 }
5330 5333 break;
5331 5334 case 3:
5332 5335 /* XXX: For now we support only a single FPU context. */
5333   - tcg_gen_helper_1_1i(do_cfc1, cpu_T[0], cpu_T[0], rt);
  5336 + tcg_gen_helper_1_1i(do_cfc1, t0, t0, rt);
5334 5337 break;
5335 5338 /* COP2: Not implemented. */
5336 5339 case 4:
... ... @@ -5345,10 +5348,12 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5345 5348 rt, u, sel, h);
5346 5349 }
5347 5350 #endif
5348   - gen_store_gpr(cpu_T[0], rd);
  5351 + gen_store_gpr(t0, rd);
  5352 + tcg_temp_free(t0);
5349 5353 return;
5350 5354  
5351 5355 die:
  5356 + tcg_temp_free(t0);
5352 5357 #if defined MIPS_DEBUG_DISAS
5353 5358 if (loglevel & CPU_LOG_TB_IN_ASM) {
5354 5359 fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",
... ... @@ -5362,8 +5367,9 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5362 5367 int u, int sel, int h)
5363 5368 {
5364 5369 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  5370 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5365 5371  
5366   - gen_load_gpr(cpu_T[0], rt);
  5372 + gen_load_gpr(t0, rt);
5367 5373 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5368 5374 ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) !=
5369 5375 (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE))))
... ... @@ -5376,108 +5382,108 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5376 5382 case 2:
5377 5383 switch (sel) {
5378 5384 case 1:
5379   - tcg_gen_helper_0_1(do_mttc0_tcstatus, cpu_T[0]);
  5385 + tcg_gen_helper_0_1(do_mttc0_tcstatus, t0);
5380 5386 break;
5381 5387 case 2:
5382   - tcg_gen_helper_0_1(do_mttc0_tcbind, cpu_T[0]);
  5388 + tcg_gen_helper_0_1(do_mttc0_tcbind, t0);
5383 5389 break;
5384 5390 case 3:
5385   - tcg_gen_helper_0_1(do_mttc0_tcrestart, cpu_T[0]);
  5391 + tcg_gen_helper_0_1(do_mttc0_tcrestart, t0);
5386 5392 break;
5387 5393 case 4:
5388   - tcg_gen_helper_0_1(do_mttc0_tchalt, cpu_T[0]);
  5394 + tcg_gen_helper_0_1(do_mttc0_tchalt, t0);
5389 5395 break;
5390 5396 case 5:
5391   - tcg_gen_helper_0_1(do_mttc0_tccontext, cpu_T[0]);
  5397 + tcg_gen_helper_0_1(do_mttc0_tccontext, t0);
5392 5398 break;
5393 5399 case 6:
5394   - tcg_gen_helper_0_1(do_mttc0_tcschedule, cpu_T[0]);
  5400 + tcg_gen_helper_0_1(do_mttc0_tcschedule, t0);
5395 5401 break;
5396 5402 case 7:
5397   - tcg_gen_helper_0_1(do_mttc0_tcschefback, cpu_T[0]);
  5403 + tcg_gen_helper_0_1(do_mttc0_tcschefback, t0);
5398 5404 break;
5399 5405 default:
5400   - gen_mtc0(env, ctx, rd, sel);
  5406 + gen_mtc0(env, ctx, t0, rd, sel);
5401 5407 break;
5402 5408 }
5403 5409 break;
5404 5410 case 10:
5405 5411 switch (sel) {
5406 5412 case 0:
5407   - tcg_gen_helper_0_1(do_mttc0_entryhi, cpu_T[0]);
  5413 + tcg_gen_helper_0_1(do_mttc0_entryhi, t0);
5408 5414 break;
5409 5415 default:
5410   - gen_mtc0(env, ctx, rd, sel);
  5416 + gen_mtc0(env, ctx, t0, rd, sel);
5411 5417 break;
5412 5418 }
5413 5419 case 12:
5414 5420 switch (sel) {
5415 5421 case 0:
5416   - tcg_gen_helper_0_1(do_mttc0_status, cpu_T[0]);
  5422 + tcg_gen_helper_0_1(do_mttc0_status, t0);
5417 5423 break;
5418 5424 default:
5419   - gen_mtc0(env, ctx, rd, sel);
  5425 + gen_mtc0(env, ctx, t0, rd, sel);
5420 5426 break;
5421 5427 }
5422 5428 case 23:
5423 5429 switch (sel) {
5424 5430 case 0:
5425   - tcg_gen_helper_0_1(do_mttc0_debug, cpu_T[0]);
  5431 + tcg_gen_helper_0_1(do_mttc0_debug, t0);
5426 5432 break;
5427 5433 default:
5428   - gen_mtc0(env, ctx, rd, sel);
  5434 + gen_mtc0(env, ctx, t0, rd, sel);
5429 5435 break;
5430 5436 }
5431 5437 break;
5432 5438 default:
5433   - gen_mtc0(env, ctx, rd, sel);
  5439 + gen_mtc0(env, ctx, t0, rd, sel);
5434 5440 }
5435 5441 } else switch (sel) {
5436 5442 /* GPR registers. */
5437 5443 case 0:
5438   - tcg_gen_helper_0_1i(do_mttgpr, cpu_T[0], rd);
  5444 + tcg_gen_helper_0_1i(do_mttgpr, t0, rd);
5439 5445 break;
5440 5446 /* Auxiliary CPU registers */
5441 5447 case 1:
5442 5448 switch (rd) {
5443 5449 case 0:
5444   - tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 0);
  5450 + tcg_gen_helper_0_1i(do_mttlo, t0, 0);
5445 5451 break;
5446 5452 case 1:
5447   - tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 0);
  5453 + tcg_gen_helper_0_1i(do_mtthi, t0, 0);
5448 5454 break;
5449 5455 case 2:
5450   - tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 0);
  5456 + tcg_gen_helper_0_1i(do_mttacx, t0, 0);
5451 5457 break;
5452 5458 case 4:
5453   - tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 1);
  5459 + tcg_gen_helper_0_1i(do_mttlo, t0, 1);
5454 5460 break;
5455 5461 case 5:
5456   - tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 1);
  5462 + tcg_gen_helper_0_1i(do_mtthi, t0, 1);
5457 5463 break;
5458 5464 case 6:
5459   - tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 1);
  5465 + tcg_gen_helper_0_1i(do_mttacx, t0, 1);
5460 5466 break;
5461 5467 case 8:
5462   - tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 2);
  5468 + tcg_gen_helper_0_1i(do_mttlo, t0, 2);
5463 5469 break;
5464 5470 case 9:
5465   - tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 2);
  5471 + tcg_gen_helper_0_1i(do_mtthi, t0, 2);
5466 5472 break;
5467 5473 case 10:
5468   - tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 2);
  5474 + tcg_gen_helper_0_1i(do_mttacx, t0, 2);
5469 5475 break;
5470 5476 case 12:
5471   - tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 3);
  5477 + tcg_gen_helper_0_1i(do_mttlo, t0, 3);
5472 5478 break;
5473 5479 case 13:
5474   - tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 3);
  5480 + tcg_gen_helper_0_1i(do_mtthi, t0, 3);
5475 5481 break;
5476 5482 case 14:
5477   - tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 3);
  5483 + tcg_gen_helper_0_1i(do_mttacx, t0, 3);
5478 5484 break;
5479 5485 case 16:
5480   - tcg_gen_helper_0_1(do_mttdsp, cpu_T[0]);
  5486 + tcg_gen_helper_0_1(do_mttdsp, t0);
5481 5487 break;
5482 5488 default:
5483 5489 goto die;
... ... @@ -5487,16 +5493,16 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5487 5493 case 2:
5488 5494 /* XXX: For now we support only a single FPU context. */
5489 5495 if (h == 0) {
5490   - tcg_gen_trunc_tl_i32(fpu32_T[0], cpu_T[0]);
  5496 + tcg_gen_trunc_tl_i32(fpu32_T[0], t0);
5491 5497 gen_store_fpr32(fpu32_T[0], rd);
5492 5498 } else {
5493   - tcg_gen_trunc_tl_i32(fpu32h_T[0], cpu_T[0]);
  5499 + tcg_gen_trunc_tl_i32(fpu32h_T[0], t0);
5494 5500 gen_store_fpr32h(fpu32h_T[0], rd);
5495 5501 }
5496 5502 break;
5497 5503 case 3:
5498 5504 /* XXX: For now we support only a single FPU context. */
5499   - tcg_gen_helper_0_1i(do_ctc1, cpu_T[0], rd);
  5505 + tcg_gen_helper_0_1i(do_ctc1, t0, rd);
5500 5506 break;
5501 5507 /* COP2: Not implemented. */
5502 5508 case 4:
... ... @@ -5511,9 +5517,11 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5511 5517 rd, u, sel, h);
5512 5518 }
5513 5519 #endif
  5520 + tcg_temp_free(t0);
5514 5521 return;
5515 5522  
5516 5523 die:
  5524 + tcg_temp_free(t0);
5517 5525 #if defined MIPS_DEBUG_DISAS
5518 5526 if (loglevel & CPU_LOG_TB_IN_ASM) {
5519 5527 fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",
... ... @@ -5533,14 +5541,24 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5533 5541 /* Treat as NOP. */
5534 5542 return;
5535 5543 }
5536   - gen_mfc0(env, ctx, rd, ctx->opcode & 0x7);
5537   - gen_store_gpr(cpu_T[0], rt);
  5544 + {
  5545 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  5546 +
  5547 + gen_mfc0(env, ctx, t0, rd, ctx->opcode & 0x7);
  5548 + gen_store_gpr(t0, rt);
  5549 + tcg_temp_free(t0);
  5550 + }
5538 5551 opn = "mfc0";
5539 5552 break;
5540 5553 case OPC_MTC0:
5541   - gen_load_gpr(cpu_T[0], rt);
5542   - save_cpu_state(ctx, 1);
5543   - gen_mtc0(env, ctx, rd, ctx->opcode & 0x7);
  5554 + {
  5555 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  5556 +
  5557 + gen_load_gpr(t0, rt);
  5558 + save_cpu_state(ctx, 1);
  5559 + gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
  5560 + tcg_temp_free(t0);
  5561 + }
5544 5562 opn = "mtc0";
5545 5563 break;
5546 5564 #if defined(TARGET_MIPS64)
... ... @@ -5550,15 +5568,25 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5550 5568 /* Treat as NOP. */
5551 5569 return;
5552 5570 }
5553   - gen_dmfc0(env, ctx, rd, ctx->opcode & 0x7);
5554   - gen_store_gpr(cpu_T[0], rt);
  5571 + {
  5572 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  5573 +
  5574 + gen_dmfc0(env, ctx, t0, rd, ctx->opcode & 0x7);
  5575 + gen_store_gpr(t0, rt);
  5576 + tcg_temp_free(t0);
  5577 + }
5555 5578 opn = "dmfc0";
5556 5579 break;
5557 5580 case OPC_DMTC0:
5558 5581 check_insn(env, ctx, ISA_MIPS3);
5559   - gen_load_gpr(cpu_T[0], rt);
5560   - save_cpu_state(ctx, 1);
5561   - gen_dmtc0(env, ctx, rd, ctx->opcode & 0x7);
  5582 + {
  5583 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  5584 +
  5585 + gen_load_gpr(t0, rt);
  5586 + save_cpu_state(ctx, 1);
  5587 + gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
  5588 + tcg_temp_free(t0);
  5589 + }
5562 5590 opn = "dmtc0";
5563 5591 break;
5564 5592 #endif
... ... @@ -8069,12 +8097,6 @@ static void mips_tcg_init(void)
8069 8097 TCG_AREG0,
8070 8098 offsetof(CPUState, fpu),
8071 8099 "current_fpu");
8072   -#if TARGET_LONG_BITS > HOST_LONG_BITS
8073   - cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
8074   - TCG_AREG0, offsetof(CPUState, t0), "T0");
8075   -#else
8076   - cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
8077   -#endif
8078 8100  
8079 8101 /* register helpers */
8080 8102 #undef DEF_HELPER
... ...