gwj / at91sam9263 · Commits

Commit 1a2fb1c0093c9ac1bceec8b5cbe550c478f2e7b3

Authored by blueswir1
1 parent f8422f52

Modify Sparc32/64 to use TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3989 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 7 changed files with 878 additions and 1551 deletions
target-sparc/exec.h
  View file @1a2fb1c
@@ -52,12 +52,6 @@ register uint32_t T2 asm(AREG3); @@ -52,12 +52,6 @@ register uint32_t T2 asm(AREG3);
52 void cpu_lock(void); 52 void cpu_lock(void);
53 void cpu_unlock(void); 53 void cpu_unlock(void);
54 void cpu_loop_exit(void); 54 void cpu_loop_exit(void);
55 -void helper_flush(target_ulong addr);  
56 -void helper_ld_asi(int asi, int size, int sign);  
57 -void helper_st_asi(int asi, int size);  
58 -void helper_ldf_asi(int asi, int size, int rd);  
59 -void helper_stf_asi(int asi, int size, int rd);  
60 -void helper_rett(void);  
61 void helper_ldfsr(void); 55 void helper_ldfsr(void);
62 void set_cwp(int new_cwp); 56 void set_cwp(int new_cwp);
63 void do_fitos(void); 57 void do_fitos(void);
@@ -101,23 +95,13 @@ void do_fcmpeq_fcc1(void); @@ -101,23 +95,13 @@ void do_fcmpeq_fcc1(void);
101 void do_fcmpeq_fcc2(void); 95 void do_fcmpeq_fcc2(void);
102 void do_fcmpeq_fcc3(void); 96 void do_fcmpeq_fcc3(void);
103 #endif 97 #endif
104 -void do_popc();  
105 -void do_wrpstate();  
106 -void do_done();  
107 -void do_retry();  
108 #endif 98 #endif
109 -void do_ldd_kernel(target_ulong addr);  
110 -void do_ldd_user(target_ulong addr);  
111 -void do_ldd_raw(target_ulong addr);  
112 void do_interrupt(int intno); 99 void do_interrupt(int intno);
113 void raise_exception(int tt); 100 void raise_exception(int tt);
114 void check_ieee_exceptions(); 101 void check_ieee_exceptions();
115 void memcpy32(target_ulong *dst, const target_ulong *src); 102 void memcpy32(target_ulong *dst, const target_ulong *src);
116 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev); 103 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev);
117 void dump_mmu(CPUState *env); 104 void dump_mmu(CPUState *env);
118 -void helper_debug();  
119 -void do_wrpsr();  
120 -void do_rdpsr();  
121 105
122 /* XXX: move that to a generic header */ 106 /* XXX: move that to a generic header */
123 #if !defined(CONFIG_USER_ONLY) 107 #if !defined(CONFIG_USER_ONLY)
target-sparc/helper.h 0 → 100644
  View file @1a2fb1c
  1 +#define TCG_HELPER_PROTO
  2 +
  3 +#ifndef TARGET_SPARC64
  4 +void TCG_HELPER_PROTO helper_rett(void);
  5 +void TCG_HELPER_PROTO helper_wrpsr(target_ulong new_psr);
  6 +target_ulong TCG_HELPER_PROTO helper_rdpsr(void);
  7 +#else
  8 +void TCG_HELPER_PROTO helper_wrpstate(target_ulong new_state);
  9 +void TCG_HELPER_PROTO helper_done(void);
  10 +void TCG_HELPER_PROTO helper_retry(void);
  11 +target_ulong TCG_HELPER_PROTO helper_popc(target_ulong val);
  12 +void TCG_HELPER_PROTO helper_ldf_asi(target_ulong addr, int asi, int size,
  13 + int rd);
  14 +void TCG_HELPER_PROTO helper_stf_asi(target_ulong addr, int asi, int size,
  15 + int rd);
  16 +target_ulong TCG_HELPER_PROTO
  17 +helper_cas_asi(target_ulong addr, target_ulong val1,
  18 + target_ulong val2, uint32_t asi);
  19 +target_ulong TCG_HELPER_PROTO
  20 +helper_casx_asi(target_ulong addr, target_ulong val1,
  21 + target_ulong val2, uint32_t asi);
  22 +#endif
  23 +void TCG_HELPER_PROTO helper_trap(target_ulong nb_trap);
  24 +void TCG_HELPER_PROTO helper_trapcc(target_ulong nb_trap,
  25 + target_ulong do_trap);
  26 +void TCG_HELPER_PROTO helper_debug(void);
  27 +void TCG_HELPER_PROTO helper_flush(target_ulong addr);
  28 +uint64_t TCG_HELPER_PROTO helper_pack64(target_ulong high, target_ulong low);
  29 +uint64_t TCG_HELPER_PROTO helper_ld_asi(target_ulong addr, int asi,
  30 + int size, int sign);
  31 +void TCG_HELPER_PROTO helper_st_asi(target_ulong addr, uint64_t val, int asi,
  32 + int size);
target-sparc/op.c
  View file @1a2fb1c
@@ -19,104 +19,7 @@ @@ -19,104 +19,7 @@
19 */ 19 */
20 20
21 #include "exec.h" 21 #include "exec.h"
22 -  
23 - /*XXX*/  
24 -#define REGNAME g0  
25 -#define REG (env->gregs[0])  
26 -#include "op_template.h"  
27 -#define REGNAME g1  
28 -#define REG (env->gregs[1])  
29 -#include "op_template.h"  
30 -#define REGNAME g2  
31 -#define REG (env->gregs[2])  
32 -#include "op_template.h"  
33 -#define REGNAME g3  
34 -#define REG (env->gregs[3])  
35 -#include "op_template.h"  
36 -#define REGNAME g4  
37 -#define REG (env->gregs[4])  
38 -#include "op_template.h"  
39 -#define REGNAME g5  
40 -#define REG (env->gregs[5])  
41 -#include "op_template.h"  
42 -#define REGNAME g6  
43 -#define REG (env->gregs[6])  
44 -#include "op_template.h"  
45 -#define REGNAME g7  
46 -#define REG (env->gregs[7])  
47 -#include "op_template.h"  
48 -#define REGNAME i0  
49 -#define REG (REGWPTR[16])  
50 -#include "op_template.h"  
51 -#define REGNAME i1  
52 -#define REG (REGWPTR[17])  
53 -#include "op_template.h"  
54 -#define REGNAME i2  
55 -#define REG (REGWPTR[18])  
56 -#include "op_template.h"  
57 -#define REGNAME i3  
58 -#define REG (REGWPTR[19])  
59 -#include "op_template.h"  
60 -#define REGNAME i4  
61 -#define REG (REGWPTR[20])  
62 -#include "op_template.h"  
63 -#define REGNAME i5  
64 -#define REG (REGWPTR[21])  
65 -#include "op_template.h"  
66 -#define REGNAME i6  
67 -#define REG (REGWPTR[22])  
68 -#include "op_template.h"  
69 -#define REGNAME i7  
70 -#define REG (REGWPTR[23])  
71 -#include "op_template.h"  
72 -#define REGNAME l0  
73 -#define REG (REGWPTR[8])  
74 -#include "op_template.h"  
75 -#define REGNAME l1  
76 -#define REG (REGWPTR[9])  
77 -#include "op_template.h"  
78 -#define REGNAME l2  
79 -#define REG (REGWPTR[10])  
80 -#include "op_template.h"  
81 -#define REGNAME l3  
82 -#define REG (REGWPTR[11])  
83 -#include "op_template.h"  
84 -#define REGNAME l4  
85 -#define REG (REGWPTR[12])  
86 -#include "op_template.h"  
87 -#define REGNAME l5  
88 -#define REG (REGWPTR[13])  
89 -#include "op_template.h"  
90 -#define REGNAME l6  
91 -#define REG (REGWPTR[14])  
92 -#include "op_template.h"  
93 -#define REGNAME l7  
94 -#define REG (REGWPTR[15])  
95 -#include "op_template.h"  
96 -#define REGNAME o0  
97 -#define REG (REGWPTR[0])  
98 -#include "op_template.h"  
99 -#define REGNAME o1  
100 -#define REG (REGWPTR[1])  
101 -#include "op_template.h"  
102 -#define REGNAME o2  
103 -#define REG (REGWPTR[2])  
104 -#include "op_template.h"  
105 -#define REGNAME o3  
106 -#define REG (REGWPTR[3])  
107 -#include "op_template.h"  
108 -#define REGNAME o4  
109 -#define REG (REGWPTR[4])  
110 -#include "op_template.h"  
111 -#define REGNAME o5  
112 -#define REG (REGWPTR[5])  
113 -#include "op_template.h"  
114 -#define REGNAME o6  
115 -#define REG (REGWPTR[6])  
116 -#include "op_template.h"  
117 -#define REGNAME o7  
118 -#define REG (REGWPTR[7])  
119 -#include "op_template.h" 22 +#include "helper.h"
120 23
121 #define REGNAME f0 24 #define REGNAME f0
122 #define REG (env->fpr[0]) 25 #define REG (env->fpr[0])
@@ -267,106 +170,11 @@ @@ -267,106 +170,11 @@
267 #endif 170 #endif
268 171
269 #ifdef TARGET_SPARC64 172 #ifdef TARGET_SPARC64
270 -#ifdef WORDS_BIGENDIAN  
271 -typedef union UREG64 {  
272 - struct { uint16_t v3, v2, v1, v0; } w;  
273 - struct { uint32_t v1, v0; } l;  
274 - uint64_t q;  
275 -} UREG64;  
276 -#else  
277 -typedef union UREG64 {  
278 - struct { uint16_t v0, v1, v2, v3; } w;  
279 - struct { uint32_t v0, v1; } l;  
280 - uint64_t q;  
281 -} UREG64;  
282 -#endif  
283 -  
284 -#define PARAMQ1 \  
285 -({\  
286 - UREG64 __p;\  
287 - __p.l.v1 = PARAM1;\  
288 - __p.l.v0 = PARAM2;\  
289 - __p.q;\  
290 -})  
291 -  
292 -void OPPROTO op_movq_T0_im64(void)  
293 -{  
294 - T0 = PARAMQ1;  
295 -}  
296 -  
297 -void OPPROTO op_movq_T1_im64(void)  
298 -{  
299 - T1 = PARAMQ1;  
300 -}  
301 -  
302 #define XFLAG_SET(x) ((env->xcc&x)?1:0) 173 #define XFLAG_SET(x) ((env->xcc&x)?1:0)
303 -  
304 -#else  
305 -#define EIP (env->pc)  
306 #endif 174 #endif
307 175
308 #define FLAG_SET(x) ((env->psr&x)?1:0) 176 #define FLAG_SET(x) ((env->psr&x)?1:0)
309 177
310 -void OPPROTO op_movl_T0_0(void)  
311 -{  
312 - T0 = 0;  
313 -}  
314 -  
315 -void OPPROTO op_movl_T0_im(void)  
316 -{  
317 - T0 = (uint32_t)PARAM1;  
318 -}  
319 -  
320 -void OPPROTO op_movl_T1_im(void)  
321 -{  
322 - T1 = (uint32_t)PARAM1;  
323 -}  
324 -  
325 -void OPPROTO op_movl_T2_im(void)  
326 -{  
327 - T2 = (uint32_t)PARAM1;  
328 -}  
329 -  
330 -void OPPROTO op_movl_T0_sim(void)  
331 -{  
332 - T0 = (int32_t)PARAM1;  
333 -}  
334 -  
335 -void OPPROTO op_movl_T1_sim(void)  
336 -{  
337 - T1 = (int32_t)PARAM1;  
338 -}  
339 -  
340 -void OPPROTO op_movl_T2_sim(void)  
341 -{  
342 - T2 = (int32_t)PARAM1;  
343 -}  
344 -  
345 -void OPPROTO op_movl_T0_env(void)  
346 -{  
347 - T0 = *(uint32_t *)((char *)env + PARAM1);  
348 -}  
349 -  
350 -void OPPROTO op_movl_env_T0(void)  
351 -{  
352 - *(uint32_t *)((char *)env + PARAM1) = T0;  
353 -}  
354 -  
355 -void OPPROTO op_movtl_T0_env(void)  
356 -{  
357 - T0 = *(target_ulong *)((char *)env + PARAM1);  
358 -}  
359 -  
360 -void OPPROTO op_movtl_env_T0(void)  
361 -{  
362 - *(target_ulong *)((char *)env + PARAM1) = T0;  
363 -}  
364 -  
365 -void OPPROTO op_add_T1_T0(void)  
366 -{  
367 - T0 += T1;  
368 -}  
369 -  
370 void OPPROTO op_add_T1_T0_cc(void) 178 void OPPROTO op_add_T1_T0_cc(void)
371 { 179 {
372 target_ulong src1; 180 target_ulong src1;
@@ -565,11 +373,6 @@ void OPPROTO op_tadd_T1_T0_ccTV(void) @@ -565,11 +373,6 @@ void OPPROTO op_tadd_T1_T0_ccTV(void)
565 FORCE_RET(); 373 FORCE_RET();
566 } 374 }
567 375
568 -void OPPROTO op_sub_T1_T0(void)  
569 -{  
570 - T0 -= T1;  
571 -}  
572 -  
573 void OPPROTO op_sub_T1_T0_cc(void) 376 void OPPROTO op_sub_T1_T0_cc(void)
574 { 377 {
575 target_ulong src1; 378 target_ulong src1;
@@ -765,21 +568,6 @@ void OPPROTO op_tsub_T1_T0_ccTV(void) @@ -765,21 +568,6 @@ void OPPROTO op_tsub_T1_T0_ccTV(void)
765 FORCE_RET(); 568 FORCE_RET();
766 } 569 }
767 570
768 -void OPPROTO op_and_T1_T0(void)  
769 -{  
770 - T0 &= T1;  
771 -}  
772 -  
773 -void OPPROTO op_or_T1_T0(void)  
774 -{  
775 - T0 |= T1;  
776 -}  
777 -  
778 -void OPPROTO op_xor_T1_T0(void)  
779 -{  
780 - T0 ^= T1;  
781 -}  
782 -  
783 void OPPROTO op_andn_T1_T0(void) 571 void OPPROTO op_andn_T1_T0(void)
784 { 572 {
785 T0 &= ~T1; 573 T0 &= ~T1;
@@ -921,12 +709,6 @@ void OPPROTO op_div_cc(void) @@ -921,12 +709,6 @@ void OPPROTO op_div_cc(void)
921 } 709 }
922 710
923 #ifdef TARGET_SPARC64 711 #ifdef TARGET_SPARC64
924 -void OPPROTO op_mulx_T1_T0(void)  
925 -{  
926 - T0 *= T1;  
927 - FORCE_RET();  
928 -}  
929 -  
930 void OPPROTO op_udivx_T1_T0(void) 712 void OPPROTO op_udivx_T1_T0(void)
931 { 713 {
932 if (T1 == 0) { 714 if (T1 == 0) {
@@ -972,48 +754,6 @@ void OPPROTO op_logic_T0_cc(void) @@ -972,48 +754,6 @@ void OPPROTO op_logic_T0_cc(void)
972 FORCE_RET(); 754 FORCE_RET();
973 } 755 }
974 756
975 -void OPPROTO op_sll(void)  
976 -{  
977 - T0 <<= (T1 & 0x1f);  
978 -}  
979 -  
980 -#ifdef TARGET_SPARC64  
981 -void OPPROTO op_sllx(void)  
982 -{  
983 - T0 <<= (T1 & 0x3f);  
984 -}  
985 -  
986 -void OPPROTO op_srl(void)  
987 -{  
988 - T0 = (T0 & 0xffffffff) >> (T1 & 0x1f);  
989 -}  
990 -  
991 -void OPPROTO op_srlx(void)  
992 -{  
993 - T0 >>= (T1 & 0x3f);  
994 -}  
995 -  
996 -void OPPROTO op_sra(void)  
997 -{  
998 - T0 = ((int32_t) (T0 & 0xffffffff)) >> (T1 & 0x1f);  
999 -}  
1000 -  
1001 -void OPPROTO op_srax(void)  
1002 -{  
1003 - T0 = ((int64_t) T0) >> (T1 & 0x3f);  
1004 -}  
1005 -#else  
1006 -void OPPROTO op_srl(void)  
1007 -{  
1008 - T0 >>= (T1 & 0x1f);  
1009 -}  
1010 -  
1011 -void OPPROTO op_sra(void)  
1012 -{  
1013 - T0 = ((int32_t) T0) >> (T1 & 0x1f);  
1014 -}  
1015 -#endif  
1016 -  
1017 /* Load and store */ 757 /* Load and store */
1018 #define MEMSUFFIX _raw 758 #define MEMSUFFIX _raw
1019 #include "op_mem.h" 759 #include "op_mem.h"
@@ -1042,32 +782,6 @@ void OPPROTO op_stfsr(void) @@ -1042,32 +782,6 @@ void OPPROTO op_stfsr(void)
1042 } 782 }
1043 783
1044 #ifndef TARGET_SPARC64 784 #ifndef TARGET_SPARC64
1045 -void OPPROTO op_rdpsr(void)  
1046 -{  
1047 - do_rdpsr();  
1048 -}  
1049 -  
1050 -void OPPROTO op_wrpsr(void)  
1051 -{  
1052 - do_wrpsr();  
1053 - FORCE_RET();  
1054 -}  
1055 -  
1056 -void OPPROTO op_wrwim(void)  
1057 -{  
1058 -#if NWINDOWS == 32  
1059 - env->wim = T0;  
1060 -#else  
1061 - env->wim = T0 & ((1 << NWINDOWS) - 1);  
1062 -#endif  
1063 -}  
1064 -  
1065 -void OPPROTO op_rett(void)  
1066 -{  
1067 - helper_rett();  
1068 - FORCE_RET();  
1069 -}  
1070 -  
1071 /* XXX: use another pointer for %iN registers to avoid slow wrapping 785 /* XXX: use another pointer for %iN registers to avoid slow wrapping
1072 handling ? */ 786 handling ? */
1073 void OPPROTO op_save(void) 787 void OPPROTO op_save(void)
@@ -1178,16 +892,6 @@ void OPPROTO op_wrtt(void) @@ -1178,16 +892,6 @@ void OPPROTO op_wrtt(void)
1178 env->tt[env->tl] = T0; 892 env->tt[env->tl] = T0;
1179 } 893 }
1180 894
1181 -void OPPROTO op_rdpstate(void)  
1182 -{  
1183 - T0 = env->pstate;  
1184 -}  
1185 -  
1186 -void OPPROTO op_wrpstate(void)  
1187 -{  
1188 - do_wrpstate();  
1189 -}  
1190 -  
1191 // CWP handling is reversed in V9, but we still use the V8 register 895 // CWP handling is reversed in V9, but we still use the V8 register
1192 // order. 896 // order.
1193 void OPPROTO op_rdcwp(void) 897 void OPPROTO op_rdcwp(void)
@@ -1247,22 +951,6 @@ void OPPROTO op_exception(void) @@ -1247,22 +951,6 @@ void OPPROTO op_exception(void)
1247 FORCE_RET(); 951 FORCE_RET();
1248 } 952 }
1249 953
1250 -void OPPROTO op_trap_T0(void)  
1251 -{  
1252 - env->exception_index = TT_TRAP + (T0 & 0x7f);  
1253 - cpu_loop_exit();  
1254 - FORCE_RET();  
1255 -}  
1256 -  
1257 -void OPPROTO op_trapcc_T0(void)  
1258 -{  
1259 - if (T2) {  
1260 - env->exception_index = TT_TRAP + (T0 & 0x7f);  
1261 - cpu_loop_exit();  
1262 - }  
1263 - FORCE_RET();  
1264 -}  
1265 -  
1266 void OPPROTO op_fpexception_im(void) 954 void OPPROTO op_fpexception_im(void)
1267 { 955 {
1268 env->exception_index = TT_FP_EXCP; 956 env->exception_index = TT_FP_EXCP;
@@ -1272,11 +960,6 @@ void OPPROTO op_fpexception_im(void) @@ -1272,11 +960,6 @@ void OPPROTO op_fpexception_im(void)
1272 FORCE_RET(); 960 FORCE_RET();
1273 } 961 }
1274 962
1275 -void OPPROTO op_debug(void)  
1276 -{  
1277 - helper_debug();  
1278 -}  
1279 -  
1280 void OPPROTO op_eval_ba(void) 963 void OPPROTO op_eval_ba(void)
1281 { 964 {
1282 T2 = 1; 965 T2 = 1;
@@ -1499,33 +1182,8 @@ void OPPROTO op_eval_brgez(void) @@ -1499,33 +1182,8 @@ void OPPROTO op_eval_brgez(void)
1499 { 1182 {
1500 T2 = ((int64_t)T0 >= 0); 1183 T2 = ((int64_t)T0 >= 0);
1501 } 1184 }
1502 -  
1503 -void OPPROTO op_jmp_im64(void)  
1504 -{  
1505 - env->pc = PARAMQ1;  
1506 -}  
1507 -  
1508 -void OPPROTO op_movq_npc_im64(void)  
1509 -{  
1510 - env->npc = PARAMQ1;  
1511 -}  
1512 #endif 1185 #endif
1513 1186
1514 -void OPPROTO op_jmp_im(void)  
1515 -{  
1516 - env->pc = (uint32_t)PARAM1;  
1517 -}  
1518 -  
1519 -void OPPROTO op_movl_npc_im(void)  
1520 -{  
1521 - env->npc = (uint32_t)PARAM1;  
1522 -}  
1523 -  
1524 -void OPPROTO op_movl_npc_T0(void)  
1525 -{  
1526 - env->npc = T0;  
1527 -}  
1528 -  
1529 void OPPROTO op_mov_pc_npc(void) 1187 void OPPROTO op_mov_pc_npc(void)
1530 { 1188 {
1531 env->pc = env->npc; 1189 env->pc = env->npc;
@@ -1556,11 +1214,6 @@ void OPPROTO op_jz_T2_label(void) @@ -1556,11 +1214,6 @@ void OPPROTO op_jz_T2_label(void)
1556 FORCE_RET(); 1214 FORCE_RET();
1557 } 1215 }
1558 1216
1559 -void OPPROTO op_flush_T0(void)  
1560 -{  
1561 - helper_flush(T0);  
1562 -}  
1563 -  
1564 void OPPROTO op_clear_ieee_excp_and_FTT(void) 1217 void OPPROTO op_clear_ieee_excp_and_FTT(void)
1565 { 1218 {
1566 env->fsr &= ~(FSR_FTT_MASK | FSR_CEXC_MASK);; 1219 env->fsr &= ~(FSR_FTT_MASK | FSR_CEXC_MASK);;
@@ -1993,210 +1646,6 @@ void OPPROTO op_restored(void) @@ -1993,210 +1646,6 @@ void OPPROTO op_restored(void)
1993 env->otherwin--; 1646 env->otherwin--;
1994 FORCE_RET(); 1647 FORCE_RET();
1995 } 1648 }
1996 -  
1997 -void OPPROTO op_popc(void)  
1998 -{  
1999 - do_popc();  
2000 -}  
2001 -  
2002 -void OPPROTO op_done(void)  
2003 -{  
2004 - do_done();  
2005 -}  
2006 -  
2007 -void OPPROTO op_retry(void)  
2008 -{  
2009 - do_retry();  
2010 -}  
2011 -  
2012 -void OPPROTO op_sir(void)  
2013 -{  
2014 - T0 = 0; // XXX  
2015 -}  
2016 -  
2017 -void OPPROTO op_ld_asi_reg()  
2018 -{  
2019 - T0 += PARAM1;  
2020 - helper_ld_asi(env->asi, PARAM2, PARAM3);  
2021 -}  
2022 -  
2023 -void OPPROTO op_st_asi_reg()  
2024 -{  
2025 - T0 += PARAM1;  
2026 - helper_st_asi(env->asi, PARAM2);  
2027 -}  
2028 -  
2029 -void OPPROTO op_ldf_asi_reg()  
2030 -{  
2031 - T0 += PARAM1;  
2032 - helper_ldf_asi(env->asi, PARAM2, PARAM3);  
2033 -}  
2034 -  
2035 -void OPPROTO op_stf_asi_reg()  
2036 -{  
2037 - T0 += PARAM1;  
2038 - helper_stf_asi(env->asi, PARAM2, PARAM3);  
2039 -}  
2040 -  
2041 -void OPPROTO op_ldf_asi()  
2042 -{  
2043 - helper_ldf_asi(PARAM1, PARAM2, PARAM3);  
2044 -}  
2045 -  
2046 -void OPPROTO op_stf_asi()  
2047 -{  
2048 - helper_stf_asi(PARAM1, PARAM2, PARAM3);  
2049 -}  
2050 -  
2051 -void OPPROTO op_ldstub_asi_reg() /* XXX: should be atomically */  
2052 -{  
2053 - target_ulong tmp;  
2054 -  
2055 - T0 += PARAM1;  
2056 - helper_ld_asi(env->asi, 1, 0);  
2057 - tmp = T1;  
2058 - T1 = 0xff;  
2059 - helper_st_asi(env->asi, 1);  
2060 - T1 = tmp;  
2061 -}  
2062 -  
2063 -void OPPROTO op_swap_asi_reg() /* XXX: should be atomically */  
2064 -{  
2065 - target_ulong tmp1, tmp2;  
2066 -  
2067 - T0 += PARAM1;  
2068 - tmp1 = T1;  
2069 - helper_ld_asi(env->asi, 4, 0);  
2070 - tmp2 = T1;  
2071 - T1 = tmp1;  
2072 - helper_st_asi(env->asi, 4);  
2073 - T1 = tmp2;  
2074 -}  
2075 -  
2076 -void OPPROTO op_ldda_asi()  
2077 -{  
2078 - helper_ld_asi(PARAM1, 8, 0);  
2079 - T0 = T1 & 0xffffffffUL;  
2080 - T1 >>= 32;  
2081 -}  
2082 -  
2083 -void OPPROTO op_ldda_asi_reg()  
2084 -{  
2085 - T0 += PARAM1;  
2086 - helper_ld_asi(env->asi, 8, 0);  
2087 - T0 = T1 & 0xffffffffUL;  
2088 - T1 >>= 32;  
2089 -}  
2090 -  
2091 -void OPPROTO op_stda_asi()  
2092 -{  
2093 - T1 <<= 32;  
2094 - T1 += T2 & 0xffffffffUL;  
2095 - helper_st_asi(PARAM1, 8);  
2096 -}  
2097 -  
2098 -void OPPROTO op_stda_asi_reg()  
2099 -{  
2100 - T0 += PARAM1;  
2101 - T1 <<= 32;  
2102 - T1 += T2 & 0xffffffffUL;  
2103 - helper_st_asi(env->asi, 8);  
2104 -}  
2105 -  
2106 -void OPPROTO op_cas_asi() /* XXX: should be atomically */  
2107 -{  
2108 - target_ulong tmp;  
2109 -  
2110 - tmp = T1 & 0xffffffffUL;  
2111 - helper_ld_asi(PARAM1, 4, 0);  
2112 - if (tmp == T1) {  
2113 - tmp = T1;  
2114 - T1 = T2 & 0xffffffffUL;  
2115 - helper_st_asi(PARAM1, 4);  
2116 - T1 = tmp;  
2117 - }  
2118 - T1 &= 0xffffffffUL;  
2119 -}  
2120 -  
2121 -void OPPROTO op_cas_asi_reg() /* XXX: should be atomically */  
2122 -{  
2123 - target_ulong tmp;  
2124 -  
2125 - T0 += PARAM1;  
2126 - tmp = T1 & 0xffffffffUL;  
2127 - helper_ld_asi(env->asi, 4, 0);  
2128 - if (tmp == T1) {  
2129 - tmp = T1;  
2130 - T1 = T2 & 0xffffffffUL;  
2131 - helper_st_asi(env->asi, 4);  
2132 - T1 = tmp;  
2133 - }  
2134 - T1 &= 0xffffffffUL;  
2135 -}  
2136 -  
2137 -void OPPROTO op_casx_asi() /* XXX: should be atomically */  
2138 -{  
2139 - target_ulong tmp;  
2140 -  
2141 - tmp = T1;  
2142 - helper_ld_asi(PARAM1, 8, 0);  
2143 - if (tmp == T1) {  
2144 - tmp = T1;  
2145 - T1 = T2;  
2146 - helper_st_asi(PARAM1, 8);  
2147 - T1 = tmp;  
2148 - }  
2149 -}  
2150 -  
2151 -void OPPROTO op_casx_asi_reg() /* XXX: should be atomically */  
2152 -{  
2153 - target_ulong tmp;  
2154 -  
2155 - T0 += PARAM1;  
2156 - tmp = T1;  
2157 - helper_ld_asi(env->asi, 8, 0);  
2158 - if (tmp == T1) {  
2159 - tmp = T1;  
2160 - T1 = T2;  
2161 - helper_st_asi(env->asi, 8);  
2162 - T1 = tmp;  
2163 - }  
2164 -}  
2165 -#endif  
2166 -  
2167 -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)  
2168 -void OPPROTO op_ld_asi()  
2169 -{  
2170 - helper_ld_asi(PARAM1, PARAM2, PARAM3);  
2171 -}  
2172 -  
2173 -void OPPROTO op_st_asi()  
2174 -{  
2175 - helper_st_asi(PARAM1, PARAM2);  
2176 -}  
2177 -  
2178 -void OPPROTO op_ldstub_asi() /* XXX: should be atomically */  
2179 -{  
2180 - target_ulong tmp;  
2181 -  
2182 - helper_ld_asi(PARAM1, 1, 0);  
2183 - tmp = T1;  
2184 - T1 = 0xff;  
2185 - helper_st_asi(PARAM1, 1);  
2186 - T1 = tmp;  
2187 -}  
2188 -  
2189 -void OPPROTO op_swap_asi() /* XXX: should be atomically */  
2190 -{  
2191 - target_ulong tmp1, tmp2;  
2192 -  
2193 - tmp1 = T1;  
2194 - helper_ld_asi(PARAM1, 4, 0);  
2195 - tmp2 = T1;  
2196 - T1 = tmp1;  
2197 - helper_st_asi(PARAM1, 4);  
2198 - T1 = tmp2;  
2199 -}  
2200 #endif 1649 #endif
2201 1650
2202 #ifdef TARGET_SPARC64 1651 #ifdef TARGET_SPARC64
target-sparc/op_helper.c
  View file @1a2fb1c
1 #include "exec.h" 1 #include "exec.h"
2 #include "host-utils.h" 2 #include "host-utils.h"
  3 +#include "helper.h"
3 4
4 //#define DEBUG_PCALL 5 //#define DEBUG_PCALL
5 //#define DEBUG_MMU 6 //#define DEBUG_MMU
@@ -35,35 +36,47 @@ void raise_exception(int tt) @@ -35,35 +36,47 @@ void raise_exception(int tt)
35 cpu_loop_exit(); 36 cpu_loop_exit();
36 } 37 }
37 38
38 -void check_ieee_exceptions() 39 +void helper_trap(target_ulong nb_trap)
39 { 40 {
40 - T0 = get_float_exception_flags(&env->fp_status);  
41 - if (T0)  
42 - { 41 + env->exception_index = TT_TRAP + (nb_trap & 0x7f);
  42 + cpu_loop_exit();
  43 +}
  44 +
  45 +void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
  46 +{
  47 + if (do_trap) {
  48 + env->exception_index = TT_TRAP + (nb_trap & 0x7f);
  49 + cpu_loop_exit();
  50 + }
  51 +}
  52 +
  53 +void check_ieee_exceptions(void)
  54 +{
  55 + target_ulong status;
  56 +
  57 + status = get_float_exception_flags(&env->fp_status);
  58 + if (status) {
43 /* Copy IEEE 754 flags into FSR */ 59 /* Copy IEEE 754 flags into FSR */
44 - if (T0 & float_flag_invalid) 60 + if (status & float_flag_invalid)
45 env->fsr |= FSR_NVC; 61 env->fsr |= FSR_NVC;
46 - if (T0 & float_flag_overflow) 62 + if (status & float_flag_overflow)
47 env->fsr |= FSR_OFC; 63 env->fsr |= FSR_OFC;
48 - if (T0 & float_flag_underflow) 64 + if (status & float_flag_underflow)
49 env->fsr |= FSR_UFC; 65 env->fsr |= FSR_UFC;
50 - if (T0 & float_flag_divbyzero) 66 + if (status & float_flag_divbyzero)
51 env->fsr |= FSR_DZC; 67 env->fsr |= FSR_DZC;
52 - if (T0 & float_flag_inexact) 68 + if (status & float_flag_inexact)
53 env->fsr |= FSR_NXC; 69 env->fsr |= FSR_NXC;
54 70
55 - if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))  
56 - { 71 + if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
57 /* Unmasked exception, generate a trap */ 72 /* Unmasked exception, generate a trap */
58 env->fsr |= FSR_FTT_IEEE_EXCP; 73 env->fsr |= FSR_FTT_IEEE_EXCP;
59 raise_exception(TT_FP_EXCP); 74 raise_exception(TT_FP_EXCP);
60 - }  
61 - else  
62 - { 75 + } else {
63 /* Accumulate exceptions */ 76 /* Accumulate exceptions */
64 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5; 77 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
65 } 78 }
66 - } 79 + }
67 } 80 }
68 81
69 #ifdef USE_INT_TO_FLOAT_HELPERS 82 #ifdef USE_INT_TO_FLOAT_HELPERS
@@ -157,12 +170,14 @@ void do_fsqrtq(void) @@ -157,12 +170,14 @@ void do_fsqrtq(void)
157 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \ 170 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
158 void glue(do_, name) (void) \ 171 void glue(do_, name) (void) \
159 { \ 172 { \
  173 + target_ulong new_fsr; \
  174 + \
160 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ 175 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
161 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \ 176 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
162 case float_relation_unordered: \ 177 case float_relation_unordered: \
163 - T0 = (FSR_FCC1 | FSR_FCC0) << FS; \ 178 + new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
164 if ((env->fsr & FSR_NVM) || TRAP) { \ 179 if ((env->fsr & FSR_NVM) || TRAP) { \
165 - env->fsr |= T0; \ 180 + env->fsr |= new_fsr; \
166 env->fsr |= FSR_NVC; \ 181 env->fsr |= FSR_NVC; \
167 env->fsr |= FSR_FTT_IEEE_EXCP; \ 182 env->fsr |= FSR_FTT_IEEE_EXCP; \
168 raise_exception(TT_FP_EXCP); \ 183 raise_exception(TT_FP_EXCP); \
@@ -171,16 +186,16 @@ void do_fsqrtq(void) @@ -171,16 +186,16 @@ void do_fsqrtq(void)
171 } \ 186 } \
172 break; \ 187 break; \
173 case float_relation_less: \ 188 case float_relation_less: \
174 - T0 = FSR_FCC0 << FS; \ 189 + new_fsr = FSR_FCC0 << FS; \
175 break; \ 190 break; \
176 case float_relation_greater: \ 191 case float_relation_greater: \
177 - T0 = FSR_FCC1 << FS; \ 192 + new_fsr = FSR_FCC1 << FS; \
178 break; \ 193 break; \
179 default: \ 194 default: \
180 - T0 = 0; \ 195 + new_fsr = 0; \
181 break; \ 196 break; \
182 } \ 197 } \
183 - env->fsr |= T0; \ 198 + env->fsr |= new_fsr; \
184 } 199 }
185 200
186 GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0); 201 GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
@@ -222,10 +237,7 @@ GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); @@ -222,10 +237,7 @@ GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
222 #endif 237 #endif
223 #endif 238 #endif
224 239
225 -#ifndef TARGET_SPARC64  
226 -#ifndef CONFIG_USER_ONLY  
227 -  
228 -#ifdef DEBUG_MXCC 240 +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
229 static void dump_mxcc(CPUState *env) 241 static void dump_mxcc(CPUState *env)
230 { 242 {
231 printf("mxccdata: %016llx %016llx %016llx %016llx\n", 243 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
@@ -237,74 +249,76 @@ static void dump_mxcc(CPUState *env) @@ -237,74 +249,76 @@ static void dump_mxcc(CPUState *env)
237 } 249 }
238 #endif 250 #endif
239 251
240 -#ifdef DEBUG_ASI  
241 -static void dump_asi(const char * txt, uint32_t addr, int asi, int size,  
242 - uint32_t r1, uint32_t r2) 252 +#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
  253 + && defined(DEBUG_ASI)
  254 +static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
  255 + uint64_t r1)
243 { 256 {
244 switch (size) 257 switch (size)
245 { 258 {
246 case 1: 259 case 1:
247 - DPRINTF_ASI("%s %08x asi 0x%02x = %02x\n", txt, addr, asi, r1 & 0xff); 260 + DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
  261 + addr, asi, r1 & 0xff);
248 break; 262 break;
249 case 2: 263 case 2:
250 - DPRINTF_ASI("%s %08x asi 0x%02x = %04x\n", txt, addr, asi, r1 & 0xffff); 264 + DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
  265 + addr, asi, r1 & 0xffff);
251 break; 266 break;
252 case 4: 267 case 4:
253 - DPRINTF_ASI("%s %08x asi 0x%02x = %08x\n", txt, addr, asi, r1); 268 + DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
  269 + addr, asi, r1 & 0xffffffff);
254 break; 270 break;
255 case 8: 271 case 8:
256 - DPRINTF_ASI("%s %08x asi 0x%02x = %016llx\n", txt, addr, asi,  
257 - r2 | ((uint64_t)r1 << 32)); 272 + DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
  273 + addr, asi, r1);
258 break; 274 break;
259 } 275 }
260 } 276 }
261 #endif 277 #endif
262 278
263 -void helper_ld_asi(int asi, int size, int sign) 279 +#ifndef TARGET_SPARC64
  280 +#ifndef CONFIG_USER_ONLY
  281 +uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
264 { 282 {
265 - uint32_t ret = 0;  
266 - uint64_t tmp; 283 + uint64_t ret = 0;
267 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) 284 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
268 - uint32_t last_T0 = T0; 285 + uint32_t last_addr = addr;
269 #endif 286 #endif
270 287
271 switch (asi) { 288 switch (asi) {
272 case 2: /* SuperSparc MXCC registers */ 289 case 2: /* SuperSparc MXCC registers */
273 - switch (T0) { 290 + switch (addr) {
274 case 0x01c00a00: /* MXCC control register */ 291 case 0x01c00a00: /* MXCC control register */
275 - if (size == 8) {  
276 - ret = env->mxccregs[3] >> 32;  
277 - T0 = env->mxccregs[3];  
278 - } else  
279 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 292 + if (size == 8)
  293 + ret = env->mxccregs[3];
  294 + else
  295 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
280 break; 296 break;
281 case 0x01c00a04: /* MXCC control register */ 297 case 0x01c00a04: /* MXCC control register */
282 if (size == 4) 298 if (size == 4)
283 ret = env->mxccregs[3]; 299 ret = env->mxccregs[3];
284 else 300 else
285 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 301 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
286 break; 302 break;
287 case 0x01c00c00: /* Module reset register */ 303 case 0x01c00c00: /* Module reset register */
288 if (size == 8) { 304 if (size == 8) {
289 - ret = env->mxccregs[5] >> 32;  
290 - T0 = env->mxccregs[5]; 305 + ret = env->mxccregs[5];
291 // should we do something here? 306 // should we do something here?
292 } else 307 } else
293 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 308 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
294 break; 309 break;
295 case 0x01c00f00: /* MBus port address register */ 310 case 0x01c00f00: /* MBus port address register */
296 - if (size == 8) {  
297 - ret = env->mxccregs[7] >> 32;  
298 - T0 = env->mxccregs[7];  
299 - } else  
300 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 311 + if (size == 8)
  312 + ret = env->mxccregs[7];
  313 + else
  314 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
301 break; 315 break;
302 default: 316 default:
303 - DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size); 317 + DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
304 break; 318 break;
305 } 319 }
306 - DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"  
307 - "T0 = %08x\n", asi, size, sign, last_T0, ret, T0); 320 + DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
  321 + "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
308 #ifdef DEBUG_MXCC 322 #ifdef DEBUG_MXCC
309 dump_mxcc(env); 323 dump_mxcc(env);
310 #endif 324 #endif
@@ -313,19 +327,18 @@ void helper_ld_asi(int asi, int size, int sign) @@ -313,19 +327,18 @@ void helper_ld_asi(int asi, int size, int sign)
313 { 327 {
314 int mmulev; 328 int mmulev;
315 329
316 - mmulev = (T0 >> 8) & 15; 330 + mmulev = (addr >> 8) & 15;
317 if (mmulev > 4) 331 if (mmulev > 4)
318 ret = 0; 332 ret = 0;
319 - else {  
320 - ret = mmu_probe(env, T0, mmulev);  
321 - //bswap32s(&ret);  
322 - }  
323 - DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret); 333 + else
  334 + ret = mmu_probe(env, addr, mmulev);
  335 + DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
  336 + addr, mmulev, ret);
324 } 337 }
325 break; 338 break;
326 case 4: /* read MMU regs */ 339 case 4: /* read MMU regs */
327 { 340 {
328 - int reg = (T0 >> 8) & 0x1f; 341 + int reg = (addr >> 8) & 0x1f;
329 342
330 ret = env->mmuregs[reg]; 343 ret = env->mmuregs[reg];
331 if (reg == 3) /* Fault status cleared on read */ 344 if (reg == 3) /* Fault status cleared on read */
@@ -334,7 +347,7 @@ void helper_ld_asi(int asi, int size, int sign) @@ -334,7 +347,7 @@ void helper_ld_asi(int asi, int size, int sign)
334 ret = env->mmuregs[3]; 347 ret = env->mmuregs[3];
335 else if (reg == 0x14) /* Fault address read */ 348 else if (reg == 0x14) /* Fault address read */
336 ret = env->mmuregs[4]; 349 ret = env->mmuregs[4];
337 - DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret); 350 + DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
338 } 351 }
339 break; 352 break;
340 case 5: // Turbosparc ITLB Diagnostic 353 case 5: // Turbosparc ITLB Diagnostic
@@ -344,57 +357,51 @@ void helper_ld_asi(int asi, int size, int sign) @@ -344,57 +357,51 @@ void helper_ld_asi(int asi, int size, int sign)
344 case 9: /* Supervisor code access */ 357 case 9: /* Supervisor code access */
345 switch(size) { 358 switch(size) {
346 case 1: 359 case 1:
347 - ret = ldub_code(T0); 360 + ret = ldub_code(addr);
348 break; 361 break;
349 case 2: 362 case 2:
350 - ret = lduw_code(T0 & ~1); 363 + ret = lduw_code(addr & ~1);
351 break; 364 break;
352 default: 365 default:
353 case 4: 366 case 4:
354 - ret = ldl_code(T0 & ~3); 367 + ret = ldl_code(addr & ~3);
355 break; 368 break;
356 case 8: 369 case 8:
357 - tmp = ldq_code(T0 & ~7);  
358 - ret = tmp >> 32;  
359 - T0 = tmp; 370 + ret = ldq_code(addr & ~7);
360 break; 371 break;
361 } 372 }
362 break; 373 break;
363 case 0xa: /* User data access */ 374 case 0xa: /* User data access */
364 switch(size) { 375 switch(size) {
365 case 1: 376 case 1:
366 - ret = ldub_user(T0); 377 + ret = ldub_user(addr);
367 break; 378 break;
368 case 2: 379 case 2:
369 - ret = lduw_user(T0 & ~1); 380 + ret = lduw_user(addr & ~1);
370 break; 381 break;
371 default: 382 default:
372 case 4: 383 case 4:
373 - ret = ldl_user(T0 & ~3); 384 + ret = ldl_user(addr & ~3);
374 break; 385 break;
375 case 8: 386 case 8:
376 - tmp = ldq_user(T0 & ~7);  
377 - ret = tmp >> 32;  
378 - T0 = tmp; 387 + ret = ldq_user(addr & ~7);
379 break; 388 break;
380 } 389 }
381 break; 390 break;
382 case 0xb: /* Supervisor data access */ 391 case 0xb: /* Supervisor data access */
383 switch(size) { 392 switch(size) {
384 case 1: 393 case 1:
385 - ret = ldub_kernel(T0); 394 + ret = ldub_kernel(addr);
386 break; 395 break;
387 case 2: 396 case 2:
388 - ret = lduw_kernel(T0 & ~1); 397 + ret = lduw_kernel(addr & ~1);
389 break; 398 break;
390 default: 399 default:
391 case 4: 400 case 4:
392 - ret = ldl_kernel(T0 & ~3); 401 + ret = ldl_kernel(addr & ~3);
393 break; 402 break;
394 case 8: 403 case 8:
395 - tmp = ldq_kernel(T0 & ~7);  
396 - ret = tmp >> 32;  
397 - T0 = tmp; 404 + ret = ldq_kernel(addr & ~7);
398 break; 405 break;
399 } 406 }
400 break; 407 break;
@@ -406,42 +413,38 @@ void helper_ld_asi(int asi, int size, int sign) @@ -406,42 +413,38 @@ void helper_ld_asi(int asi, int size, int sign)
406 case 0x20: /* MMU passthrough */ 413 case 0x20: /* MMU passthrough */
407 switch(size) { 414 switch(size) {
408 case 1: 415 case 1:
409 - ret = ldub_phys(T0); 416 + ret = ldub_phys(addr);
410 break; 417 break;
411 case 2: 418 case 2:
412 - ret = lduw_phys(T0 & ~1); 419 + ret = lduw_phys(addr & ~1);
413 break; 420 break;
414 default: 421 default:
415 case 4: 422 case 4:
416 - ret = ldl_phys(T0 & ~3); 423 + ret = ldl_phys(addr & ~3);
417 break; 424 break;
418 case 8: 425 case 8:
419 - tmp = ldq_phys(T0 & ~7);  
420 - ret = tmp >> 32;  
421 - T0 = tmp; 426 + ret = ldq_phys(addr & ~7);
422 break; 427 break;
423 } 428 }
424 break; 429 break;
425 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 430 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
426 switch(size) { 431 switch(size) {
427 case 1: 432 case 1:
428 - ret = ldub_phys((target_phys_addr_t)T0 433 + ret = ldub_phys((target_phys_addr_t)addr
429 | ((target_phys_addr_t)(asi & 0xf) << 32)); 434 | ((target_phys_addr_t)(asi & 0xf) << 32));
430 break; 435 break;
431 case 2: 436 case 2:
432 - ret = lduw_phys((target_phys_addr_t)(T0 & ~1) 437 + ret = lduw_phys((target_phys_addr_t)(addr & ~1)
433 | ((target_phys_addr_t)(asi & 0xf) << 32)); 438 | ((target_phys_addr_t)(asi & 0xf) << 32));
434 break; 439 break;
435 default: 440 default:
436 case 4: 441 case 4:
437 - ret = ldl_phys((target_phys_addr_t)(T0 & ~3) 442 + ret = ldl_phys((target_phys_addr_t)(addr & ~3)
438 | ((target_phys_addr_t)(asi & 0xf) << 32)); 443 | ((target_phys_addr_t)(asi & 0xf) << 32));
439 break; 444 break;
440 case 8: 445 case 8:
441 - tmp = ldq_phys((target_phys_addr_t)(T0 & ~7) 446 + ret = ldq_phys((target_phys_addr_t)(addr & ~7)
442 | ((target_phys_addr_t)(asi & 0xf) << 32)); 447 | ((target_phys_addr_t)(asi & 0xf) << 32));
443 - ret = tmp >> 32;  
444 - T0 = tmp;  
445 break; 448 break;
446 } 449 }
447 break; 450 break;
@@ -453,64 +456,65 @@ void helper_ld_asi(int asi, int size, int sign) @@ -453,64 +456,65 @@ void helper_ld_asi(int asi, int size, int sign)
453 break; 456 break;
454 case 8: /* User code access, XXX */ 457 case 8: /* User code access, XXX */
455 default: 458 default:
456 - do_unassigned_access(T0, 0, 0, asi); 459 + do_unassigned_access(addr, 0, 0, asi);
457 ret = 0; 460 ret = 0;
458 break; 461 break;
459 } 462 }
460 if (sign) { 463 if (sign) {
461 switch(size) { 464 switch(size) {
462 case 1: 465 case 1:
463 - T1 = (int8_t) ret; 466 + ret = (int8_t) ret;
464 break; 467 break;
465 case 2: 468 case 2:
466 - T1 = (int16_t) ret; 469 + ret = (int16_t) ret;
  470 + break;
  471 + case 4:
  472 + ret = (int32_t) ret;
467 break; 473 break;
468 default: 474 default:
469 - T1 = ret;  
470 break; 475 break;
471 } 476 }
472 } 477 }
473 - else  
474 - T1 = ret;  
475 #ifdef DEBUG_ASI 478 #ifdef DEBUG_ASI
476 - dump_asi("read ", last_T0, asi, size, T1, T0); 479 + dump_asi("read ", last_addr, asi, size, ret);
477 #endif 480 #endif
  481 + return ret;
478 } 482 }
479 483
480 -void helper_st_asi(int asi, int size) 484 +void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
481 { 485 {
482 switch(asi) { 486 switch(asi) {
483 case 2: /* SuperSparc MXCC registers */ 487 case 2: /* SuperSparc MXCC registers */
484 - switch (T0) { 488 + switch (addr) {
485 case 0x01c00000: /* MXCC stream data register 0 */ 489 case 0x01c00000: /* MXCC stream data register 0 */
486 if (size == 8) 490 if (size == 8)
487 - env->mxccdata[0] = ((uint64_t)T1 << 32) | T2; 491 + env->mxccdata[0] = val;
488 else 492 else
489 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 493 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
490 break; 494 break;
491 case 0x01c00008: /* MXCC stream data register 1 */ 495 case 0x01c00008: /* MXCC stream data register 1 */
492 if (size == 8) 496 if (size == 8)
493 - env->mxccdata[1] = ((uint64_t)T1 << 32) | T2; 497 + env->mxccdata[1] = val;
494 else 498 else
495 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 499 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
496 break; 500 break;
497 case 0x01c00010: /* MXCC stream data register 2 */ 501 case 0x01c00010: /* MXCC stream data register 2 */
498 if (size == 8) 502 if (size == 8)
499 - env->mxccdata[2] = ((uint64_t)T1 << 32) | T2; 503 + env->mxccdata[2] = val;
500 else 504 else
501 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 505 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
502 break; 506 break;
503 case 0x01c00018: /* MXCC stream data register 3 */ 507 case 0x01c00018: /* MXCC stream data register 3 */
504 if (size == 8) 508 if (size == 8)
505 - env->mxccdata[3] = ((uint64_t)T1 << 32) | T2; 509 + env->mxccdata[3] = val;
506 else 510 else
507 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 511 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
508 break; 512 break;
509 case 0x01c00100: /* MXCC stream source */ 513 case 0x01c00100: /* MXCC stream source */
510 if (size == 8) 514 if (size == 8)
511 - env->mxccregs[0] = ((uint64_t)T1 << 32) | T2; 515 + env->mxccregs[0] = val;
512 else 516 else
513 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 517 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
514 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); 518 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
515 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8); 519 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
516 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16); 520 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
@@ -518,9 +522,9 @@ void helper_st_asi(int asi, int size) @@ -518,9 +522,9 @@ void helper_st_asi(int asi, int size)
518 break; 522 break;
519 case 0x01c00200: /* MXCC stream destination */ 523 case 0x01c00200: /* MXCC stream destination */
520 if (size == 8) 524 if (size == 8)
521 - env->mxccregs[1] = ((uint64_t)T1 << 32) | T2; 525 + env->mxccregs[1] = val;
522 else 526 else
523 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 527 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
524 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); 528 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
525 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]); 529 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
526 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]); 530 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
@@ -528,34 +532,34 @@ void helper_st_asi(int asi, int size) @@ -528,34 +532,34 @@ void helper_st_asi(int asi, int size)
528 break; 532 break;
529 case 0x01c00a00: /* MXCC control register */ 533 case 0x01c00a00: /* MXCC control register */
530 if (size == 8) 534 if (size == 8)
531 - env->mxccregs[3] = ((uint64_t)T1 << 32) | T2; 535 + env->mxccregs[3] = val;
532 else 536 else
533 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 537 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
534 break; 538 break;
535 case 0x01c00a04: /* MXCC control register */ 539 case 0x01c00a04: /* MXCC control register */
536 if (size == 4) 540 if (size == 4)
537 - env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | T1; 541 + env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val;
538 else 542 else
539 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 543 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
540 break; 544 break;
541 case 0x01c00e00: /* MXCC error register */ 545 case 0x01c00e00: /* MXCC error register */
542 // writing a 1 bit clears the error 546 // writing a 1 bit clears the error
543 if (size == 8) 547 if (size == 8)
544 - env->mxccregs[6] &= ~(((uint64_t)T1 << 32) | T2); 548 + env->mxccregs[6] &= ~val;
545 else 549 else
546 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 550 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
547 break; 551 break;
548 case 0x01c00f00: /* MBus port address register */ 552 case 0x01c00f00: /* MBus port address register */
549 if (size == 8) 553 if (size == 8)
550 - env->mxccregs[7] = ((uint64_t)T1 << 32) | T2; 554 + env->mxccregs[7] = val;
551 else 555 else
552 - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); 556 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
553 break; 557 break;
554 default: 558 default:
555 - DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size); 559 + DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
556 break; 560 break;
557 } 561 }
558 - DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1); 562 + DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
559 #ifdef DEBUG_MXCC 563 #ifdef DEBUG_MXCC
560 dump_mxcc(env); 564 dump_mxcc(env);
561 #endif 565 #endif
@@ -564,11 +568,11 @@ void helper_st_asi(int asi, int size) @@ -564,11 +568,11 @@ void helper_st_asi(int asi, int size)
564 { 568 {
565 int mmulev; 569 int mmulev;
566 570
567 - mmulev = (T0 >> 8) & 15; 571 + mmulev = (addr >> 8) & 15;
568 DPRINTF_MMU("mmu flush level %d\n", mmulev); 572 DPRINTF_MMU("mmu flush level %d\n", mmulev);
569 switch (mmulev) { 573 switch (mmulev) {
570 case 0: // flush page 574 case 0: // flush page
571 - tlb_flush_page(env, T0 & 0xfffff000); 575 + tlb_flush_page(env, addr & 0xfffff000);
572 break; 576 break;
573 case 1: // flush segment (256k) 577 case 1: // flush segment (256k)
574 case 2: // flush region (16M) 578 case 2: // flush region (16M)
@@ -586,14 +590,14 @@ void helper_st_asi(int asi, int size) @@ -586,14 +590,14 @@ void helper_st_asi(int asi, int size)
586 break; 590 break;
587 case 4: /* write MMU regs */ 591 case 4: /* write MMU regs */
588 { 592 {
589 - int reg = (T0 >> 8) & 0x1f; 593 + int reg = (addr >> 8) & 0x1f;
590 uint32_t oldreg; 594 uint32_t oldreg;
591 595
592 oldreg = env->mmuregs[reg]; 596 oldreg = env->mmuregs[reg];
593 switch(reg) { 597 switch(reg) {
594 case 0: // Control Register 598 case 0: // Control Register
595 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | 599 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
596 - (T1 & 0x00ffffff); 600 + (val & 0x00ffffff);
597 // Mappings generated during no-fault mode or MMU 601 // Mappings generated during no-fault mode or MMU
598 // disabled mode are invalid in normal mode 602 // disabled mode are invalid in normal mode
599 if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) != 603 if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
@@ -601,10 +605,10 @@ void helper_st_asi(int asi, int size) @@ -601,10 +605,10 @@ void helper_st_asi(int asi, int size)
601 tlb_flush(env, 1); 605 tlb_flush(env, 1);
602 break; 606 break;
603 case 1: // Context Table Pointer Register 607 case 1: // Context Table Pointer Register
604 - env->mmuregs[reg] = T1 & env->mmu_ctpr_mask; 608 + env->mmuregs[reg] = val & env->mmu_ctpr_mask;
605 break; 609 break;
606 case 2: // Context Register 610 case 2: // Context Register
607 - env->mmuregs[reg] = T1 & env->mmu_cxr_mask; 611 + env->mmuregs[reg] = val & env->mmu_cxr_mask;
608 if (oldreg != env->mmuregs[reg]) { 612 if (oldreg != env->mmuregs[reg]) {
609 /* we flush when the MMU context changes because 613 /* we flush when the MMU context changes because
610 QEMU has no MMU context support */ 614 QEMU has no MMU context support */
@@ -615,16 +619,16 @@ void helper_st_asi(int asi, int size) @@ -615,16 +619,16 @@ void helper_st_asi(int asi, int size)
615 case 4: // Synchronous Fault Address Register 619 case 4: // Synchronous Fault Address Register
616 break; 620 break;
617 case 0x10: // TLB Replacement Control Register 621 case 0x10: // TLB Replacement Control Register
618 - env->mmuregs[reg] = T1 & env->mmu_trcr_mask; 622 + env->mmuregs[reg] = val & env->mmu_trcr_mask;
619 break; 623 break;
620 case 0x13: // Synchronous Fault Status Register with Read and Clear 624 case 0x13: // Synchronous Fault Status Register with Read and Clear
621 - env->mmuregs[3] = T1 & env->mmu_sfsr_mask; 625 + env->mmuregs[3] = val & env->mmu_sfsr_mask;
622 break; 626 break;
623 case 0x14: // Synchronous Fault Address Register 627 case 0x14: // Synchronous Fault Address Register
624 - env->mmuregs[4] = T1; 628 + env->mmuregs[4] = val;
625 break; 629 break;
626 default: 630 default:
627 - env->mmuregs[reg] = T1; 631 + env->mmuregs[reg] = val;
628 break; 632 break;
629 } 633 }
630 if (oldreg != env->mmuregs[reg]) { 634 if (oldreg != env->mmuregs[reg]) {
@@ -642,34 +646,34 @@ void helper_st_asi(int asi, int size) @@ -642,34 +646,34 @@ void helper_st_asi(int asi, int size)
642 case 0xa: /* User data access */ 646 case 0xa: /* User data access */
643 switch(size) { 647 switch(size) {
644 case 1: 648 case 1:
645 - stb_user(T0, T1); 649 + stb_user(addr, val);
646 break; 650 break;
647 case 2: 651 case 2:
648 - stw_user(T0 & ~1, T1); 652 + stw_user(addr & ~1, val);
649 break; 653 break;
650 default: 654 default:
651 case 4: 655 case 4:
652 - stl_user(T0 & ~3, T1); 656 + stl_user(addr & ~3, val);
653 break; 657 break;
654 case 8: 658 case 8:
655 - stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2); 659 + stq_user(addr & ~7, val);
656 break; 660 break;
657 } 661 }
658 break; 662 break;
659 case 0xb: /* Supervisor data access */ 663 case 0xb: /* Supervisor data access */
660 switch(size) { 664 switch(size) {
661 case 1: 665 case 1:
662 - stb_kernel(T0, T1); 666 + stb_kernel(addr, val);
663 break; 667 break;
664 case 2: 668 case 2:
665 - stw_kernel(T0 & ~1, T1); 669 + stw_kernel(addr & ~1, val);
666 break; 670 break;
667 default: 671 default:
668 case 4: 672 case 4:
669 - stl_kernel(T0 & ~3, T1); 673 + stl_kernel(addr & ~3, val);
670 break; 674 break;
671 case 8: 675 case 8:
672 - stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2); 676 + stq_kernel(addr & ~7, val);
673 break; 677 break;
674 } 678 }
675 break; 679 break;
@@ -685,11 +689,11 @@ void helper_st_asi(int asi, int size) @@ -685,11 +689,11 @@ void helper_st_asi(int asi, int size)
685 break; 689 break;
686 case 0x17: /* Block copy, sta access */ 690 case 0x17: /* Block copy, sta access */
687 { 691 {
688 - // value (T1) = src  
689 - // address (T0) = dst 692 + // val = src
  693 + // addr = dst
690 // copy 32 bytes 694 // copy 32 bytes
691 unsigned int i; 695 unsigned int i;
692 - uint32_t src = T1 & ~3, dst = T0 & ~3, temp; 696 + uint32_t src = val & ~3, dst = addr & ~3, temp;
693 697
694 for (i = 0; i < 32; i += 4, src += 4, dst += 4) { 698 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
695 temp = ldl_kernel(src); 699 temp = ldl_kernel(src);
@@ -699,14 +703,10 @@ void helper_st_asi(int asi, int size) @@ -699,14 +703,10 @@ void helper_st_asi(int asi, int size)
699 break; 703 break;
700 case 0x1f: /* Block fill, stda access */ 704 case 0x1f: /* Block fill, stda access */
701 { 705 {
702 - // value (T1, T2)  
703 - // address (T0) = dst  
704 - // fill 32 bytes 706 + // addr = dst
  707 + // fill 32 bytes with val
705 unsigned int i; 708 unsigned int i;
706 - uint32_t dst = T0 & 7;  
707 - uint64_t val;  
708 -  
709 - val = (((uint64_t)T1) << 32) | T2; 709 + uint32_t dst = addr & 7;
710 710
711 for (i = 0; i < 32; i += 8, dst += 8) 711 for (i = 0; i < 32; i += 8, dst += 8)
712 stq_kernel(dst, val); 712 stq_kernel(dst, val);
@@ -716,17 +716,17 @@ void helper_st_asi(int asi, int size) @@ -716,17 +716,17 @@ void helper_st_asi(int asi, int size)
716 { 716 {
717 switch(size) { 717 switch(size) {
718 case 1: 718 case 1:
719 - stb_phys(T0, T1); 719 + stb_phys(addr, val);
720 break; 720 break;
721 case 2: 721 case 2:
722 - stw_phys(T0 & ~1, T1); 722 + stw_phys(addr & ~1, val);
723 break; 723 break;
724 case 4: 724 case 4:
725 default: 725 default:
726 - stl_phys(T0 & ~3, T1); 726 + stl_phys(addr & ~3, val);
727 break; 727 break;
728 case 8: 728 case 8:
729 - stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2); 729 + stq_phys(addr & ~7, val);
730 break; 730 break;
731 } 731 }
732 } 732 }
@@ -735,22 +735,21 @@ void helper_st_asi(int asi, int size) @@ -735,22 +735,21 @@ void helper_st_asi(int asi, int size)
735 { 735 {
736 switch(size) { 736 switch(size) {
737 case 1: 737 case 1:
738 - stb_phys((target_phys_addr_t)T0  
739 - | ((target_phys_addr_t)(asi & 0xf) << 32), T1); 738 + stb_phys((target_phys_addr_t)addr
  739 + | ((target_phys_addr_t)(asi & 0xf) << 32), val);
740 break; 740 break;
741 case 2: 741 case 2:
742 - stw_phys((target_phys_addr_t)(T0 & ~1)  
743 - | ((target_phys_addr_t)(asi & 0xf) << 32), T1); 742 + stw_phys((target_phys_addr_t)(addr & ~1)
  743 + | ((target_phys_addr_t)(asi & 0xf) << 32), val);
744 break; 744 break;
745 case 4: 745 case 4:
746 default: 746 default:
747 - stl_phys((target_phys_addr_t)(T0 & ~3)  
748 - | ((target_phys_addr_t)(asi & 0xf) << 32), T1); 747 + stl_phys((target_phys_addr_t)(addr & ~3)
  748 + | ((target_phys_addr_t)(asi & 0xf) << 32), val);
749 break; 749 break;
750 case 8: 750 case 8:
751 - stq_phys((target_phys_addr_t)(T0 & ~7)  
752 - | ((target_phys_addr_t)(asi & 0xf) << 32),  
753 - ((uint64_t)T1 << 32) | T2); 751 + stq_phys((target_phys_addr_t)(addr & ~7)
  752 + | ((target_phys_addr_t)(asi & 0xf) << 32), val);
754 break; 753 break;
755 } 754 }
756 } 755 }
@@ -767,11 +766,11 @@ void helper_st_asi(int asi, int size) @@ -767,11 +766,11 @@ void helper_st_asi(int asi, int size)
767 case 8: /* User code access, XXX */ 766 case 8: /* User code access, XXX */
768 case 9: /* Supervisor code access, XXX */ 767 case 9: /* Supervisor code access, XXX */
769 default: 768 default:
770 - do_unassigned_access(T0, 1, 0, asi); 769 + do_unassigned_access(addr, 1, 0, asi);
771 break; 770 break;
772 } 771 }
773 #ifdef DEBUG_ASI 772 #ifdef DEBUG_ASI
774 - dump_asi("write", T0, asi, size, T1, T2); 773 + dump_asi("write", addr, asi, size, val);
775 #endif 774 #endif
776 } 775 }
777 776
@@ -779,9 +778,12 @@ void helper_st_asi(int asi, int size) @@ -779,9 +778,12 @@ void helper_st_asi(int asi, int size)
779 #else /* TARGET_SPARC64 */ 778 #else /* TARGET_SPARC64 */
780 779
781 #ifdef CONFIG_USER_ONLY 780 #ifdef CONFIG_USER_ONLY
782 -void helper_ld_asi(int asi, int size, int sign) 781 +uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
783 { 782 {
784 uint64_t ret = 0; 783 uint64_t ret = 0;
  784 +#if defined(DEBUG_ASI)
  785 + target_ulong last_addr = addr;
  786 +#endif
785 787
786 if (asi < 0x80) 788 if (asi < 0x80)
787 raise_exception(TT_PRIV_ACT); 789 raise_exception(TT_PRIV_ACT);
@@ -794,17 +796,17 @@ void helper_ld_asi(int asi, int size, int sign) @@ -794,17 +796,17 @@ void helper_ld_asi(int asi, int size, int sign)
794 { 796 {
795 switch(size) { 797 switch(size) {
796 case 1: 798 case 1:
797 - ret = ldub_raw(T0); 799 + ret = ldub_raw(addr);
798 break; 800 break;
799 case 2: 801 case 2:
800 - ret = lduw_raw(T0 & ~1); 802 + ret = lduw_raw(addr & ~1);
801 break; 803 break;
802 case 4: 804 case 4:
803 - ret = ldl_raw(T0 & ~3); 805 + ret = ldl_raw(addr & ~3);
804 break; 806 break;
805 default: 807 default:
806 case 8: 808 case 8:
807 - ret = ldq_raw(T0 & ~7); 809 + ret = ldq_raw(addr & ~7);
808 break; 810 break;
809 } 811 }
810 } 812 }
@@ -858,11 +860,17 @@ void helper_ld_asi(int asi, int size, int sign) @@ -858,11 +860,17 @@ void helper_ld_asi(int asi, int size, int sign)
858 break; 860 break;
859 } 861 }
860 } 862 }
861 - T1 = ret; 863 +#ifdef DEBUG_ASI
  864 + dump_asi("read ", last_addr, asi, size, ret);
  865 +#endif
  866 + return ret;
862 } 867 }
863 868
864 -void helper_st_asi(int asi, int size) 869 +void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
865 { 870 {
  871 +#ifdef DEBUG_ASI
  872 + dump_asi("write", addr, asi, size, val);
  873 +#endif
866 if (asi < 0x80) 874 if (asi < 0x80)
867 raise_exception(TT_PRIV_ACT); 875 raise_exception(TT_PRIV_ACT);
868 876
@@ -872,13 +880,13 @@ void helper_st_asi(int asi, int size) @@ -872,13 +880,13 @@ void helper_st_asi(int asi, int size)
872 case 0x89: // Secondary LE 880 case 0x89: // Secondary LE
873 switch(size) { 881 switch(size) {
874 case 2: 882 case 2:
875 - T0 = bswap16(T0); 883 + addr = bswap16(addr);
876 break; 884 break;
877 case 4: 885 case 4:
878 - T0 = bswap32(T0); 886 + addr = bswap32(addr);
879 break; 887 break;
880 case 8: 888 case 8:
881 - T0 = bswap64(T0); 889 + addr = bswap64(addr);
882 break; 890 break;
883 default: 891 default:
884 break; 892 break;
@@ -893,17 +901,17 @@ void helper_st_asi(int asi, int size) @@ -893,17 +901,17 @@ void helper_st_asi(int asi, int size)
893 { 901 {
894 switch(size) { 902 switch(size) {
895 case 1: 903 case 1:
896 - stb_raw(T0, T1); 904 + stb_raw(addr, val);
897 break; 905 break;
898 case 2: 906 case 2:
899 - stw_raw(T0 & ~1, T1); 907 + stw_raw(addr & ~1, val);
900 break; 908 break;
901 case 4: 909 case 4:
902 - stl_raw(T0 & ~3, T1); 910 + stl_raw(addr & ~3, val);
903 break; 911 break;
904 case 8: 912 case 8:
905 default: 913 default:
906 - stq_raw(T0 & ~7, T1); 914 + stq_raw(addr & ~7, val);
907 break; 915 break;
908 } 916 }
909 } 917 }
@@ -918,16 +926,19 @@ void helper_st_asi(int asi, int size) @@ -918,16 +926,19 @@ void helper_st_asi(int asi, int size)
918 case 0x8a: // Primary no-fault LE, RO 926 case 0x8a: // Primary no-fault LE, RO
919 case 0x8b: // Secondary no-fault LE, RO 927 case 0x8b: // Secondary no-fault LE, RO
920 default: 928 default:
921 - do_unassigned_access(T0, 1, 0, 1); 929 + do_unassigned_access(addr, 1, 0, 1);
922 return; 930 return;
923 } 931 }
924 } 932 }
925 933
926 #else /* CONFIG_USER_ONLY */ 934 #else /* CONFIG_USER_ONLY */
927 935
928 -void helper_ld_asi(int asi, int size, int sign) 936 +uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
929 { 937 {
930 uint64_t ret = 0; 938 uint64_t ret = 0;
  939 +#if defined(DEBUG_ASI)
  940 + target_ulong last_addr = addr;
  941 +#endif
931 942
932 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) 943 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
933 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) 944 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
@@ -944,50 +955,50 @@ void helper_ld_asi(int asi, int size, int sign) @@ -944,50 +955,50 @@ void helper_ld_asi(int asi, int size, int sign)
944 if (env->hpstate & HS_PRIV) { 955 if (env->hpstate & HS_PRIV) {
945 switch(size) { 956 switch(size) {
946 case 1: 957 case 1:
947 - ret = ldub_hypv(T0); 958 + ret = ldub_hypv(addr);
948 break; 959 break;
949 case 2: 960 case 2:
950 - ret = lduw_hypv(T0 & ~1); 961 + ret = lduw_hypv(addr & ~1);
951 break; 962 break;
952 case 4: 963 case 4:
953 - ret = ldl_hypv(T0 & ~3); 964 + ret = ldl_hypv(addr & ~3);
954 break; 965 break;
955 default: 966 default:
956 case 8: 967 case 8:
957 - ret = ldq_hypv(T0 & ~7); 968 + ret = ldq_hypv(addr & ~7);
958 break; 969 break;
959 } 970 }
960 } else { 971 } else {
961 switch(size) { 972 switch(size) {
962 case 1: 973 case 1:
963 - ret = ldub_kernel(T0); 974 + ret = ldub_kernel(addr);
964 break; 975 break;
965 case 2: 976 case 2:
966 - ret = lduw_kernel(T0 & ~1); 977 + ret = lduw_kernel(addr & ~1);
967 break; 978 break;
968 case 4: 979 case 4:
969 - ret = ldl_kernel(T0 & ~3); 980 + ret = ldl_kernel(addr & ~3);
970 break; 981 break;
971 default: 982 default:
972 case 8: 983 case 8:
973 - ret = ldq_kernel(T0 & ~7); 984 + ret = ldq_kernel(addr & ~7);
974 break; 985 break;
975 } 986 }
976 } 987 }
977 } else { 988 } else {
978 switch(size) { 989 switch(size) {
979 case 1: 990 case 1:
980 - ret = ldub_user(T0); 991 + ret = ldub_user(addr);
981 break; 992 break;
982 case 2: 993 case 2:
983 - ret = lduw_user(T0 & ~1); 994 + ret = lduw_user(addr & ~1);
984 break; 995 break;
985 case 4: 996 case 4:
986 - ret = ldl_user(T0 & ~3); 997 + ret = ldl_user(addr & ~3);
987 break; 998 break;
988 default: 999 default:
989 case 8: 1000 case 8:
990 - ret = ldq_user(T0 & ~7); 1001 + ret = ldq_user(addr & ~7);
991 break; 1002 break;
992 } 1003 }
993 } 1004 }
@@ -999,17 +1010,17 @@ void helper_ld_asi(int asi, int size, int sign) @@ -999,17 +1010,17 @@ void helper_ld_asi(int asi, int size, int sign)
999 { 1010 {
1000 switch(size) { 1011 switch(size) {
1001 case 1: 1012 case 1:
1002 - ret = ldub_phys(T0); 1013 + ret = ldub_phys(addr);
1003 break; 1014 break;
1004 case 2: 1015 case 2:
1005 - ret = lduw_phys(T0 & ~1); 1016 + ret = lduw_phys(addr & ~1);
1006 break; 1017 break;
1007 case 4: 1018 case 4:
1008 - ret = ldl_phys(T0 & ~3); 1019 + ret = ldl_phys(addr & ~3);
1009 break; 1020 break;
1010 default: 1021 default:
1011 case 8: 1022 case 8:
1012 - ret = ldq_phys(T0 & ~7); 1023 + ret = ldq_phys(addr & ~7);
1013 break; 1024 break;
1014 } 1025 }
1015 break; 1026 break;
@@ -1032,7 +1043,7 @@ void helper_ld_asi(int asi, int size, int sign) @@ -1032,7 +1043,7 @@ void helper_ld_asi(int asi, int size, int sign)
1032 break; 1043 break;
1033 case 0x50: // I-MMU regs 1044 case 0x50: // I-MMU regs
1034 { 1045 {
1035 - int reg = (T0 >> 3) & 0xf; 1046 + int reg = (addr >> 3) & 0xf;
1036 1047
1037 ret = env->immuregs[reg]; 1048 ret = env->immuregs[reg];
1038 break; 1049 break;
@@ -1049,7 +1060,7 @@ void helper_ld_asi(int asi, int size, int sign) @@ -1049,7 +1060,7 @@ void helper_ld_asi(int asi, int size, int sign)
1049 for (i = 0; i < 64; i++) { 1060 for (i = 0; i < 64; i++) {
1050 // Valid, ctx match, vaddr match 1061 // Valid, ctx match, vaddr match
1051 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && 1062 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
1052 - env->itlb_tag[i] == T0) { 1063 + env->itlb_tag[i] == addr) {
1053 ret = env->itlb_tag[i]; 1064 ret = env->itlb_tag[i];
1054 break; 1065 break;
1055 } 1066 }
@@ -1058,7 +1069,7 @@ void helper_ld_asi(int asi, int size, int sign) @@ -1058,7 +1069,7 @@ void helper_ld_asi(int asi, int size, int sign)
1058 } 1069 }
1059 case 0x58: // D-MMU regs 1070 case 0x58: // D-MMU regs
1060 { 1071 {
1061 - int reg = (T0 >> 3) & 0xf; 1072 + int reg = (addr >> 3) & 0xf;
1062 1073
1063 ret = env->dmmuregs[reg]; 1074 ret = env->dmmuregs[reg];
1064 break; 1075 break;
@@ -1070,7 +1081,7 @@ void helper_ld_asi(int asi, int size, int sign) @@ -1070,7 +1081,7 @@ void helper_ld_asi(int asi, int size, int sign)
1070 for (i = 0; i < 64; i++) { 1081 for (i = 0; i < 64; i++) {
1071 // Valid, ctx match, vaddr match 1082 // Valid, ctx match, vaddr match
1072 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && 1083 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
1073 - env->dtlb_tag[i] == T0) { 1084 + env->dtlb_tag[i] == addr) {
1074 ret = env->dtlb_tag[i]; 1085 ret = env->dtlb_tag[i];
1075 break; 1086 break;
1076 } 1087 }
@@ -1092,7 +1103,7 @@ void helper_ld_asi(int asi, int size, int sign) @@ -1092,7 +1103,7 @@ void helper_ld_asi(int asi, int size, int sign)
1092 case 0x5f: // D-MMU demap, WO 1103 case 0x5f: // D-MMU demap, WO
1093 case 0x77: // Interrupt vector, WO 1104 case 0x77: // Interrupt vector, WO
1094 default: 1105 default:
1095 - do_unassigned_access(T0, 0, 0, 1); 1106 + do_unassigned_access(addr, 0, 0, 1);
1096 ret = 0; 1107 ret = 0;
1097 break; 1108 break;
1098 } 1109 }
@@ -1141,11 +1152,17 @@ void helper_ld_asi(int asi, int size, int sign) @@ -1141,11 +1152,17 @@ void helper_ld_asi(int asi, int size, int sign)
1141 break; 1152 break;
1142 } 1153 }
1143 } 1154 }
1144 - T1 = ret; 1155 +#ifdef DEBUG_ASI
  1156 + dump_asi("read ", last_addr, asi, size, ret);
  1157 +#endif
  1158 + return ret;
1145 } 1159 }
1146 1160
1147 -void helper_st_asi(int asi, int size) 1161 +void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1148 { 1162 {
  1163 +#ifdef DEBUG_ASI
  1164 + dump_asi("write", addr, asi, size, val);
  1165 +#endif
1149 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) 1166 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1150 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) 1167 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
1151 raise_exception(TT_PRIV_ACT); 1168 raise_exception(TT_PRIV_ACT);
@@ -1161,13 +1178,13 @@ void helper_st_asi(int asi, int size) @@ -1161,13 +1178,13 @@ void helper_st_asi(int asi, int size)
1161 case 0x89: // Secondary LE 1178 case 0x89: // Secondary LE
1162 switch(size) { 1179 switch(size) {
1163 case 2: 1180 case 2:
1164 - T0 = bswap16(T0); 1181 + addr = bswap16(addr);
1165 break; 1182 break;
1166 case 4: 1183 case 4:
1167 - T0 = bswap32(T0); 1184 + addr = bswap32(addr);
1168 break; 1185 break;
1169 case 8: 1186 case 8:
1170 - T0 = bswap64(T0); 1187 + addr = bswap64(addr);
1171 break; 1188 break;
1172 default: 1189 default:
1173 break; 1190 break;
@@ -1185,50 +1202,50 @@ void helper_st_asi(int asi, int size) @@ -1185,50 +1202,50 @@ void helper_st_asi(int asi, int size)
1185 if (env->hpstate & HS_PRIV) { 1202 if (env->hpstate & HS_PRIV) {
1186 switch(size) { 1203 switch(size) {
1187 case 1: 1204 case 1:
1188 - stb_hypv(T0, T1); 1205 + stb_hypv(addr, val);
1189 break; 1206 break;
1190 case 2: 1207 case 2:
1191 - stw_hypv(T0 & ~1, T1); 1208 + stw_hypv(addr & ~1, val);
1192 break; 1209 break;
1193 case 4: 1210 case 4:
1194 - stl_hypv(T0 & ~3, T1); 1211 + stl_hypv(addr & ~3, val);
1195 break; 1212 break;
1196 case 8: 1213 case 8:
1197 default: 1214 default:
1198 - stq_hypv(T0 & ~7, T1); 1215 + stq_hypv(addr & ~7, val);
1199 break; 1216 break;
1200 } 1217 }
1201 } else { 1218 } else {
1202 switch(size) { 1219 switch(size) {
1203 case 1: 1220 case 1:
1204 - stb_kernel(T0, T1); 1221 + stb_kernel(addr, val);
1205 break; 1222 break;
1206 case 2: 1223 case 2:
1207 - stw_kernel(T0 & ~1, T1); 1224 + stw_kernel(addr & ~1, val);
1208 break; 1225 break;
1209 case 4: 1226 case 4:
1210 - stl_kernel(T0 & ~3, T1); 1227 + stl_kernel(addr & ~3, val);
1211 break; 1228 break;
1212 case 8: 1229 case 8:
1213 default: 1230 default:
1214 - stq_kernel(T0 & ~7, T1); 1231 + stq_kernel(addr & ~7, val);
1215 break; 1232 break;
1216 } 1233 }
1217 } 1234 }
1218 } else { 1235 } else {
1219 switch(size) { 1236 switch(size) {
1220 case 1: 1237 case 1:
1221 - stb_user(T0, T1); 1238 + stb_user(addr, val);
1222 break; 1239 break;
1223 case 2: 1240 case 2:
1224 - stw_user(T0 & ~1, T1); 1241 + stw_user(addr & ~1, val);
1225 break; 1242 break;
1226 case 4: 1243 case 4:
1227 - stl_user(T0 & ~3, T1); 1244 + stl_user(addr & ~3, val);
1228 break; 1245 break;
1229 case 8: 1246 case 8:
1230 default: 1247 default:
1231 - stq_user(T0 & ~7, T1); 1248 + stq_user(addr & ~7, val);
1232 break; 1249 break;
1233 } 1250 }
1234 } 1251 }
@@ -1240,17 +1257,17 @@ void helper_st_asi(int asi, int size) @@ -1240,17 +1257,17 @@ void helper_st_asi(int asi, int size)
1240 { 1257 {
1241 switch(size) { 1258 switch(size) {
1242 case 1: 1259 case 1:
1243 - stb_phys(T0, T1); 1260 + stb_phys(addr, val);
1244 break; 1261 break;
1245 case 2: 1262 case 2:
1246 - stw_phys(T0 & ~1, T1); 1263 + stw_phys(addr & ~1, val);
1247 break; 1264 break;
1248 case 4: 1265 case 4:
1249 - stl_phys(T0 & ~3, T1); 1266 + stl_phys(addr & ~3, val);
1250 break; 1267 break;
1251 case 8: 1268 case 8:
1252 default: 1269 default:
1253 - stq_phys(T0 & ~7, T1); 1270 + stq_phys(addr & ~7, val);
1254 break; 1271 break;
1255 } 1272 }
1256 } 1273 }
@@ -1271,7 +1288,7 @@ void helper_st_asi(int asi, int size) @@ -1271,7 +1288,7 @@ void helper_st_asi(int asi, int size)
1271 uint64_t oldreg; 1288 uint64_t oldreg;
1272 1289
1273 oldreg = env->lsu; 1290 oldreg = env->lsu;
1274 - env->lsu = T1 & (DMMU_E | IMMU_E); 1291 + env->lsu = val & (DMMU_E | IMMU_E);
1275 // Mappings generated during D/I MMU disabled mode are 1292 // Mappings generated during D/I MMU disabled mode are
1276 // invalid in normal mode 1293 // invalid in normal mode
1277 if (oldreg != env->lsu) { 1294 if (oldreg != env->lsu) {
@@ -1285,7 +1302,7 @@ void helper_st_asi(int asi, int size) @@ -1285,7 +1302,7 @@ void helper_st_asi(int asi, int size)
1285 } 1302 }
1286 case 0x50: // I-MMU regs 1303 case 0x50: // I-MMU regs
1287 { 1304 {
1288 - int reg = (T0 >> 3) & 0xf; 1305 + int reg = (addr >> 3) & 0xf;
1289 uint64_t oldreg; 1306 uint64_t oldreg;
1290 1307
1291 oldreg = env->immuregs[reg]; 1308 oldreg = env->immuregs[reg];
@@ -1299,15 +1316,15 @@ void helper_st_asi(int asi, int size) @@ -1299,15 +1316,15 @@ void helper_st_asi(int asi, int size)
1299 case 8: 1316 case 8:
1300 return; 1317 return;
1301 case 3: // SFSR 1318 case 3: // SFSR
1302 - if ((T1 & 1) == 0)  
1303 - T1 = 0; // Clear SFSR 1319 + if ((val & 1) == 0)
  1320 + val = 0; // Clear SFSR
1304 break; 1321 break;
1305 case 5: // TSB access 1322 case 5: // TSB access
1306 case 6: // Tag access 1323 case 6: // Tag access
1307 default: 1324 default:
1308 break; 1325 break;
1309 } 1326 }
1310 - env->immuregs[reg] = T1; 1327 + env->immuregs[reg] = val;
1311 if (oldreg != env->immuregs[reg]) { 1328 if (oldreg != env->immuregs[reg]) {
1312 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]); 1329 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1313 } 1330 }
@@ -1324,7 +1341,7 @@ void helper_st_asi(int asi, int size) @@ -1324,7 +1341,7 @@ void helper_st_asi(int asi, int size)
1324 for (i = 0; i < 64; i++) { 1341 for (i = 0; i < 64; i++) {
1325 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { 1342 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1326 env->itlb_tag[i] = env->immuregs[6]; 1343 env->itlb_tag[i] = env->immuregs[6];
1327 - env->itlb_tte[i] = T1; 1344 + env->itlb_tte[i] = val;
1328 return; 1345 return;
1329 } 1346 }
1330 } 1347 }
@@ -1332,7 +1349,7 @@ void helper_st_asi(int asi, int size) @@ -1332,7 +1349,7 @@ void helper_st_asi(int asi, int size)
1332 for (i = 0; i < 64; i++) { 1349 for (i = 0; i < 64; i++) {
1333 if ((env->itlb_tte[i] & 0x40) == 0) { 1350 if ((env->itlb_tte[i] & 0x40) == 0) {
1334 env->itlb_tag[i] = env->immuregs[6]; 1351 env->itlb_tag[i] = env->immuregs[6];
1335 - env->itlb_tte[i] = T1; 1352 + env->itlb_tte[i] = val;
1336 return; 1353 return;
1337 } 1354 }
1338 } 1355 }
@@ -1341,10 +1358,10 @@ void helper_st_asi(int asi, int size) @@ -1341,10 +1358,10 @@ void helper_st_asi(int asi, int size)
1341 } 1358 }
1342 case 0x55: // I-MMU data access 1359 case 0x55: // I-MMU data access
1343 { 1360 {
1344 - unsigned int i = (T0 >> 3) & 0x3f; 1361 + unsigned int i = (addr >> 3) & 0x3f;
1345 1362
1346 env->itlb_tag[i] = env->immuregs[6]; 1363 env->itlb_tag[i] = env->immuregs[6];
1347 - env->itlb_tte[i] = T1; 1364 + env->itlb_tte[i] = val;
1348 return; 1365 return;
1349 } 1366 }
1350 case 0x57: // I-MMU demap 1367 case 0x57: // I-MMU demap
@@ -1352,7 +1369,7 @@ void helper_st_asi(int asi, int size) @@ -1352,7 +1369,7 @@ void helper_st_asi(int asi, int size)
1352 return; 1369 return;
1353 case 0x58: // D-MMU regs 1370 case 0x58: // D-MMU regs
1354 { 1371 {
1355 - int reg = (T0 >> 3) & 0xf; 1372 + int reg = (addr >> 3) & 0xf;
1356 uint64_t oldreg; 1373 uint64_t oldreg;
1357 1374
1358 oldreg = env->dmmuregs[reg]; 1375 oldreg = env->dmmuregs[reg];
@@ -1361,11 +1378,11 @@ void helper_st_asi(int asi, int size) @@ -1361,11 +1378,11 @@ void helper_st_asi(int asi, int size)
1361 case 4: 1378 case 4:
1362 return; 1379 return;
1363 case 3: // SFSR 1380 case 3: // SFSR
1364 - if ((T1 & 1) == 0) {  
1365 - T1 = 0; // Clear SFSR, Fault address 1381 + if ((val & 1) == 0) {
  1382 + val = 0; // Clear SFSR, Fault address
1366 env->dmmuregs[4] = 0; 1383 env->dmmuregs[4] = 0;
1367 } 1384 }
1368 - env->dmmuregs[reg] = T1; 1385 + env->dmmuregs[reg] = val;
1369 break; 1386 break;
1370 case 1: // Primary context 1387 case 1: // Primary context
1371 case 2: // Secondary context 1388 case 2: // Secondary context
@@ -1376,7 +1393,7 @@ void helper_st_asi(int asi, int size) @@ -1376,7 +1393,7 @@ void helper_st_asi(int asi, int size)
1376 default: 1393 default:
1377 break; 1394 break;
1378 } 1395 }
1379 - env->dmmuregs[reg] = T1; 1396 + env->dmmuregs[reg] = val;
1380 if (oldreg != env->dmmuregs[reg]) { 1397 if (oldreg != env->dmmuregs[reg]) {
1381 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); 1398 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1382 } 1399 }
@@ -1393,7 +1410,7 @@ void helper_st_asi(int asi, int size) @@ -1393,7 +1410,7 @@ void helper_st_asi(int asi, int size)
1393 for (i = 0; i < 64; i++) { 1410 for (i = 0; i < 64; i++) {
1394 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { 1411 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1395 env->dtlb_tag[i] = env->dmmuregs[6]; 1412 env->dtlb_tag[i] = env->dmmuregs[6];
1396 - env->dtlb_tte[i] = T1; 1413 + env->dtlb_tte[i] = val;
1397 return; 1414 return;
1398 } 1415 }
1399 } 1416 }
@@ -1401,7 +1418,7 @@ void helper_st_asi(int asi, int size) @@ -1401,7 +1418,7 @@ void helper_st_asi(int asi, int size)
1401 for (i = 0; i < 64; i++) { 1418 for (i = 0; i < 64; i++) {
1402 if ((env->dtlb_tte[i] & 0x40) == 0) { 1419 if ((env->dtlb_tte[i] & 0x40) == 0) {
1403 env->dtlb_tag[i] = env->dmmuregs[6]; 1420 env->dtlb_tag[i] = env->dmmuregs[6];
1404 - env->dtlb_tte[i] = T1; 1421 + env->dtlb_tte[i] = val;
1405 return; 1422 return;
1406 } 1423 }
1407 } 1424 }
@@ -1410,10 +1427,10 @@ void helper_st_asi(int asi, int size) @@ -1410,10 +1427,10 @@ void helper_st_asi(int asi, int size)
1410 } 1427 }
1411 case 0x5d: // D-MMU data access 1428 case 0x5d: // D-MMU data access
1412 { 1429 {
1413 - unsigned int i = (T0 >> 3) & 0x3f; 1430 + unsigned int i = (addr >> 3) & 0x3f;
1414 1431
1415 env->dtlb_tag[i] = env->dmmuregs[6]; 1432 env->dtlb_tag[i] = env->dmmuregs[6];
1416 - env->dtlb_tte[i] = T1; 1433 + env->dtlb_tte[i] = val;
1417 return; 1434 return;
1418 } 1435 }
1419 case 0x5f: // D-MMU demap 1436 case 0x5f: // D-MMU demap
@@ -1434,16 +1451,16 @@ void helper_st_asi(int asi, int size) @@ -1434,16 +1451,16 @@ void helper_st_asi(int asi, int size)
1434 case 0x8a: // Primary no-fault LE, RO 1451 case 0x8a: // Primary no-fault LE, RO
1435 case 0x8b: // Secondary no-fault LE, RO 1452 case 0x8b: // Secondary no-fault LE, RO
1436 default: 1453 default:
1437 - do_unassigned_access(T0, 1, 0, 1); 1454 + do_unassigned_access(addr, 1, 0, 1);
1438 return; 1455 return;
1439 } 1456 }
1440 } 1457 }
1441 #endif /* CONFIG_USER_ONLY */ 1458 #endif /* CONFIG_USER_ONLY */
1442 1459
1443 -void helper_ldf_asi(int asi, int size, int rd) 1460 +void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
1444 { 1461 {
1445 - target_ulong tmp_T0 = T0, tmp_T1 = T1;  
1446 unsigned int i; 1462 unsigned int i;
  1463 + target_ulong val;
1447 1464
1448 switch (asi) { 1465 switch (asi) {
1449 case 0xf0: // Block load primary 1466 case 0xf0: // Block load primary
@@ -1454,31 +1471,28 @@ void helper_ldf_asi(int asi, int size, int rd) @@ -1454,31 +1471,28 @@ void helper_ldf_asi(int asi, int size, int rd)
1454 raise_exception(TT_ILL_INSN); 1471 raise_exception(TT_ILL_INSN);
1455 return; 1472 return;
1456 } 1473 }
1457 - if (T0 & 0x3f) { 1474 + if (addr & 0x3f) {
1458 raise_exception(TT_UNALIGNED); 1475 raise_exception(TT_UNALIGNED);
1459 return; 1476 return;
1460 } 1477 }
1461 for (i = 0; i < 16; i++) { 1478 for (i = 0; i < 16; i++) {
1462 - helper_ld_asi(asi & 0x8f, 4, 0);  
1463 - *(uint32_t *)&env->fpr[rd++] = T1;  
1464 - T0 += 4; 1479 + *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0);
  1480 + addr += 4;
1465 } 1481 }
1466 - T0 = tmp_T0;  
1467 - T1 = tmp_T1;  
1468 1482
1469 return; 1483 return;
1470 default: 1484 default:
1471 break; 1485 break;
1472 } 1486 }
1473 1487
1474 - helper_ld_asi(asi, size, 0); 1488 + val = helper_ld_asi(addr, asi, size, 0);
1475 switch(size) { 1489 switch(size) {
1476 default: 1490 default:
1477 case 4: 1491 case 4:
1478 - *((uint32_t *)&FT0) = T1; 1492 + *((uint32_t *)&FT0) = val;
1479 break; 1493 break;
1480 case 8: 1494 case 8:
1481 - *((int64_t *)&DT0) = T1; 1495 + *((int64_t *)&DT0) = val;
1482 break; 1496 break;
1483 #if defined(CONFIG_USER_ONLY) 1497 #if defined(CONFIG_USER_ONLY)
1484 case 16: 1498 case 16:
@@ -1486,13 +1500,12 @@ void helper_ldf_asi(int asi, int size, int rd) @@ -1486,13 +1500,12 @@ void helper_ldf_asi(int asi, int size, int rd)
1486 break; 1500 break;
1487 #endif 1501 #endif
1488 } 1502 }
1489 - T1 = tmp_T1;  
1490 } 1503 }
1491 1504
1492 -void helper_stf_asi(int asi, int size, int rd) 1505 +void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
1493 { 1506 {
1494 - target_ulong tmp_T0 = T0, tmp_T1 = T1;  
1495 unsigned int i; 1507 unsigned int i;
  1508 + target_ulong val = 0;
1496 1509
1497 switch (asi) { 1510 switch (asi) {
1498 case 0xf0: // Block store primary 1511 case 0xf0: // Block store primary
@@ -1503,17 +1516,15 @@ void helper_stf_asi(int asi, int size, int rd) @@ -1503,17 +1516,15 @@ void helper_stf_asi(int asi, int size, int rd)
1503 raise_exception(TT_ILL_INSN); 1516 raise_exception(TT_ILL_INSN);
1504 return; 1517 return;
1505 } 1518 }
1506 - if (T0 & 0x3f) { 1519 + if (addr & 0x3f) {
1507 raise_exception(TT_UNALIGNED); 1520 raise_exception(TT_UNALIGNED);
1508 return; 1521 return;
1509 } 1522 }
1510 for (i = 0; i < 16; i++) { 1523 for (i = 0; i < 16; i++) {
1511 - T1 = *(uint32_t *)&env->fpr[rd++];  
1512 - helper_st_asi(asi & 0x8f, 4);  
1513 - T0 += 4; 1524 + val = *(uint32_t *)&env->fpr[rd++];
  1525 + helper_st_asi(addr, val, asi & 0x8f, 4);
  1526 + addr += 4;
1514 } 1527 }
1515 - T0 = tmp_T0;  
1516 - T1 = tmp_T1;  
1517 1528
1518 return; 1529 return;
1519 default: 1530 default:
@@ -1523,10 +1534,10 @@ void helper_stf_asi(int asi, int size, int rd) @@ -1523,10 +1534,10 @@ void helper_stf_asi(int asi, int size, int rd)
1523 switch(size) { 1534 switch(size) {
1524 default: 1535 default:
1525 case 4: 1536 case 4:
1526 - T1 = *((uint32_t *)&FT0); 1537 + val = *((uint32_t *)&FT0);
1527 break; 1538 break;
1528 case 8: 1539 case 8:
1529 - T1 = *((int64_t *)&DT0); 1540 + val = *((int64_t *)&DT0);
1530 break; 1541 break;
1531 #if defined(CONFIG_USER_ONLY) 1542 #if defined(CONFIG_USER_ONLY)
1532 case 16: 1543 case 16:
@@ -1534,14 +1545,36 @@ void helper_stf_asi(int asi, int size, int rd) @@ -1534,14 +1545,36 @@ void helper_stf_asi(int asi, int size, int rd)
1534 break; 1545 break;
1535 #endif 1546 #endif
1536 } 1547 }
1537 - helper_st_asi(asi, size);  
1538 - T1 = tmp_T1; 1548 + helper_st_asi(addr, val, asi, size);
1539 } 1549 }
1540 1550
  1551 +target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
  1552 + target_ulong val2, uint32_t asi)
  1553 +{
  1554 + target_ulong ret;
  1555 +
  1556 + val1 &= 0xffffffffUL;
  1557 + ret = helper_ld_asi(addr, asi, 4, 0);
  1558 + ret &= 0xffffffffUL;
  1559 + if (val1 == ret)
  1560 + helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4);
  1561 + return ret;
  1562 +}
  1563 +
  1564 +target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
  1565 + target_ulong val2, uint32_t asi)
  1566 +{
  1567 + target_ulong ret;
  1568 +
  1569 + ret = helper_ld_asi(addr, asi, 8, 0);
  1570 + if (val1 == ret)
  1571 + helper_st_asi(addr, val2, asi, 8);
  1572 + return ret;
  1573 +}
1541 #endif /* TARGET_SPARC64 */ 1574 #endif /* TARGET_SPARC64 */
1542 1575
1543 #ifndef TARGET_SPARC64 1576 #ifndef TARGET_SPARC64
1544 -void helper_rett() 1577 +void helper_rett(void)
1545 { 1578 {
1546 unsigned int cwp; 1579 unsigned int cwp;
1547 1580
@@ -1558,6 +1591,11 @@ void helper_rett() @@ -1558,6 +1591,11 @@ void helper_rett()
1558 } 1591 }
1559 #endif 1592 #endif
1560 1593
  1594 +uint64_t helper_pack64(target_ulong high, target_ulong low)
  1595 +{
  1596 + return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff);
  1597 +}
  1598 +
1561 void helper_ldfsr(void) 1599 void helper_ldfsr(void)
1562 { 1600 {
1563 int rnd_mode; 1601 int rnd_mode;
@@ -1586,24 +1624,24 @@ void helper_debug() @@ -1586,24 +1624,24 @@ void helper_debug()
1586 } 1624 }
1587 1625
1588 #ifndef TARGET_SPARC64 1626 #ifndef TARGET_SPARC64
1589 -void do_wrpsr() 1627 +void helper_wrpsr(target_ulong new_psr)
1590 { 1628 {
1591 - if ((T0 & PSR_CWP) >= NWINDOWS) 1629 + if ((new_psr & PSR_CWP) >= NWINDOWS)
1592 raise_exception(TT_ILL_INSN); 1630 raise_exception(TT_ILL_INSN);
1593 else 1631 else
1594 - PUT_PSR(env, T0); 1632 + PUT_PSR(env, new_psr);
1595 } 1633 }
1596 1634
1597 -void do_rdpsr() 1635 +target_ulong helper_rdpsr(void)
1598 { 1636 {
1599 - T0 = GET_PSR(env); 1637 + return GET_PSR(env);
1600 } 1638 }
1601 1639
1602 #else 1640 #else
1603 1641
1604 -void do_popc() 1642 +target_ulong helper_popc(target_ulong val)
1605 { 1643 {
1606 - T0 = ctpop64(T1); 1644 + return ctpop64(val);
1607 } 1645 }
1608 1646
1609 static inline uint64_t *get_gregset(uint64_t pstate) 1647 static inline uint64_t *get_gregset(uint64_t pstate)
@@ -1638,12 +1676,12 @@ static inline void change_pstate(uint64_t new_pstate) @@ -1638,12 +1676,12 @@ static inline void change_pstate(uint64_t new_pstate)
1638 env->pstate = new_pstate; 1676 env->pstate = new_pstate;
1639 } 1677 }
1640 1678
1641 -void do_wrpstate(void) 1679 +void helper_wrpstate(target_ulong new_state)
1642 { 1680 {
1643 - change_pstate(T0 & 0xf3f); 1681 + change_pstate(new_state & 0xf3f);
1644 } 1682 }
1645 1683
1646 -void do_done(void) 1684 +void helper_done(void)
1647 { 1685 {
1648 env->tl--; 1686 env->tl--;
1649 env->pc = env->tnpc[env->tl]; 1687 env->pc = env->tnpc[env->tl];
@@ -1654,7 +1692,7 @@ void do_done(void) @@ -1654,7 +1692,7 @@ void do_done(void)
1654 PUT_CWP64(env, env->tstate[env->tl] & 0xff); 1692 PUT_CWP64(env, env->tstate[env->tl] & 0xff);
1655 } 1693 }
1656 1694
1657 -void do_retry(void) 1695 +void helper_retry(void)
1658 { 1696 {
1659 env->tl--; 1697 env->tl--;
1660 env->pc = env->tpc[env->tl]; 1698 env->pc = env->tpc[env->tl];
target-sparc/op_mem.h
  View file @1a2fb1c
@@ -4,65 +4,6 @@ @@ -4,65 +4,6 @@
4 #define ADDR(x) (x) 4 #define ADDR(x) (x)
5 #endif 5 #endif
6 6
7 -/*** Integer load ***/  
8 -#define SPARC_LD_OP(name, qp) \  
9 -void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \  
10 -{ \  
11 - T1 = (target_ulong)glue(qp, MEMSUFFIX)(ADDR(T0)); \  
12 -}  
13 -  
14 -#define SPARC_LD_OP_S(name, qp) \  
15 - void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \  
16 - { \  
17 - T1 = (target_long)glue(qp, MEMSUFFIX)(ADDR(T0)); \  
18 - }  
19 -  
20 -#define SPARC_ST_OP(name, op) \  
21 -void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \  
22 -{ \  
23 - glue(op, MEMSUFFIX)(ADDR(T0), T1); \  
24 -}  
25 -  
26 -SPARC_LD_OP(ld, ldl);  
27 -SPARC_LD_OP(ldub, ldub);  
28 -SPARC_LD_OP(lduh, lduw);  
29 -SPARC_LD_OP_S(ldsb, ldsb);  
30 -SPARC_LD_OP_S(ldsh, ldsw);  
31 -  
32 -/*** Integer store ***/  
33 -SPARC_ST_OP(st, stl);  
34 -SPARC_ST_OP(stb, stb);  
35 -SPARC_ST_OP(sth, stw);  
36 -  
37 -void OPPROTO glue(op_std, MEMSUFFIX)(void)  
38 -{  
39 - uint64_t tmp = ((uint64_t)T1 << 32) | (uint64_t)(T2 & 0xffffffff);  
40 -  
41 - glue(stq, MEMSUFFIX)(ADDR(T0), tmp);  
42 -}  
43 -  
44 -void OPPROTO glue(op_ldstub, MEMSUFFIX)(void)  
45 -{  
46 - T1 = glue(ldub, MEMSUFFIX)(ADDR(T0));  
47 - glue(stb, MEMSUFFIX)(ADDR(T0), 0xff); /* XXX: Should be Atomically */  
48 -}  
49 -  
50 -void OPPROTO glue(op_swap, MEMSUFFIX)(void)  
51 -{  
52 - target_ulong tmp = glue(ldl, MEMSUFFIX)(ADDR(T0));  
53 - glue(stl, MEMSUFFIX)(ADDR(T0), T1); /* XXX: Should be Atomically */  
54 - T1 = tmp;  
55 -}  
56 -  
57 -void OPPROTO glue(op_ldd, MEMSUFFIX)(void)  
58 -{  
59 - uint64_t tmp;  
60 -  
61 - tmp = glue(ldq, MEMSUFFIX)(ADDR(T0));  
62 - T1 = tmp >> 32;  
63 - T0 = tmp & 0xffffffff;  
64 -}  
65 -  
66 /*** Floating-point store ***/ 7 /*** Floating-point store ***/
67 void OPPROTO glue(op_stf, MEMSUFFIX) (void) 8 void OPPROTO glue(op_stf, MEMSUFFIX) (void)
68 { 9 {
@@ -107,18 +48,4 @@ void OPPROTO glue(op_stqf, MEMSUFFIX) (void) @@ -107,18 +48,4 @@ void OPPROTO glue(op_stqf, MEMSUFFIX) (void)
107 } 48 }
108 #endif 49 #endif
109 50
110 -#ifdef TARGET_SPARC64  
111 -void OPPROTO glue(op_lduw, MEMSUFFIX)(void)  
112 -{  
113 - T1 = (uint64_t)(glue(ldl, MEMSUFFIX)(ADDR(T0)) & 0xffffffff);  
114 -}  
115 -  
116 -void OPPROTO glue(op_ldsw, MEMSUFFIX)(void)  
117 -{  
118 - T1 = (int64_t)(glue(ldl, MEMSUFFIX)(ADDR(T0)) & 0xffffffff);  
119 -}  
120 -  
121 -SPARC_LD_OP(ldx, ldq);  
122 -SPARC_ST_OP(stx, stq);  
123 -#endif  
124 #undef MEMSUFFIX 51 #undef MEMSUFFIX
target-sparc/op_template.h deleted 100644 → 0
  View file @f8422f5
1 -/*  
2 - * SPARC micro operations (templates for various register related  
3 - * operations)  
4 - *  
5 - * Copyright (c) 2003 Fabrice Bellard  
6 - *  
7 - * This library is free software; you can redistribute it and/or  
8 - * modify it under the terms of the GNU Lesser General Public  
9 - * License as published by the Free Software Foundation; either  
10 - * version 2 of the License, or (at your option) any later version.  
11 - *  
12 - * This library is distributed in the hope that it will be useful,  
13 - * but WITHOUT ANY WARRANTY; without even the implied warranty of  
14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU  
15 - * Lesser General Public License for more details.  
16 - *  
17 - * You should have received a copy of the GNU Lesser General Public  
18 - * License along with this library; if not, write to the Free Software  
19 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  
20 - */  
21 -  
22 -void OPPROTO glue(op_movl_T0_, REGNAME)(void)  
23 -{  
24 - T0 = REG;  
25 -}  
26 -  
27 -void OPPROTO glue(op_movl_T1_, REGNAME)(void)  
28 -{  
29 - T1 = REG;  
30 -}  
31 -  
32 -void OPPROTO glue(op_movl_T2_, REGNAME)(void)  
33 -{  
34 - T2 = REG;  
35 -}  
36 -  
37 -void OPPROTO glue(glue(op_movl_, REGNAME), _T0)(void)  
38 -{  
39 - REG = T0;  
40 -}  
41 -  
42 -void OPPROTO glue(glue(op_movl_, REGNAME), _T1)(void)  
43 -{  
44 - REG = T1;  
45 -}  
46 -  
47 -#undef REG  
48 -#undef REGNAME  
target-sparc/translate.c
  View file @1a2fb1c
@@ -36,6 +36,7 @@ @@ -36,6 +36,7 @@
36 #include "cpu.h" 36 #include "cpu.h"
37 #include "exec-all.h" 37 #include "exec-all.h"
38 #include "disas.h" 38 #include "disas.h"
  39 +#include "helper.h"
39 #include "tcg-op.h" 40 #include "tcg-op.h"
40 41
41 #define DEBUG_DISAS 42 #define DEBUG_DISAS
@@ -44,6 +45,11 @@ @@ -44,6 +45,11 @@
44 #define JUMP_PC 2 /* dynamic pc value which takes only two values 45 #define JUMP_PC 2 /* dynamic pc value which takes only two values
45 according to jump_pc[T2] */ 46 according to jump_pc[T2] */
46 47
  48 +/* global register indexes */
  49 +static TCGv cpu_env, cpu_T[3], cpu_regwptr;
  50 +/* local register indexes (only used inside old micro ops) */
  51 +static TCGv cpu_tmp0;
  52 +
47 typedef struct DisasContext { 53 typedef struct DisasContext {
48 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ 54 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
49 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ 55 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
@@ -102,195 +108,6 @@ static int sign_extend(int x, int len) @@ -102,195 +108,6 @@ static int sign_extend(int x, int len)
102 108
103 static void disas_sparc_insn(DisasContext * dc); 109 static void disas_sparc_insn(DisasContext * dc);
104 110
105 -static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {  
106 - {  
107 - gen_op_movl_g0_T0,  
108 - gen_op_movl_g1_T0,  
109 - gen_op_movl_g2_T0,  
110 - gen_op_movl_g3_T0,  
111 - gen_op_movl_g4_T0,  
112 - gen_op_movl_g5_T0,  
113 - gen_op_movl_g6_T0,  
114 - gen_op_movl_g7_T0,  
115 - gen_op_movl_o0_T0,  
116 - gen_op_movl_o1_T0,  
117 - gen_op_movl_o2_T0,  
118 - gen_op_movl_o3_T0,  
119 - gen_op_movl_o4_T0,  
120 - gen_op_movl_o5_T0,  
121 - gen_op_movl_o6_T0,  
122 - gen_op_movl_o7_T0,  
123 - gen_op_movl_l0_T0,  
124 - gen_op_movl_l1_T0,  
125 - gen_op_movl_l2_T0,  
126 - gen_op_movl_l3_T0,  
127 - gen_op_movl_l4_T0,  
128 - gen_op_movl_l5_T0,  
129 - gen_op_movl_l6_T0,  
130 - gen_op_movl_l7_T0,  
131 - gen_op_movl_i0_T0,  
132 - gen_op_movl_i1_T0,  
133 - gen_op_movl_i2_T0,  
134 - gen_op_movl_i3_T0,  
135 - gen_op_movl_i4_T0,  
136 - gen_op_movl_i5_T0,  
137 - gen_op_movl_i6_T0,  
138 - gen_op_movl_i7_T0,  
139 - },  
140 - {  
141 - gen_op_movl_g0_T1,  
142 - gen_op_movl_g1_T1,  
143 - gen_op_movl_g2_T1,  
144 - gen_op_movl_g3_T1,  
145 - gen_op_movl_g4_T1,  
146 - gen_op_movl_g5_T1,  
147 - gen_op_movl_g6_T1,  
148 - gen_op_movl_g7_T1,  
149 - gen_op_movl_o0_T1,  
150 - gen_op_movl_o1_T1,  
151 - gen_op_movl_o2_T1,  
152 - gen_op_movl_o3_T1,  
153 - gen_op_movl_o4_T1,  
154 - gen_op_movl_o5_T1,  
155 - gen_op_movl_o6_T1,  
156 - gen_op_movl_o7_T1,  
157 - gen_op_movl_l0_T1,  
158 - gen_op_movl_l1_T1,  
159 - gen_op_movl_l2_T1,  
160 - gen_op_movl_l3_T1,  
161 - gen_op_movl_l4_T1,  
162 - gen_op_movl_l5_T1,  
163 - gen_op_movl_l6_T1,  
164 - gen_op_movl_l7_T1,  
165 - gen_op_movl_i0_T1,  
166 - gen_op_movl_i1_T1,  
167 - gen_op_movl_i2_T1,  
168 - gen_op_movl_i3_T1,  
169 - gen_op_movl_i4_T1,  
170 - gen_op_movl_i5_T1,  
171 - gen_op_movl_i6_T1,  
172 - gen_op_movl_i7_T1,  
173 - }  
174 -};  
175 -  
176 -static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {  
177 - {  
178 - gen_op_movl_T0_g0,  
179 - gen_op_movl_T0_g1,  
180 - gen_op_movl_T0_g2,  
181 - gen_op_movl_T0_g3,  
182 - gen_op_movl_T0_g4,  
183 - gen_op_movl_T0_g5,  
184 - gen_op_movl_T0_g6,  
185 - gen_op_movl_T0_g7,  
186 - gen_op_movl_T0_o0,  
187 - gen_op_movl_T0_o1,  
188 - gen_op_movl_T0_o2,  
189 - gen_op_movl_T0_o3,  
190 - gen_op_movl_T0_o4,  
191 - gen_op_movl_T0_o5,  
192 - gen_op_movl_T0_o6,  
193 - gen_op_movl_T0_o7,  
194 - gen_op_movl_T0_l0,  
195 - gen_op_movl_T0_l1,  
196 - gen_op_movl_T0_l2,  
197 - gen_op_movl_T0_l3,  
198 - gen_op_movl_T0_l4,  
199 - gen_op_movl_T0_l5,  
200 - gen_op_movl_T0_l6,  
201 - gen_op_movl_T0_l7,  
202 - gen_op_movl_T0_i0,  
203 - gen_op_movl_T0_i1,  
204 - gen_op_movl_T0_i2,  
205 - gen_op_movl_T0_i3,  
206 - gen_op_movl_T0_i4,  
207 - gen_op_movl_T0_i5,  
208 - gen_op_movl_T0_i6,  
209 - gen_op_movl_T0_i7,  
210 - },  
211 - {  
212 - gen_op_movl_T1_g0,  
213 - gen_op_movl_T1_g1,  
214 - gen_op_movl_T1_g2,  
215 - gen_op_movl_T1_g3,  
216 - gen_op_movl_T1_g4,  
217 - gen_op_movl_T1_g5,  
218 - gen_op_movl_T1_g6,  
219 - gen_op_movl_T1_g7,  
220 - gen_op_movl_T1_o0,  
221 - gen_op_movl_T1_o1,  
222 - gen_op_movl_T1_o2,  
223 - gen_op_movl_T1_o3,  
224 - gen_op_movl_T1_o4,  
225 - gen_op_movl_T1_o5,  
226 - gen_op_movl_T1_o6,  
227 - gen_op_movl_T1_o7,  
228 - gen_op_movl_T1_l0,  
229 - gen_op_movl_T1_l1,  
230 - gen_op_movl_T1_l2,  
231 - gen_op_movl_T1_l3,  
232 - gen_op_movl_T1_l4,  
233 - gen_op_movl_T1_l5,  
234 - gen_op_movl_T1_l6,  
235 - gen_op_movl_T1_l7,  
236 - gen_op_movl_T1_i0,  
237 - gen_op_movl_T1_i1,  
238 - gen_op_movl_T1_i2,  
239 - gen_op_movl_T1_i3,  
240 - gen_op_movl_T1_i4,  
241 - gen_op_movl_T1_i5,  
242 - gen_op_movl_T1_i6,  
243 - gen_op_movl_T1_i7,  
244 - },  
245 - {  
246 - gen_op_movl_T2_g0,  
247 - gen_op_movl_T2_g1,  
248 - gen_op_movl_T2_g2,  
249 - gen_op_movl_T2_g3,  
250 - gen_op_movl_T2_g4,  
251 - gen_op_movl_T2_g5,  
252 - gen_op_movl_T2_g6,  
253 - gen_op_movl_T2_g7,  
254 - gen_op_movl_T2_o0,  
255 - gen_op_movl_T2_o1,  
256 - gen_op_movl_T2_o2,  
257 - gen_op_movl_T2_o3,  
258 - gen_op_movl_T2_o4,  
259 - gen_op_movl_T2_o5,  
260 - gen_op_movl_T2_o6,  
261 - gen_op_movl_T2_o7,  
262 - gen_op_movl_T2_l0,  
263 - gen_op_movl_T2_l1,  
264 - gen_op_movl_T2_l2,  
265 - gen_op_movl_T2_l3,  
266 - gen_op_movl_T2_l4,  
267 - gen_op_movl_T2_l5,  
268 - gen_op_movl_T2_l6,  
269 - gen_op_movl_T2_l7,  
270 - gen_op_movl_T2_i0,  
271 - gen_op_movl_T2_i1,  
272 - gen_op_movl_T2_i2,  
273 - gen_op_movl_T2_i3,  
274 - gen_op_movl_T2_i4,  
275 - gen_op_movl_T2_i5,  
276 - gen_op_movl_T2_i6,  
277 - gen_op_movl_T2_i7,  
278 - }  
279 -};  
280 -  
281 -static GenOpFunc1 * const gen_op_movl_TN_im[3] = {  
282 - gen_op_movl_T0_im,  
283 - gen_op_movl_T1_im,  
284 - gen_op_movl_T2_im  
285 -};  
286 -  
287 -// Sign extending version  
288 -static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {  
289 - gen_op_movl_T0_sim,  
290 - gen_op_movl_T1_sim,  
291 - gen_op_movl_T2_sim  
292 -};  
293 -  
294 #ifdef TARGET_SPARC64 111 #ifdef TARGET_SPARC64
295 #define GEN32(func, NAME) \ 112 #define GEN32(func, NAME) \
296 static GenOpFunc * const NAME ## _table [64] = { \ 113 static GenOpFunc * const NAME ## _table [64] = { \
@@ -375,307 +192,112 @@ GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf); @@ -375,307 +192,112 @@ GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
375 #endif 192 #endif
376 193
377 #ifndef CONFIG_USER_ONLY 194 #ifndef CONFIG_USER_ONLY
378 -OP_LD_TABLE(ld);  
379 -OP_LD_TABLE(st);  
380 -OP_LD_TABLE(ldub);  
381 -OP_LD_TABLE(lduh);  
382 -OP_LD_TABLE(ldsb);  
383 -OP_LD_TABLE(ldsh);  
384 -OP_LD_TABLE(stb);  
385 -OP_LD_TABLE(sth);  
386 -OP_LD_TABLE(std);  
387 -OP_LD_TABLE(ldstub);  
388 -OP_LD_TABLE(swap);  
389 -OP_LD_TABLE(ldd);  
390 OP_LD_TABLE(stf); 195 OP_LD_TABLE(stf);
391 OP_LD_TABLE(stdf); 196 OP_LD_TABLE(stdf);
392 OP_LD_TABLE(ldf); 197 OP_LD_TABLE(ldf);
393 OP_LD_TABLE(lddf); 198 OP_LD_TABLE(lddf);
394 -  
395 -#ifdef TARGET_SPARC64  
396 -OP_LD_TABLE(lduw);  
397 -OP_LD_TABLE(ldsw);  
398 -OP_LD_TABLE(ldx);  
399 -OP_LD_TABLE(stx);  
400 -#endif  
401 #endif 199 #endif
402 200
403 -/* asi moves */  
404 -#ifdef TARGET_SPARC64  
405 -static inline void gen_ld_asi(int insn, int size, int sign)  
406 -{  
407 - int asi, offset;  
408 -  
409 - if (IS_IMM) {  
410 - offset = GET_FIELD(insn, 25, 31);  
411 - gen_op_ld_asi_reg(offset, size, sign);  
412 - } else {  
413 - asi = GET_FIELD(insn, 19, 26);  
414 - gen_op_ld_asi(asi, size, sign);  
415 - }  
416 -}  
417 -  
418 -static inline void gen_st_asi(int insn, int size)  
419 -{  
420 - int asi, offset;  
421 -  
422 - if (IS_IMM) {  
423 - offset = GET_FIELD(insn, 25, 31);  
424 - gen_op_st_asi_reg(offset, size);  
425 - } else {  
426 - asi = GET_FIELD(insn, 19, 26);  
427 - gen_op_st_asi(asi, size);  
428 - }  
429 -}  
430 -  
431 -static inline void gen_ldf_asi(int insn, int size, int rd)  
432 -{  
433 - int asi, offset;  
434 -  
435 - if (IS_IMM) {  
436 - offset = GET_FIELD(insn, 25, 31);  
437 - gen_op_ldf_asi_reg(offset, size, rd);  
438 - } else {  
439 - asi = GET_FIELD(insn, 19, 26);  
440 - gen_op_ldf_asi(asi, size, rd);  
441 - }  
442 -}  
443 -  
444 -static inline void gen_stf_asi(int insn, int size, int rd)  
445 -{  
446 - int asi, offset;  
447 -  
448 - if (IS_IMM) {  
449 - offset = GET_FIELD(insn, 25, 31);  
450 - gen_op_stf_asi_reg(offset, size, rd);  
451 - } else {  
452 - asi = GET_FIELD(insn, 19, 26);  
453 - gen_op_stf_asi(asi, size, rd);  
454 - }  
455 -} 201 +#ifdef TARGET_ABI32
  202 +#define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
  203 +#else
  204 +#define ABI32_MASK(addr)
  205 +#endif
456 206
457 -static inline void gen_swap_asi(int insn) 207 +static inline void gen_movl_simm_T1(int32_t val)
458 { 208 {
459 - int asi, offset;  
460 -  
461 - if (IS_IMM) {  
462 - offset = GET_FIELD(insn, 25, 31);  
463 - gen_op_swap_asi_reg(offset);  
464 - } else {  
465 - asi = GET_FIELD(insn, 19, 26);  
466 - gen_op_swap_asi(asi);  
467 - } 209 + tcg_gen_movi_tl(cpu_T[1], val);
468 } 210 }
469 211
470 -static inline void gen_ldstub_asi(int insn) 212 +static inline void gen_movl_reg_TN(int reg, TCGv tn)
471 { 213 {
472 - int asi, offset;  
473 -  
474 - if (IS_IMM) {  
475 - offset = GET_FIELD(insn, 25, 31);  
476 - gen_op_ldstub_asi_reg(offset);  
477 - } else {  
478 - asi = GET_FIELD(insn, 19, 26);  
479 - gen_op_ldstub_asi(asi); 214 + if (reg == 0)
  215 + tcg_gen_movi_tl(tn, 0);
  216 + else if (reg < 8)
  217 + tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUState, gregs[reg]));
  218 + else {
  219 + tcg_gen_ld_ptr(cpu_regwptr, cpu_env, offsetof(CPUState, regwptr)); // XXX
  220 + tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
480 } 221 }
481 } 222 }
482 223
483 -static inline void gen_ldda_asi(int insn) 224 +static inline void gen_movl_reg_T0(int reg)
484 { 225 {
485 - int asi, offset;  
486 -  
487 - if (IS_IMM) {  
488 - offset = GET_FIELD(insn, 25, 31);  
489 - gen_op_ldda_asi_reg(offset);  
490 - } else {  
491 - asi = GET_FIELD(insn, 19, 26);  
492 - gen_op_ldda_asi(asi);  
493 - } 226 + gen_movl_reg_TN(reg, cpu_T[0]);
494 } 227 }
495 228
496 -static inline void gen_stda_asi(int insn) 229 +static inline void gen_movl_reg_T1(int reg)
497 { 230 {
498 - int asi, offset;  
499 -  
500 - if (IS_IMM) {  
501 - offset = GET_FIELD(insn, 25, 31);  
502 - gen_op_stda_asi_reg(offset);  
503 - } else {  
504 - asi = GET_FIELD(insn, 19, 26);  
505 - gen_op_stda_asi(asi);  
506 - } 231 + gen_movl_reg_TN(reg, cpu_T[1]);
507 } 232 }
508 233
509 -static inline void gen_cas_asi(int insn) 234 +static inline void gen_movl_TN_reg(int reg, TCGv tn)
510 { 235 {
511 - int asi, offset;  
512 -  
513 - if (IS_IMM) {  
514 - offset = GET_FIELD(insn, 25, 31);  
515 - gen_op_cas_asi_reg(offset);  
516 - } else {  
517 - asi = GET_FIELD(insn, 19, 26);  
518 - gen_op_cas_asi(asi); 236 + if (reg == 0)
  237 + return;
  238 + else if (reg < 8)
  239 + tcg_gen_st_tl(tn, cpu_env, offsetof(CPUState, gregs[reg]));
  240 + else {
  241 + tcg_gen_ld_ptr(cpu_regwptr, cpu_env, offsetof(CPUState, regwptr)); // XXX
  242 + tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
519 } 243 }
520 } 244 }
521 245
522 -static inline void gen_casx_asi(int insn)  
523 -{  
524 - int asi, offset;  
525 -  
526 - if (IS_IMM) {  
527 - offset = GET_FIELD(insn, 25, 31);  
528 - gen_op_casx_asi_reg(offset);  
529 - } else {  
530 - asi = GET_FIELD(insn, 19, 26);  
531 - gen_op_casx_asi(asi);  
532 - }  
533 -}  
534 -  
535 -#elif !defined(CONFIG_USER_ONLY)  
536 -  
537 -static inline void gen_ld_asi(int insn, int size, int sign)  
538 -{  
539 - int asi;  
540 -  
541 - asi = GET_FIELD(insn, 19, 26);  
542 - gen_op_ld_asi(asi, size, sign);  
543 -}  
544 -  
545 -static inline void gen_st_asi(int insn, int size)  
546 -{  
547 - int asi;  
548 -  
549 - asi = GET_FIELD(insn, 19, 26);  
550 - gen_op_st_asi(asi, size);  
551 -}  
552 -  
553 -static inline void gen_ldstub_asi(int insn)  
554 -{  
555 - int asi;  
556 -  
557 - asi = GET_FIELD(insn, 19, 26);  
558 - gen_op_ldstub_asi(asi);  
559 -}  
560 -  
561 -static inline void gen_swap_asi(int insn)  
562 -{  
563 - int asi;  
564 -  
565 - asi = GET_FIELD(insn, 19, 26);  
566 - gen_op_swap_asi(asi);  
567 -}  
568 -  
569 -static inline void gen_ldda_asi(int insn)  
570 -{  
571 - int asi;  
572 -  
573 - asi = GET_FIELD(insn, 19, 26);  
574 - gen_op_ld_asi(asi, 8, 0);  
575 -}  
576 -  
577 -static inline void gen_stda_asi(int insn)  
578 -{  
579 - int asi;  
580 -  
581 - asi = GET_FIELD(insn, 19, 26);  
582 - gen_op_st_asi(asi, 8);  
583 -}  
584 -#endif  
585 -  
586 -static inline void gen_movl_imm_TN(int reg, uint32_t imm)  
587 -{  
588 - gen_op_movl_TN_im[reg](imm);  
589 -}  
590 -  
591 -static inline void gen_movl_imm_T1(uint32_t val)  
592 -{  
593 - gen_movl_imm_TN(1, val);  
594 -}  
595 -  
596 -static inline void gen_movl_imm_T0(uint32_t val)  
597 -{  
598 - gen_movl_imm_TN(0, val);  
599 -}  
600 -  
601 -static inline void gen_movl_simm_TN(int reg, int32_t imm)  
602 -{  
603 - gen_op_movl_TN_sim[reg](imm);  
604 -}  
605 -  
606 -static inline void gen_movl_simm_T1(int32_t val) 246 +static inline void gen_movl_T0_reg(int reg)
607 { 247 {
608 - gen_movl_simm_TN(1, val); 248 + gen_movl_TN_reg(reg, cpu_T[0]);
609 } 249 }
610 250
611 -static inline void gen_movl_simm_T0(int32_t val) 251 +static inline void gen_movl_T1_reg(int reg)
612 { 252 {
613 - gen_movl_simm_TN(0, val); 253 + gen_movl_TN_reg(reg, cpu_T[1]);
614 } 254 }
615 255
616 -static inline void gen_movl_reg_TN(int reg, int t) 256 +static inline void gen_op_movl_T0_env(size_t offset)
617 { 257 {
618 - if (reg)  
619 - gen_op_movl_reg_TN[t][reg] ();  
620 - else  
621 - gen_movl_imm_TN(t, 0); 258 + tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
622 } 259 }
623 260
624 -static inline void gen_movl_reg_T0(int reg) 261 +static inline void gen_op_movl_env_T0(size_t offset)
625 { 262 {
626 - gen_movl_reg_TN(reg, 0); 263 + tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
627 } 264 }
628 265
629 -static inline void gen_movl_reg_T1(int reg) 266 +static inline void gen_op_movtl_T0_env(size_t offset)
630 { 267 {
631 - gen_movl_reg_TN(reg, 1); 268 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
632 } 269 }
633 270
634 -static inline void gen_movl_reg_T2(int reg) 271 +static inline void gen_op_movtl_env_T0(size_t offset)
635 { 272 {
636 - gen_movl_reg_TN(reg, 2); 273 + tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
637 } 274 }
638 275
639 -static inline void gen_movl_TN_reg(int reg, int t) 276 +static inline void gen_op_add_T1_T0(void)
640 { 277 {
641 - if (reg)  
642 - gen_op_movl_TN_reg[t][reg] (); 278 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
643 } 279 }
644 280
645 -static inline void gen_movl_T0_reg(int reg) 281 +static inline void gen_op_or_T1_T0(void)
646 { 282 {
647 - gen_movl_TN_reg(reg, 0); 283 + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
648 } 284 }
649 285
650 -static inline void gen_movl_T1_reg(int reg) 286 +static inline void gen_op_xor_T1_T0(void)
651 { 287 {
652 - gen_movl_TN_reg(reg, 1); 288 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
653 } 289 }
654 290
655 static inline void gen_jmp_im(target_ulong pc) 291 static inline void gen_jmp_im(target_ulong pc)
656 { 292 {
657 -#ifdef TARGET_SPARC64  
658 - if (pc == (uint32_t)pc) {  
659 - gen_op_jmp_im(pc);  
660 - } else {  
661 - gen_op_jmp_im64(pc >> 32, pc);  
662 - }  
663 -#else  
664 - gen_op_jmp_im(pc);  
665 -#endif 293 + tcg_gen_movi_tl(cpu_tmp0, pc);
  294 + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, pc));
666 } 295 }
667 296
668 static inline void gen_movl_npc_im(target_ulong npc) 297 static inline void gen_movl_npc_im(target_ulong npc)
669 { 298 {
670 -#ifdef TARGET_SPARC64  
671 - if (npc == (uint32_t)npc) {  
672 - gen_op_movl_npc_im(npc);  
673 - } else {  
674 - gen_op_movq_npc_im64(npc >> 32, npc);  
675 - }  
676 -#else  
677 - gen_op_movl_npc_im(npc);  
678 -#endif 299 + tcg_gen_movi_tl(cpu_tmp0, npc);
  300 + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, npc));
679 } 301 }
680 302
681 static inline void gen_goto_tb(DisasContext *s, int tb_num, 303 static inline void gen_goto_tb(DisasContext *s, int tb_num,
@@ -1095,6 +717,270 @@ static int gen_trap_ifnofpu(DisasContext * dc) @@ -1095,6 +717,270 @@ static int gen_trap_ifnofpu(DisasContext * dc)
1095 return 0; 717 return 0;
1096 } 718 }
1097 719
  720 +/* asi moves */
  721 +#ifdef TARGET_SPARC64
  722 +static inline void gen_ld_asi(int insn, int size, int sign)
  723 +{
  724 + int asi, offset;
  725 + TCGv r_size, r_sign;
  726 +
  727 + r_size = tcg_temp_new(TCG_TYPE_I32);
  728 + r_sign = tcg_temp_new(TCG_TYPE_I32);
  729 + tcg_gen_movi_i32(r_size, size);
  730 + tcg_gen_movi_i32(r_sign, sign);
  731 + if (IS_IMM) {
  732 + offset = GET_FIELD(insn, 25, 31);
  733 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
  734 + tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
  735 + } else {
  736 + asi = GET_FIELD(insn, 19, 26);
  737 + tcg_gen_movi_i32(cpu_T[1], asi);
  738 + }
  739 + tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], cpu_T[1], r_size,
  740 + r_sign);
  741 +}
  742 +
  743 +static inline void gen_st_asi(int insn, int size)
  744 +{
  745 + int asi, offset;
  746 + TCGv r_asi, r_size;
  747 +
  748 + r_asi = tcg_temp_new(TCG_TYPE_I32);
  749 + r_size = tcg_temp_new(TCG_TYPE_I32);
  750 + tcg_gen_movi_i32(r_size, size);
  751 + if (IS_IMM) {
  752 + offset = GET_FIELD(insn, 25, 31);
  753 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
  754 + tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
  755 + } else {
  756 + asi = GET_FIELD(insn, 19, 26);
  757 + tcg_gen_movi_i32(r_asi, asi);
  758 + }
  759 + tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, r_size);
  760 +}
  761 +
  762 +static inline void gen_ldf_asi(int insn, int size, int rd)
  763 +{
  764 + int asi, offset;
  765 + TCGv r_asi, r_size, r_rd;
  766 +
  767 + r_asi = tcg_temp_new(TCG_TYPE_I32);
  768 + r_size = tcg_temp_new(TCG_TYPE_I32);
  769 + r_rd = tcg_temp_new(TCG_TYPE_I32);
  770 + tcg_gen_movi_i32(r_size, size);
  771 + tcg_gen_movi_i32(r_rd, rd);
  772 + if (IS_IMM) {
  773 + offset = GET_FIELD(insn, 25, 31);
  774 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
  775 + tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
  776 + } else {
  777 + asi = GET_FIELD(insn, 19, 26);
  778 + tcg_gen_movi_i32(r_asi, asi);
  779 + }
  780 + tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, r_size, r_rd);
  781 +}
  782 +
  783 +static inline void gen_stf_asi(int insn, int size, int rd)
  784 +{
  785 + int asi, offset;
  786 + TCGv r_asi, r_size, r_rd;
  787 +
  788 + r_asi = tcg_temp_new(TCG_TYPE_I32);
  789 + r_size = tcg_temp_new(TCG_TYPE_I32);
  790 + r_rd = tcg_temp_new(TCG_TYPE_I32);
  791 + tcg_gen_movi_i32(r_size, size);
  792 + tcg_gen_movi_i32(r_rd, rd);
  793 + if (IS_IMM) {
  794 + offset = GET_FIELD(insn, 25, 31);
  795 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
  796 + tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
  797 + } else {
  798 + asi = GET_FIELD(insn, 19, 26);
  799 + tcg_gen_movi_i32(r_asi, asi);
  800 + }
  801 + tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, r_size, r_rd);
  802 +}
  803 +
  804 +static inline void gen_swap_asi(int insn)
  805 +{
  806 + int asi, offset;
  807 + TCGv r_size, r_sign, r_temp;
  808 +
  809 + r_size = tcg_temp_new(TCG_TYPE_I32);
  810 + r_sign = tcg_temp_new(TCG_TYPE_I32);
  811 + r_temp = tcg_temp_new(TCG_TYPE_I32);
  812 + tcg_gen_movi_i32(r_size, 4);
  813 + tcg_gen_movi_i32(r_sign, 0);
  814 + if (IS_IMM) {
  815 + offset = GET_FIELD(insn, 25, 31);
  816 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
  817 + tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
  818 + } else {
  819 + asi = GET_FIELD(insn, 19, 26);
  820 + tcg_gen_movi_i32(cpu_T[1], asi);
  821 + }
  822 + tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
  823 + r_sign);
  824 + tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
  825 + tcg_gen_mov_i32(cpu_T[1], r_temp);
  826 +}
  827 +
  828 +static inline void gen_ldda_asi(int insn)
  829 +{
  830 + int asi, offset;
  831 + TCGv r_size, r_sign, r_dword;
  832 +
  833 + r_size = tcg_temp_new(TCG_TYPE_I32);
  834 + r_sign = tcg_temp_new(TCG_TYPE_I32);
  835 + r_dword = tcg_temp_new(TCG_TYPE_I64);
  836 + tcg_gen_movi_i32(r_size, 8);
  837 + tcg_gen_movi_i32(r_sign, 0);
  838 + if (IS_IMM) {
  839 + offset = GET_FIELD(insn, 25, 31);
  840 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
  841 + tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
  842 + } else {
  843 + asi = GET_FIELD(insn, 19, 26);
  844 + tcg_gen_movi_i32(cpu_T[1], asi);
  845 + }
  846 + tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
  847 + r_sign);
  848 + tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
  849 + tcg_gen_shri_i64(r_dword, r_dword, 32);
  850 + tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
  851 +}
  852 +
  853 +static inline void gen_cas_asi(int insn, int rd)
  854 +{
  855 + int asi, offset;
  856 + TCGv r_val1, r_asi;
  857 +
  858 + r_val1 = tcg_temp_new(TCG_TYPE_I32);
  859 + r_asi = tcg_temp_new(TCG_TYPE_I32);
  860 + gen_movl_reg_TN(rd, r_val1);
  861 + if (IS_IMM) {
  862 + offset = GET_FIELD(insn, 25, 31);
  863 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
  864 + tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
  865 + } else {
  866 + asi = GET_FIELD(insn, 19, 26);
  867 + tcg_gen_movi_i32(r_asi, asi);
  868 + }
  869 + tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
  870 + r_asi);
  871 +}
  872 +
  873 +static inline void gen_casx_asi(int insn, int rd)
  874 +{
  875 + int asi, offset;
  876 + TCGv r_val1, r_asi;
  877 +
  878 + r_val1 = tcg_temp_new(TCG_TYPE_I64);
  879 + r_asi = tcg_temp_new(TCG_TYPE_I32);
  880 + gen_movl_reg_TN(rd, r_val1);
  881 + if (IS_IMM) {
  882 + offset = GET_FIELD(insn, 25, 31);
  883 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
  884 + tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
  885 + } else {
  886 + asi = GET_FIELD(insn, 19, 26);
  887 + tcg_gen_movi_i32(r_asi, asi);
  888 + }
  889 + tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
  890 + r_asi);
  891 +}
  892 +
  893 +#elif !defined(CONFIG_USER_ONLY)
  894 +
  895 +static inline void gen_ld_asi(int insn, int size, int sign)
  896 +{
  897 + int asi;
  898 + TCGv r_size, r_sign, r_dword;
  899 +
  900 + r_size = tcg_temp_new(TCG_TYPE_I32);
  901 + r_sign = tcg_temp_new(TCG_TYPE_I32);
  902 + r_dword = tcg_temp_new(TCG_TYPE_I64);
  903 + tcg_gen_movi_i32(r_size, size);
  904 + tcg_gen_movi_i32(r_sign, sign);
  905 + asi = GET_FIELD(insn, 19, 26);
  906 + tcg_gen_movi_i32(cpu_T[1], asi);
  907 + tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
  908 + r_sign);
  909 + tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
  910 +}
  911 +
  912 +static inline void gen_st_asi(int insn, int size)
  913 +{
  914 + int asi;
  915 + TCGv r_dword, r_asi, r_size;
  916 +
  917 + r_dword = tcg_temp_new(TCG_TYPE_I64);
  918 + tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
  919 + r_asi = tcg_temp_new(TCG_TYPE_I32);
  920 + r_size = tcg_temp_new(TCG_TYPE_I32);
  921 + asi = GET_FIELD(insn, 19, 26);
  922 + tcg_gen_movi_i32(r_asi, asi);
  923 + tcg_gen_movi_i32(r_size, size);
  924 + tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
  925 +}
  926 +
  927 +static inline void gen_swap_asi(int insn)
  928 +{
  929 + int asi;
  930 + TCGv r_size, r_sign, r_temp;
  931 +
  932 + r_size = tcg_temp_new(TCG_TYPE_I32);
  933 + r_sign = tcg_temp_new(TCG_TYPE_I32);
  934 + r_temp = tcg_temp_new(TCG_TYPE_I32);
  935 + tcg_gen_movi_i32(r_size, 4);
  936 + tcg_gen_movi_i32(r_sign, 0);
  937 + asi = GET_FIELD(insn, 19, 26);
  938 + tcg_gen_movi_i32(cpu_T[1], asi);
  939 + tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
  940 + r_sign);
  941 + tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
  942 + tcg_gen_mov_i32(cpu_T[1], r_temp);
  943 +}
  944 +
  945 +static inline void gen_ldda_asi(int insn)
  946 +{
  947 + int asi;
  948 + TCGv r_size, r_sign, r_dword;
  949 +
  950 + r_size = tcg_temp_new(TCG_TYPE_I32);
  951 + r_sign = tcg_temp_new(TCG_TYPE_I32);
  952 + r_dword = tcg_temp_new(TCG_TYPE_I64);
  953 + tcg_gen_movi_i32(r_size, 8);
  954 + tcg_gen_movi_i32(r_sign, 0);
  955 + asi = GET_FIELD(insn, 19, 26);
  956 + tcg_gen_movi_i32(cpu_T[1], asi);
  957 + tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
  958 + r_sign);
  959 + tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
  960 + tcg_gen_shri_i64(r_dword, r_dword, 32);
  961 + tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
  962 +}
  963 +#endif
  964 +
  965 +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
  966 +static inline void gen_ldstub_asi(int insn)
  967 +{
  968 + int asi;
  969 + TCGv r_dword, r_asi, r_size;
  970 +
  971 + gen_ld_asi(insn, 1, 0);
  972 +
  973 + r_dword = tcg_temp_new(TCG_TYPE_I64);
  974 + r_asi = tcg_temp_new(TCG_TYPE_I32);
  975 + r_size = tcg_temp_new(TCG_TYPE_I32);
  976 + asi = GET_FIELD(insn, 19, 26);
  977 + tcg_gen_movi_i32(r_dword, 0xff);
  978 + tcg_gen_movi_i32(r_asi, asi);
  979 + tcg_gen_movi_i32(r_size, 1);
  980 + tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
  981 +}
  982 +#endif
  983 +
1098 /* before an instruction, dc->pc must be static */ 984 /* before an instruction, dc->pc must be static */
1099 static void disas_sparc_insn(DisasContext * dc) 985 static void disas_sparc_insn(DisasContext * dc)
1100 { 986 {
@@ -1179,7 +1065,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1179,7 +1065,7 @@ static void disas_sparc_insn(DisasContext * dc)
1179 if (rd) { // nop 1065 if (rd) { // nop
1180 #endif 1066 #endif
1181 uint32_t value = GET_FIELD(insn, 10, 31); 1067 uint32_t value = GET_FIELD(insn, 10, 31);
1182 - gen_movl_imm_T0(value << 10); 1068 + tcg_gen_movi_tl(cpu_T[0], value << 10);
1183 gen_movl_T0_reg(rd); 1069 gen_movl_T0_reg(rd);
1184 #if defined(OPTIM) 1070 #if defined(OPTIM)
1185 } 1071 }
@@ -1196,15 +1082,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1196,15 +1082,7 @@ static void disas_sparc_insn(DisasContext * dc)
1196 /*CALL*/ { 1082 /*CALL*/ {
1197 target_long target = GET_FIELDs(insn, 2, 31) << 2; 1083 target_long target = GET_FIELDs(insn, 2, 31) << 2;
1198 1084
1199 -#ifdef TARGET_SPARC64  
1200 - if (dc->pc == (uint32_t)dc->pc) {  
1201 - gen_op_movl_T0_im(dc->pc);  
1202 - } else {  
1203 - gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);  
1204 - }  
1205 -#else  
1206 - gen_op_movl_T0_im(dc->pc);  
1207 -#endif 1085 + tcg_gen_movi_tl(cpu_T[0], dc->pc);
1208 gen_movl_T0_reg(15); 1086 gen_movl_T0_reg(15);
1209 target += dc->pc; 1087 target += dc->pc;
1210 gen_mov_pc_npc(dc); 1088 gen_mov_pc_npc(dc);
@@ -1221,14 +1099,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1221,14 +1099,7 @@ static void disas_sparc_insn(DisasContext * dc)
1221 gen_movl_reg_T0(rs1); 1099 gen_movl_reg_T0(rs1);
1222 if (IS_IMM) { 1100 if (IS_IMM) {
1223 rs2 = GET_FIELD(insn, 25, 31); 1101 rs2 = GET_FIELD(insn, 25, 31);
1224 -#if defined(OPTIM)  
1225 - if (rs2 != 0) {  
1226 -#endif  
1227 - gen_movl_simm_T1(rs2);  
1228 - gen_op_add_T1_T0();  
1229 -#if defined(OPTIM)  
1230 - }  
1231 -#endif 1102 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
1232 } else { 1103 } else {
1233 rs2 = GET_FIELD(insn, 27, 31); 1104 rs2 = GET_FIELD(insn, 27, 31);
1234 #if defined(OPTIM) 1105 #if defined(OPTIM)
@@ -1243,7 +1114,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1243,7 +1114,7 @@ static void disas_sparc_insn(DisasContext * dc)
1243 cond = GET_FIELD(insn, 3, 6); 1114 cond = GET_FIELD(insn, 3, 6);
1244 if (cond == 0x8) { 1115 if (cond == 0x8) {
1245 save_state(dc); 1116 save_state(dc);
1246 - gen_op_trap_T0(); 1117 + tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
1247 } else if (cond != 0) { 1118 } else if (cond != 0) {
1248 #ifdef TARGET_SPARC64 1119 #ifdef TARGET_SPARC64
1249 /* V9 icc/xcc */ 1120 /* V9 icc/xcc */
@@ -1261,7 +1132,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1261,7 +1132,7 @@ static void disas_sparc_insn(DisasContext * dc)
1261 save_state(dc); 1132 save_state(dc);
1262 gen_cond[0][cond](); 1133 gen_cond[0][cond]();
1263 #endif 1134 #endif
1264 - gen_op_trapcc_T0(); 1135 + tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], cpu_T[2]);
1265 } 1136 }
1266 gen_op_next_insn(); 1137 gen_op_next_insn();
1267 tcg_gen_exit_tb(0); 1138 tcg_gen_exit_tb(0);
@@ -1298,11 +1169,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1298,11 +1169,7 @@ static void disas_sparc_insn(DisasContext * dc)
1298 gen_movl_T0_reg(rd); 1169 gen_movl_T0_reg(rd);
1299 break; 1170 break;
1300 case 0x5: /* V9 rdpc */ 1171 case 0x5: /* V9 rdpc */
1301 - if (dc->pc == (uint32_t)dc->pc) {  
1302 - gen_op_movl_T0_im(dc->pc);  
1303 - } else {  
1304 - gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);  
1305 - } 1172 + tcg_gen_movi_tl(cpu_T[0], dc->pc);
1306 gen_movl_T0_reg(rd); 1173 gen_movl_T0_reg(rd);
1307 break; 1174 break;
1308 case 0x6: /* V9 rdfprs */ 1175 case 0x6: /* V9 rdfprs */
@@ -1344,7 +1211,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1344,7 +1211,7 @@ static void disas_sparc_insn(DisasContext * dc)
1344 #ifndef TARGET_SPARC64 1211 #ifndef TARGET_SPARC64
1345 if (!supervisor(dc)) 1212 if (!supervisor(dc))
1346 goto priv_insn; 1213 goto priv_insn;
1347 - gen_op_rdpsr(); 1214 + tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]);
1348 #else 1215 #else
1349 if (!hypervisor(dc)) 1216 if (!hypervisor(dc))
1350 goto priv_insn; 1217 goto priv_insn;
@@ -1399,7 +1266,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1399,7 +1266,7 @@ static void disas_sparc_insn(DisasContext * dc)
1399 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); 1266 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1400 break; 1267 break;
1401 case 6: // pstate 1268 case 6: // pstate
1402 - gen_op_rdpstate(); 1269 + gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate));
1403 break; 1270 break;
1404 case 7: // tl 1271 case 7: // tl
1405 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); 1272 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
@@ -2078,24 +1945,19 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2078,24 +1945,19 @@ static void disas_sparc_insn(DisasContext * dc)
2078 1945
2079 rs1 = GET_FIELD(insn, 13, 17); 1946 rs1 = GET_FIELD(insn, 13, 17);
2080 if (rs1 == 0) { 1947 if (rs1 == 0) {
2081 - // or %g0, x, y -> mov T1, x; mov y, T1 1948 + // or %g0, x, y -> mov T0, x; mov y, T0
2082 if (IS_IMM) { /* immediate */ 1949 if (IS_IMM) { /* immediate */
2083 rs2 = GET_FIELDs(insn, 19, 31); 1950 rs2 = GET_FIELDs(insn, 19, 31);
2084 - gen_movl_simm_T1(rs2); 1951 + tcg_gen_movi_tl(cpu_T[0], (int)rs2);
2085 } else { /* register */ 1952 } else { /* register */
2086 rs2 = GET_FIELD(insn, 27, 31); 1953 rs2 = GET_FIELD(insn, 27, 31);
2087 - gen_movl_reg_T1(rs2); 1954 + gen_movl_reg_T0(rs2);
2088 } 1955 }
2089 - gen_movl_T1_reg(rd);  
2090 } else { 1956 } else {
2091 gen_movl_reg_T0(rs1); 1957 gen_movl_reg_T0(rs1);
2092 if (IS_IMM) { /* immediate */ 1958 if (IS_IMM) { /* immediate */
2093 - // or x, #0, y -> mov T1, x; mov y, T1  
2094 rs2 = GET_FIELDs(insn, 19, 31); 1959 rs2 = GET_FIELDs(insn, 19, 31);
2095 - if (rs2 != 0) {  
2096 - gen_movl_simm_T1(rs2);  
2097 - gen_op_or_T1_T0();  
2098 - } 1960 + tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
2099 } else { /* register */ 1961 } else { /* register */
2100 // or x, %g0, y -> mov T1, x; mov y, T1 1962 // or x, %g0, y -> mov T1, x; mov y, T1
2101 rs2 = GET_FIELD(insn, 27, 31); 1963 rs2 = GET_FIELD(insn, 27, 31);
@@ -2104,8 +1966,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2104,8 +1966,8 @@ static void disas_sparc_insn(DisasContext * dc)
2104 gen_op_or_T1_T0(); 1966 gen_op_or_T1_T0();
2105 } 1967 }
2106 } 1968 }
2107 - gen_movl_T0_reg(rd);  
2108 } 1969 }
  1970 + gen_movl_T0_reg(rd);
2109 #endif 1971 #endif
2110 #ifdef TARGET_SPARC64 1972 #ifdef TARGET_SPARC64
2111 } else if (xop == 0x25) { /* sll, V9 sllx */ 1973 } else if (xop == 0x25) { /* sll, V9 sllx */
@@ -2113,45 +1975,73 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2113,45 +1975,73 @@ static void disas_sparc_insn(DisasContext * dc)
2113 gen_movl_reg_T0(rs1); 1975 gen_movl_reg_T0(rs1);
2114 if (IS_IMM) { /* immediate */ 1976 if (IS_IMM) { /* immediate */
2115 rs2 = GET_FIELDs(insn, 20, 31); 1977 rs2 = GET_FIELDs(insn, 20, 31);
2116 - gen_movl_simm_T1(rs2); 1978 + if (insn & (1 << 12)) {
  1979 + tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
  1980 + } else {
  1981 + tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
  1982 + tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
  1983 + }
2117 } else { /* register */ 1984 } else { /* register */
2118 rs2 = GET_FIELD(insn, 27, 31); 1985 rs2 = GET_FIELD(insn, 27, 31);
2119 gen_movl_reg_T1(rs2); 1986 gen_movl_reg_T1(rs2);
  1987 + if (insn & (1 << 12)) {
  1988 + tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
  1989 + tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
  1990 + } else {
  1991 + tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
  1992 + tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
  1993 + tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
  1994 + }
2120 } 1995 }
2121 - if (insn & (1 << 12))  
2122 - gen_op_sllx();  
2123 - else  
2124 - gen_op_sll();  
2125 gen_movl_T0_reg(rd); 1996 gen_movl_T0_reg(rd);
2126 } else if (xop == 0x26) { /* srl, V9 srlx */ 1997 } else if (xop == 0x26) { /* srl, V9 srlx */
2127 rs1 = GET_FIELD(insn, 13, 17); 1998 rs1 = GET_FIELD(insn, 13, 17);
2128 gen_movl_reg_T0(rs1); 1999 gen_movl_reg_T0(rs1);
2129 if (IS_IMM) { /* immediate */ 2000 if (IS_IMM) { /* immediate */
2130 rs2 = GET_FIELDs(insn, 20, 31); 2001 rs2 = GET_FIELDs(insn, 20, 31);
2131 - gen_movl_simm_T1(rs2); 2002 + if (insn & (1 << 12)) {
  2003 + tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
  2004 + } else {
  2005 + tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
  2006 + tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
  2007 + }
2132 } else { /* register */ 2008 } else { /* register */
2133 rs2 = GET_FIELD(insn, 27, 31); 2009 rs2 = GET_FIELD(insn, 27, 31);
2134 gen_movl_reg_T1(rs2); 2010 gen_movl_reg_T1(rs2);
  2011 + if (insn & (1 << 12)) {
  2012 + tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
  2013 + tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
  2014 + } else {
  2015 + tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
  2016 + tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
  2017 + tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
  2018 + }
2135 } 2019 }
2136 - if (insn & (1 << 12))  
2137 - gen_op_srlx();  
2138 - else  
2139 - gen_op_srl();  
2140 gen_movl_T0_reg(rd); 2020 gen_movl_T0_reg(rd);
2141 } else if (xop == 0x27) { /* sra, V9 srax */ 2021 } else if (xop == 0x27) { /* sra, V9 srax */
2142 rs1 = GET_FIELD(insn, 13, 17); 2022 rs1 = GET_FIELD(insn, 13, 17);
2143 gen_movl_reg_T0(rs1); 2023 gen_movl_reg_T0(rs1);
2144 if (IS_IMM) { /* immediate */ 2024 if (IS_IMM) { /* immediate */
2145 rs2 = GET_FIELDs(insn, 20, 31); 2025 rs2 = GET_FIELDs(insn, 20, 31);
2146 - gen_movl_simm_T1(rs2); 2026 + if (insn & (1 << 12)) {
  2027 + tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
  2028 + } else {
  2029 + tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
  2030 + tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]);
  2031 + tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
  2032 + }
2147 } else { /* register */ 2033 } else { /* register */
2148 rs2 = GET_FIELD(insn, 27, 31); 2034 rs2 = GET_FIELD(insn, 27, 31);
2149 gen_movl_reg_T1(rs2); 2035 gen_movl_reg_T1(rs2);
  2036 + if (insn & (1 << 12)) {
  2037 + tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
  2038 + tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
  2039 + } else {
  2040 + tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
  2041 + tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
  2042 + tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
  2043 + }
2150 } 2044 }
2151 - if (insn & (1 << 12))  
2152 - gen_op_srax();  
2153 - else  
2154 - gen_op_sra();  
2155 gen_movl_T0_reg(rd); 2045 gen_movl_T0_reg(rd);
2156 #endif 2046 #endif
2157 } else if (xop < 0x36) { 2047 } else if (xop < 0x36) {
@@ -2173,17 +2063,17 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2173,17 +2063,17 @@ static void disas_sparc_insn(DisasContext * dc)
2173 gen_op_add_T1_T0(); 2063 gen_op_add_T1_T0();
2174 break; 2064 break;
2175 case 0x1: 2065 case 0x1:
2176 - gen_op_and_T1_T0(); 2066 + tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2177 if (xop & 0x10) 2067 if (xop & 0x10)
2178 gen_op_logic_T0_cc(); 2068 gen_op_logic_T0_cc();
2179 break; 2069 break;
2180 case 0x2: 2070 case 0x2:
2181 - gen_op_or_T1_T0(); 2071 + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2182 if (xop & 0x10) 2072 if (xop & 0x10)
2183 gen_op_logic_T0_cc(); 2073 gen_op_logic_T0_cc();
2184 break; 2074 break;
2185 case 0x3: 2075 case 0x3:
2186 - gen_op_xor_T1_T0(); 2076 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2187 if (xop & 0x10) 2077 if (xop & 0x10)
2188 gen_op_logic_T0_cc(); 2078 gen_op_logic_T0_cc();
2189 break; 2079 break;
@@ -2191,7 +2081,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2191,7 +2081,7 @@ static void disas_sparc_insn(DisasContext * dc)
2191 if (xop & 0x10) 2081 if (xop & 0x10)
2192 gen_op_sub_T1_T0_cc(); 2082 gen_op_sub_T1_T0_cc();
2193 else 2083 else
2194 - gen_op_sub_T1_T0(); 2084 + tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2195 break; 2085 break;
2196 case 0x5: 2086 case 0x5:
2197 gen_op_andn_T1_T0(); 2087 gen_op_andn_T1_T0();
@@ -2216,7 +2106,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2216,7 +2106,7 @@ static void disas_sparc_insn(DisasContext * dc)
2216 break; 2106 break;
2217 #ifdef TARGET_SPARC64 2107 #ifdef TARGET_SPARC64
2218 case 0x9: /* V9 mulx */ 2108 case 0x9: /* V9 mulx */
2219 - gen_op_mulx_T1_T0(); 2109 + tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2220 break; 2110 break;
2221 #endif 2111 #endif
2222 case 0xa: 2112 case 0xa:
@@ -2280,15 +2170,18 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2280,15 +2170,18 @@ static void disas_sparc_insn(DisasContext * dc)
2280 break; 2170 break;
2281 #ifndef TARGET_SPARC64 2171 #ifndef TARGET_SPARC64
2282 case 0x25: /* sll */ 2172 case 0x25: /* sll */
2283 - gen_op_sll(); 2173 + tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
  2174 + tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
2284 gen_movl_T0_reg(rd); 2175 gen_movl_T0_reg(rd);
2285 break; 2176 break;
2286 case 0x26: /* srl */ 2177 case 0x26: /* srl */
2287 - gen_op_srl(); 2178 + tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
  2179 + tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
2288 gen_movl_T0_reg(rd); 2180 gen_movl_T0_reg(rd);
2289 break; 2181 break;
2290 case 0x27: /* sra */ 2182 case 0x27: /* sra */
2291 - gen_op_sra(); 2183 + tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
  2184 + tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
2292 gen_movl_T0_reg(rd); 2185 gen_movl_T0_reg(rd);
2293 break; 2186 break;
2294 #endif 2187 #endif
@@ -2329,7 +2222,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2329,7 +2222,7 @@ static void disas_sparc_insn(DisasContext * dc)
2329 case 0xf: /* V9 sir, nop if user */ 2222 case 0xf: /* V9 sir, nop if user */
2330 #if !defined(CONFIG_USER_ONLY) 2223 #if !defined(CONFIG_USER_ONLY)
2331 if (supervisor(dc)) 2224 if (supervisor(dc))
2332 - gen_op_sir(); 2225 + ; // XXX
2333 #endif 2226 #endif
2334 break; 2227 break;
2335 case 0x13: /* Graphics Status */ 2228 case 0x13: /* Graphics Status */
@@ -2400,7 +2293,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2400,7 +2293,7 @@ static void disas_sparc_insn(DisasContext * dc)
2400 } 2293 }
2401 #else 2294 #else
2402 gen_op_xor_T1_T0(); 2295 gen_op_xor_T1_T0();
2403 - gen_op_wrpsr(); 2296 + tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
2404 save_state(dc); 2297 save_state(dc);
2405 gen_op_next_insn(); 2298 gen_op_next_insn();
2406 tcg_gen_exit_tb(0); 2299 tcg_gen_exit_tb(0);
@@ -2434,8 +2327,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2434,8 +2327,8 @@ static void disas_sparc_insn(DisasContext * dc)
2434 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); 2327 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2435 break; 2328 break;
2436 case 6: // pstate 2329 case 6: // pstate
2437 - gen_op_wrpstate();  
2438 save_state(dc); 2330 save_state(dc);
  2331 + tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
2439 gen_op_next_insn(); 2332 gen_op_next_insn();
2440 tcg_gen_exit_tb(0); 2333 tcg_gen_exit_tb(0);
2441 dc->is_br = 1; 2334 dc->is_br = 1;
@@ -2476,7 +2369,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2476,7 +2369,8 @@ static void disas_sparc_insn(DisasContext * dc)
2476 goto illegal_insn; 2369 goto illegal_insn;
2477 } 2370 }
2478 #else 2371 #else
2479 - gen_op_wrwim(); 2372 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
  2373 + gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
2480 #endif 2374 #endif
2481 } 2375 }
2482 break; 2376 break;
@@ -2564,7 +2458,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2564,7 +2458,8 @@ static void disas_sparc_insn(DisasContext * dc)
2564 rs2 = GET_FIELD_SP(insn, 0, 4); 2458 rs2 = GET_FIELD_SP(insn, 0, 4);
2565 gen_movl_reg_T1(rs2); 2459 gen_movl_reg_T1(rs2);
2566 } 2460 }
2567 - gen_op_popc(); 2461 + tcg_gen_helper_1_1(helper_popc, cpu_T[0],
  2462 + cpu_T[1]);
2568 gen_movl_T0_reg(rd); 2463 gen_movl_T0_reg(rd);
2569 } 2464 }
2570 case 0x2f: /* V9 movr */ 2465 case 0x2f: /* V9 movr */
@@ -3003,14 +2898,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3003,14 +2898,7 @@ static void disas_sparc_insn(DisasContext * dc)
3003 gen_movl_reg_T0(rs1); 2898 gen_movl_reg_T0(rs1);
3004 if (IS_IMM) { /* immediate */ 2899 if (IS_IMM) { /* immediate */
3005 rs2 = GET_FIELDs(insn, 19, 31); 2900 rs2 = GET_FIELDs(insn, 19, 31);
3006 -#if defined(OPTIM)  
3007 - if (rs2) {  
3008 -#endif  
3009 - gen_movl_simm_T1(rs2);  
3010 - gen_op_add_T1_T0();  
3011 -#if defined(OPTIM)  
3012 - }  
3013 -#endif 2901 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
3014 } else { /* register */ 2902 } else { /* register */
3015 rs2 = GET_FIELD(insn, 27, 31); 2903 rs2 = GET_FIELD(insn, 27, 31);
3016 #if defined(OPTIM) 2904 #if defined(OPTIM)
@@ -3025,7 +2913,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3025,7 +2913,7 @@ static void disas_sparc_insn(DisasContext * dc)
3025 gen_op_restore(); 2913 gen_op_restore();
3026 gen_mov_pc_npc(dc); 2914 gen_mov_pc_npc(dc);
3027 gen_op_check_align_T0_3(); 2915 gen_op_check_align_T0_3();
3028 - gen_op_movl_npc_T0(); 2916 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
3029 dc->npc = DYNAMIC_PC; 2917 dc->npc = DYNAMIC_PC;
3030 goto jmp_insn; 2918 goto jmp_insn;
3031 #endif 2919 #endif
@@ -3034,14 +2922,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3034,14 +2922,7 @@ static void disas_sparc_insn(DisasContext * dc)
3034 gen_movl_reg_T0(rs1); 2922 gen_movl_reg_T0(rs1);
3035 if (IS_IMM) { /* immediate */ 2923 if (IS_IMM) { /* immediate */
3036 rs2 = GET_FIELDs(insn, 19, 31); 2924 rs2 = GET_FIELDs(insn, 19, 31);
3037 -#if defined(OPTIM)  
3038 - if (rs2) {  
3039 -#endif  
3040 - gen_movl_simm_T1(rs2);  
3041 - gen_op_add_T1_T0();  
3042 -#if defined(OPTIM)  
3043 - }  
3044 -#endif 2925 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
3045 } else { /* register */ 2926 } else { /* register */
3046 rs2 = GET_FIELD(insn, 27, 31); 2927 rs2 = GET_FIELD(insn, 27, 31);
3047 #if defined(OPTIM) 2928 #if defined(OPTIM)
@@ -3057,20 +2938,12 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3057,20 +2938,12 @@ static void disas_sparc_insn(DisasContext * dc)
3057 case 0x38: /* jmpl */ 2938 case 0x38: /* jmpl */
3058 { 2939 {
3059 if (rd != 0) { 2940 if (rd != 0) {
3060 -#ifdef TARGET_SPARC64  
3061 - if (dc->pc == (uint32_t)dc->pc) {  
3062 - gen_op_movl_T1_im(dc->pc);  
3063 - } else {  
3064 - gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);  
3065 - }  
3066 -#else  
3067 - gen_op_movl_T1_im(dc->pc);  
3068 -#endif 2941 + tcg_gen_movi_tl(cpu_T[1], dc->pc);
3069 gen_movl_T1_reg(rd); 2942 gen_movl_T1_reg(rd);
3070 } 2943 }
3071 gen_mov_pc_npc(dc); 2944 gen_mov_pc_npc(dc);
3072 gen_op_check_align_T0_3(); 2945 gen_op_check_align_T0_3();
3073 - gen_op_movl_npc_T0(); 2946 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
3074 dc->npc = DYNAMIC_PC; 2947 dc->npc = DYNAMIC_PC;
3075 } 2948 }
3076 goto jmp_insn; 2949 goto jmp_insn;
@@ -3081,14 +2954,14 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3081,14 +2954,14 @@ static void disas_sparc_insn(DisasContext * dc)
3081 goto priv_insn; 2954 goto priv_insn;
3082 gen_mov_pc_npc(dc); 2955 gen_mov_pc_npc(dc);
3083 gen_op_check_align_T0_3(); 2956 gen_op_check_align_T0_3();
3084 - gen_op_movl_npc_T0(); 2957 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
3085 dc->npc = DYNAMIC_PC; 2958 dc->npc = DYNAMIC_PC;
3086 - gen_op_rett(); 2959 + tcg_gen_helper_0_0(helper_rett);
3087 } 2960 }
3088 goto jmp_insn; 2961 goto jmp_insn;
3089 #endif 2962 #endif
3090 case 0x3b: /* flush */ 2963 case 0x3b: /* flush */
3091 - gen_op_flush_T0(); 2964 + tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
3092 break; 2965 break;
3093 case 0x3c: /* save */ 2966 case 0x3c: /* save */
3094 save_state(dc); 2967 save_state(dc);
@@ -3109,14 +2982,14 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3109,14 +2982,14 @@ static void disas_sparc_insn(DisasContext * dc)
3109 goto priv_insn; 2982 goto priv_insn;
3110 dc->npc = DYNAMIC_PC; 2983 dc->npc = DYNAMIC_PC;
3111 dc->pc = DYNAMIC_PC; 2984 dc->pc = DYNAMIC_PC;
3112 - gen_op_done(); 2985 + tcg_gen_helper_0_0(helper_done);
3113 goto jmp_insn; 2986 goto jmp_insn;
3114 case 1: 2987 case 1:
3115 if (!supervisor(dc)) 2988 if (!supervisor(dc))
3116 goto priv_insn; 2989 goto priv_insn;
3117 dc->npc = DYNAMIC_PC; 2990 dc->npc = DYNAMIC_PC;
3118 dc->pc = DYNAMIC_PC; 2991 dc->pc = DYNAMIC_PC;
3119 - gen_op_retry(); 2992 + tcg_gen_helper_0_0(helper_retry);
3120 goto jmp_insn; 2993 goto jmp_insn;
3121 default: 2994 default:
3122 goto illegal_insn; 2995 goto illegal_insn;
@@ -3144,14 +3017,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3144,14 +3017,7 @@ static void disas_sparc_insn(DisasContext * dc)
3144 } 3017 }
3145 else if (IS_IMM) { /* immediate */ 3018 else if (IS_IMM) { /* immediate */
3146 rs2 = GET_FIELDs(insn, 19, 31); 3019 rs2 = GET_FIELDs(insn, 19, 31);
3147 -#if defined(OPTIM)  
3148 - if (rs2 != 0) {  
3149 -#endif  
3150 - gen_movl_simm_T1(rs2);  
3151 - gen_op_add_T1_T0();  
3152 -#if defined(OPTIM)  
3153 - }  
3154 -#endif 3020 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
3155 } else { /* register */ 3021 } else { /* register */
3156 rs2 = GET_FIELD(insn, 27, 31); 3022 rs2 = GET_FIELD(insn, 27, 31);
3157 #if defined(OPTIM) 3023 #if defined(OPTIM)
@@ -3167,42 +3033,58 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3167,42 +3033,58 @@ static void disas_sparc_insn(DisasContext * dc)
3167 (xop > 0x17 && xop <= 0x1d ) || 3033 (xop > 0x17 && xop <= 0x1d ) ||
3168 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { 3034 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
3169 switch (xop) { 3035 switch (xop) {
3170 - case 0x0: /* load word */ 3036 + case 0x0: /* load unsigned word */
3171 gen_op_check_align_T0_3(); 3037 gen_op_check_align_T0_3();
3172 -#ifndef TARGET_SPARC64  
3173 - gen_op_ldst(ld);  
3174 -#else  
3175 - gen_op_ldst(lduw);  
3176 -#endif 3038 + ABI32_MASK(cpu_T[0]);
  3039 + tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx);
3177 break; 3040 break;
3178 case 0x1: /* load unsigned byte */ 3041 case 0x1: /* load unsigned byte */
3179 - gen_op_ldst(ldub); 3042 + ABI32_MASK(cpu_T[0]);
  3043 + tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx);
3180 break; 3044 break;
3181 case 0x2: /* load unsigned halfword */ 3045 case 0x2: /* load unsigned halfword */
3182 gen_op_check_align_T0_1(); 3046 gen_op_check_align_T0_1();
3183 - gen_op_ldst(lduh); 3047 + ABI32_MASK(cpu_T[0]);
  3048 + tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx);
3184 break; 3049 break;
3185 case 0x3: /* load double word */ 3050 case 0x3: /* load double word */
3186 if (rd & 1) 3051 if (rd & 1)
3187 goto illegal_insn; 3052 goto illegal_insn;
3188 - gen_op_check_align_T0_7();  
3189 - gen_op_ldst(ldd);  
3190 - gen_movl_T0_reg(rd + 1); 3053 + else {
  3054 + TCGv r_dword;
  3055 +
  3056 + r_dword = tcg_temp_new(TCG_TYPE_I64);
  3057 + gen_op_check_align_T0_7();
  3058 + ABI32_MASK(cpu_T[0]);
  3059 + tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
  3060 + tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
  3061 + gen_movl_T0_reg(rd + 1);
  3062 + tcg_gen_shri_i64(r_dword, r_dword, 32);
  3063 + tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
  3064 + }
3191 break; 3065 break;
3192 case 0x9: /* load signed byte */ 3066 case 0x9: /* load signed byte */
3193 - gen_op_ldst(ldsb); 3067 + ABI32_MASK(cpu_T[0]);
  3068 + tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
3194 break; 3069 break;
3195 case 0xa: /* load signed halfword */ 3070 case 0xa: /* load signed halfword */
3196 gen_op_check_align_T0_1(); 3071 gen_op_check_align_T0_1();
3197 - gen_op_ldst(ldsh); 3072 + ABI32_MASK(cpu_T[0]);
  3073 + tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
3198 break; 3074 break;
3199 case 0xd: /* ldstub -- XXX: should be atomically */ 3075 case 0xd: /* ldstub -- XXX: should be atomically */
3200 - gen_op_ldst(ldstub); 3076 + tcg_gen_movi_i32(cpu_tmp0, 0xff);
  3077 + ABI32_MASK(cpu_T[0]);
  3078 + tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
  3079 + tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
3201 break; 3080 break;
3202 case 0x0f: /* swap register with memory. Also atomically */ 3081 case 0x0f: /* swap register with memory. Also atomically */
3203 gen_op_check_align_T0_3(); 3082 gen_op_check_align_T0_3();
3204 gen_movl_reg_T1(rd); 3083 gen_movl_reg_T1(rd);
3205 - gen_op_ldst(swap); 3084 + ABI32_MASK(cpu_T[0]);
  3085 + tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
  3086 + tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
  3087 + tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
3206 break; 3088 break;
3207 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 3089 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3208 case 0x10: /* load word alternate */ 3090 case 0x10: /* load word alternate */
@@ -3297,11 +3179,13 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3297,11 +3179,13 @@ static void disas_sparc_insn(DisasContext * dc)
3297 #ifdef TARGET_SPARC64 3179 #ifdef TARGET_SPARC64
3298 case 0x08: /* V9 ldsw */ 3180 case 0x08: /* V9 ldsw */
3299 gen_op_check_align_T0_3(); 3181 gen_op_check_align_T0_3();
3300 - gen_op_ldst(ldsw); 3182 + ABI32_MASK(cpu_T[0]);
  3183 + tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx);
3301 break; 3184 break;
3302 case 0x0b: /* V9 ldx */ 3185 case 0x0b: /* V9 ldx */
3303 gen_op_check_align_T0_7(); 3186 gen_op_check_align_T0_7();
3304 - gen_op_ldst(ldx); 3187 + ABI32_MASK(cpu_T[0]);
  3188 + tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx);
3305 break; 3189 break;
3306 case 0x18: /* V9 ldswa */ 3190 case 0x18: /* V9 ldswa */
3307 gen_op_check_align_T0_3(); 3191 gen_op_check_align_T0_3();
@@ -3374,27 +3258,37 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3374,27 +3258,37 @@ static void disas_sparc_insn(DisasContext * dc)
3374 xop == 0xe || xop == 0x1e) { 3258 xop == 0xe || xop == 0x1e) {
3375 gen_movl_reg_T1(rd); 3259 gen_movl_reg_T1(rd);
3376 switch (xop) { 3260 switch (xop) {
3377 - case 0x4: 3261 + case 0x4: /* store word */
3378 gen_op_check_align_T0_3(); 3262 gen_op_check_align_T0_3();
3379 - gen_op_ldst(st); 3263 + ABI32_MASK(cpu_T[0]);
  3264 + tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
3380 break; 3265 break;
3381 - case 0x5:  
3382 - gen_op_ldst(stb); 3266 + case 0x5: /* store byte */
  3267 + ABI32_MASK(cpu_T[0]);
  3268 + tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx);
3383 break; 3269 break;
3384 - case 0x6: 3270 + case 0x6: /* store halfword */
3385 gen_op_check_align_T0_1(); 3271 gen_op_check_align_T0_1();
3386 - gen_op_ldst(sth); 3272 + ABI32_MASK(cpu_T[0]);
  3273 + tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx);
3387 break; 3274 break;
3388 - case 0x7: 3275 + case 0x7: /* store double word */
3389 if (rd & 1) 3276 if (rd & 1)
3390 goto illegal_insn; 3277 goto illegal_insn;
3391 - gen_op_check_align_T0_7();  
3392 - flush_T2(dc);  
3393 - gen_movl_reg_T2(rd + 1);  
3394 - gen_op_ldst(std); 3278 + else {
  3279 + TCGv r_dword, r_low;
  3280 +
  3281 + gen_op_check_align_T0_7();
  3282 + r_dword = tcg_temp_new(TCG_TYPE_I64);
  3283 + r_low = tcg_temp_new(TCG_TYPE_I32);
  3284 + gen_movl_reg_TN(rd + 1, r_low);
  3285 + tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
  3286 + r_low);
  3287 + tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
  3288 + }
3395 break; 3289 break;
3396 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 3290 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3397 - case 0x14: 3291 + case 0x14: /* store word alternate */
3398 #ifndef TARGET_SPARC64 3292 #ifndef TARGET_SPARC64
3399 if (IS_IMM) 3293 if (IS_IMM)
3400 goto illegal_insn; 3294 goto illegal_insn;
@@ -3404,7 +3298,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3404,7 +3298,7 @@ static void disas_sparc_insn(DisasContext * dc)
3404 gen_op_check_align_T0_3(); 3298 gen_op_check_align_T0_3();
3405 gen_st_asi(insn, 4); 3299 gen_st_asi(insn, 4);
3406 break; 3300 break;
3407 - case 0x15: 3301 + case 0x15: /* store byte alternate */
3408 #ifndef TARGET_SPARC64 3302 #ifndef TARGET_SPARC64
3409 if (IS_IMM) 3303 if (IS_IMM)
3410 goto illegal_insn; 3304 goto illegal_insn;
@@ -3413,7 +3307,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3413,7 +3307,7 @@ static void disas_sparc_insn(DisasContext * dc)
3413 #endif 3307 #endif
3414 gen_st_asi(insn, 1); 3308 gen_st_asi(insn, 1);
3415 break; 3309 break;
3416 - case 0x16: 3310 + case 0x16: /* store halfword alternate */
3417 #ifndef TARGET_SPARC64 3311 #ifndef TARGET_SPARC64
3418 if (IS_IMM) 3312 if (IS_IMM)
3419 goto illegal_insn; 3313 goto illegal_insn;
@@ -3423,7 +3317,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3423,7 +3317,7 @@ static void disas_sparc_insn(DisasContext * dc)
3423 gen_op_check_align_T0_1(); 3317 gen_op_check_align_T0_1();
3424 gen_st_asi(insn, 2); 3318 gen_st_asi(insn, 2);
3425 break; 3319 break;
3426 - case 0x17: 3320 + case 0x17: /* store double word alternate */
3427 #ifndef TARGET_SPARC64 3321 #ifndef TARGET_SPARC64
3428 if (IS_IMM) 3322 if (IS_IMM)
3429 goto illegal_insn; 3323 goto illegal_insn;
@@ -3432,16 +3326,41 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3432,16 +3326,41 @@ static void disas_sparc_insn(DisasContext * dc)
3432 #endif 3326 #endif
3433 if (rd & 1) 3327 if (rd & 1)
3434 goto illegal_insn; 3328 goto illegal_insn;
3435 - gen_op_check_align_T0_7();  
3436 - flush_T2(dc);  
3437 - gen_movl_reg_T2(rd + 1);  
3438 - gen_stda_asi(insn); 3329 + else {
  3330 + int asi;
  3331 + TCGv r_dword, r_temp, r_size;
  3332 +
  3333 + gen_op_check_align_T0_7();
  3334 + r_dword = tcg_temp_new(TCG_TYPE_I64);
  3335 + r_temp = tcg_temp_new(TCG_TYPE_I32);
  3336 + r_size = tcg_temp_new(TCG_TYPE_I32);
  3337 + gen_movl_reg_TN(rd + 1, r_temp);
  3338 + tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
  3339 + r_temp);
  3340 +#ifdef TARGET_SPARC64
  3341 + if (IS_IMM) {
  3342 + int offset;
  3343 +
  3344 + offset = GET_FIELD(insn, 25, 31);
  3345 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
  3346 + tcg_gen_ld_i32(r_dword, cpu_env, offsetof(CPUSPARCState, asi));
  3347 + } else {
  3348 +#endif
  3349 + asi = GET_FIELD(insn, 19, 26);
  3350 + tcg_gen_movi_i32(r_temp, asi);
  3351 +#ifdef TARGET_SPARC64
  3352 + }
  3353 +#endif
  3354 + tcg_gen_movi_i32(r_size, 8);
  3355 + tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_temp, r_size);
  3356 + }
3439 break; 3357 break;
3440 #endif 3358 #endif
3441 #ifdef TARGET_SPARC64 3359 #ifdef TARGET_SPARC64
3442 case 0x0e: /* V9 stx */ 3360 case 0x0e: /* V9 stx */
3443 gen_op_check_align_T0_7(); 3361 gen_op_check_align_T0_7();
3444 - gen_op_ldst(stx); 3362 + ABI32_MASK(cpu_T[0]);
  3363 + tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx);
3445 break; 3364 break;
3446 case 0x1e: /* V9 stxa */ 3365 case 0x1e: /* V9 stxa */
3447 gen_op_check_align_T0_7(); 3366 gen_op_check_align_T0_7();
@@ -3522,16 +3441,12 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3522,16 +3441,12 @@ static void disas_sparc_insn(DisasContext * dc)
3522 break; 3441 break;
3523 case 0x3c: /* V9 casa */ 3442 case 0x3c: /* V9 casa */
3524 gen_op_check_align_T0_3(); 3443 gen_op_check_align_T0_3();
3525 - flush_T2(dc);  
3526 - gen_movl_reg_T2(rd);  
3527 - gen_cas_asi(insn); 3444 + gen_cas_asi(insn, rd);
3528 gen_movl_T1_reg(rd); 3445 gen_movl_T1_reg(rd);
3529 break; 3446 break;
3530 case 0x3e: /* V9 casxa */ 3447 case 0x3e: /* V9 casxa */
3531 gen_op_check_align_T0_7(); 3448 gen_op_check_align_T0_7();
3532 - flush_T2(dc);  
3533 - gen_movl_reg_T2(rd);  
3534 - gen_casx_asi(insn); 3449 + gen_casx_asi(insn, rd);
3535 gen_movl_T1_reg(rd); 3450 gen_movl_T1_reg(rd);
3536 break; 3451 break;
3537 #else 3452 #else
@@ -3597,6 +3512,10 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3597,6 +3512,10 @@ static void disas_sparc_insn(DisasContext * dc)
3597 #endif 3512 #endif
3598 } 3513 }
3599 3514
  3515 +static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
  3516 +{
  3517 +}
  3518 +
3600 static inline int gen_intermediate_code_internal(TranslationBlock * tb, 3519 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3601 int spc, CPUSPARCState *env) 3520 int spc, CPUSPARCState *env)
3602 { 3521 {
@@ -3615,13 +3534,16 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb, @@ -3615,13 +3534,16 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3615 dc->fpu_enabled = cpu_fpu_enabled(env); 3534 dc->fpu_enabled = cpu_fpu_enabled(env);
3616 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; 3535 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3617 3536
  3537 + cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
  3538 + cpu_regwptr = tcg_temp_new(TCG_TYPE_PTR); // XXX
  3539 +
3618 do { 3540 do {
3619 if (env->nb_breakpoints > 0) { 3541 if (env->nb_breakpoints > 0) {
3620 for(j = 0; j < env->nb_breakpoints; j++) { 3542 for(j = 0; j < env->nb_breakpoints; j++) {
3621 if (env->breakpoints[j] == dc->pc) { 3543 if (env->breakpoints[j] == dc->pc) {
3622 if (dc->pc != pc_start) 3544 if (dc->pc != pc_start)
3623 save_state(dc); 3545 save_state(dc);
3624 - gen_op_debug(); 3546 + tcg_gen_helper_0_0(helper_debug);
3625 tcg_gen_exit_tb(0); 3547 tcg_gen_exit_tb(0);
3626 dc->is_br = 1; 3548 dc->is_br = 1;
3627 goto exit_gen_loop; 3549 goto exit_gen_loop;
@@ -3748,6 +3670,7 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model) @@ -3748,6 +3670,7 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model)
3748 { 3670 {
3749 CPUSPARCState *env; 3671 CPUSPARCState *env;
3750 const sparc_def_t *def; 3672 const sparc_def_t *def;
  3673 + static int inited;
3751 3674
3752 def = cpu_sparc_find_by_name(cpu_model); 3675 def = cpu_sparc_find_by_name(cpu_model);
3753 if (!def) 3676 if (!def)
@@ -3769,6 +3692,28 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model) @@ -3769,6 +3692,28 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model)
3769 env->mmuregs[0] |= def->mmu_version; 3692 env->mmuregs[0] |= def->mmu_version;
3770 cpu_sparc_set_id(env, 0); 3693 cpu_sparc_set_id(env, 0);
3771 #endif 3694 #endif
  3695 +
  3696 + /* init various static tables */
  3697 + if (!inited) {
  3698 + inited = 1;
  3699 +
  3700 + tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
  3701 + cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
  3702 + //#if TARGET_LONG_BITS > HOST_LONG_BITS
  3703 +#ifdef TARGET_SPARC64
  3704 + cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
  3705 + TCG_AREG0, offsetof(CPUState, t0), "T0");
  3706 + cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
  3707 + TCG_AREG0, offsetof(CPUState, t1), "T1");
  3708 + cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
  3709 + TCG_AREG0, offsetof(CPUState, t2), "T2");
  3710 +#else
  3711 + cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
  3712 + cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
  3713 + cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
  3714 +#endif
  3715 + }
  3716 +
3772 cpu_reset(env); 3717 cpu_reset(env);
3773 3718
3774 return env; 3719 return env;