gwj / at91sam9263 · Commits

Commit 0f8a249a0ba252d7ff61410791712ae9b3449063

Authored by blueswir1
1 parent 2e03286b

Detabify 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3195 c046a42c-6fe2-441c-8c8c-71466251a162
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target-sparc/cpu.h
  View file @0f8a249
... ... @@ -22,9 +22,9 @@
22 22 #define TARGET_HAS_ICE 1
23 23  
24 24 #if !defined(TARGET_SPARC64)
25   -#define ELF_MACHINE EM_SPARC
  25 +#define ELF_MACHINE EM_SPARC
26 26 #else
27   -#define ELF_MACHINE EM_SPARCV9
  27 +#define ELF_MACHINE EM_SPARCV9
28 28 #endif
29 29  
30 30 /*#define EXCP_INTERRUPT 0x100*/
... ... @@ -143,8 +143,8 @@
143 143 #define FSR_FCC0 (1<<10)
144 144  
145 145 /* MMU */
146   -#define MMU_E (1<<0)
147   -#define MMU_NF (1<<1)
  146 +#define MMU_E (1<<0)
  147 +#define MMU_NF (1<<1)
148 148  
149 149 #define PTE_ENTRYTYPE_MASK 3
150 150 #define PTE_ACCESS_MASK 0x1c
... ... @@ -152,8 +152,8 @@
152 152 #define PTE_PPN_SHIFT 7
153 153 #define PTE_ADDR_MASK 0xffffff00
154 154  
155   -#define PG_ACCESSED_BIT 5
156   -#define PG_MODIFIED_BIT 6
  155 +#define PG_ACCESSED_BIT 5
  156 +#define PG_MODIFIED_BIT 6
157 157 #define PG_CACHE_BIT 7
158 158  
159 159 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
... ... @@ -221,7 +221,7 @@ typedef struct CPUSPARCState {
221 221 uint64_t tnpc[MAXTL];
222 222 uint64_t tstate[MAXTL];
223 223 uint32_t tt[MAXTL];
224   - uint32_t xcc; /* Extended integer condition codes */
  224 + uint32_t xcc; /* Extended integer condition codes */
225 225 uint32_t asi;
226 226 uint32_t pstate;
227 227 uint32_t tl;
... ... @@ -245,12 +245,12 @@ typedef struct CPUSPARCState {
245 245 } CPUSPARCState;
246 246 #if defined(TARGET_SPARC64)
247 247 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
248   -#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
249   - env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
  248 +#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
  249 + env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
250 250 } while (0)
251 251 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
252   -#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
253   - env->fsr = _tmp & 0x3fcfc1c3ffULL; \
  252 +#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
  253 + env->fsr = _tmp & 0x3fcfc1c3ffULL; \
254 254 } while (0)
255 255 #else
256 256 #define GET_FSR32(env) (env->fsr)
... ... @@ -268,31 +268,31 @@ void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
268 268 int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def);
269 269  
270 270 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
271   - (env->psref? PSR_EF : 0) | \
272   - (env->psrpil << 8) | \
273   - (env->psrs? PSR_S : 0) | \
274   - (env->psrps? PSR_PS : 0) | \
275   - (env->psret? PSR_ET : 0) | env->cwp)
  271 + (env->psref? PSR_EF : 0) | \
  272 + (env->psrpil << 8) | \
  273 + (env->psrs? PSR_S : 0) | \
  274 + (env->psrps? PSR_PS : 0) | \
  275 + (env->psret? PSR_ET : 0) | env->cwp)
276 276  
277 277 #ifndef NO_CPU_IO_DEFS
278 278 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
279 279 #endif
280 280  
281   -#define PUT_PSR(env, val) do { int _tmp = val; \
282   - env->psr = _tmp & PSR_ICC; \
283   - env->psref = (_tmp & PSR_EF)? 1 : 0; \
284   - env->psrpil = (_tmp & PSR_PIL) >> 8; \
285   - env->psrs = (_tmp & PSR_S)? 1 : 0; \
286   - env->psrps = (_tmp & PSR_PS)? 1 : 0; \
287   - env->psret = (_tmp & PSR_ET)? 1 : 0; \
  281 +#define PUT_PSR(env, val) do { int _tmp = val; \
  282 + env->psr = _tmp & PSR_ICC; \
  283 + env->psref = (_tmp & PSR_EF)? 1 : 0; \
  284 + env->psrpil = (_tmp & PSR_PIL) >> 8; \
  285 + env->psrs = (_tmp & PSR_S)? 1 : 0; \
  286 + env->psrps = (_tmp & PSR_PS)? 1 : 0; \
  287 + env->psret = (_tmp & PSR_ET)? 1 : 0; \
288 288 cpu_set_cwp(env, _tmp & PSR_CWP); \
289 289 } while (0)
290 290  
291 291 #ifdef TARGET_SPARC64
292 292 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
293   -#define PUT_CCR(env, val) do { int _tmp = val; \
294   - env->xcc = (_tmp >> 4) << 20; \
295   - env->psr = (_tmp & 0xf) << 20; \
  293 +#define PUT_CCR(env, val) do { int _tmp = val; \
  294 + env->xcc = (_tmp >> 4) << 20; \
  295 + env->psr = (_tmp & 0xf) << 20; \
296 296 } while (0)
297 297 #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
298 298 #define PUT_CWP64(env, val) \
... ...
target-sparc/helper.c
  View file @0f8a249
... ... @@ -99,8 +99,8 @@ static const int perm_table[2][8] = {
99 99 };
100 100  
101 101 int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
102   - int *access_index, target_ulong address, int rw,
103   - int is_user)
  102 + int *access_index, target_ulong address, int rw,
  103 + int is_user)
104 104 {
105 105 int access_perms = 0;
106 106 target_phys_addr_t pde_ptr;
... ... @@ -111,7 +111,7 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
111 111  
112 112 virt_addr = address & TARGET_PAGE_MASK;
113 113 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
114   - *physical = address;
  114 + *physical = address;
115 115 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
116 116 return 0;
117 117 }
... ... @@ -128,70 +128,70 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
128 128 switch (pde & PTE_ENTRYTYPE_MASK) {
129 129 default:
130 130 case 0: /* Invalid */
131   - return 1 << 2;
  131 + return 1 << 2;
132 132 case 2: /* L0 PTE, maybe should not happen? */
133 133 case 3: /* Reserved */
134 134 return 4 << 2;
135 135 case 1: /* L0 PDE */
136   - pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
  136 + pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
137 137 pde = ldl_phys(pde_ptr);
138 138  
139   - switch (pde & PTE_ENTRYTYPE_MASK) {
140   - default:
141   - case 0: /* Invalid */
142   - return (1 << 8) | (1 << 2);
143   - case 3: /* Reserved */
144   - return (1 << 8) | (4 << 2);
145   - case 1: /* L1 PDE */
146   - pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
  139 + switch (pde & PTE_ENTRYTYPE_MASK) {
  140 + default:
  141 + case 0: /* Invalid */
  142 + return (1 << 8) | (1 << 2);
  143 + case 3: /* Reserved */
  144 + return (1 << 8) | (4 << 2);
  145 + case 1: /* L1 PDE */
  146 + pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
147 147 pde = ldl_phys(pde_ptr);
148 148  
149   - switch (pde & PTE_ENTRYTYPE_MASK) {
150   - default:
151   - case 0: /* Invalid */
152   - return (2 << 8) | (1 << 2);
153   - case 3: /* Reserved */
154   - return (2 << 8) | (4 << 2);
155   - case 1: /* L2 PDE */
156   - pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
  149 + switch (pde & PTE_ENTRYTYPE_MASK) {
  150 + default:
  151 + case 0: /* Invalid */
  152 + return (2 << 8) | (1 << 2);
  153 + case 3: /* Reserved */
  154 + return (2 << 8) | (4 << 2);
  155 + case 1: /* L2 PDE */
  156 + pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
157 157 pde = ldl_phys(pde_ptr);
158 158  
159   - switch (pde & PTE_ENTRYTYPE_MASK) {
160   - default:
161   - case 0: /* Invalid */
162   - return (3 << 8) | (1 << 2);
163   - case 1: /* PDE, should not happen */
164   - case 3: /* Reserved */
165   - return (3 << 8) | (4 << 2);
166   - case 2: /* L3 PTE */
167   - virt_addr = address & TARGET_PAGE_MASK;
168   - page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
169   - }
170   - break;
171   - case 2: /* L2 PTE */
172   - virt_addr = address & ~0x3ffff;
173   - page_offset = address & 0x3ffff;
174   - }
175   - break;
176   - case 2: /* L1 PTE */
177   - virt_addr = address & ~0xffffff;
178   - page_offset = address & 0xffffff;
179   - }
  159 + switch (pde & PTE_ENTRYTYPE_MASK) {
  160 + default:
  161 + case 0: /* Invalid */
  162 + return (3 << 8) | (1 << 2);
  163 + case 1: /* PDE, should not happen */
  164 + case 3: /* Reserved */
  165 + return (3 << 8) | (4 << 2);
  166 + case 2: /* L3 PTE */
  167 + virt_addr = address & TARGET_PAGE_MASK;
  168 + page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
  169 + }
  170 + break;
  171 + case 2: /* L2 PTE */
  172 + virt_addr = address & ~0x3ffff;
  173 + page_offset = address & 0x3ffff;
  174 + }
  175 + break;
  176 + case 2: /* L1 PTE */
  177 + virt_addr = address & ~0xffffff;
  178 + page_offset = address & 0xffffff;
  179 + }
180 180 }
181 181  
182 182 /* update page modified and dirty bits */
183 183 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
184 184 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
185   - pde |= PG_ACCESSED_MASK;
186   - if (is_dirty)
187   - pde |= PG_MODIFIED_MASK;
  185 + pde |= PG_ACCESSED_MASK;
  186 + if (is_dirty)
  187 + pde |= PG_MODIFIED_MASK;
188 188 stl_phys_notdirty(pde_ptr, pde);
189 189 }
190 190 /* check access */
191 191 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
192 192 error_code = access_table[*access_index][access_perms];
193 193 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
194   - return error_code;
  194 + return error_code;
195 195  
196 196 /* the page can be put in the TLB */
197 197 *prot = perm_table[is_user][access_perms];
... ... @@ -217,18 +217,18 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
217 217  
218 218 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
219 219 if (error_code == 0) {
220   - vaddr = address & TARGET_PAGE_MASK;
221   - paddr &= TARGET_PAGE_MASK;
  220 + vaddr = address & TARGET_PAGE_MASK;
  221 + paddr &= TARGET_PAGE_MASK;
222 222 #ifdef DEBUG_MMU
223   - printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
  223 + printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
224 224 TARGET_FMT_lx "\n", address, paddr, vaddr);
225 225 #endif
226   - ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
227   - return ret;
  226 + ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
  227 + return ret;
228 228 }
229 229  
230 230 if (env->mmuregs[3]) /* Fault status register */
231   - env->mmuregs[3] = 1; /* overflow (not read before another fault) */
  231 + env->mmuregs[3] = 1; /* overflow (not read before another fault) */
232 232 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
233 233 env->mmuregs[4] = address; /* Fault address register */
234 234  
... ... @@ -237,10 +237,10 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
237 237 // permissions. If no mapping is available, redirect accesses to
238 238 // neverland. Fake/overridden mappings will be flushed when
239 239 // switching to normal mode.
240   - vaddr = address & TARGET_PAGE_MASK;
  240 + vaddr = address & TARGET_PAGE_MASK;
241 241 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
242 242 ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
243   - return ret;
  243 + return ret;
244 244 } else {
245 245 if (rw & 2)
246 246 env->exception_index = TT_TFAULT;
... ... @@ -265,50 +265,50 @@ target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
265 265 case 0: /* Invalid */
266 266 case 2: /* PTE, maybe should not happen? */
267 267 case 3: /* Reserved */
268   - return 0;
  268 + return 0;
269 269 case 1: /* L1 PDE */
270   - if (mmulev == 3)
271   - return pde;
272   - pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
  270 + if (mmulev == 3)
  271 + return pde;
  272 + pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
273 273 pde = ldl_phys(pde_ptr);
274 274  
275   - switch (pde & PTE_ENTRYTYPE_MASK) {
276   - default:
277   - case 0: /* Invalid */
278   - case 3: /* Reserved */
279   - return 0;
280   - case 2: /* L1 PTE */
281   - return pde;
282   - case 1: /* L2 PDE */
283   - if (mmulev == 2)
284   - return pde;
285   - pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
  275 + switch (pde & PTE_ENTRYTYPE_MASK) {
  276 + default:
  277 + case 0: /* Invalid */
  278 + case 3: /* Reserved */
  279 + return 0;
  280 + case 2: /* L1 PTE */
  281 + return pde;
  282 + case 1: /* L2 PDE */
  283 + if (mmulev == 2)
  284 + return pde;
  285 + pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
286 286 pde = ldl_phys(pde_ptr);
287 287  
288   - switch (pde & PTE_ENTRYTYPE_MASK) {
289   - default:
290   - case 0: /* Invalid */
291   - case 3: /* Reserved */
292   - return 0;
293   - case 2: /* L2 PTE */
294   - return pde;
295   - case 1: /* L3 PDE */
296   - if (mmulev == 1)
297   - return pde;
298   - pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
  288 + switch (pde & PTE_ENTRYTYPE_MASK) {
  289 + default:
  290 + case 0: /* Invalid */
  291 + case 3: /* Reserved */
  292 + return 0;
  293 + case 2: /* L2 PTE */
  294 + return pde;
  295 + case 1: /* L3 PDE */
  296 + if (mmulev == 1)
  297 + return pde;
  298 + pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
299 299 pde = ldl_phys(pde_ptr);
300 300  
301   - switch (pde & PTE_ENTRYTYPE_MASK) {
302   - default:
303   - case 0: /* Invalid */
304   - case 1: /* PDE, should not happen */
305   - case 3: /* Reserved */
306   - return 0;
307   - case 2: /* L3 PTE */
308   - return pde;
309   - }
310   - }
311   - }
  301 + switch (pde & PTE_ENTRYTYPE_MASK) {
  302 + default:
  303 + case 0: /* Invalid */
  304 + case 1: /* PDE, should not happen */
  305 + case 3: /* Reserved */
  306 + return 0;
  307 + case 2: /* L3 PTE */
  308 + return pde;
  309 + }
  310 + }
  311 + }
312 312 }
313 313 return 0;
314 314 }
... ... @@ -327,29 +327,29 @@ void dump_mmu(CPUState *env)
327 327 printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
328 328 (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
329 329 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
330   - pde = mmu_probe(env, va, 2);
331   - if (pde) {
332   - pa = cpu_get_phys_page_debug(env, va);
333   - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
  330 + pde = mmu_probe(env, va, 2);
  331 + if (pde) {
  332 + pa = cpu_get_phys_page_debug(env, va);
  333 + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
334 334 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
335   - for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
336   - pde = mmu_probe(env, va1, 1);
337   - if (pde) {
338   - pa = cpu_get_phys_page_debug(env, va1);
339   - printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
  335 + for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
  336 + pde = mmu_probe(env, va1, 1);
  337 + if (pde) {
  338 + pa = cpu_get_phys_page_debug(env, va1);
  339 + printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
340 340 " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
341   - for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
342   - pde = mmu_probe(env, va2, 0);
343   - if (pde) {
344   - pa = cpu_get_phys_page_debug(env, va2);
345   - printf(" VA: " TARGET_FMT_lx ", PA: "
  341 + for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
  342 + pde = mmu_probe(env, va2, 0);
  343 + if (pde) {
  344 + pa = cpu_get_phys_page_debug(env, va2);
  345 + printf(" VA: " TARGET_FMT_lx ", PA: "
346 346 TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
347 347 va2, pa, pde);
348   - }
349   - }
350   - }
351   - }
352   - }
  348 + }
  349 + }
  350 + }
  351 + }
  352 + }
353 353 }
354 354 printf("MMU dump ends\n");
355 355 }
... ... @@ -360,57 +360,57 @@ void dump_mmu(CPUState *env)
360 360 * UltraSparc IIi I/DMMUs
361 361 */
362 362 static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
363   - int *access_index, target_ulong address, int rw,
364   - int is_user)
  363 + int *access_index, target_ulong address, int rw,
  364 + int is_user)
365 365 {
366 366 target_ulong mask;
367 367 unsigned int i;
368 368  
369 369 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
370   - *physical = address;
371   - *prot = PAGE_READ | PAGE_WRITE;
  370 + *physical = address;
  371 + *prot = PAGE_READ | PAGE_WRITE;
372 372 return 0;
373 373 }
374 374  
375 375 for (i = 0; i < 64; i++) {
376   - switch ((env->dtlb_tte[i] >> 61) & 3) {
377   - default:
378   - case 0x0: // 8k
379   - mask = 0xffffffffffffe000ULL;
380   - break;
381   - case 0x1: // 64k
382   - mask = 0xffffffffffff0000ULL;
383   - break;
384   - case 0x2: // 512k
385   - mask = 0xfffffffffff80000ULL;
386   - break;
387   - case 0x3: // 4M
388   - mask = 0xffffffffffc00000ULL;
389   - break;
390   - }
391   - // ctx match, vaddr match?
392   - if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
393   - (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
394   - // valid, access ok?
395   - if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
396   - ((env->dtlb_tte[i] & 0x4) && is_user) ||
397   - (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
398   - if (env->dmmuregs[3]) /* Fault status register */
399   - env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
400   - env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
401   - env->dmmuregs[4] = address; /* Fault address register */
402   - env->exception_index = TT_DFAULT;
  376 + switch ((env->dtlb_tte[i] >> 61) & 3) {
  377 + default:
  378 + case 0x0: // 8k
  379 + mask = 0xffffffffffffe000ULL;
  380 + break;
  381 + case 0x1: // 64k
  382 + mask = 0xffffffffffff0000ULL;
  383 + break;
  384 + case 0x2: // 512k
  385 + mask = 0xfffffffffff80000ULL;
  386 + break;
  387 + case 0x3: // 4M
  388 + mask = 0xffffffffffc00000ULL;
  389 + break;
  390 + }
  391 + // ctx match, vaddr match?
  392 + if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
  393 + (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
  394 + // valid, access ok?
  395 + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
  396 + ((env->dtlb_tte[i] & 0x4) && is_user) ||
  397 + (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
  398 + if (env->dmmuregs[3]) /* Fault status register */
  399 + env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
  400 + env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
  401 + env->dmmuregs[4] = address; /* Fault address register */
  402 + env->exception_index = TT_DFAULT;
403 403 #ifdef DEBUG_MMU
404   - printf("DFAULT at 0x%" PRIx64 "\n", address);
  404 + printf("DFAULT at 0x%" PRIx64 "\n", address);
405 405 #endif
406   - return 1;
407   - }
408   - *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
409   - *prot = PAGE_READ;
410   - if (env->dtlb_tte[i] & 0x2)
411   - *prot |= PAGE_WRITE;
412   - return 0;
413   - }
  406 + return 1;
  407 + }
  408 + *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
  409 + *prot = PAGE_READ;
  410 + if (env->dtlb_tte[i] & 0x2)
  411 + *prot |= PAGE_WRITE;
  412 + return 0;
  413 + }
414 414 }
415 415 #ifdef DEBUG_MMU
416 416 printf("DMISS at 0x%" PRIx64 "\n", address);
... ... @@ -420,53 +420,53 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
420 420 }
421 421  
422 422 static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
423   - int *access_index, target_ulong address, int rw,
424   - int is_user)
  423 + int *access_index, target_ulong address, int rw,
  424 + int is_user)
425 425 {
426 426 target_ulong mask;
427 427 unsigned int i;
428 428  
429 429 if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
430   - *physical = address;
431   - *prot = PAGE_EXEC;
  430 + *physical = address;
  431 + *prot = PAGE_EXEC;
432 432 return 0;
433 433 }
434 434  
435 435 for (i = 0; i < 64; i++) {
436   - switch ((env->itlb_tte[i] >> 61) & 3) {
437   - default:
438   - case 0x0: // 8k
439   - mask = 0xffffffffffffe000ULL;
440   - break;
441   - case 0x1: // 64k
442   - mask = 0xffffffffffff0000ULL;
443   - break;
444   - case 0x2: // 512k
445   - mask = 0xfffffffffff80000ULL;
446   - break;
447   - case 0x3: // 4M
448   - mask = 0xffffffffffc00000ULL;
449   - break;
450   - }
451   - // ctx match, vaddr match?
452   - if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
453   - (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
454   - // valid, access ok?
455   - if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
456   - ((env->itlb_tte[i] & 0x4) && is_user)) {
457   - if (env->immuregs[3]) /* Fault status register */
458   - env->immuregs[3] = 2; /* overflow (not read before another fault) */
459   - env->immuregs[3] |= (is_user << 3) | 1;
460   - env->exception_index = TT_TFAULT;
  436 + switch ((env->itlb_tte[i] >> 61) & 3) {
  437 + default:
  438 + case 0x0: // 8k
  439 + mask = 0xffffffffffffe000ULL;
  440 + break;
  441 + case 0x1: // 64k
  442 + mask = 0xffffffffffff0000ULL;
  443 + break;
  444 + case 0x2: // 512k
  445 + mask = 0xfffffffffff80000ULL;
  446 + break;
  447 + case 0x3: // 4M
  448 + mask = 0xffffffffffc00000ULL;
  449 + break;
  450 + }
  451 + // ctx match, vaddr match?
  452 + if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
  453 + (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
  454 + // valid, access ok?
  455 + if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
  456 + ((env->itlb_tte[i] & 0x4) && is_user)) {
  457 + if (env->immuregs[3]) /* Fault status register */
  458 + env->immuregs[3] = 2; /* overflow (not read before another fault) */
  459 + env->immuregs[3] |= (is_user << 3) | 1;
  460 + env->exception_index = TT_TFAULT;
461 461 #ifdef DEBUG_MMU
462   - printf("TFAULT at 0x%" PRIx64 "\n", address);
  462 + printf("TFAULT at 0x%" PRIx64 "\n", address);
463 463 #endif
464   - return 1;
465   - }
466   - *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
467   - *prot = PAGE_EXEC;
468   - return 0;
469   - }
  464 + return 1;
  465 + }
  466 + *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
  467 + *prot = PAGE_EXEC;
  468 + return 0;
  469 + }
470 470 }
471 471 #ifdef DEBUG_MMU
472 472 printf("TMISS at 0x%" PRIx64 "\n", address);
... ... @@ -476,13 +476,13 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical
476 476 }
477 477  
478 478 int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
479   - int *access_index, target_ulong address, int rw,
480   - int is_user)
  479 + int *access_index, target_ulong address, int rw,
  480 + int is_user)
481 481 {
482 482 if (rw == 2)
483   - return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
  483 + return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
484 484 else
485   - return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
  485 + return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
486 486 }
487 487  
488 488 /* Perform address translation */
... ... @@ -495,13 +495,13 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
495 495  
496 496 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
497 497 if (error_code == 0) {
498   - virt_addr = address & TARGET_PAGE_MASK;
499   - vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
  498 + virt_addr = address & TARGET_PAGE_MASK;
  499 + vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
500 500 #ifdef DEBUG_MMU
501   - printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
  501 + printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
502 502 #endif
503   - ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
504   - return ret;
  503 + ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
  504 + return ret;
505 505 }
506 506 // XXX
507 507 return 1;
... ... @@ -515,67 +515,67 @@ void dump_mmu(CPUState *env)
515 515  
516 516 printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
517 517 if ((env->lsu & DMMU_E) == 0) {
518   - printf("DMMU disabled\n");
  518 + printf("DMMU disabled\n");
519 519 } else {
520   - printf("DMMU dump:\n");
521   - for (i = 0; i < 64; i++) {
522   - switch ((env->dtlb_tte[i] >> 61) & 3) {
523   - default:
524   - case 0x0:
525   - mask = " 8k";
526   - break;
527   - case 0x1:
528   - mask = " 64k";
529   - break;
530   - case 0x2:
531   - mask = "512k";
532   - break;
533   - case 0x3:
534   - mask = " 4M";
535   - break;
536   - }
537   - if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
538   - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
539   - env->dtlb_tag[i] & ~0x1fffULL,
540   - env->dtlb_tte[i] & 0x1ffffffe000ULL,
541   - mask,
542   - env->dtlb_tte[i] & 0x4? "priv": "user",
543   - env->dtlb_tte[i] & 0x2? "RW": "RO",
544   - env->dtlb_tte[i] & 0x40? "locked": "unlocked",
545   - env->dtlb_tag[i] & 0x1fffULL);
546   - }
547   - }
  520 + printf("DMMU dump:\n");
  521 + for (i = 0; i < 64; i++) {
  522 + switch ((env->dtlb_tte[i] >> 61) & 3) {
  523 + default:
  524 + case 0x0:
  525 + mask = " 8k";
  526 + break;
  527 + case 0x1:
  528 + mask = " 64k";
  529 + break;
  530 + case 0x2:
  531 + mask = "512k";
  532 + break;
  533 + case 0x3:
  534 + mask = " 4M";
  535 + break;
  536 + }
  537 + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
  538 + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
  539 + env->dtlb_tag[i] & ~0x1fffULL,
  540 + env->dtlb_tte[i] & 0x1ffffffe000ULL,
  541 + mask,
  542 + env->dtlb_tte[i] & 0x4? "priv": "user",
  543 + env->dtlb_tte[i] & 0x2? "RW": "RO",
  544 + env->dtlb_tte[i] & 0x40? "locked": "unlocked",
  545 + env->dtlb_tag[i] & 0x1fffULL);
  546 + }
  547 + }
548 548 }
549 549 if ((env->lsu & IMMU_E) == 0) {
550   - printf("IMMU disabled\n");
  550 + printf("IMMU disabled\n");
551 551 } else {
552   - printf("IMMU dump:\n");
553   - for (i = 0; i < 64; i++) {
554   - switch ((env->itlb_tte[i] >> 61) & 3) {
555   - default:
556   - case 0x0:
557   - mask = " 8k";
558   - break;
559   - case 0x1:
560   - mask = " 64k";
561   - break;
562   - case 0x2:
563   - mask = "512k";
564   - break;
565   - case 0x3:
566   - mask = " 4M";
567   - break;
568   - }
569   - if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
570   - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
571   - env->itlb_tag[i] & ~0x1fffULL,
572   - env->itlb_tte[i] & 0x1ffffffe000ULL,
573   - mask,
574   - env->itlb_tte[i] & 0x4? "priv": "user",
575   - env->itlb_tte[i] & 0x40? "locked": "unlocked",
576   - env->itlb_tag[i] & 0x1fffULL);
577   - }
578   - }
  552 + printf("IMMU dump:\n");
  553 + for (i = 0; i < 64; i++) {
  554 + switch ((env->itlb_tte[i] >> 61) & 3) {
  555 + default:
  556 + case 0x0:
  557 + mask = " 8k";
  558 + break;
  559 + case 0x1:
  560 + mask = " 64k";
  561 + break;
  562 + case 0x2:
  563 + mask = "512k";
  564 + break;
  565 + case 0x3:
  566 + mask = " 4M";
  567 + break;
  568 + }
  569 + if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
  570 + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
  571 + env->itlb_tag[i] & ~0x1fffULL,
  572 + env->itlb_tte[i] & 0x1ffffffe000ULL,
  573 + mask,
  574 + env->itlb_tte[i] & 0x4? "priv": "user",
  575 + env->itlb_tte[i] & 0x40? "locked": "unlocked",
  576 + env->itlb_tag[i] & 0x1fffULL);
  577 + }
  578 + }
579 579 }
580 580 }
581 581 #endif /* DEBUG_MMU */
... ...
target-sparc/op.c
  View file @0f8a249
... ... @@ -376,33 +376,33 @@ void OPPROTO op_add_T1_T0_cc(void)
376 376 env->psr = 0;
377 377 #ifdef TARGET_SPARC64
378 378 if (!(T0 & 0xffffffff))
379   - env->psr |= PSR_ZERO;
  379 + env->psr |= PSR_ZERO;
380 380 if ((int32_t) T0 < 0)
381   - env->psr |= PSR_NEG;
  381 + env->psr |= PSR_NEG;
382 382 if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
383   - env->psr |= PSR_CARRY;
  383 + env->psr |= PSR_CARRY;
384 384 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
385   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
386   - env->psr |= PSR_OVF;
  385 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  386 + env->psr |= PSR_OVF;
387 387  
388 388 env->xcc = 0;
389 389 if (!T0)
390   - env->xcc |= PSR_ZERO;
  390 + env->xcc |= PSR_ZERO;
391 391 if ((int64_t) T0 < 0)
392   - env->xcc |= PSR_NEG;
  392 + env->xcc |= PSR_NEG;
393 393 if (T0 < src1)
394   - env->xcc |= PSR_CARRY;
  394 + env->xcc |= PSR_CARRY;
395 395 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
396   - env->xcc |= PSR_OVF;
  396 + env->xcc |= PSR_OVF;
397 397 #else
398 398 if (!T0)
399   - env->psr |= PSR_ZERO;
  399 + env->psr |= PSR_ZERO;
400 400 if ((int32_t) T0 < 0)
401   - env->psr |= PSR_NEG;
  401 + env->psr |= PSR_NEG;
402 402 if (T0 < src1)
403   - env->psr |= PSR_CARRY;
  403 + env->psr |= PSR_CARRY;
404 404 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
405   - env->psr |= PSR_OVF;
  405 + env->psr |= PSR_OVF;
406 406 #endif
407 407 FORCE_RET();
408 408 }
... ... @@ -448,26 +448,26 @@ void OPPROTO op_addx_T1_T0_cc(void)
448 448 }
449 449 #ifdef TARGET_SPARC64
450 450 if (!(T0 & 0xffffffff))
451   - env->psr |= PSR_ZERO;
  451 + env->psr |= PSR_ZERO;
452 452 if ((int32_t) T0 < 0)
453   - env->psr |= PSR_NEG;
  453 + env->psr |= PSR_NEG;
454 454 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
455   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
456   - env->psr |= PSR_OVF;
  455 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  456 + env->psr |= PSR_OVF;
457 457  
458 458 if (!T0)
459   - env->xcc |= PSR_ZERO;
  459 + env->xcc |= PSR_ZERO;
460 460 if ((int64_t) T0 < 0)
461   - env->xcc |= PSR_NEG;
  461 + env->xcc |= PSR_NEG;
462 462 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
463   - env->xcc |= PSR_OVF;
  463 + env->xcc |= PSR_OVF;
464 464 #else
465 465 if (!T0)
466   - env->psr |= PSR_ZERO;
  466 + env->psr |= PSR_ZERO;
467 467 if ((int32_t) T0 < 0)
468   - env->psr |= PSR_NEG;
  468 + env->psr |= PSR_NEG;
469 469 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
470   - env->psr |= PSR_OVF;
  470 + env->psr |= PSR_OVF;
471 471 #endif
472 472 FORCE_RET();
473 473 }
... ... @@ -481,37 +481,37 @@ void OPPROTO op_tadd_T1_T0_cc(void)
481 481 env->psr = 0;
482 482 #ifdef TARGET_SPARC64
483 483 if (!(T0 & 0xffffffff))
484   - env->psr |= PSR_ZERO;
  484 + env->psr |= PSR_ZERO;
485 485 if ((int32_t) T0 < 0)
486   - env->psr |= PSR_NEG;
  486 + env->psr |= PSR_NEG;
487 487 if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
488   - env->psr |= PSR_CARRY;
  488 + env->psr |= PSR_CARRY;
489 489 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
490   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
491   - env->psr |= PSR_OVF;
  490 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  491 + env->psr |= PSR_OVF;
492 492 if ((src1 & 0x03) || (T1 & 0x03))
493   - env->psr |= PSR_OVF;
  493 + env->psr |= PSR_OVF;
494 494  
495 495 env->xcc = 0;
496 496 if (!T0)
497   - env->xcc |= PSR_ZERO;
  497 + env->xcc |= PSR_ZERO;
498 498 if ((int64_t) T0 < 0)
499   - env->xcc |= PSR_NEG;
  499 + env->xcc |= PSR_NEG;
500 500 if (T0 < src1)
501   - env->xcc |= PSR_CARRY;
  501 + env->xcc |= PSR_CARRY;
502 502 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
503   - env->xcc |= PSR_OVF;
  503 + env->xcc |= PSR_OVF;
504 504 #else
505 505 if (!T0)
506   - env->psr |= PSR_ZERO;
  506 + env->psr |= PSR_ZERO;
507 507 if ((int32_t) T0 < 0)
508   - env->psr |= PSR_NEG;
  508 + env->psr |= PSR_NEG;
509 509 if (T0 < src1)
510   - env->psr |= PSR_CARRY;
  510 + env->psr |= PSR_CARRY;
511 511 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
512   - env->psr |= PSR_OVF;
  512 + env->psr |= PSR_OVF;
513 513 if ((src1 & 0x03) || (T1 & 0x03))
514   - env->psr |= PSR_OVF;
  514 + env->psr |= PSR_OVF;
515 515 #endif
516 516 FORCE_RET();
517 517 }
... ... @@ -528,7 +528,7 @@ void OPPROTO op_tadd_T1_T0_ccTV(void)
528 528  
529 529 #ifdef TARGET_SPARC64
530 530 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
531   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  531 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
532 532 raise_exception(TT_TOVF);
533 533 #else
534 534 if ((src1 & 0x03) || (T1 & 0x03))
... ... @@ -538,26 +538,26 @@ void OPPROTO op_tadd_T1_T0_ccTV(void)
538 538 env->psr = 0;
539 539 #ifdef TARGET_SPARC64
540 540 if (!(T0 & 0xffffffff))
541   - env->psr |= PSR_ZERO;
  541 + env->psr |= PSR_ZERO;
542 542 if ((int32_t) T0 < 0)
543   - env->psr |= PSR_NEG;
  543 + env->psr |= PSR_NEG;
544 544 if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
545   - env->psr |= PSR_CARRY;
  545 + env->psr |= PSR_CARRY;
546 546  
547 547 env->xcc = 0;
548 548 if (!T0)
549   - env->xcc |= PSR_ZERO;
  549 + env->xcc |= PSR_ZERO;
550 550 if ((int64_t) T0 < 0)
551   - env->xcc |= PSR_NEG;
  551 + env->xcc |= PSR_NEG;
552 552 if (T0 < src1)
553   - env->xcc |= PSR_CARRY;
  553 + env->xcc |= PSR_CARRY;
554 554 #else
555 555 if (!T0)
556   - env->psr |= PSR_ZERO;
  556 + env->psr |= PSR_ZERO;
557 557 if ((int32_t) T0 < 0)
558   - env->psr |= PSR_NEG;
  558 + env->psr |= PSR_NEG;
559 559 if (T0 < src1)
560   - env->psr |= PSR_CARRY;
  560 + env->psr |= PSR_CARRY;
561 561 #endif
562 562 FORCE_RET();
563 563 }
... ... @@ -576,33 +576,33 @@ void OPPROTO op_sub_T1_T0_cc(void)
576 576 env->psr = 0;
577 577 #ifdef TARGET_SPARC64
578 578 if (!(T0 & 0xffffffff))
579   - env->psr |= PSR_ZERO;
  579 + env->psr |= PSR_ZERO;
580 580 if ((int32_t) T0 < 0)
581   - env->psr |= PSR_NEG;
  581 + env->psr |= PSR_NEG;
582 582 if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
583   - env->psr |= PSR_CARRY;
  583 + env->psr |= PSR_CARRY;
584 584 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
585   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
586   - env->psr |= PSR_OVF;
  585 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  586 + env->psr |= PSR_OVF;
587 587  
588 588 env->xcc = 0;
589 589 if (!T0)
590   - env->xcc |= PSR_ZERO;
  590 + env->xcc |= PSR_ZERO;
591 591 if ((int64_t) T0 < 0)
592   - env->xcc |= PSR_NEG;
  592 + env->xcc |= PSR_NEG;
593 593 if (src1 < T1)
594   - env->xcc |= PSR_CARRY;
  594 + env->xcc |= PSR_CARRY;
595 595 if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
596   - env->xcc |= PSR_OVF;
  596 + env->xcc |= PSR_OVF;
597 597 #else
598 598 if (!T0)
599   - env->psr |= PSR_ZERO;
  599 + env->psr |= PSR_ZERO;
600 600 if ((int32_t) T0 < 0)
601   - env->psr |= PSR_NEG;
  601 + env->psr |= PSR_NEG;
602 602 if (src1 < T1)
603   - env->psr |= PSR_CARRY;
  603 + env->psr |= PSR_CARRY;
604 604 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
605   - env->psr |= PSR_OVF;
  605 + env->psr |= PSR_OVF;
606 606 #endif
607 607 FORCE_RET();
608 608 }
... ... @@ -648,26 +648,26 @@ void OPPROTO op_subx_T1_T0_cc(void)
648 648 }
649 649 #ifdef TARGET_SPARC64
650 650 if (!(T0 & 0xffffffff))
651   - env->psr |= PSR_ZERO;
  651 + env->psr |= PSR_ZERO;
652 652 if ((int32_t) T0 < 0)
653   - env->psr |= PSR_NEG;
  653 + env->psr |= PSR_NEG;
654 654 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
655   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
656   - env->psr |= PSR_OVF;
  655 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  656 + env->psr |= PSR_OVF;
657 657  
658 658 if (!T0)
659   - env->xcc |= PSR_ZERO;
  659 + env->xcc |= PSR_ZERO;
660 660 if ((int64_t) T0 < 0)
661   - env->xcc |= PSR_NEG;
  661 + env->xcc |= PSR_NEG;
662 662 if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
663   - env->xcc |= PSR_OVF;
  663 + env->xcc |= PSR_OVF;
664 664 #else
665 665 if (!T0)
666   - env->psr |= PSR_ZERO;
  666 + env->psr |= PSR_ZERO;
667 667 if ((int32_t) T0 < 0)
668   - env->psr |= PSR_NEG;
  668 + env->psr |= PSR_NEG;
669 669 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
670   - env->psr |= PSR_OVF;
  670 + env->psr |= PSR_OVF;
671 671 #endif
672 672 FORCE_RET();
673 673 }
... ... @@ -681,37 +681,37 @@ void OPPROTO op_tsub_T1_T0_cc(void)
681 681 env->psr = 0;
682 682 #ifdef TARGET_SPARC64
683 683 if (!(T0 & 0xffffffff))
684   - env->psr |= PSR_ZERO;
  684 + env->psr |= PSR_ZERO;
685 685 if ((int32_t) T0 < 0)
686   - env->psr |= PSR_NEG;
  686 + env->psr |= PSR_NEG;
687 687 if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
688   - env->psr |= PSR_CARRY;
  688 + env->psr |= PSR_CARRY;
689 689 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
690   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
691   - env->psr |= PSR_OVF;
  690 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  691 + env->psr |= PSR_OVF;
692 692 if ((src1 & 0x03) || (T1 & 0x03))
693   - env->psr |= PSR_OVF;
  693 + env->psr |= PSR_OVF;
694 694  
695 695 env->xcc = 0;
696 696 if (!T0)
697   - env->xcc |= PSR_ZERO;
  697 + env->xcc |= PSR_ZERO;
698 698 if ((int64_t) T0 < 0)
699   - env->xcc |= PSR_NEG;
  699 + env->xcc |= PSR_NEG;
700 700 if (src1 < T1)
701   - env->xcc |= PSR_CARRY;
  701 + env->xcc |= PSR_CARRY;
702 702 if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
703   - env->xcc |= PSR_OVF;
  703 + env->xcc |= PSR_OVF;
704 704 #else
705 705 if (!T0)
706   - env->psr |= PSR_ZERO;
  706 + env->psr |= PSR_ZERO;
707 707 if ((int32_t) T0 < 0)
708   - env->psr |= PSR_NEG;
  708 + env->psr |= PSR_NEG;
709 709 if (src1 < T1)
710   - env->psr |= PSR_CARRY;
  710 + env->psr |= PSR_CARRY;
711 711 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
712   - env->psr |= PSR_OVF;
  712 + env->psr |= PSR_OVF;
713 713 if ((src1 & 0x03) || (T1 & 0x03))
714   - env->psr |= PSR_OVF;
  714 + env->psr |= PSR_OVF;
715 715 #endif
716 716 FORCE_RET();
717 717 }
... ... @@ -728,7 +728,7 @@ void OPPROTO op_tsub_T1_T0_ccTV(void)
728 728  
729 729 #ifdef TARGET_SPARC64
730 730 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
731   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  731 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
732 732 raise_exception(TT_TOVF);
733 733 #else
734 734 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
... ... @@ -738,26 +738,26 @@ void OPPROTO op_tsub_T1_T0_ccTV(void)
738 738 env->psr = 0;
739 739 #ifdef TARGET_SPARC64
740 740 if (!(T0 & 0xffffffff))
741   - env->psr |= PSR_ZERO;
  741 + env->psr |= PSR_ZERO;
742 742 if ((int32_t) T0 < 0)
743   - env->psr |= PSR_NEG;
  743 + env->psr |= PSR_NEG;
744 744 if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
745   - env->psr |= PSR_CARRY;
  745 + env->psr |= PSR_CARRY;
746 746  
747 747 env->xcc = 0;
748 748 if (!T0)
749   - env->xcc |= PSR_ZERO;
  749 + env->xcc |= PSR_ZERO;
750 750 if ((int64_t) T0 < 0)
751   - env->xcc |= PSR_NEG;
  751 + env->xcc |= PSR_NEG;
752 752 if (src1 < T1)
753   - env->xcc |= PSR_CARRY;
  753 + env->xcc |= PSR_CARRY;
754 754 #else
755 755 if (!T0)
756   - env->psr |= PSR_ZERO;
  756 + env->psr |= PSR_ZERO;
757 757 if ((int32_t) T0 < 0)
758   - env->psr |= PSR_NEG;
  758 + env->psr |= PSR_NEG;
759 759 if (src1 < T1)
760   - env->psr |= PSR_CARRY;
  760 + env->psr |= PSR_CARRY;
761 761 #endif
762 762 FORCE_RET();
763 763 }
... ... @@ -833,13 +833,13 @@ void OPPROTO op_mulscc_T1_T0(void)
833 833 T0 += T1;
834 834 env->psr = 0;
835 835 if (!T0)
836   - env->psr |= PSR_ZERO;
  836 + env->psr |= PSR_ZERO;
837 837 if ((int32_t) T0 < 0)
838   - env->psr |= PSR_NEG;
  838 + env->psr |= PSR_NEG;
839 839 if (T0 < src1)
840   - env->psr |= PSR_CARRY;
  840 + env->psr |= PSR_CARRY;
841 841 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
842   - env->psr |= PSR_OVF;
  842 + env->psr |= PSR_OVF;
843 843 env->y = (b2 << 31) | (env->y >> 1);
844 844 FORCE_RET();
845 845 }
... ... @@ -858,11 +858,11 @@ void OPPROTO op_udiv_T1_T0(void)
858 858  
859 859 x0 = x0 / x1;
860 860 if (x0 > 0xffffffff) {
861   - T0 = 0xffffffff;
862   - T1 = 1;
  861 + T0 = 0xffffffff;
  862 + T1 = 1;
863 863 } else {
864   - T0 = x0;
865   - T1 = 0;
  864 + T0 = x0;
  865 + T1 = 0;
866 866 }
867 867 FORCE_RET();
868 868 }
... ... @@ -881,11 +881,11 @@ void OPPROTO op_sdiv_T1_T0(void)
881 881  
882 882 x0 = x0 / x1;
883 883 if ((int32_t) x0 != x0) {
884   - T0 = x0 < 0? 0x80000000: 0x7fffffff;
885   - T1 = 1;
  884 + T0 = x0 < 0? 0x80000000: 0x7fffffff;
  885 + T1 = 1;
886 886 } else {
887   - T0 = x0;
888   - T1 = 0;
  887 + T0 = x0;
  888 + T1 = 0;
889 889 }
890 890 FORCE_RET();
891 891 }
... ... @@ -895,24 +895,24 @@ void OPPROTO op_div_cc(void)
895 895 env->psr = 0;
896 896 #ifdef TARGET_SPARC64
897 897 if (!T0)
898   - env->psr |= PSR_ZERO;
  898 + env->psr |= PSR_ZERO;
899 899 if ((int32_t) T0 < 0)
900   - env->psr |= PSR_NEG;
  900 + env->psr |= PSR_NEG;
901 901 if (T1)
902   - env->psr |= PSR_OVF;
  902 + env->psr |= PSR_OVF;
903 903  
904 904 env->xcc = 0;
905 905 if (!T0)
906   - env->xcc |= PSR_ZERO;
  906 + env->xcc |= PSR_ZERO;
907 907 if ((int64_t) T0 < 0)
908   - env->xcc |= PSR_NEG;
  908 + env->xcc |= PSR_NEG;
909 909 #else
910 910 if (!T0)
911   - env->psr |= PSR_ZERO;
  911 + env->psr |= PSR_ZERO;
912 912 if ((int32_t) T0 < 0)
913   - env->psr |= PSR_NEG;
  913 + env->psr |= PSR_NEG;
914 914 if (T1)
915   - env->psr |= PSR_OVF;
  915 + env->psr |= PSR_OVF;
916 916 #endif
917 917 FORCE_RET();
918 918 }
... ... @@ -939,9 +939,9 @@ void OPPROTO op_sdivx_T1_T0(void)
939 939 raise_exception(TT_DIV_ZERO);
940 940 }
941 941 if (T0 == INT64_MIN && T1 == -1)
942   - T0 = INT64_MIN;
  942 + T0 = INT64_MIN;
943 943 else
944   - T0 /= (target_long) T1;
  944 + T0 /= (target_long) T1;
945 945 FORCE_RET();
946 946 }
947 947 #endif
... ... @@ -951,20 +951,20 @@ void OPPROTO op_logic_T0_cc(void)
951 951 env->psr = 0;
952 952 #ifdef TARGET_SPARC64
953 953 if (!(T0 & 0xffffffff))
954   - env->psr |= PSR_ZERO;
  954 + env->psr |= PSR_ZERO;
955 955 if ((int32_t) T0 < 0)
956   - env->psr |= PSR_NEG;
  956 + env->psr |= PSR_NEG;
957 957  
958 958 env->xcc = 0;
959 959 if (!T0)
960   - env->xcc |= PSR_ZERO;
  960 + env->xcc |= PSR_ZERO;
961 961 if ((int64_t) T0 < 0)
962   - env->xcc |= PSR_NEG;
  962 + env->xcc |= PSR_NEG;
963 963 #else
964 964 if (!T0)
965   - env->psr |= PSR_ZERO;
  965 + env->psr |= PSR_ZERO;
966 966 if ((int32_t) T0 < 0)
967   - env->psr |= PSR_NEG;
  967 + env->psr |= PSR_NEG;
968 968 #endif
969 969 FORCE_RET();
970 970 }
... ... @@ -1200,17 +1200,17 @@ void OPPROTO op_save(void)
1200 1200 cwp = (env->cwp - 1) & (NWINDOWS - 1);
1201 1201 if (env->cansave == 0) {
1202 1202 raise_exception(TT_SPILL | (env->otherwin != 0 ?
1203   - (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1204   - ((env->wstate & 0x7) << 2)));
  1203 + (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
  1204 + ((env->wstate & 0x7) << 2)));
1205 1205 } else {
1206   - if (env->cleanwin - env->canrestore == 0) {
1207   - // XXX Clean windows without trap
1208   - raise_exception(TT_CLRWIN);
1209   - } else {
1210   - env->cansave--;
1211   - env->canrestore++;
1212   - set_cwp(cwp);
1213   - }
  1206 + if (env->cleanwin - env->canrestore == 0) {
  1207 + // XXX Clean windows without trap
  1208 + raise_exception(TT_CLRWIN);
  1209 + } else {
  1210 + env->cansave--;
  1211 + env->canrestore++;
  1212 + set_cwp(cwp);
  1213 + }
1214 1214 }
1215 1215 FORCE_RET();
1216 1216 }
... ... @@ -1221,12 +1221,12 @@ void OPPROTO op_restore(void)
1221 1221 cwp = (env->cwp + 1) & (NWINDOWS - 1);
1222 1222 if (env->canrestore == 0) {
1223 1223 raise_exception(TT_FILL | (env->otherwin != 0 ?
1224   - (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1225   - ((env->wstate & 0x7) << 2)));
  1224 + (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
  1225 + ((env->wstate & 0x7) << 2)));
1226 1226 } else {
1227   - env->cansave++;
1228   - env->canrestore--;
1229   - set_cwp(cwp);
  1227 + env->cansave++;
  1228 + env->canrestore--;
  1229 + set_cwp(cwp);
1230 1230 }
1231 1231 FORCE_RET();
1232 1232 }
... ... @@ -1576,15 +1576,15 @@ void OPPROTO op_clear_ieee_excp_and_FTT(void)
1576 1576 #define F_BINOP(name) \
1577 1577 F_OP(name, s) \
1578 1578 { \
1579   - set_float_exception_flags(0, &env->fp_status); \
  1579 + set_float_exception_flags(0, &env->fp_status); \
1580 1580 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
1581   - check_ieee_exceptions(); \
  1581 + check_ieee_exceptions(); \
1582 1582 } \
1583 1583 F_OP(name, d) \
1584 1584 { \
1585   - set_float_exception_flags(0, &env->fp_status); \
  1585 + set_float_exception_flags(0, &env->fp_status); \
1586 1586 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
1587   - check_ieee_exceptions(); \
  1587 + check_ieee_exceptions(); \
1588 1588 }
1589 1589  
1590 1590 F_BINOP(add);
... ... @@ -1784,27 +1784,27 @@ void OPPROTO op_fdtox(void)
1784 1784 void OPPROTO op_fmovs_cc(void)
1785 1785 {
1786 1786 if (T2)
1787   - FT0 = FT1;
  1787 + FT0 = FT1;
1788 1788 }
1789 1789  
1790 1790 void OPPROTO op_fmovd_cc(void)
1791 1791 {
1792 1792 if (T2)
1793   - DT0 = DT1;
  1793 + DT0 = DT1;
1794 1794 }
1795 1795  
1796 1796 void OPPROTO op_mov_cc(void)
1797 1797 {
1798 1798 if (T2)
1799   - T0 = T1;
  1799 + T0 = T1;
1800 1800 }
1801 1801  
1802 1802 void OPPROTO op_flushw(void)
1803 1803 {
1804 1804 if (env->cansave != NWINDOWS - 2) {
1805 1805 raise_exception(TT_SPILL | (env->otherwin != 0 ?
1806   - (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1807   - ((env->wstate & 0x7) << 2)));
  1806 + (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
  1807 + ((env->wstate & 0x7) << 2)));
1808 1808 }
1809 1809 }
1810 1810  
... ... @@ -1812,9 +1812,9 @@ void OPPROTO op_saved(void)
1812 1812 {
1813 1813 env->cansave++;
1814 1814 if (env->otherwin == 0)
1815   - env->canrestore--;
  1815 + env->canrestore--;
1816 1816 else
1817   - env->otherwin--;
  1817 + env->otherwin--;
1818 1818 FORCE_RET();
1819 1819 }
1820 1820  
... ... @@ -1822,11 +1822,11 @@ void OPPROTO op_restored(void)
1822 1822 {
1823 1823 env->canrestore++;
1824 1824 if (env->cleanwin < NWINDOWS - 1)
1825   - env->cleanwin++;
  1825 + env->cleanwin++;
1826 1826 if (env->otherwin == 0)
1827   - env->cansave--;
  1827 + env->cansave--;
1828 1828 else
1829   - env->otherwin--;
  1829 + env->otherwin--;
1830 1830 FORCE_RET();
1831 1831 }
1832 1832  
... ...
target-sparc/op_helper.c
  View file @0f8a249
... ... @@ -16,29 +16,29 @@ void check_ieee_exceptions()
16 16 T0 = get_float_exception_flags(&env->fp_status);
17 17 if (T0)
18 18 {
19   - /* Copy IEEE 754 flags into FSR */
20   - if (T0 & float_flag_invalid)
21   - env->fsr |= FSR_NVC;
22   - if (T0 & float_flag_overflow)
23   - env->fsr |= FSR_OFC;
24   - if (T0 & float_flag_underflow)
25   - env->fsr |= FSR_UFC;
26   - if (T0 & float_flag_divbyzero)
27   - env->fsr |= FSR_DZC;
28   - if (T0 & float_flag_inexact)
29   - env->fsr |= FSR_NXC;
30   -
31   - if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
32   - {
33   - /* Unmasked exception, generate a trap */
34   - env->fsr |= FSR_FTT_IEEE_EXCP;
35   - raise_exception(TT_FP_EXCP);
36   - }
37   - else
38   - {
39   - /* Accumulate exceptions */
40   - env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
41   - }
  19 + /* Copy IEEE 754 flags into FSR */
  20 + if (T0 & float_flag_invalid)
  21 + env->fsr |= FSR_NVC;
  22 + if (T0 & float_flag_overflow)
  23 + env->fsr |= FSR_OFC;
  24 + if (T0 & float_flag_underflow)
  25 + env->fsr |= FSR_UFC;
  26 + if (T0 & float_flag_divbyzero)
  27 + env->fsr |= FSR_DZC;
  28 + if (T0 & float_flag_inexact)
  29 + env->fsr |= FSR_NXC;
  30 +
  31 + if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
  32 + {
  33 + /* Unmasked exception, generate a trap */
  34 + env->fsr |= FSR_FTT_IEEE_EXCP;
  35 + raise_exception(TT_FP_EXCP);
  36 + }
  37 + else
  38 + {
  39 + /* Accumulate exceptions */
  40 + env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
  41 + }
42 42 }
43 43 }
44 44  
... ... @@ -155,33 +155,33 @@ void helper_ld_asi(int asi, int size, int sign)
155 155 case 2: /* SuperSparc MXCC registers */
156 156 break;
157 157 case 3: /* MMU probe */
158   - {
159   - int mmulev;
160   -
161   - mmulev = (T0 >> 8) & 15;
162   - if (mmulev > 4)
163   - ret = 0;
164   - else {
165   - ret = mmu_probe(env, T0, mmulev);
166   - //bswap32s(&ret);
167   - }
  158 + {
  159 + int mmulev;
  160 +
  161 + mmulev = (T0 >> 8) & 15;
  162 + if (mmulev > 4)
  163 + ret = 0;
  164 + else {
  165 + ret = mmu_probe(env, T0, mmulev);
  166 + //bswap32s(&ret);
  167 + }
168 168 #ifdef DEBUG_MMU
169   - printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
  169 + printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
170 170 #endif
171   - }
172   - break;
  171 + }
  172 + break;
173 173 case 4: /* read MMU regs */
174   - {
175   - int reg = (T0 >> 8) & 0xf;
  174 + {
  175 + int reg = (T0 >> 8) & 0xf;
176 176  
177   - ret = env->mmuregs[reg];
178   - if (reg == 3) /* Fault status cleared on read */
179   - env->mmuregs[reg] = 0;
  177 + ret = env->mmuregs[reg];
  178 + if (reg == 3) /* Fault status cleared on read */
  179 + env->mmuregs[reg] = 0;
180 180 #ifdef DEBUG_MMU
181   - printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
  181 + printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
182 182 #endif
183   - }
184   - break;
  183 + }
  184 + break;
185 185 case 9: /* Supervisor code access */
186 186 switch(size) {
187 187 case 1:
... ... @@ -218,11 +218,11 @@ void helper_ld_asi(int asi, int size, int sign)
218 218 ret = ldl_phys(T0 & ~3);
219 219 break;
220 220 case 8:
221   - ret = ldl_phys(T0 & ~3);
222   - T0 = ldl_phys((T0 + 4) & ~3);
223   - break;
  221 + ret = ldl_phys(T0 & ~3);
  222 + T0 = ldl_phys((T0 + 4) & ~3);
  223 + break;
224 224 }
225   - break;
  225 + break;
226 226 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
227 227 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
228 228 switch(size) {
... ... @@ -244,14 +244,14 @@ void helper_ld_asi(int asi, int size, int sign)
244 244 | ((target_phys_addr_t)(asi & 0xf) << 32));
245 245 T0 = ldl_phys((target_phys_addr_t)((T0 + 4) & ~3)
246 246 | ((target_phys_addr_t)(asi & 0xf) << 32));
247   - break;
  247 + break;
248 248 }
249   - break;
  249 + break;
250 250 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
251 251 default:
252 252 do_unassigned_access(T0, 0, 0, 1);
253   - ret = 0;
254   - break;
  253 + ret = 0;
  254 + break;
255 255 }
256 256 T1 = ret;
257 257 }
... ... @@ -262,48 +262,48 @@ void helper_st_asi(int asi, int size, int sign)
262 262 case 2: /* SuperSparc MXCC registers */
263 263 break;
264 264 case 3: /* MMU flush */
265   - {
266   - int mmulev;
  265 + {
  266 + int mmulev;
267 267  
268   - mmulev = (T0 >> 8) & 15;
  268 + mmulev = (T0 >> 8) & 15;
269 269 #ifdef DEBUG_MMU
270   - printf("mmu flush level %d\n", mmulev);
  270 + printf("mmu flush level %d\n", mmulev);
271 271 #endif
272   - switch (mmulev) {
273   - case 0: // flush page
274   - tlb_flush_page(env, T0 & 0xfffff000);
275   - break;
276   - case 1: // flush segment (256k)
277   - case 2: // flush region (16M)
278   - case 3: // flush context (4G)
279   - case 4: // flush entire
280   - tlb_flush(env, 1);
281   - break;
282   - default:
283   - break;
284   - }
  272 + switch (mmulev) {
  273 + case 0: // flush page
  274 + tlb_flush_page(env, T0 & 0xfffff000);
  275 + break;
  276 + case 1: // flush segment (256k)
  277 + case 2: // flush region (16M)
  278 + case 3: // flush context (4G)
  279 + case 4: // flush entire
  280 + tlb_flush(env, 1);
  281 + break;
  282 + default:
  283 + break;
  284 + }
285 285 #ifdef DEBUG_MMU
286   - dump_mmu(env);
  286 + dump_mmu(env);
287 287 #endif
288   - return;
289   - }
  288 + return;
  289 + }
290 290 case 4: /* write MMU regs */
291   - {
292   - int reg = (T0 >> 8) & 0xf;
293   - uint32_t oldreg;
  291 + {
  292 + int reg = (T0 >> 8) & 0xf;
  293 + uint32_t oldreg;
294 294  
295   - oldreg = env->mmuregs[reg];
  295 + oldreg = env->mmuregs[reg];
296 296 switch(reg) {
297 297 case 0:
298   - env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
299   - env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
300   - // Mappings generated during no-fault mode or MMU
301   - // disabled mode are invalid in normal mode
  298 + env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
  299 + env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
  300 + // Mappings generated during no-fault mode or MMU
  301 + // disabled mode are invalid in normal mode
302 302 if (oldreg != env->mmuregs[reg])
303 303 tlb_flush(env, 1);
304 304 break;
305 305 case 2:
306   - env->mmuregs[reg] = T1;
  306 + env->mmuregs[reg] = T1;
307 307 if (oldreg != env->mmuregs[reg]) {
308 308 /* we flush when the MMU context changes because
309 309 QEMU has no MMU context support */
... ... @@ -314,17 +314,17 @@ void helper_st_asi(int asi, int size, int sign)
314 314 case 4:
315 315 break;
316 316 default:
317   - env->mmuregs[reg] = T1;
  317 + env->mmuregs[reg] = T1;
318 318 break;
319 319 }
320 320 #ifdef DEBUG_MMU
321 321 if (oldreg != env->mmuregs[reg]) {
322 322 printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
323 323 }
324   - dump_mmu(env);
  324 + dump_mmu(env);
325 325 #endif
326   - return;
327   - }
  326 + return;
  327 + }
328 328 case 0xc: /* I-cache tag */
329 329 case 0xd: /* I-cache data */
330 330 case 0xe: /* D-cache tag */
... ... @@ -336,10 +336,10 @@ void helper_st_asi(int asi, int size, int sign)
336 336 case 0x14: /* I/D-cache flush user */
337 337 break;
338 338 case 0x17: /* Block copy, sta access */
339   - {
340   - // value (T1) = src
341   - // address (T0) = dst
342   - // copy 32 bytes
  339 + {
  340 + // value (T1) = src
  341 + // address (T0) = dst
  342 + // copy 32 bytes
343 343 unsigned int i;
344 344 uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
345 345  
... ... @@ -347,13 +347,13 @@ void helper_st_asi(int asi, int size, int sign)
347 347 temp = ldl_kernel(src);
348 348 stl_kernel(dst, temp);
349 349 }
350   - }
351   - return;
  350 + }
  351 + return;
352 352 case 0x1f: /* Block fill, stda access */
353   - {
354   - // value (T1, T2)
355   - // address (T0) = dst
356   - // fill 32 bytes
  353 + {
  354 + // value (T1, T2)
  355 + // address (T0) = dst
  356 + // fill 32 bytes
357 357 unsigned int i;
358 358 uint32_t dst = T0 & 7;
359 359 uint64_t val;
... ... @@ -362,10 +362,10 @@ void helper_st_asi(int asi, int size, int sign)
362 362  
363 363 for (i = 0; i < 32; i += 8, dst += 8)
364 364 stq_kernel(dst, val);
365   - }
366   - return;
  365 + }
  366 + return;
367 367 case 0x20: /* MMU passthrough */
368   - {
  368 + {
369 369 switch(size) {
370 370 case 1:
371 371 stb_phys(T0, T1);
... ... @@ -382,11 +382,11 @@ void helper_st_asi(int asi, int size, int sign)
382 382 stl_phys((T0 + 4) & ~3, T2);
383 383 break;
384 384 }
385   - }
386   - return;
  385 + }
  386 + return;
387 387 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
388 388 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
389   - {
  389 + {
390 390 switch(size) {
391 391 case 1:
392 392 stb_phys((target_phys_addr_t)T0
... ... @@ -408,8 +408,8 @@ void helper_st_asi(int asi, int size, int sign)
408 408 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
409 409 break;
410 410 }
411   - }
412   - return;
  411 + }
  412 + return;
413 413 case 0x31: /* Ross RT620 I-cache flush */
414 414 case 0x36: /* I-cache flash clear */
415 415 case 0x37: /* D-cache flash clear */
... ... @@ -418,7 +418,7 @@ void helper_st_asi(int asi, int size, int sign)
418 418 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
419 419 default:
420 420 do_unassigned_access(T0, 1, 0, 1);
421   - return;
  421 + return;
422 422 }
423 423 }
424 424  
... ... @@ -429,12 +429,12 @@ void helper_ld_asi(int asi, int size, int sign)
429 429 uint64_t ret = 0;
430 430  
431 431 if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
432   - raise_exception(TT_PRIV_ACT);
  432 + raise_exception(TT_PRIV_ACT);
433 433  
434 434 switch (asi) {
435 435 case 0x14: // Bypass
436 436 case 0x15: // Bypass, non-cacheable
437   - {
  437 + {
438 438 switch(size) {
439 439 case 1:
440 440 ret = ldub_phys(T0);
... ... @@ -450,8 +450,8 @@ void helper_ld_asi(int asi, int size, int sign)
450 450 ret = ldq_phys(T0 & ~7);
451 451 break;
452 452 }
453   - break;
454   - }
  453 + break;
  454 + }
455 455 case 0x04: // Nucleus
456 456 case 0x0c: // Nucleus Little Endian (LE)
457 457 case 0x10: // As if user primary
... ... @@ -469,58 +469,58 @@ void helper_ld_asi(int asi, int size, int sign)
469 469 case 0x89: // Secondary LE
470 470 case 0x8a: // Primary no-fault LE
471 471 case 0x8b: // Secondary no-fault LE
472   - // XXX
473   - break;
  472 + // XXX
  473 + break;
474 474 case 0x45: // LSU
475   - ret = env->lsu;
476   - break;
  475 + ret = env->lsu;
  476 + break;
477 477 case 0x50: // I-MMU regs
478   - {
479   - int reg = (T0 >> 3) & 0xf;
  478 + {
  479 + int reg = (T0 >> 3) & 0xf;
480 480  
481   - ret = env->immuregs[reg];
482   - break;
483   - }
  481 + ret = env->immuregs[reg];
  482 + break;
  483 + }
484 484 case 0x51: // I-MMU 8k TSB pointer
485 485 case 0x52: // I-MMU 64k TSB pointer
486 486 case 0x55: // I-MMU data access
487   - // XXX
488   - break;
  487 + // XXX
  488 + break;
489 489 case 0x56: // I-MMU tag read
490   - {
491   - unsigned int i;
492   -
493   - for (i = 0; i < 64; i++) {
494   - // Valid, ctx match, vaddr match
495   - if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
496   - env->itlb_tag[i] == T0) {
497   - ret = env->itlb_tag[i];
498   - break;
499   - }
500   - }
501   - break;
502   - }
  490 + {
  491 + unsigned int i;
  492 +
  493 + for (i = 0; i < 64; i++) {
  494 + // Valid, ctx match, vaddr match
  495 + if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
  496 + env->itlb_tag[i] == T0) {
  497 + ret = env->itlb_tag[i];
  498 + break;
  499 + }
  500 + }
  501 + break;
  502 + }
503 503 case 0x58: // D-MMU regs
504   - {
505   - int reg = (T0 >> 3) & 0xf;
  504 + {
  505 + int reg = (T0 >> 3) & 0xf;
506 506  
507   - ret = env->dmmuregs[reg];
508   - break;
509   - }
  507 + ret = env->dmmuregs[reg];
  508 + break;
  509 + }
510 510 case 0x5e: // D-MMU tag read
511   - {
512   - unsigned int i;
513   -
514   - for (i = 0; i < 64; i++) {
515   - // Valid, ctx match, vaddr match
516   - if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
517   - env->dtlb_tag[i] == T0) {
518   - ret = env->dtlb_tag[i];
519   - break;
520   - }
521   - }
522   - break;
523   - }
  511 + {
  512 + unsigned int i;
  513 +
  514 + for (i = 0; i < 64; i++) {
  515 + // Valid, ctx match, vaddr match
  516 + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
  517 + env->dtlb_tag[i] == T0) {
  518 + ret = env->dtlb_tag[i];
  519 + break;
  520 + }
  521 + }
  522 + break;
  523 + }
524 524 case 0x59: // D-MMU 8k TSB pointer
525 525 case 0x5a: // D-MMU 64k TSB pointer
526 526 case 0x5b: // D-MMU data pointer
... ... @@ -528,8 +528,8 @@ void helper_ld_asi(int asi, int size, int sign)
528 528 case 0x48: // Interrupt dispatch, RO
529 529 case 0x49: // Interrupt data receive
530 530 case 0x7f: // Incoming interrupt vector, RO
531   - // XXX
532   - break;
  531 + // XXX
  532 + break;
533 533 case 0x54: // I-MMU data in, WO
534 534 case 0x57: // I-MMU demap, WO
535 535 case 0x5c: // D-MMU data in, WO
... ... @@ -537,8 +537,8 @@ void helper_ld_asi(int asi, int size, int sign)
537 537 case 0x77: // Interrupt vector, WO
538 538 default:
539 539 do_unassigned_access(T0, 0, 0, 1);
540   - ret = 0;
541   - break;
  540 + ret = 0;
  541 + break;
542 542 }
543 543 T1 = ret;
544 544 }
... ... @@ -546,12 +546,12 @@ void helper_ld_asi(int asi, int size, int sign)
546 546 void helper_st_asi(int asi, int size, int sign)
547 547 {
548 548 if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
549   - raise_exception(TT_PRIV_ACT);
  549 + raise_exception(TT_PRIV_ACT);
550 550  
551 551 switch(asi) {
552 552 case 0x14: // Bypass
553 553 case 0x15: // Bypass, non-cacheable
554   - {
  554 + {
555 555 switch(size) {
556 556 case 1:
557 557 stb_phys(T0, T1);
... ... @@ -567,8 +567,8 @@ void helper_st_asi(int asi, int size, int sign)
567 567 stq_phys(T0 & ~7, T1);
568 568 break;
569 569 }
570   - }
571   - return;
  570 + }
  571 + return;
572 572 case 0x04: // Nucleus
573 573 case 0x0c: // Nucleus Little Endian (LE)
574 574 case 0x10: // As if user primary
... ... @@ -582,31 +582,31 @@ void helper_st_asi(int asi, int size, int sign)
582 582 case 0x4a: // UPA config
583 583 case 0x88: // Primary LE
584 584 case 0x89: // Secondary LE
585   - // XXX
586   - return;
  585 + // XXX
  586 + return;
587 587 case 0x45: // LSU
588   - {
589   - uint64_t oldreg;
590   -
591   - oldreg = env->lsu;
592   - env->lsu = T1 & (DMMU_E | IMMU_E);
593   - // Mappings generated during D/I MMU disabled mode are
594   - // invalid in normal mode
595   - if (oldreg != env->lsu) {
  588 + {
  589 + uint64_t oldreg;
  590 +
  591 + oldreg = env->lsu;
  592 + env->lsu = T1 & (DMMU_E | IMMU_E);
  593 + // Mappings generated during D/I MMU disabled mode are
  594 + // invalid in normal mode
  595 + if (oldreg != env->lsu) {
596 596 #ifdef DEBUG_MMU
597 597 printf("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
598   - dump_mmu(env);
  598 + dump_mmu(env);
599 599 #endif
600   - tlb_flush(env, 1);
601   - }
602   - return;
603   - }
  600 + tlb_flush(env, 1);
  601 + }
  602 + return;
  603 + }
604 604 case 0x50: // I-MMU regs
605   - {
606   - int reg = (T0 >> 3) & 0xf;
607   - uint64_t oldreg;
  605 + {
  606 + int reg = (T0 >> 3) & 0xf;
  607 + uint64_t oldreg;
608 608  
609   - oldreg = env->immuregs[reg];
  609 + oldreg = env->immuregs[reg];
610 610 switch(reg) {
611 611 case 0: // RO
612 612 case 4:
... ... @@ -617,73 +617,73 @@ void helper_st_asi(int asi, int size, int sign)
617 617 case 8:
618 618 return;
619 619 case 3: // SFSR
620   - if ((T1 & 1) == 0)
621   - T1 = 0; // Clear SFSR
  620 + if ((T1 & 1) == 0)
  621 + T1 = 0; // Clear SFSR
622 622 break;
623 623 case 5: // TSB access
624 624 case 6: // Tag access
625 625 default:
626 626 break;
627 627 }
628   - env->immuregs[reg] = T1;
  628 + env->immuregs[reg] = T1;
629 629 #ifdef DEBUG_MMU
630 630 if (oldreg != env->immuregs[reg]) {
631 631 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
632 632 }
633   - dump_mmu(env);
  633 + dump_mmu(env);
634 634 #endif
635   - return;
636   - }
  635 + return;
  636 + }
637 637 case 0x54: // I-MMU data in
638   - {
639   - unsigned int i;
640   -
641   - // Try finding an invalid entry
642   - for (i = 0; i < 64; i++) {
643   - if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
644   - env->itlb_tag[i] = env->immuregs[6];
645   - env->itlb_tte[i] = T1;
646   - return;
647   - }
648   - }
649   - // Try finding an unlocked entry
650   - for (i = 0; i < 64; i++) {
651   - if ((env->itlb_tte[i] & 0x40) == 0) {
652   - env->itlb_tag[i] = env->immuregs[6];
653   - env->itlb_tte[i] = T1;
654   - return;
655   - }
656   - }
657   - // error state?
658   - return;
659   - }
  638 + {
  639 + unsigned int i;
  640 +
  641 + // Try finding an invalid entry
  642 + for (i = 0; i < 64; i++) {
  643 + if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
  644 + env->itlb_tag[i] = env->immuregs[6];
  645 + env->itlb_tte[i] = T1;
  646 + return;
  647 + }
  648 + }
  649 + // Try finding an unlocked entry
  650 + for (i = 0; i < 64; i++) {
  651 + if ((env->itlb_tte[i] & 0x40) == 0) {
  652 + env->itlb_tag[i] = env->immuregs[6];
  653 + env->itlb_tte[i] = T1;
  654 + return;
  655 + }
  656 + }
  657 + // error state?
  658 + return;
  659 + }
660 660 case 0x55: // I-MMU data access
661   - {
662   - unsigned int i = (T0 >> 3) & 0x3f;
  661 + {
  662 + unsigned int i = (T0 >> 3) & 0x3f;
663 663  
664   - env->itlb_tag[i] = env->immuregs[6];
665   - env->itlb_tte[i] = T1;
666   - return;
667   - }
  664 + env->itlb_tag[i] = env->immuregs[6];
  665 + env->itlb_tte[i] = T1;
  666 + return;
  667 + }
668 668 case 0x57: // I-MMU demap
669   - // XXX
670   - return;
  669 + // XXX
  670 + return;
671 671 case 0x58: // D-MMU regs
672   - {
673   - int reg = (T0 >> 3) & 0xf;
674   - uint64_t oldreg;
  672 + {
  673 + int reg = (T0 >> 3) & 0xf;
  674 + uint64_t oldreg;
675 675  
676   - oldreg = env->dmmuregs[reg];
  676 + oldreg = env->dmmuregs[reg];
677 677 switch(reg) {
678 678 case 0: // RO
679 679 case 4:
680 680 return;
681 681 case 3: // SFSR
682   - if ((T1 & 1) == 0) {
683   - T1 = 0; // Clear SFSR, Fault address
684   - env->dmmuregs[4] = 0;
685   - }
686   - env->dmmuregs[reg] = T1;
  682 + if ((T1 & 1) == 0) {
  683 + T1 = 0; // Clear SFSR, Fault address
  684 + env->dmmuregs[4] = 0;
  685 + }
  686 + env->dmmuregs[reg] = T1;
687 687 break;
688 688 case 1: // Primary context
689 689 case 2: // Secondary context
... ... @@ -694,50 +694,50 @@ void helper_st_asi(int asi, int size, int sign)
694 694 default:
695 695 break;
696 696 }
697   - env->dmmuregs[reg] = T1;
  697 + env->dmmuregs[reg] = T1;
698 698 #ifdef DEBUG_MMU
699 699 if (oldreg != env->dmmuregs[reg]) {
700 700 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
701 701 }
702   - dump_mmu(env);
  702 + dump_mmu(env);
703 703 #endif
704   - return;
705   - }
  704 + return;
  705 + }
706 706 case 0x5c: // D-MMU data in
707   - {
708   - unsigned int i;
709   -
710   - // Try finding an invalid entry
711   - for (i = 0; i < 64; i++) {
712   - if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
713   - env->dtlb_tag[i] = env->dmmuregs[6];
714   - env->dtlb_tte[i] = T1;
715   - return;
716   - }
717   - }
718   - // Try finding an unlocked entry
719   - for (i = 0; i < 64; i++) {
720   - if ((env->dtlb_tte[i] & 0x40) == 0) {
721   - env->dtlb_tag[i] = env->dmmuregs[6];
722   - env->dtlb_tte[i] = T1;
723   - return;
724   - }
725   - }
726   - // error state?
727   - return;
728   - }
  707 + {
  708 + unsigned int i;
  709 +
  710 + // Try finding an invalid entry
  711 + for (i = 0; i < 64; i++) {
  712 + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
  713 + env->dtlb_tag[i] = env->dmmuregs[6];
  714 + env->dtlb_tte[i] = T1;
  715 + return;
  716 + }
  717 + }
  718 + // Try finding an unlocked entry
  719 + for (i = 0; i < 64; i++) {
  720 + if ((env->dtlb_tte[i] & 0x40) == 0) {
  721 + env->dtlb_tag[i] = env->dmmuregs[6];
  722 + env->dtlb_tte[i] = T1;
  723 + return;
  724 + }
  725 + }
  726 + // error state?
  727 + return;
  728 + }
729 729 case 0x5d: // D-MMU data access
730   - {
731   - unsigned int i = (T0 >> 3) & 0x3f;
  730 + {
  731 + unsigned int i = (T0 >> 3) & 0x3f;
732 732  
733   - env->dtlb_tag[i] = env->dmmuregs[6];
734   - env->dtlb_tte[i] = T1;
735   - return;
736   - }
  733 + env->dtlb_tag[i] = env->dmmuregs[6];
  734 + env->dtlb_tte[i] = T1;
  735 + return;
  736 + }
737 737 case 0x5f: // D-MMU demap
738 738 case 0x49: // Interrupt data receive
739   - // XXX
740   - return;
  739 + // XXX
  740 + return;
741 741 case 0x51: // I-MMU 8k TSB pointer, RO
742 742 case 0x52: // I-MMU 64k TSB pointer, RO
743 743 case 0x56: // I-MMU tag read, RO
... ... @@ -753,7 +753,7 @@ void helper_st_asi(int asi, int size, int sign)
753 753 case 0x8b: // Secondary no-fault LE, RO
754 754 default:
755 755 do_unassigned_access(T0, 1, 0, 1);
756   - return;
  756 + return;
757 757 }
758 758 }
759 759 #endif
... ... @@ -783,17 +783,17 @@ void helper_ldfsr(void)
783 783 switch (env->fsr & FSR_RD_MASK) {
784 784 case FSR_RD_NEAREST:
785 785 rnd_mode = float_round_nearest_even;
786   - break;
  786 + break;
787 787 default:
788 788 case FSR_RD_ZERO:
789 789 rnd_mode = float_round_to_zero;
790   - break;
  790 + break;
791 791 case FSR_RD_POS:
792 792 rnd_mode = float_round_up;
793   - break;
  793 + break;
794 794 case FSR_RD_NEG:
795 795 rnd_mode = float_round_down;
796   - break;
  796 + break;
797 797 }
798 798 set_float_rounding_mode(rnd_mode, &env->fp_status);
799 799 }
... ... @@ -835,13 +835,13 @@ static inline uint64_t *get_gregset(uint64_t pstate)
835 835 switch (pstate) {
836 836 default:
837 837 case 0:
838   - return env->bgregs;
  838 + return env->bgregs;
839 839 case PS_AG:
840   - return env->agregs;
  840 + return env->agregs;
841 841 case PS_MG:
842   - return env->mgregs;
  842 + return env->mgregs;
843 843 case PS_IG:
844   - return env->igregs;
  844 + return env->igregs;
845 845 }
846 846 }
847 847  
... ... @@ -853,11 +853,11 @@ static inline void change_pstate(uint64_t new_pstate)
853 853 pstate_regs = env->pstate & 0xc01;
854 854 new_pstate_regs = new_pstate & 0xc01;
855 855 if (new_pstate_regs != pstate_regs) {
856   - // Switch global register bank
857   - src = get_gregset(new_pstate_regs);
858   - dst = get_gregset(pstate_regs);
859   - memcpy32(dst, env->gregs);
860   - memcpy32(env->gregs, src);
  856 + // Switch global register bank
  857 + src = get_gregset(new_pstate_regs);
  858 + dst = get_gregset(pstate_regs);
  859 + memcpy32(dst, env->gregs);
  860 + memcpy32(env->gregs, src);
861 861 }
862 862 env->pstate = new_pstate;
863 863 }
... ... @@ -927,36 +927,36 @@ void do_interrupt(int intno)
927 927 {
928 928 #ifdef DEBUG_PCALL
929 929 if (loglevel & CPU_LOG_INT) {
930   - static int count;
931   - fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
  930 + static int count;
  931 + fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
932 932 count, intno,
933 933 env->pc,
934 934 env->npc, env->regwptr[6]);
935   - cpu_dump_state(env, logfile, fprintf, 0);
  935 + cpu_dump_state(env, logfile, fprintf, 0);
936 936 #if 0
937   - {
938   - int i;
939   - uint8_t *ptr;
940   -
941   - fprintf(logfile, " code=");
942   - ptr = (uint8_t *)env->pc;
943   - for(i = 0; i < 16; i++) {
944   - fprintf(logfile, " %02x", ldub(ptr + i));
945   - }
946   - fprintf(logfile, "\n");
947   - }
  937 + {
  938 + int i;
  939 + uint8_t *ptr;
  940 +
  941 + fprintf(logfile, " code=");
  942 + ptr = (uint8_t *)env->pc;
  943 + for(i = 0; i < 16; i++) {
  944 + fprintf(logfile, " %02x", ldub(ptr + i));
  945 + }
  946 + fprintf(logfile, "\n");
  947 + }
948 948 #endif
949   - count++;
  949 + count++;
950 950 }
951 951 #endif
952 952 #if !defined(CONFIG_USER_ONLY)
953 953 if (env->tl == MAXTL) {
954 954 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
955   - return;
  955 + return;
956 956 }
957 957 #endif
958 958 env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
959   - ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
  959 + ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
960 960 env->tpc[env->tl] = env->pc;
961 961 env->tnpc[env->tl] = env->npc;
962 962 env->tt[env->tl] = intno;
... ... @@ -971,11 +971,11 @@ void do_interrupt(int intno)
971 971 env->tbr &= ~0x7fffULL;
972 972 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
973 973 if (env->tl < MAXTL - 1) {
974   - env->tl++;
  974 + env->tl++;
975 975 } else {
976   - env->pstate |= PS_RED;
977   - if (env->tl != MAXTL)
978   - env->tl++;
  976 + env->pstate |= PS_RED;
  977 + if (env->tl != MAXTL)
  978 + env->tl++;
979 979 }
980 980 env->pc = env->tbr;
981 981 env->npc = env->pc + 4;
... ... @@ -988,32 +988,32 @@ void do_interrupt(int intno)
988 988  
989 989 #ifdef DEBUG_PCALL
990 990 if (loglevel & CPU_LOG_INT) {
991   - static int count;
992   - fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
  991 + static int count;
  992 + fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
993 993 count, intno,
994 994 env->pc,
995 995 env->npc, env->regwptr[6]);
996   - cpu_dump_state(env, logfile, fprintf, 0);
  996 + cpu_dump_state(env, logfile, fprintf, 0);
997 997 #if 0
998   - {
999   - int i;
1000   - uint8_t *ptr;
1001   -
1002   - fprintf(logfile, " code=");
1003   - ptr = (uint8_t *)env->pc;
1004   - for(i = 0; i < 16; i++) {
1005   - fprintf(logfile, " %02x", ldub(ptr + i));
1006   - }
1007   - fprintf(logfile, "\n");
1008   - }
  998 + {
  999 + int i;
  1000 + uint8_t *ptr;
  1001 +
  1002 + fprintf(logfile, " code=");
  1003 + ptr = (uint8_t *)env->pc;
  1004 + for(i = 0; i < 16; i++) {
  1005 + fprintf(logfile, " %02x", ldub(ptr + i));
  1006 + }
  1007 + fprintf(logfile, "\n");
  1008 + }
1009 1009 #endif
1010   - count++;
  1010 + count++;
1011 1011 }
1012 1012 #endif
1013 1013 #if !defined(CONFIG_USER_ONLY)
1014 1014 if (env->psret == 0) {
1015 1015 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
1016   - return;
  1016 + return;
1017 1017 }
1018 1018 #endif
1019 1019 env->psret = 0;
... ... @@ -1106,7 +1106,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1106 1106 saved_env = env;
1107 1107 env = cpu_single_env;
1108 1108 if (env->mmuregs[3]) /* Fault status register */
1109   - env->mmuregs[3] = 1; /* overflow (not read before another fault) */
  1109 + env->mmuregs[3] = 1; /* overflow (not read before another fault) */
1110 1110 if (is_asi)
1111 1111 env->mmuregs[3] |= 1 << 16;
1112 1112 if (env->psrs)
... ...
target-sparc/op_mem.h
  View file @0f8a249
... ... @@ -2,13 +2,13 @@
2 2 #define SPARC_LD_OP(name, qp) \
3 3 void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
4 4 { \
5   - T1 = (target_ulong)glue(qp, MEMSUFFIX)(T0); \
  5 + T1 = (target_ulong)glue(qp, MEMSUFFIX)(T0); \
6 6 }
7 7  
8   -#define SPARC_LD_OP_S(name, qp) \
9   - void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
10   - { \
11   - T1 = (target_long)glue(qp, MEMSUFFIX)(T0); \
  8 +#define SPARC_LD_OP_S(name, qp) \
  9 + void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
  10 + { \
  11 + T1 = (target_long)glue(qp, MEMSUFFIX)(T0); \
12 12 }
13 13  
14 14 #define SPARC_ST_OP(name, op) \
... ... @@ -85,7 +85,7 @@ void OPPROTO glue(op_cas, MEMSUFFIX)(void)
85 85 tmp = glue(ldl, MEMSUFFIX)(T0);
86 86 T2 &= 0xffffffffULL;
87 87 if (tmp == (T1 & 0xffffffffULL)) {
88   - glue(stl, MEMSUFFIX)(T0, T2);
  88 + glue(stl, MEMSUFFIX)(T0, T2);
89 89 }
90 90 T2 = tmp;
91 91 }
... ... @@ -98,7 +98,7 @@ void OPPROTO glue(op_casx, MEMSUFFIX)(void)
98 98 tmp = (uint64_t)glue(ldl, MEMSUFFIX)(T0) << 32;
99 99 tmp |= glue(ldl, MEMSUFFIX)(T0);
100 100 if (tmp == T1) {
101   - glue(stq, MEMSUFFIX)(T0, T2);
  101 + glue(stq, MEMSUFFIX)(T0, T2);
102 102 }
103 103 T2 = tmp;
104 104 }
... ...