gwj / at91sam9263 · Commits

Commit 0f8a249a0ba252d7ff61410791712ae9b3449063

Authored by blueswir1
1 parent 2e03286b

Detabify 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3195 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 6 changed files with 2212 additions and 2212 deletions
target-sparc/cpu.h
  View file @0f8a249
... ... @@ -22,9 +22,9 @@
22 22 #define TARGET_HAS_ICE 1
23 23  
24 24 #if !defined(TARGET_SPARC64)
25   -#define ELF_MACHINE EM_SPARC
  25 +#define ELF_MACHINE EM_SPARC
26 26 #else
27   -#define ELF_MACHINE EM_SPARCV9
  27 +#define ELF_MACHINE EM_SPARCV9
28 28 #endif
29 29  
30 30 /*#define EXCP_INTERRUPT 0x100*/
... ... @@ -143,8 +143,8 @@
143 143 #define FSR_FCC0 (1<<10)
144 144  
145 145 /* MMU */
146   -#define MMU_E (1<<0)
147   -#define MMU_NF (1<<1)
  146 +#define MMU_E (1<<0)
  147 +#define MMU_NF (1<<1)
148 148  
149 149 #define PTE_ENTRYTYPE_MASK 3
150 150 #define PTE_ACCESS_MASK 0x1c
... ... @@ -152,8 +152,8 @@
152 152 #define PTE_PPN_SHIFT 7
153 153 #define PTE_ADDR_MASK 0xffffff00
154 154  
155   -#define PG_ACCESSED_BIT 5
156   -#define PG_MODIFIED_BIT 6
  155 +#define PG_ACCESSED_BIT 5
  156 +#define PG_MODIFIED_BIT 6
157 157 #define PG_CACHE_BIT 7
158 158  
159 159 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
... ... @@ -221,7 +221,7 @@ typedef struct CPUSPARCState {
221 221 uint64_t tnpc[MAXTL];
222 222 uint64_t tstate[MAXTL];
223 223 uint32_t tt[MAXTL];
224   - uint32_t xcc; /* Extended integer condition codes */
  224 + uint32_t xcc; /* Extended integer condition codes */
225 225 uint32_t asi;
226 226 uint32_t pstate;
227 227 uint32_t tl;
... ... @@ -245,12 +245,12 @@ typedef struct CPUSPARCState {
245 245 } CPUSPARCState;
246 246 #if defined(TARGET_SPARC64)
247 247 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
248   -#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
249   - env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
  248 +#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
  249 + env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
250 250 } while (0)
251 251 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
252   -#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
253   - env->fsr = _tmp & 0x3fcfc1c3ffULL; \
  252 +#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
  253 + env->fsr = _tmp & 0x3fcfc1c3ffULL; \
254 254 } while (0)
255 255 #else
256 256 #define GET_FSR32(env) (env->fsr)
... ... @@ -268,31 +268,31 @@ void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
268 268 int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def);
269 269  
270 270 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
271   - (env->psref? PSR_EF : 0) | \
272   - (env->psrpil << 8) | \
273   - (env->psrs? PSR_S : 0) | \
274   - (env->psrps? PSR_PS : 0) | \
275   - (env->psret? PSR_ET : 0) | env->cwp)
  271 + (env->psref? PSR_EF : 0) | \
  272 + (env->psrpil << 8) | \
  273 + (env->psrs? PSR_S : 0) | \
  274 + (env->psrps? PSR_PS : 0) | \
  275 + (env->psret? PSR_ET : 0) | env->cwp)
276 276  
277 277 #ifndef NO_CPU_IO_DEFS
278 278 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
279 279 #endif
280 280  
281   -#define PUT_PSR(env, val) do { int _tmp = val; \
282   - env->psr = _tmp & PSR_ICC; \
283   - env->psref = (_tmp & PSR_EF)? 1 : 0; \
284   - env->psrpil = (_tmp & PSR_PIL) >> 8; \
285   - env->psrs = (_tmp & PSR_S)? 1 : 0; \
286   - env->psrps = (_tmp & PSR_PS)? 1 : 0; \
287   - env->psret = (_tmp & PSR_ET)? 1 : 0; \
  281 +#define PUT_PSR(env, val) do { int _tmp = val; \
  282 + env->psr = _tmp & PSR_ICC; \
  283 + env->psref = (_tmp & PSR_EF)? 1 : 0; \
  284 + env->psrpil = (_tmp & PSR_PIL) >> 8; \
  285 + env->psrs = (_tmp & PSR_S)? 1 : 0; \
  286 + env->psrps = (_tmp & PSR_PS)? 1 : 0; \
  287 + env->psret = (_tmp & PSR_ET)? 1 : 0; \
288 288 cpu_set_cwp(env, _tmp & PSR_CWP); \
289 289 } while (0)
290 290  
291 291 #ifdef TARGET_SPARC64
292 292 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
293   -#define PUT_CCR(env, val) do { int _tmp = val; \
294   - env->xcc = (_tmp >> 4) << 20; \
295   - env->psr = (_tmp & 0xf) << 20; \
  293 +#define PUT_CCR(env, val) do { int _tmp = val; \
  294 + env->xcc = (_tmp >> 4) << 20; \
  295 + env->psr = (_tmp & 0xf) << 20; \
296 296 } while (0)
297 297 #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
298 298 #define PUT_CWP64(env, val) \
... ...
target-sparc/helper.c
  View file @0f8a249
... ... @@ -99,8 +99,8 @@ static const int perm_table[2][8] = {
99 99 };
100 100  
101 101 int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
102   - int *access_index, target_ulong address, int rw,
103   - int is_user)
  102 + int *access_index, target_ulong address, int rw,
  103 + int is_user)
104 104 {
105 105 int access_perms = 0;
106 106 target_phys_addr_t pde_ptr;
... ... @@ -111,7 +111,7 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
111 111  
112 112 virt_addr = address & TARGET_PAGE_MASK;
113 113 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
114   - *physical = address;
  114 + *physical = address;
115 115 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
116 116 return 0;
117 117 }
... ... @@ -128,70 +128,70 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
128 128 switch (pde & PTE_ENTRYTYPE_MASK) {
129 129 default:
130 130 case 0: /* Invalid */
131   - return 1 << 2;
  131 + return 1 << 2;
132 132 case 2: /* L0 PTE, maybe should not happen? */
133 133 case 3: /* Reserved */
134 134 return 4 << 2;
135 135 case 1: /* L0 PDE */
136   - pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
  136 + pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
137 137 pde = ldl_phys(pde_ptr);
138 138  
139   - switch (pde & PTE_ENTRYTYPE_MASK) {
140   - default:
141   - case 0: /* Invalid */
142   - return (1 << 8) | (1 << 2);
143   - case 3: /* Reserved */
144   - return (1 << 8) | (4 << 2);
145   - case 1: /* L1 PDE */
146   - pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
  139 + switch (pde & PTE_ENTRYTYPE_MASK) {
  140 + default:
  141 + case 0: /* Invalid */
  142 + return (1 << 8) | (1 << 2);
  143 + case 3: /* Reserved */
  144 + return (1 << 8) | (4 << 2);
  145 + case 1: /* L1 PDE */
  146 + pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
147 147 pde = ldl_phys(pde_ptr);
148 148  
149   - switch (pde & PTE_ENTRYTYPE_MASK) {
150   - default:
151   - case 0: /* Invalid */
152   - return (2 << 8) | (1 << 2);
153   - case 3: /* Reserved */
154   - return (2 << 8) | (4 << 2);
155   - case 1: /* L2 PDE */
156   - pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
  149 + switch (pde & PTE_ENTRYTYPE_MASK) {
  150 + default:
  151 + case 0: /* Invalid */
  152 + return (2 << 8) | (1 << 2);
  153 + case 3: /* Reserved */
  154 + return (2 << 8) | (4 << 2);
  155 + case 1: /* L2 PDE */
  156 + pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
157 157 pde = ldl_phys(pde_ptr);
158 158  
159   - switch (pde & PTE_ENTRYTYPE_MASK) {
160   - default:
161   - case 0: /* Invalid */
162   - return (3 << 8) | (1 << 2);
163   - case 1: /* PDE, should not happen */
164   - case 3: /* Reserved */
165   - return (3 << 8) | (4 << 2);
166   - case 2: /* L3 PTE */
167   - virt_addr = address & TARGET_PAGE_MASK;
168   - page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
169   - }
170   - break;
171   - case 2: /* L2 PTE */
172   - virt_addr = address & ~0x3ffff;
173   - page_offset = address & 0x3ffff;
174   - }
175   - break;
176   - case 2: /* L1 PTE */
177   - virt_addr = address & ~0xffffff;
178   - page_offset = address & 0xffffff;
179   - }
  159 + switch (pde & PTE_ENTRYTYPE_MASK) {
  160 + default:
  161 + case 0: /* Invalid */
  162 + return (3 << 8) | (1 << 2);
  163 + case 1: /* PDE, should not happen */
  164 + case 3: /* Reserved */
  165 + return (3 << 8) | (4 << 2);
  166 + case 2: /* L3 PTE */
  167 + virt_addr = address & TARGET_PAGE_MASK;
  168 + page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
  169 + }
  170 + break;
  171 + case 2: /* L2 PTE */
  172 + virt_addr = address & ~0x3ffff;
  173 + page_offset = address & 0x3ffff;
  174 + }
  175 + break;
  176 + case 2: /* L1 PTE */
  177 + virt_addr = address & ~0xffffff;
  178 + page_offset = address & 0xffffff;
  179 + }
180 180 }
181 181  
182 182 /* update page modified and dirty bits */
183 183 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
184 184 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
185   - pde |= PG_ACCESSED_MASK;
186   - if (is_dirty)
187   - pde |= PG_MODIFIED_MASK;
  185 + pde |= PG_ACCESSED_MASK;
  186 + if (is_dirty)
  187 + pde |= PG_MODIFIED_MASK;
188 188 stl_phys_notdirty(pde_ptr, pde);
189 189 }
190 190 /* check access */
191 191 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
192 192 error_code = access_table[*access_index][access_perms];
193 193 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
194   - return error_code;
  194 + return error_code;
195 195  
196 196 /* the page can be put in the TLB */
197 197 *prot = perm_table[is_user][access_perms];
... ... @@ -217,18 +217,18 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
217 217  
218 218 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
219 219 if (error_code == 0) {
220   - vaddr = address & TARGET_PAGE_MASK;
221   - paddr &= TARGET_PAGE_MASK;
  220 + vaddr = address & TARGET_PAGE_MASK;
  221 + paddr &= TARGET_PAGE_MASK;
222 222 #ifdef DEBUG_MMU
223   - printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
  223 + printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
224 224 TARGET_FMT_lx "\n", address, paddr, vaddr);
225 225 #endif
226   - ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
227   - return ret;
  226 + ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
  227 + return ret;
228 228 }
229 229  
230 230 if (env->mmuregs[3]) /* Fault status register */
231   - env->mmuregs[3] = 1; /* overflow (not read before another fault) */
  231 + env->mmuregs[3] = 1; /* overflow (not read before another fault) */
232 232 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
233 233 env->mmuregs[4] = address; /* Fault address register */
234 234  
... ... @@ -237,10 +237,10 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
237 237 // permissions. If no mapping is available, redirect accesses to
238 238 // neverland. Fake/overridden mappings will be flushed when
239 239 // switching to normal mode.
240   - vaddr = address & TARGET_PAGE_MASK;
  240 + vaddr = address & TARGET_PAGE_MASK;
241 241 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
242 242 ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
243   - return ret;
  243 + return ret;
244 244 } else {
245 245 if (rw & 2)
246 246 env->exception_index = TT_TFAULT;
... ... @@ -265,50 +265,50 @@ target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
265 265 case 0: /* Invalid */
266 266 case 2: /* PTE, maybe should not happen? */
267 267 case 3: /* Reserved */
268   - return 0;
  268 + return 0;
269 269 case 1: /* L1 PDE */
270   - if (mmulev == 3)
271   - return pde;
272   - pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
  270 + if (mmulev == 3)
  271 + return pde;
  272 + pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
273 273 pde = ldl_phys(pde_ptr);
274 274  
275   - switch (pde & PTE_ENTRYTYPE_MASK) {
276   - default:
277   - case 0: /* Invalid */
278   - case 3: /* Reserved */
279   - return 0;
280   - case 2: /* L1 PTE */
281   - return pde;
282   - case 1: /* L2 PDE */
283   - if (mmulev == 2)
284   - return pde;
285   - pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
  275 + switch (pde & PTE_ENTRYTYPE_MASK) {
  276 + default:
  277 + case 0: /* Invalid */
  278 + case 3: /* Reserved */
  279 + return 0;
  280 + case 2: /* L1 PTE */
  281 + return pde;
  282 + case 1: /* L2 PDE */
  283 + if (mmulev == 2)
  284 + return pde;
  285 + pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
286 286 pde = ldl_phys(pde_ptr);
287 287  
288   - switch (pde & PTE_ENTRYTYPE_MASK) {
289   - default:
290   - case 0: /* Invalid */
291   - case 3: /* Reserved */
292   - return 0;
293   - case 2: /* L2 PTE */
294   - return pde;
295   - case 1: /* L3 PDE */
296   - if (mmulev == 1)
297   - return pde;
298   - pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
  288 + switch (pde & PTE_ENTRYTYPE_MASK) {
  289 + default:
  290 + case 0: /* Invalid */
  291 + case 3: /* Reserved */
  292 + return 0;
  293 + case 2: /* L2 PTE */
  294 + return pde;
  295 + case 1: /* L3 PDE */
  296 + if (mmulev == 1)
  297 + return pde;
  298 + pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
299 299 pde = ldl_phys(pde_ptr);
300 300  
301   - switch (pde & PTE_ENTRYTYPE_MASK) {
302   - default:
303   - case 0: /* Invalid */
304   - case 1: /* PDE, should not happen */
305   - case 3: /* Reserved */
306   - return 0;
307   - case 2: /* L3 PTE */
308   - return pde;
309   - }
310   - }
311   - }
  301 + switch (pde & PTE_ENTRYTYPE_MASK) {
  302 + default:
  303 + case 0: /* Invalid */
  304 + case 1: /* PDE, should not happen */
  305 + case 3: /* Reserved */
  306 + return 0;
  307 + case 2: /* L3 PTE */
  308 + return pde;
  309 + }
  310 + }
  311 + }
312 312 }
313 313 return 0;
314 314 }
... ... @@ -327,29 +327,29 @@ void dump_mmu(CPUState *env)
327 327 printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
328 328 (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
329 329 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
330   - pde = mmu_probe(env, va, 2);
331   - if (pde) {
332   - pa = cpu_get_phys_page_debug(env, va);
333   - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
  330 + pde = mmu_probe(env, va, 2);
  331 + if (pde) {
  332 + pa = cpu_get_phys_page_debug(env, va);
  333 + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
334 334 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
335   - for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
336   - pde = mmu_probe(env, va1, 1);
337   - if (pde) {
338   - pa = cpu_get_phys_page_debug(env, va1);
339   - printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
  335 + for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
  336 + pde = mmu_probe(env, va1, 1);
  337 + if (pde) {
  338 + pa = cpu_get_phys_page_debug(env, va1);
  339 + printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
340 340 " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
341   - for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
342   - pde = mmu_probe(env, va2, 0);
343   - if (pde) {
344   - pa = cpu_get_phys_page_debug(env, va2);
345   - printf(" VA: " TARGET_FMT_lx ", PA: "
  341 + for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
  342 + pde = mmu_probe(env, va2, 0);
  343 + if (pde) {
  344 + pa = cpu_get_phys_page_debug(env, va2);
  345 + printf(" VA: " TARGET_FMT_lx ", PA: "
346 346 TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
347 347 va2, pa, pde);
348   - }
349   - }
350   - }
351   - }
352   - }
  348 + }
  349 + }
  350 + }
  351 + }
  352 + }
353 353 }
354 354 printf("MMU dump ends\n");
355 355 }
... ... @@ -360,57 +360,57 @@ void dump_mmu(CPUState *env)
360 360 * UltraSparc IIi I/DMMUs
361 361 */
362 362 static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
363   - int *access_index, target_ulong address, int rw,
364   - int is_user)
  363 + int *access_index, target_ulong address, int rw,
  364 + int is_user)
365 365 {
366 366 target_ulong mask;
367 367 unsigned int i;
368 368  
369 369 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
370   - *physical = address;
371   - *prot = PAGE_READ | PAGE_WRITE;
  370 + *physical = address;
  371 + *prot = PAGE_READ | PAGE_WRITE;
372 372 return 0;
373 373 }
374 374  
375 375 for (i = 0; i < 64; i++) {
376   - switch ((env->dtlb_tte[i] >> 61) & 3) {
377   - default:
378   - case 0x0: // 8k
379   - mask = 0xffffffffffffe000ULL;
380   - break;
381   - case 0x1: // 64k
382   - mask = 0xffffffffffff0000ULL;
383   - break;
384   - case 0x2: // 512k
385   - mask = 0xfffffffffff80000ULL;
386   - break;
387   - case 0x3: // 4M
388   - mask = 0xffffffffffc00000ULL;
389   - break;
390   - }
391   - // ctx match, vaddr match?
392   - if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
393   - (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
394   - // valid, access ok?
395   - if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
396   - ((env->dtlb_tte[i] & 0x4) && is_user) ||
397   - (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
398   - if (env->dmmuregs[3]) /* Fault status register */
399   - env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
400   - env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
401   - env->dmmuregs[4] = address; /* Fault address register */
402   - env->exception_index = TT_DFAULT;
  376 + switch ((env->dtlb_tte[i] >> 61) & 3) {
  377 + default:
  378 + case 0x0: // 8k
  379 + mask = 0xffffffffffffe000ULL;
  380 + break;
  381 + case 0x1: // 64k
  382 + mask = 0xffffffffffff0000ULL;
  383 + break;
  384 + case 0x2: // 512k
  385 + mask = 0xfffffffffff80000ULL;
  386 + break;
  387 + case 0x3: // 4M
  388 + mask = 0xffffffffffc00000ULL;
  389 + break;
  390 + }
  391 + // ctx match, vaddr match?
  392 + if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
  393 + (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
  394 + // valid, access ok?
  395 + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
  396 + ((env->dtlb_tte[i] & 0x4) && is_user) ||
  397 + (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
  398 + if (env->dmmuregs[3]) /* Fault status register */
  399 + env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
  400 + env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
  401 + env->dmmuregs[4] = address; /* Fault address register */
  402 + env->exception_index = TT_DFAULT;
403 403 #ifdef DEBUG_MMU
404   - printf("DFAULT at 0x%" PRIx64 "\n", address);
  404 + printf("DFAULT at 0x%" PRIx64 "\n", address);
405 405 #endif
406   - return 1;
407   - }
408   - *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
409   - *prot = PAGE_READ;
410   - if (env->dtlb_tte[i] & 0x2)
411   - *prot |= PAGE_WRITE;
412   - return 0;
413   - }
  406 + return 1;
  407 + }
  408 + *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
  409 + *prot = PAGE_READ;
  410 + if (env->dtlb_tte[i] & 0x2)
  411 + *prot |= PAGE_WRITE;
  412 + return 0;
  413 + }
414 414 }
415 415 #ifdef DEBUG_MMU
416 416 printf("DMISS at 0x%" PRIx64 "\n", address);
... ... @@ -420,53 +420,53 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
420 420 }
421 421  
422 422 static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
423   - int *access_index, target_ulong address, int rw,
424   - int is_user)
  423 + int *access_index, target_ulong address, int rw,
  424 + int is_user)
425 425 {
426 426 target_ulong mask;
427 427 unsigned int i;
428 428  
429 429 if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
430   - *physical = address;
431   - *prot = PAGE_EXEC;
  430 + *physical = address;
  431 + *prot = PAGE_EXEC;
432 432 return 0;
433 433 }
434 434  
435 435 for (i = 0; i < 64; i++) {
436   - switch ((env->itlb_tte[i] >> 61) & 3) {
437   - default:
438   - case 0x0: // 8k
439   - mask = 0xffffffffffffe000ULL;
440   - break;
441   - case 0x1: // 64k
442   - mask = 0xffffffffffff0000ULL;
443   - break;
444   - case 0x2: // 512k
445   - mask = 0xfffffffffff80000ULL;
446   - break;
447   - case 0x3: // 4M
448   - mask = 0xffffffffffc00000ULL;
449   - break;
450   - }
451   - // ctx match, vaddr match?
452   - if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
453   - (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
454   - // valid, access ok?
455   - if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
456   - ((env->itlb_tte[i] & 0x4) && is_user)) {
457   - if (env->immuregs[3]) /* Fault status register */
458   - env->immuregs[3] = 2; /* overflow (not read before another fault) */
459   - env->immuregs[3] |= (is_user << 3) | 1;
460   - env->exception_index = TT_TFAULT;
  436 + switch ((env->itlb_tte[i] >> 61) & 3) {
  437 + default:
  438 + case 0x0: // 8k
  439 + mask = 0xffffffffffffe000ULL;
  440 + break;
  441 + case 0x1: // 64k
  442 + mask = 0xffffffffffff0000ULL;
  443 + break;
  444 + case 0x2: // 512k
  445 + mask = 0xfffffffffff80000ULL;
  446 + break;
  447 + case 0x3: // 4M
  448 + mask = 0xffffffffffc00000ULL;
  449 + break;
  450 + }
  451 + // ctx match, vaddr match?
  452 + if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
  453 + (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
  454 + // valid, access ok?
  455 + if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
  456 + ((env->itlb_tte[i] & 0x4) && is_user)) {
  457 + if (env->immuregs[3]) /* Fault status register */
  458 + env->immuregs[3] = 2; /* overflow (not read before another fault) */
  459 + env->immuregs[3] |= (is_user << 3) | 1;
  460 + env->exception_index = TT_TFAULT;
461 461 #ifdef DEBUG_MMU
462   - printf("TFAULT at 0x%" PRIx64 "\n", address);
  462 + printf("TFAULT at 0x%" PRIx64 "\n", address);
463 463 #endif
464   - return 1;
465   - }
466   - *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
467   - *prot = PAGE_EXEC;
468   - return 0;
469   - }
  464 + return 1;
  465 + }
  466 + *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
  467 + *prot = PAGE_EXEC;
  468 + return 0;
  469 + }
470 470 }
471 471 #ifdef DEBUG_MMU
472 472 printf("TMISS at 0x%" PRIx64 "\n", address);
... ... @@ -476,13 +476,13 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical
476 476 }
477 477  
478 478 int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
479   - int *access_index, target_ulong address, int rw,
480   - int is_user)
  479 + int *access_index, target_ulong address, int rw,
  480 + int is_user)
481 481 {
482 482 if (rw == 2)
483   - return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
  483 + return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
484 484 else
485   - return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
  485 + return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
486 486 }
487 487  
488 488 /* Perform address translation */
... ... @@ -495,13 +495,13 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
495 495  
496 496 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
497 497 if (error_code == 0) {
498   - virt_addr = address & TARGET_PAGE_MASK;
499   - vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
  498 + virt_addr = address & TARGET_PAGE_MASK;
  499 + vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
500 500 #ifdef DEBUG_MMU
501   - printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
  501 + printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
502 502 #endif
503   - ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
504   - return ret;
  503 + ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
  504 + return ret;
505 505 }
506 506 // XXX
507 507 return 1;
... ... @@ -515,67 +515,67 @@ void dump_mmu(CPUState *env)
515 515  
516 516 printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
517 517 if ((env->lsu & DMMU_E) == 0) {
518   - printf("DMMU disabled\n");
  518 + printf("DMMU disabled\n");
519 519 } else {
520   - printf("DMMU dump:\n");
521   - for (i = 0; i < 64; i++) {
522   - switch ((env->dtlb_tte[i] >> 61) & 3) {
523   - default:
524   - case 0x0:
525   - mask = " 8k";
526   - break;
527   - case 0x1:
528   - mask = " 64k";
529   - break;
530   - case 0x2:
531   - mask = "512k";
532   - break;
533   - case 0x3:
534   - mask = " 4M";
535   - break;
536   - }
537   - if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
538   - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
539   - env->dtlb_tag[i] & ~0x1fffULL,
540   - env->dtlb_tte[i] & 0x1ffffffe000ULL,
541   - mask,
542   - env->dtlb_tte[i] & 0x4? "priv": "user",
543   - env->dtlb_tte[i] & 0x2? "RW": "RO",
544   - env->dtlb_tte[i] & 0x40? "locked": "unlocked",
545   - env->dtlb_tag[i] & 0x1fffULL);
546   - }
547   - }
  520 + printf("DMMU dump:\n");
  521 + for (i = 0; i < 64; i++) {
  522 + switch ((env->dtlb_tte[i] >> 61) & 3) {
  523 + default:
  524 + case 0x0:
  525 + mask = " 8k";
  526 + break;
  527 + case 0x1:
  528 + mask = " 64k";
  529 + break;
  530 + case 0x2:
  531 + mask = "512k";
  532 + break;
  533 + case 0x3:
  534 + mask = " 4M";
  535 + break;
  536 + }
  537 + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
  538 + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
  539 + env->dtlb_tag[i] & ~0x1fffULL,
  540 + env->dtlb_tte[i] & 0x1ffffffe000ULL,
  541 + mask,
  542 + env->dtlb_tte[i] & 0x4? "priv": "user",
  543 + env->dtlb_tte[i] & 0x2? "RW": "RO",
  544 + env->dtlb_tte[i] & 0x40? "locked": "unlocked",
  545 + env->dtlb_tag[i] & 0x1fffULL);
  546 + }
  547 + }
548 548 }
549 549 if ((env->lsu & IMMU_E) == 0) {
550   - printf("IMMU disabled\n");
  550 + printf("IMMU disabled\n");
551 551 } else {
552   - printf("IMMU dump:\n");
553   - for (i = 0; i < 64; i++) {
554   - switch ((env->itlb_tte[i] >> 61) & 3) {
555   - default:
556   - case 0x0:
557   - mask = " 8k";
558   - break;
559   - case 0x1:
560   - mask = " 64k";
561   - break;
562   - case 0x2:
563   - mask = "512k";
564   - break;
565   - case 0x3:
566   - mask = " 4M";
567   - break;
568   - }
569   - if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
570   - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
571   - env->itlb_tag[i] & ~0x1fffULL,
572   - env->itlb_tte[i] & 0x1ffffffe000ULL,
573   - mask,
574   - env->itlb_tte[i] & 0x4? "priv": "user",
575   - env->itlb_tte[i] & 0x40? "locked": "unlocked",
576   - env->itlb_tag[i] & 0x1fffULL);
577   - }
578   - }
  552 + printf("IMMU dump:\n");
  553 + for (i = 0; i < 64; i++) {
  554 + switch ((env->itlb_tte[i] >> 61) & 3) {
  555 + default:
  556 + case 0x0:
  557 + mask = " 8k";
  558 + break;
  559 + case 0x1:
  560 + mask = " 64k";
  561 + break;
  562 + case 0x2:
  563 + mask = "512k";
  564 + break;
  565 + case 0x3:
  566 + mask = " 4M";
  567 + break;
  568 + }
  569 + if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
  570 + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
  571 + env->itlb_tag[i] & ~0x1fffULL,
  572 + env->itlb_tte[i] & 0x1ffffffe000ULL,
  573 + mask,
  574 + env->itlb_tte[i] & 0x4? "priv": "user",
  575 + env->itlb_tte[i] & 0x40? "locked": "unlocked",
  576 + env->itlb_tag[i] & 0x1fffULL);
  577 + }
  578 + }
579 579 }
580 580 }
581 581 #endif /* DEBUG_MMU */
... ...
target-sparc/op.c
  View file @0f8a249
... ... @@ -376,33 +376,33 @@ void OPPROTO op_add_T1_T0_cc(void)
376 376 env->psr = 0;
377 377 #ifdef TARGET_SPARC64
378 378 if (!(T0 & 0xffffffff))
379   - env->psr |= PSR_ZERO;
  379 + env->psr |= PSR_ZERO;
380 380 if ((int32_t) T0 < 0)
381   - env->psr |= PSR_NEG;
  381 + env->psr |= PSR_NEG;
382 382 if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
383   - env->psr |= PSR_CARRY;
  383 + env->psr |= PSR_CARRY;
384 384 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
385   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
386   - env->psr |= PSR_OVF;
  385 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  386 + env->psr |= PSR_OVF;
387 387  
388 388 env->xcc = 0;
389 389 if (!T0)
390   - env->xcc |= PSR_ZERO;
  390 + env->xcc |= PSR_ZERO;
391 391 if ((int64_t) T0 < 0)
392   - env->xcc |= PSR_NEG;
  392 + env->xcc |= PSR_NEG;
393 393 if (T0 < src1)
394   - env->xcc |= PSR_CARRY;
  394 + env->xcc |= PSR_CARRY;
395 395 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
396   - env->xcc |= PSR_OVF;
  396 + env->xcc |= PSR_OVF;
397 397 #else
398 398 if (!T0)
399   - env->psr |= PSR_ZERO;
  399 + env->psr |= PSR_ZERO;
400 400 if ((int32_t) T0 < 0)
401   - env->psr |= PSR_NEG;
  401 + env->psr |= PSR_NEG;
402 402 if (T0 < src1)
403   - env->psr |= PSR_CARRY;
  403 + env->psr |= PSR_CARRY;
404 404 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
405   - env->psr |= PSR_OVF;
  405 + env->psr |= PSR_OVF;
406 406 #endif
407 407 FORCE_RET();
408 408 }
... ... @@ -448,26 +448,26 @@ void OPPROTO op_addx_T1_T0_cc(void)
448 448 }
449 449 #ifdef TARGET_SPARC64
450 450 if (!(T0 & 0xffffffff))
451   - env->psr |= PSR_ZERO;
  451 + env->psr |= PSR_ZERO;
452 452 if ((int32_t) T0 < 0)
453   - env->psr |= PSR_NEG;
  453 + env->psr |= PSR_NEG;
454 454 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
455   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
456   - env->psr |= PSR_OVF;
  455 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  456 + env->psr |= PSR_OVF;
457 457  
458 458 if (!T0)
459   - env->xcc |= PSR_ZERO;
  459 + env->xcc |= PSR_ZERO;
460 460 if ((int64_t) T0 < 0)
461   - env->xcc |= PSR_NEG;
  461 + env->xcc |= PSR_NEG;
462 462 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
463   - env->xcc |= PSR_OVF;
  463 + env->xcc |= PSR_OVF;
464 464 #else
465 465 if (!T0)
466   - env->psr |= PSR_ZERO;
  466 + env->psr |= PSR_ZERO;
467 467 if ((int32_t) T0 < 0)
468   - env->psr |= PSR_NEG;
  468 + env->psr |= PSR_NEG;
469 469 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
470   - env->psr |= PSR_OVF;
  470 + env->psr |= PSR_OVF;
471 471 #endif
472 472 FORCE_RET();
473 473 }
... ... @@ -481,37 +481,37 @@ void OPPROTO op_tadd_T1_T0_cc(void)
481 481 env->psr = 0;
482 482 #ifdef TARGET_SPARC64
483 483 if (!(T0 & 0xffffffff))
484   - env->psr |= PSR_ZERO;
  484 + env->psr |= PSR_ZERO;
485 485 if ((int32_t) T0 < 0)
486   - env->psr |= PSR_NEG;
  486 + env->psr |= PSR_NEG;
487 487 if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
488   - env->psr |= PSR_CARRY;
  488 + env->psr |= PSR_CARRY;
489 489 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
490   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
491   - env->psr |= PSR_OVF;
  490 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  491 + env->psr |= PSR_OVF;
492 492 if ((src1 & 0x03) || (T1 & 0x03))
493   - env->psr |= PSR_OVF;
  493 + env->psr |= PSR_OVF;
494 494  
495 495 env->xcc = 0;
496 496 if (!T0)
497   - env->xcc |= PSR_ZERO;
  497 + env->xcc |= PSR_ZERO;
498 498 if ((int64_t) T0 < 0)
499   - env->xcc |= PSR_NEG;
  499 + env->xcc |= PSR_NEG;
500 500 if (T0 < src1)
501   - env->xcc |= PSR_CARRY;
  501 + env->xcc |= PSR_CARRY;
502 502 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
503   - env->xcc |= PSR_OVF;
  503 + env->xcc |= PSR_OVF;
504 504 #else
505 505 if (!T0)
506   - env->psr |= PSR_ZERO;
  506 + env->psr |= PSR_ZERO;
507 507 if ((int32_t) T0 < 0)
508   - env->psr |= PSR_NEG;
  508 + env->psr |= PSR_NEG;
509 509 if (T0 < src1)
510   - env->psr |= PSR_CARRY;
  510 + env->psr |= PSR_CARRY;
511 511 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
512   - env->psr |= PSR_OVF;
  512 + env->psr |= PSR_OVF;
513 513 if ((src1 & 0x03) || (T1 & 0x03))
514   - env->psr |= PSR_OVF;
  514 + env->psr |= PSR_OVF;
515 515 #endif
516 516 FORCE_RET();
517 517 }
... ... @@ -528,7 +528,7 @@ void OPPROTO op_tadd_T1_T0_ccTV(void)
528 528  
529 529 #ifdef TARGET_SPARC64
530 530 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
531   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  531 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
532 532 raise_exception(TT_TOVF);
533 533 #else
534 534 if ((src1 & 0x03) || (T1 & 0x03))
... ... @@ -538,26 +538,26 @@ void OPPROTO op_tadd_T1_T0_ccTV(void)
538 538 env->psr = 0;
539 539 #ifdef TARGET_SPARC64
540 540 if (!(T0 & 0xffffffff))
541   - env->psr |= PSR_ZERO;
  541 + env->psr |= PSR_ZERO;
542 542 if ((int32_t) T0 < 0)
543   - env->psr |= PSR_NEG;
  543 + env->psr |= PSR_NEG;
544 544 if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
545   - env->psr |= PSR_CARRY;
  545 + env->psr |= PSR_CARRY;
546 546  
547 547 env->xcc = 0;
548 548 if (!T0)
549   - env->xcc |= PSR_ZERO;
  549 + env->xcc |= PSR_ZERO;
550 550 if ((int64_t) T0 < 0)
551   - env->xcc |= PSR_NEG;
  551 + env->xcc |= PSR_NEG;
552 552 if (T0 < src1)
553   - env->xcc |= PSR_CARRY;
  553 + env->xcc |= PSR_CARRY;
554 554 #else
555 555 if (!T0)
556   - env->psr |= PSR_ZERO;
  556 + env->psr |= PSR_ZERO;
557 557 if ((int32_t) T0 < 0)
558   - env->psr |= PSR_NEG;
  558 + env->psr |= PSR_NEG;
559 559 if (T0 < src1)
560   - env->psr |= PSR_CARRY;
  560 + env->psr |= PSR_CARRY;
561 561 #endif
562 562 FORCE_RET();
563 563 }
... ... @@ -576,33 +576,33 @@ void OPPROTO op_sub_T1_T0_cc(void)
576 576 env->psr = 0;
577 577 #ifdef TARGET_SPARC64
578 578 if (!(T0 & 0xffffffff))
579   - env->psr |= PSR_ZERO;
  579 + env->psr |= PSR_ZERO;
580 580 if ((int32_t) T0 < 0)
581   - env->psr |= PSR_NEG;
  581 + env->psr |= PSR_NEG;
582 582 if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
583   - env->psr |= PSR_CARRY;
  583 + env->psr |= PSR_CARRY;
584 584 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
585   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
586   - env->psr |= PSR_OVF;
  585 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  586 + env->psr |= PSR_OVF;
587 587  
588 588 env->xcc = 0;
589 589 if (!T0)
590   - env->xcc |= PSR_ZERO;
  590 + env->xcc |= PSR_ZERO;
591 591 if ((int64_t) T0 < 0)
592   - env->xcc |= PSR_NEG;
  592 + env->xcc |= PSR_NEG;
593 593 if (src1 < T1)
594   - env->xcc |= PSR_CARRY;
  594 + env->xcc |= PSR_CARRY;
595 595 if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
596   - env->xcc |= PSR_OVF;
  596 + env->xcc |= PSR_OVF;
597 597 #else
598 598 if (!T0)
599   - env->psr |= PSR_ZERO;
  599 + env->psr |= PSR_ZERO;
600 600 if ((int32_t) T0 < 0)
601   - env->psr |= PSR_NEG;
  601 + env->psr |= PSR_NEG;
602 602 if (src1 < T1)
603   - env->psr |= PSR_CARRY;
  603 + env->psr |= PSR_CARRY;
604 604 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
605   - env->psr |= PSR_OVF;
  605 + env->psr |= PSR_OVF;
606 606 #endif
607 607 FORCE_RET();
608 608 }
... ... @@ -648,26 +648,26 @@ void OPPROTO op_subx_T1_T0_cc(void)
648 648 }
649 649 #ifdef TARGET_SPARC64
650 650 if (!(T0 & 0xffffffff))
651   - env->psr |= PSR_ZERO;
  651 + env->psr |= PSR_ZERO;
652 652 if ((int32_t) T0 < 0)
653   - env->psr |= PSR_NEG;
  653 + env->psr |= PSR_NEG;
654 654 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
655   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
656   - env->psr |= PSR_OVF;
  655 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  656 + env->psr |= PSR_OVF;
657 657  
658 658 if (!T0)
659   - env->xcc |= PSR_ZERO;
  659 + env->xcc |= PSR_ZERO;
660 660 if ((int64_t) T0 < 0)
661   - env->xcc |= PSR_NEG;
  661 + env->xcc |= PSR_NEG;
662 662 if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
663   - env->xcc |= PSR_OVF;
  663 + env->xcc |= PSR_OVF;
664 664 #else
665 665 if (!T0)
666   - env->psr |= PSR_ZERO;
  666 + env->psr |= PSR_ZERO;
667 667 if ((int32_t) T0 < 0)
668   - env->psr |= PSR_NEG;
  668 + env->psr |= PSR_NEG;
669 669 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
670   - env->psr |= PSR_OVF;
  670 + env->psr |= PSR_OVF;
671 671 #endif
672 672 FORCE_RET();
673 673 }
... ... @@ -681,37 +681,37 @@ void OPPROTO op_tsub_T1_T0_cc(void)
681 681 env->psr = 0;
682 682 #ifdef TARGET_SPARC64
683 683 if (!(T0 & 0xffffffff))
684   - env->psr |= PSR_ZERO;
  684 + env->psr |= PSR_ZERO;
685 685 if ((int32_t) T0 < 0)
686   - env->psr |= PSR_NEG;
  686 + env->psr |= PSR_NEG;
687 687 if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
688   - env->psr |= PSR_CARRY;
  688 + env->psr |= PSR_CARRY;
689 689 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
690   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
691   - env->psr |= PSR_OVF;
  690 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  691 + env->psr |= PSR_OVF;
692 692 if ((src1 & 0x03) || (T1 & 0x03))
693   - env->psr |= PSR_OVF;
  693 + env->psr |= PSR_OVF;
694 694  
695 695 env->xcc = 0;
696 696 if (!T0)
697   - env->xcc |= PSR_ZERO;
  697 + env->xcc |= PSR_ZERO;
698 698 if ((int64_t) T0 < 0)
699   - env->xcc |= PSR_NEG;
  699 + env->xcc |= PSR_NEG;
700 700 if (src1 < T1)
701   - env->xcc |= PSR_CARRY;
  701 + env->xcc |= PSR_CARRY;
702 702 if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
703   - env->xcc |= PSR_OVF;
  703 + env->xcc |= PSR_OVF;
704 704 #else
705 705 if (!T0)
706   - env->psr |= PSR_ZERO;
  706 + env->psr |= PSR_ZERO;
707 707 if ((int32_t) T0 < 0)
708   - env->psr |= PSR_NEG;
  708 + env->psr |= PSR_NEG;
709 709 if (src1 < T1)
710   - env->psr |= PSR_CARRY;
  710 + env->psr |= PSR_CARRY;
711 711 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
712   - env->psr |= PSR_OVF;
  712 + env->psr |= PSR_OVF;
713 713 if ((src1 & 0x03) || (T1 & 0x03))
714   - env->psr |= PSR_OVF;
  714 + env->psr |= PSR_OVF;
715 715 #endif
716 716 FORCE_RET();
717 717 }
... ... @@ -728,7 +728,7 @@ void OPPROTO op_tsub_T1_T0_ccTV(void)
728 728  
729 729 #ifdef TARGET_SPARC64
730 730 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
731   - ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
  731 + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
732 732 raise_exception(TT_TOVF);
733 733 #else
734 734 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
... ... @@ -738,26 +738,26 @@ void OPPROTO op_tsub_T1_T0_ccTV(void)
738 738 env->psr = 0;
739 739 #ifdef TARGET_SPARC64
740 740 if (!(T0 & 0xffffffff))
741   - env->psr |= PSR_ZERO;
  741 + env->psr |= PSR_ZERO;
742 742 if ((int32_t) T0 < 0)
743   - env->psr |= PSR_NEG;
  743 + env->psr |= PSR_NEG;
744 744 if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
745   - env->psr |= PSR_CARRY;
  745 + env->psr |= PSR_CARRY;
746 746  
747 747 env->xcc = 0;
748 748 if (!T0)
749   - env->xcc |= PSR_ZERO;
  749 + env->xcc |= PSR_ZERO;
750 750 if ((int64_t) T0 < 0)
751   - env->xcc |= PSR_NEG;
  751 + env->xcc |= PSR_NEG;
752 752 if (src1 < T1)
753   - env->xcc |= PSR_CARRY;
  753 + env->xcc |= PSR_CARRY;
754 754 #else
755 755 if (!T0)
756   - env->psr |= PSR_ZERO;
  756 + env->psr |= PSR_ZERO;
757 757 if ((int32_t) T0 < 0)
758   - env->psr |= PSR_NEG;
  758 + env->psr |= PSR_NEG;
759 759 if (src1 < T1)
760   - env->psr |= PSR_CARRY;
  760 + env->psr |= PSR_CARRY;
761 761 #endif
762 762 FORCE_RET();
763 763 }
... ... @@ -833,13 +833,13 @@ void OPPROTO op_mulscc_T1_T0(void)
833 833 T0 += T1;
834 834 env->psr = 0;
835 835 if (!T0)
836   - env->psr |= PSR_ZERO;
  836 + env->psr |= PSR_ZERO;
837 837 if ((int32_t) T0 < 0)
838   - env->psr |= PSR_NEG;
  838 + env->psr |= PSR_NEG;
839 839 if (T0 < src1)
840   - env->psr |= PSR_CARRY;
  840 + env->psr |= PSR_CARRY;
841 841 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
842   - env->psr |= PSR_OVF;
  842 + env->psr |= PSR_OVF;
843 843 env->y = (b2 << 31) | (env->y >> 1);
844 844 FORCE_RET();
845 845 }
... ... @@ -858,11 +858,11 @@ void OPPROTO op_udiv_T1_T0(void)
858 858  
859 859 x0 = x0 / x1;
860 860 if (x0 > 0xffffffff) {
861   - T0 = 0xffffffff;
862   - T1 = 1;
  861 + T0 = 0xffffffff;
  862 + T1 = 1;
863 863 } else {
864   - T0 = x0;
865   - T1 = 0;
  864 + T0 = x0;
  865 + T1 = 0;
866 866 }
867 867 FORCE_RET();
868 868 }
... ... @@ -881,11 +881,11 @@ void OPPROTO op_sdiv_T1_T0(void)
881 881  
882 882 x0 = x0 / x1;
883 883 if ((int32_t) x0 != x0) {
884   - T0 = x0 < 0? 0x80000000: 0x7fffffff;
885   - T1 = 1;
  884 + T0 = x0 < 0? 0x80000000: 0x7fffffff;
  885 + T1 = 1;
886 886 } else {
887   - T0 = x0;
888   - T1 = 0;
  887 + T0 = x0;
  888 + T1 = 0;
889 889 }
890 890 FORCE_RET();
891 891 }
... ... @@ -895,24 +895,24 @@ void OPPROTO op_div_cc(void)
895 895 env->psr = 0;
896 896 #ifdef TARGET_SPARC64
897 897 if (!T0)
898   - env->psr |= PSR_ZERO;
  898 + env->psr |= PSR_ZERO;
899 899 if ((int32_t) T0 < 0)
900   - env->psr |= PSR_NEG;
  900 + env->psr |= PSR_NEG;
901 901 if (T1)
902   - env->psr |= PSR_OVF;
  902 + env->psr |= PSR_OVF;
903 903  
904 904 env->xcc = 0;
905 905 if (!T0)
906   - env->xcc |= PSR_ZERO;
  906 + env->xcc |= PSR_ZERO;
907 907 if ((int64_t) T0 < 0)
908   - env->xcc |= PSR_NEG;
  908 + env->xcc |= PSR_NEG;
909 909 #else
910 910 if (!T0)
911   - env->psr |= PSR_ZERO;
  911 + env->psr |= PSR_ZERO;
912 912 if ((int32_t) T0 < 0)
913   - env->psr |= PSR_NEG;
  913 + env->psr |= PSR_NEG;
914 914 if (T1)
915   - env->psr |= PSR_OVF;
  915 + env->psr |= PSR_OVF;
916 916 #endif
917 917 FORCE_RET();
918 918 }
... ... @@ -939,9 +939,9 @@ void OPPROTO op_sdivx_T1_T0(void)
939 939 raise_exception(TT_DIV_ZERO);
940 940 }
941 941 if (T0 == INT64_MIN && T1 == -1)
942   - T0 = INT64_MIN;
  942 + T0 = INT64_MIN;
943 943 else
944   - T0 /= (target_long) T1;
  944 + T0 /= (target_long) T1;
945 945 FORCE_RET();
946 946 }
947 947 #endif
... ... @@ -951,20 +951,20 @@ void OPPROTO op_logic_T0_cc(void)
951 951 env->psr = 0;
952 952 #ifdef TARGET_SPARC64
953 953 if (!(T0 & 0xffffffff))
954   - env->psr |= PSR_ZERO;
  954 + env->psr |= PSR_ZERO;
955 955 if ((int32_t) T0 < 0)
956   - env->psr |= PSR_NEG;
  956 + env->psr |= PSR_NEG;
957 957  
958 958 env->xcc = 0;
959 959 if (!T0)
960   - env->xcc |= PSR_ZERO;
  960 + env->xcc |= PSR_ZERO;
961 961 if ((int64_t) T0 < 0)
962   - env->xcc |= PSR_NEG;
  962 + env->xcc |= PSR_NEG;
963 963 #else
964 964 if (!T0)
965   - env->psr |= PSR_ZERO;
  965 + env->psr |= PSR_ZERO;
966 966 if ((int32_t) T0 < 0)
967   - env->psr |= PSR_NEG;
  967 + env->psr |= PSR_NEG;
968 968 #endif
969 969 FORCE_RET();
970 970 }
... ... @@ -1200,17 +1200,17 @@ void OPPROTO op_save(void)
1200 1200 cwp = (env->cwp - 1) & (NWINDOWS - 1);
1201 1201 if (env->cansave == 0) {
1202 1202 raise_exception(TT_SPILL | (env->otherwin != 0 ?
1203   - (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1204   - ((env->wstate & 0x7) << 2)));
  1203 + (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
  1204 + ((env->wstate & 0x7) << 2)));
1205 1205 } else {
1206   - if (env->cleanwin - env->canrestore == 0) {
1207   - // XXX Clean windows without trap
1208   - raise_exception(TT_CLRWIN);
1209   - } else {
1210   - env->cansave--;
1211   - env->canrestore++;
1212   - set_cwp(cwp);
1213   - }
  1206 + if (env->cleanwin - env->canrestore == 0) {
  1207 + // XXX Clean windows without trap
  1208 + raise_exception(TT_CLRWIN);
  1209 + } else {
  1210 + env->cansave--;
  1211 + env->canrestore++;
  1212 + set_cwp(cwp);
  1213 + }
1214 1214 }
1215 1215 FORCE_RET();
1216 1216 }
... ... @@ -1221,12 +1221,12 @@ void OPPROTO op_restore(void)
1221 1221 cwp = (env->cwp + 1) & (NWINDOWS - 1);
1222 1222 if (env->canrestore == 0) {
1223 1223 raise_exception(TT_FILL | (env->otherwin != 0 ?
1224   - (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1225   - ((env->wstate & 0x7) << 2)));
  1224 + (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
  1225 + ((env->wstate & 0x7) << 2)));
1226 1226 } else {
1227   - env->cansave++;
1228   - env->canrestore--;
1229   - set_cwp(cwp);
  1227 + env->cansave++;
  1228 + env->canrestore--;
  1229 + set_cwp(cwp);
1230 1230 }
1231 1231 FORCE_RET();
1232 1232 }
... ... @@ -1576,15 +1576,15 @@ void OPPROTO op_clear_ieee_excp_and_FTT(void)
1576 1576 #define F_BINOP(name) \
1577 1577 F_OP(name, s) \
1578 1578 { \
1579   - set_float_exception_flags(0, &env->fp_status); \
  1579 + set_float_exception_flags(0, &env->fp_status); \
1580 1580 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
1581   - check_ieee_exceptions(); \
  1581 + check_ieee_exceptions(); \
1582 1582 } \
1583 1583 F_OP(name, d) \
1584 1584 { \
1585   - set_float_exception_flags(0, &env->fp_status); \
  1585 + set_float_exception_flags(0, &env->fp_status); \
1586 1586 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
1587   - check_ieee_exceptions(); \
  1587 + check_ieee_exceptions(); \
1588 1588 }
1589 1589  
1590 1590 F_BINOP(add);
... ... @@ -1784,27 +1784,27 @@ void OPPROTO op_fdtox(void)
1784 1784 void OPPROTO op_fmovs_cc(void)
1785 1785 {
1786 1786 if (T2)
1787   - FT0 = FT1;
  1787 + FT0 = FT1;
1788 1788 }
1789 1789  
1790 1790 void OPPROTO op_fmovd_cc(void)
1791 1791 {
1792 1792 if (T2)
1793   - DT0 = DT1;
  1793 + DT0 = DT1;
1794 1794 }
1795 1795  
1796 1796 void OPPROTO op_mov_cc(void)
1797 1797 {
1798 1798 if (T2)
1799   - T0 = T1;
  1799 + T0 = T1;
1800 1800 }
1801 1801  
1802 1802 void OPPROTO op_flushw(void)
1803 1803 {
1804 1804 if (env->cansave != NWINDOWS - 2) {
1805 1805 raise_exception(TT_SPILL | (env->otherwin != 0 ?
1806   - (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1807   - ((env->wstate & 0x7) << 2)));
  1806 + (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
  1807 + ((env->wstate & 0x7) << 2)));
1808 1808 }
1809 1809 }
1810 1810  
... ... @@ -1812,9 +1812,9 @@ void OPPROTO op_saved(void)
1812 1812 {
1813 1813 env->cansave++;
1814 1814 if (env->otherwin == 0)
1815   - env->canrestore--;
  1815 + env->canrestore--;
1816 1816 else
1817   - env->otherwin--;
  1817 + env->otherwin--;
1818 1818 FORCE_RET();
1819 1819 }
1820 1820  
... ... @@ -1822,11 +1822,11 @@ void OPPROTO op_restored(void)
1822 1822 {
1823 1823 env->canrestore++;
1824 1824 if (env->cleanwin < NWINDOWS - 1)
1825   - env->cleanwin++;
  1825 + env->cleanwin++;
1826 1826 if (env->otherwin == 0)
1827   - env->cansave--;
  1827 + env->cansave--;
1828 1828 else
1829   - env->otherwin--;
  1829 + env->otherwin--;
1830 1830 FORCE_RET();
1831 1831 }
1832 1832  
... ...
target-sparc/op_helper.c
  View file @0f8a249
... ... @@ -16,29 +16,29 @@ void check_ieee_exceptions()
16 16 T0 = get_float_exception_flags(&env->fp_status);
17 17 if (T0)
18 18 {
19   - /* Copy IEEE 754 flags into FSR */
20   - if (T0 & float_flag_invalid)
21   - env->fsr |= FSR_NVC;
22   - if (T0 & float_flag_overflow)
23   - env->fsr |= FSR_OFC;
24   - if (T0 & float_flag_underflow)
25   - env->fsr |= FSR_UFC;
26   - if (T0 & float_flag_divbyzero)
27   - env->fsr |= FSR_DZC;
28   - if (T0 & float_flag_inexact)
29   - env->fsr |= FSR_NXC;
30   -
31   - if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
32   - {
33   - /* Unmasked exception, generate a trap */
34   - env->fsr |= FSR_FTT_IEEE_EXCP;
35   - raise_exception(TT_FP_EXCP);
36   - }
37   - else
38   - {
39   - /* Accumulate exceptions */
40   - env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
41   - }
  19 + /* Copy IEEE 754 flags into FSR */
  20 + if (T0 & float_flag_invalid)
  21 + env->fsr |= FSR_NVC;
  22 + if (T0 & float_flag_overflow)
  23 + env->fsr |= FSR_OFC;
  24 + if (T0 & float_flag_underflow)
  25 + env->fsr |= FSR_UFC;
  26 + if (T0 & float_flag_divbyzero)
  27 + env->fsr |= FSR_DZC;
  28 + if (T0 & float_flag_inexact)
  29 + env->fsr |= FSR_NXC;
  30 +
  31 + if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
  32 + {
  33 + /* Unmasked exception, generate a trap */
  34 + env->fsr |= FSR_FTT_IEEE_EXCP;
  35 + raise_exception(TT_FP_EXCP);
  36 + }
  37 + else
  38 + {
  39 + /* Accumulate exceptions */
  40 + env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
  41 + }
42 42 }
43 43 }
44 44  
... ... @@ -155,33 +155,33 @@ void helper_ld_asi(int asi, int size, int sign)
155 155 case 2: /* SuperSparc MXCC registers */
156 156 break;
157 157 case 3: /* MMU probe */
158   - {
159   - int mmulev;
160   -
161   - mmulev = (T0 >> 8) & 15;
162   - if (mmulev > 4)
163   - ret = 0;
164   - else {
165   - ret = mmu_probe(env, T0, mmulev);
166   - //bswap32s(&ret);
167   - }
  158 + {
  159 + int mmulev;
  160 +
  161 + mmulev = (T0 >> 8) & 15;
  162 + if (mmulev > 4)
  163 + ret = 0;
  164 + else {
  165 + ret = mmu_probe(env, T0, mmulev);
  166 + //bswap32s(&ret);
  167 + }
168 168 #ifdef DEBUG_MMU
169   - printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
  169 + printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
170 170 #endif
171   - }
172   - break;
  171 + }
  172 + break;
173 173 case 4: /* read MMU regs */
174   - {
175   - int reg = (T0 >> 8) & 0xf;
  174 + {
  175 + int reg = (T0 >> 8) & 0xf;
176 176  
177   - ret = env->mmuregs[reg];
178   - if (reg == 3) /* Fault status cleared on read */
179   - env->mmuregs[reg] = 0;
  177 + ret = env->mmuregs[reg];
  178 + if (reg == 3) /* Fault status cleared on read */
  179 + env->mmuregs[reg] = 0;
180 180 #ifdef DEBUG_MMU
181   - printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
  181 + printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
182 182 #endif
183   - }
184   - break;
  183 + }
  184 + break;
185 185 case 9: /* Supervisor code access */
186 186 switch(size) {
187 187 case 1:
... ... @@ -218,11 +218,11 @@ void helper_ld_asi(int asi, int size, int sign)
218 218 ret = ldl_phys(T0 & ~3);
219 219 break;
220 220 case 8:
221   - ret = ldl_phys(T0 & ~3);
222   - T0 = ldl_phys((T0 + 4) & ~3);
223   - break;
  221 + ret = ldl_phys(T0 & ~3);
  222 + T0 = ldl_phys((T0 + 4) & ~3);
  223 + break;
224 224 }
225   - break;
  225 + break;
226 226 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
227 227 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
228 228 switch(size) {
... ... @@ -244,14 +244,14 @@ void helper_ld_asi(int asi, int size, int sign)
244 244 | ((target_phys_addr_t)(asi & 0xf) << 32));
245 245 T0 = ldl_phys((target_phys_addr_t)((T0 + 4) & ~3)
246 246 | ((target_phys_addr_t)(asi & 0xf) << 32));
247   - break;
  247 + break;
248 248 }
249   - break;
  249 + break;
250 250 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
251 251 default:
252 252 do_unassigned_access(T0, 0, 0, 1);
253   - ret = 0;
254   - break;
  253 + ret = 0;
  254 + break;
255 255 }
256 256 T1 = ret;
257 257 }
... ... @@ -262,48 +262,48 @@ void helper_st_asi(int asi, int size, int sign)
262 262 case 2: /* SuperSparc MXCC registers */
263 263 break;
264 264 case 3: /* MMU flush */
265   - {
266   - int mmulev;
  265 + {
  266 + int mmulev;
267 267  
268   - mmulev = (T0 >> 8) & 15;
  268 + mmulev = (T0 >> 8) & 15;
269 269 #ifdef DEBUG_MMU
270   - printf("mmu flush level %d\n", mmulev);
  270 + printf("mmu flush level %d\n", mmulev);
271 271 #endif
272   - switch (mmulev) {
273   - case 0: // flush page
274   - tlb_flush_page(env, T0 & 0xfffff000);
275   - break;
276   - case 1: // flush segment (256k)
277   - case 2: // flush region (16M)
278   - case 3: // flush context (4G)
279   - case 4: // flush entire
280   - tlb_flush(env, 1);
281   - break;
282   - default:
283   - break;
284   - }
  272 + switch (mmulev) {
  273 + case 0: // flush page
  274 + tlb_flush_page(env, T0 & 0xfffff000);
  275 + break;
  276 + case 1: // flush segment (256k)
  277 + case 2: // flush region (16M)
  278 + case 3: // flush context (4G)
  279 + case 4: // flush entire
  280 + tlb_flush(env, 1);
  281 + break;
  282 + default:
  283 + break;
  284 + }
285 285 #ifdef DEBUG_MMU
286   - dump_mmu(env);
  286 + dump_mmu(env);
287 287 #endif
288   - return;
289   - }
  288 + return;
  289 + }
290 290 case 4: /* write MMU regs */
291   - {
292   - int reg = (T0 >> 8) & 0xf;
293   - uint32_t oldreg;
  291 + {
  292 + int reg = (T0 >> 8) & 0xf;
  293 + uint32_t oldreg;
294 294  
295   - oldreg = env->mmuregs[reg];
  295 + oldreg = env->mmuregs[reg];
296 296 switch(reg) {
297 297 case 0:
298   - env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
299   - env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
300   - // Mappings generated during no-fault mode or MMU
301   - // disabled mode are invalid in normal mode
  298 + env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
  299 + env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
  300 + // Mappings generated during no-fault mode or MMU
  301 + // disabled mode are invalid in normal mode
302 302 if (oldreg != env->mmuregs[reg])
303 303 tlb_flush(env, 1);
304 304 break;
305 305 case 2:
306   - env->mmuregs[reg] = T1;
  306 + env->mmuregs[reg] = T1;
307 307 if (oldreg != env->mmuregs[reg]) {
308 308 /* we flush when the MMU context changes because
309 309 QEMU has no MMU context support */
... ... @@ -314,17 +314,17 @@ void helper_st_asi(int asi, int size, int sign)
314 314 case 4:
315 315 break;
316 316 default:
317   - env->mmuregs[reg] = T1;
  317 + env->mmuregs[reg] = T1;
318 318 break;
319 319 }
320 320 #ifdef DEBUG_MMU
321 321 if (oldreg != env->mmuregs[reg]) {
322 322 printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
323 323 }
324   - dump_mmu(env);
  324 + dump_mmu(env);
325 325 #endif
326   - return;
327   - }
  326 + return;
  327 + }
328 328 case 0xc: /* I-cache tag */
329 329 case 0xd: /* I-cache data */
330 330 case 0xe: /* D-cache tag */
... ... @@ -336,10 +336,10 @@ void helper_st_asi(int asi, int size, int sign)
336 336 case 0x14: /* I/D-cache flush user */
337 337 break;
338 338 case 0x17: /* Block copy, sta access */
339   - {
340   - // value (T1) = src
341   - // address (T0) = dst
342   - // copy 32 bytes
  339 + {
  340 + // value (T1) = src
  341 + // address (T0) = dst
  342 + // copy 32 bytes
343 343 unsigned int i;
344 344 uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
345 345  
... ... @@ -347,13 +347,13 @@ void helper_st_asi(int asi, int size, int sign)
347 347 temp = ldl_kernel(src);
348 348 stl_kernel(dst, temp);
349 349 }
350   - }
351   - return;
  350 + }
  351 + return;
352 352 case 0x1f: /* Block fill, stda access */
353   - {
354   - // value (T1, T2)
355   - // address (T0) = dst
356   - // fill 32 bytes
  353 + {
  354 + // value (T1, T2)
  355 + // address (T0) = dst
  356 + // fill 32 bytes
357 357 unsigned int i;
358 358 uint32_t dst = T0 & 7;
359 359 uint64_t val;
... ... @@ -362,10 +362,10 @@ void helper_st_asi(int asi, int size, int sign)
362 362  
363 363 for (i = 0; i < 32; i += 8, dst += 8)
364 364 stq_kernel(dst, val);
365   - }
366   - return;
  365 + }
  366 + return;
367 367 case 0x20: /* MMU passthrough */
368   - {
  368 + {
369 369 switch(size) {
370 370 case 1:
371 371 stb_phys(T0, T1);
... ... @@ -382,11 +382,11 @@ void helper_st_asi(int asi, int size, int sign)
382 382 stl_phys((T0 + 4) & ~3, T2);
383 383 break;
384 384 }
385   - }
386   - return;
  385 + }
  386 + return;
387 387 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
388 388 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
389   - {
  389 + {
390 390 switch(size) {
391 391 case 1:
392 392 stb_phys((target_phys_addr_t)T0
... ... @@ -408,8 +408,8 @@ void helper_st_asi(int asi, int size, int sign)
408 408 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
409 409 break;
410 410 }
411   - }
412   - return;
  411 + }
  412 + return;
413 413 case 0x31: /* Ross RT620 I-cache flush */
414 414 case 0x36: /* I-cache flash clear */
415 415 case 0x37: /* D-cache flash clear */
... ... @@ -418,7 +418,7 @@ void helper_st_asi(int asi, int size, int sign)
418 418 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
419 419 default:
420 420 do_unassigned_access(T0, 1, 0, 1);
421   - return;
  421 + return;
422 422 }
423 423 }
424 424  
... ... @@ -429,12 +429,12 @@ void helper_ld_asi(int asi, int size, int sign)
429 429 uint64_t ret = 0;
430 430  
431 431 if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
432   - raise_exception(TT_PRIV_ACT);
  432 + raise_exception(TT_PRIV_ACT);
433 433  
434 434 switch (asi) {
435 435 case 0x14: // Bypass
436 436 case 0x15: // Bypass, non-cacheable
437   - {
  437 + {
438 438 switch(size) {
439 439 case 1:
440 440 ret = ldub_phys(T0);
... ... @@ -450,8 +450,8 @@ void helper_ld_asi(int asi, int size, int sign)
450 450 ret = ldq_phys(T0 & ~7);
451 451 break;
452 452 }
453   - break;
454   - }
  453 + break;
  454 + }
455 455 case 0x04: // Nucleus
456 456 case 0x0c: // Nucleus Little Endian (LE)
457 457 case 0x10: // As if user primary
... ... @@ -469,58 +469,58 @@ void helper_ld_asi(int asi, int size, int sign)
469 469 case 0x89: // Secondary LE
470 470 case 0x8a: // Primary no-fault LE
471 471 case 0x8b: // Secondary no-fault LE
472   - // XXX
473   - break;
  472 + // XXX
  473 + break;
474 474 case 0x45: // LSU
475   - ret = env->lsu;
476   - break;
  475 + ret = env->lsu;
  476 + break;
477 477 case 0x50: // I-MMU regs
478   - {
479   - int reg = (T0 >> 3) & 0xf;
  478 + {
  479 + int reg = (T0 >> 3) & 0xf;
480 480  
481   - ret = env->immuregs[reg];
482   - break;
483   - }
  481 + ret = env->immuregs[reg];
  482 + break;
  483 + }
484 484 case 0x51: // I-MMU 8k TSB pointer
485 485 case 0x52: // I-MMU 64k TSB pointer
486 486 case 0x55: // I-MMU data access
487   - // XXX
488   - break;
  487 + // XXX
  488 + break;
489 489 case 0x56: // I-MMU tag read
490   - {
491   - unsigned int i;
492   -
493   - for (i = 0; i < 64; i++) {
494   - // Valid, ctx match, vaddr match
495   - if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
496   - env->itlb_tag[i] == T0) {
497   - ret = env->itlb_tag[i];
498   - break;
499   - }
500   - }
501   - break;
502   - }
  490 + {
  491 + unsigned int i;
  492 +
  493 + for (i = 0; i < 64; i++) {
  494 + // Valid, ctx match, vaddr match
  495 + if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
  496 + env->itlb_tag[i] == T0) {
  497 + ret = env->itlb_tag[i];
  498 + break;
  499 + }
  500 + }
  501 + break;
  502 + }
503 503 case 0x58: // D-MMU regs
504   - {
505   - int reg = (T0 >> 3) & 0xf;
  504 + {
  505 + int reg = (T0 >> 3) & 0xf;
506 506  
507   - ret = env->dmmuregs[reg];
508   - break;
509   - }
  507 + ret = env->dmmuregs[reg];
  508 + break;
  509 + }
510 510 case 0x5e: // D-MMU tag read
511   - {
512   - unsigned int i;
513   -
514   - for (i = 0; i < 64; i++) {
515   - // Valid, ctx match, vaddr match
516   - if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
517   - env->dtlb_tag[i] == T0) {
518   - ret = env->dtlb_tag[i];
519   - break;
520   - }
521   - }
522   - break;
523   - }
  511 + {
  512 + unsigned int i;
  513 +
  514 + for (i = 0; i < 64; i++) {
  515 + // Valid, ctx match, vaddr match
  516 + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
  517 + env->dtlb_tag[i] == T0) {
  518 + ret = env->dtlb_tag[i];
  519 + break;
  520 + }
  521 + }
  522 + break;
  523 + }
524 524 case 0x59: // D-MMU 8k TSB pointer
525 525 case 0x5a: // D-MMU 64k TSB pointer
526 526 case 0x5b: // D-MMU data pointer
... ... @@ -528,8 +528,8 @@ void helper_ld_asi(int asi, int size, int sign)
528 528 case 0x48: // Interrupt dispatch, RO
529 529 case 0x49: // Interrupt data receive
530 530 case 0x7f: // Incoming interrupt vector, RO
531   - // XXX
532   - break;
  531 + // XXX
  532 + break;
533 533 case 0x54: // I-MMU data in, WO
534 534 case 0x57: // I-MMU demap, WO
535 535 case 0x5c: // D-MMU data in, WO
... ... @@ -537,8 +537,8 @@ void helper_ld_asi(int asi, int size, int sign)
537 537 case 0x77: // Interrupt vector, WO
538 538 default:
539 539 do_unassigned_access(T0, 0, 0, 1);
540   - ret = 0;
541   - break;
  540 + ret = 0;
  541 + break;
542 542 }
543 543 T1 = ret;
544 544 }
... ... @@ -546,12 +546,12 @@ void helper_ld_asi(int asi, int size, int sign)
546 546 void helper_st_asi(int asi, int size, int sign)
547 547 {
548 548 if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
549   - raise_exception(TT_PRIV_ACT);
  549 + raise_exception(TT_PRIV_ACT);
550 550  
551 551 switch(asi) {
552 552 case 0x14: // Bypass
553 553 case 0x15: // Bypass, non-cacheable
554   - {
  554 + {
555 555 switch(size) {
556 556 case 1:
557 557 stb_phys(T0, T1);
... ... @@ -567,8 +567,8 @@ void helper_st_asi(int asi, int size, int sign)
567 567 stq_phys(T0 & ~7, T1);
568 568 break;
569 569 }
570   - }
571   - return;
  570 + }
  571 + return;
572 572 case 0x04: // Nucleus
573 573 case 0x0c: // Nucleus Little Endian (LE)
574 574 case 0x10: // As if user primary
... ... @@ -582,31 +582,31 @@ void helper_st_asi(int asi, int size, int sign)
582 582 case 0x4a: // UPA config
583 583 case 0x88: // Primary LE
584 584 case 0x89: // Secondary LE
585   - // XXX
586   - return;
  585 + // XXX
  586 + return;
587 587 case 0x45: // LSU
588   - {
589   - uint64_t oldreg;
590   -
591   - oldreg = env->lsu;
592   - env->lsu = T1 & (DMMU_E | IMMU_E);
593   - // Mappings generated during D/I MMU disabled mode are
594   - // invalid in normal mode
595   - if (oldreg != env->lsu) {
  588 + {
  589 + uint64_t oldreg;
  590 +
  591 + oldreg = env->lsu;
  592 + env->lsu = T1 & (DMMU_E | IMMU_E);
  593 + // Mappings generated during D/I MMU disabled mode are
  594 + // invalid in normal mode
  595 + if (oldreg != env->lsu) {
596 596 #ifdef DEBUG_MMU
597 597 printf("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
598   - dump_mmu(env);
  598 + dump_mmu(env);
599 599 #endif
600   - tlb_flush(env, 1);
601   - }
602   - return;
603   - }
  600 + tlb_flush(env, 1);
  601 + }
  602 + return;
  603 + }
604 604 case 0x50: // I-MMU regs
605   - {
606   - int reg = (T0 >> 3) & 0xf;
607   - uint64_t oldreg;
  605 + {
  606 + int reg = (T0 >> 3) & 0xf;
  607 + uint64_t oldreg;
608 608  
609   - oldreg = env->immuregs[reg];
  609 + oldreg = env->immuregs[reg];
610 610 switch(reg) {
611 611 case 0: // RO
612 612 case 4:
... ... @@ -617,73 +617,73 @@ void helper_st_asi(int asi, int size, int sign)
617 617 case 8:
618 618 return;
619 619 case 3: // SFSR
620   - if ((T1 & 1) == 0)
621   - T1 = 0; // Clear SFSR
  620 + if ((T1 & 1) == 0)
  621 + T1 = 0; // Clear SFSR
622 622 break;
623 623 case 5: // TSB access
624 624 case 6: // Tag access
625 625 default:
626 626 break;
627 627 }
628   - env->immuregs[reg] = T1;
  628 + env->immuregs[reg] = T1;
629 629 #ifdef DEBUG_MMU
630 630 if (oldreg != env->immuregs[reg]) {
631 631 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
632 632 }
633   - dump_mmu(env);
  633 + dump_mmu(env);
634 634 #endif
635   - return;
636   - }
  635 + return;
  636 + }
637 637 case 0x54: // I-MMU data in
638   - {
639   - unsigned int i;
640   -
641   - // Try finding an invalid entry
642   - for (i = 0; i < 64; i++) {
643   - if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
644   - env->itlb_tag[i] = env->immuregs[6];
645   - env->itlb_tte[i] = T1;
646   - return;
647   - }
648   - }
649   - // Try finding an unlocked entry
650   - for (i = 0; i < 64; i++) {
651   - if ((env->itlb_tte[i] & 0x40) == 0) {
652   - env->itlb_tag[i] = env->immuregs[6];
653   - env->itlb_tte[i] = T1;
654   - return;
655   - }
656   - }
657   - // error state?
658   - return;
659   - }
  638 + {
  639 + unsigned int i;
  640 +
  641 + // Try finding an invalid entry
  642 + for (i = 0; i < 64; i++) {
  643 + if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
  644 + env->itlb_tag[i] = env->immuregs[6];
  645 + env->itlb_tte[i] = T1;
  646 + return;
  647 + }
  648 + }
  649 + // Try finding an unlocked entry
  650 + for (i = 0; i < 64; i++) {
  651 + if ((env->itlb_tte[i] & 0x40) == 0) {
  652 + env->itlb_tag[i] = env->immuregs[6];
  653 + env->itlb_tte[i] = T1;
  654 + return;
  655 + }
  656 + }
  657 + // error state?
  658 + return;
  659 + }
660 660 case 0x55: // I-MMU data access
661   - {
662   - unsigned int i = (T0 >> 3) & 0x3f;
  661 + {
  662 + unsigned int i = (T0 >> 3) & 0x3f;
663 663  
664   - env->itlb_tag[i] = env->immuregs[6];
665   - env->itlb_tte[i] = T1;
666   - return;
667   - }
  664 + env->itlb_tag[i] = env->immuregs[6];
  665 + env->itlb_tte[i] = T1;
  666 + return;
  667 + }
668 668 case 0x57: // I-MMU demap
669   - // XXX
670   - return;
  669 + // XXX
  670 + return;
671 671 case 0x58: // D-MMU regs
672   - {
673   - int reg = (T0 >> 3) & 0xf;
674   - uint64_t oldreg;
  672 + {
  673 + int reg = (T0 >> 3) & 0xf;
  674 + uint64_t oldreg;
675 675  
676   - oldreg = env->dmmuregs[reg];
  676 + oldreg = env->dmmuregs[reg];
677 677 switch(reg) {
678 678 case 0: // RO
679 679 case 4:
680 680 return;
681 681 case 3: // SFSR
682   - if ((T1 & 1) == 0) {
683   - T1 = 0; // Clear SFSR, Fault address
684   - env->dmmuregs[4] = 0;
685   - }
686   - env->dmmuregs[reg] = T1;
  682 + if ((T1 & 1) == 0) {
  683 + T1 = 0; // Clear SFSR, Fault address
  684 + env->dmmuregs[4] = 0;
  685 + }
  686 + env->dmmuregs[reg] = T1;
687 687 break;
688 688 case 1: // Primary context
689 689 case 2: // Secondary context
... ... @@ -694,50 +694,50 @@ void helper_st_asi(int asi, int size, int sign)
694 694 default:
695 695 break;
696 696 }
697   - env->dmmuregs[reg] = T1;
  697 + env->dmmuregs[reg] = T1;
698 698 #ifdef DEBUG_MMU
699 699 if (oldreg != env->dmmuregs[reg]) {
700 700 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
701 701 }
702   - dump_mmu(env);
  702 + dump_mmu(env);
703 703 #endif
704   - return;
705   - }
  704 + return;
  705 + }
706 706 case 0x5c: // D-MMU data in
707   - {
708   - unsigned int i;
709   -
710   - // Try finding an invalid entry
711   - for (i = 0; i < 64; i++) {
712   - if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
713   - env->dtlb_tag[i] = env->dmmuregs[6];
714   - env->dtlb_tte[i] = T1;
715   - return;
716   - }
717   - }
718   - // Try finding an unlocked entry
719   - for (i = 0; i < 64; i++) {
720   - if ((env->dtlb_tte[i] & 0x40) == 0) {
721   - env->dtlb_tag[i] = env->dmmuregs[6];
722   - env->dtlb_tte[i] = T1;
723   - return;
724   - }
725   - }
726   - // error state?
727   - return;
728   - }
  707 + {
  708 + unsigned int i;
  709 +
  710 + // Try finding an invalid entry
  711 + for (i = 0; i < 64; i++) {
  712 + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
  713 + env->dtlb_tag[i] = env->dmmuregs[6];
  714 + env->dtlb_tte[i] = T1;
  715 + return;
  716 + }
  717 + }
  718 + // Try finding an unlocked entry
  719 + for (i = 0; i < 64; i++) {
  720 + if ((env->dtlb_tte[i] & 0x40) == 0) {
  721 + env->dtlb_tag[i] = env->dmmuregs[6];
  722 + env->dtlb_tte[i] = T1;
  723 + return;
  724 + }
  725 + }
  726 + // error state?
  727 + return;
  728 + }
729 729 case 0x5d: // D-MMU data access
730   - {
731   - unsigned int i = (T0 >> 3) & 0x3f;
  730 + {
  731 + unsigned int i = (T0 >> 3) & 0x3f;
732 732  
733   - env->dtlb_tag[i] = env->dmmuregs[6];
734   - env->dtlb_tte[i] = T1;
735   - return;
736   - }
  733 + env->dtlb_tag[i] = env->dmmuregs[6];
  734 + env->dtlb_tte[i] = T1;
  735 + return;
  736 + }
737 737 case 0x5f: // D-MMU demap
738 738 case 0x49: // Interrupt data receive
739   - // XXX
740   - return;
  739 + // XXX
  740 + return;
741 741 case 0x51: // I-MMU 8k TSB pointer, RO
742 742 case 0x52: // I-MMU 64k TSB pointer, RO
743 743 case 0x56: // I-MMU tag read, RO
... ... @@ -753,7 +753,7 @@ void helper_st_asi(int asi, int size, int sign)
753 753 case 0x8b: // Secondary no-fault LE, RO
754 754 default:
755 755 do_unassigned_access(T0, 1, 0, 1);
756   - return;
  756 + return;
757 757 }
758 758 }
759 759 #endif
... ... @@ -783,17 +783,17 @@ void helper_ldfsr(void)
783 783 switch (env->fsr & FSR_RD_MASK) {
784 784 case FSR_RD_NEAREST:
785 785 rnd_mode = float_round_nearest_even;
786   - break;
  786 + break;
787 787 default:
788 788 case FSR_RD_ZERO:
789 789 rnd_mode = float_round_to_zero;
790   - break;
  790 + break;
791 791 case FSR_RD_POS:
792 792 rnd_mode = float_round_up;
793   - break;
  793 + break;
794 794 case FSR_RD_NEG:
795 795 rnd_mode = float_round_down;
796   - break;
  796 + break;
797 797 }
798 798 set_float_rounding_mode(rnd_mode, &env->fp_status);
799 799 }
... ... @@ -835,13 +835,13 @@ static inline uint64_t *get_gregset(uint64_t pstate)
835 835 switch (pstate) {
836 836 default:
837 837 case 0:
838   - return env->bgregs;
  838 + return env->bgregs;
839 839 case PS_AG:
840   - return env->agregs;
  840 + return env->agregs;
841 841 case PS_MG:
842   - return env->mgregs;
  842 + return env->mgregs;
843 843 case PS_IG:
844   - return env->igregs;
  844 + return env->igregs;
845 845 }
846 846 }
847 847  
... ... @@ -853,11 +853,11 @@ static inline void change_pstate(uint64_t new_pstate)
853 853 pstate_regs = env->pstate & 0xc01;
854 854 new_pstate_regs = new_pstate & 0xc01;
855 855 if (new_pstate_regs != pstate_regs) {
856   - // Switch global register bank
857   - src = get_gregset(new_pstate_regs);
858   - dst = get_gregset(pstate_regs);
859   - memcpy32(dst, env->gregs);
860   - memcpy32(env->gregs, src);
  856 + // Switch global register bank
  857 + src = get_gregset(new_pstate_regs);
  858 + dst = get_gregset(pstate_regs);
  859 + memcpy32(dst, env->gregs);
  860 + memcpy32(env->gregs, src);
861 861 }
862 862 env->pstate = new_pstate;
863 863 }
... ... @@ -927,36 +927,36 @@ void do_interrupt(int intno)
927 927 {
928 928 #ifdef DEBUG_PCALL
929 929 if (loglevel & CPU_LOG_INT) {
930   - static int count;
931   - fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
  930 + static int count;
  931 + fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
932 932 count, intno,
933 933 env->pc,
934 934 env->npc, env->regwptr[6]);
935   - cpu_dump_state(env, logfile, fprintf, 0);
  935 + cpu_dump_state(env, logfile, fprintf, 0);
936 936 #if 0
937   - {
938   - int i;
939   - uint8_t *ptr;
940   -
941   - fprintf(logfile, " code=");
942   - ptr = (uint8_t *)env->pc;
943   - for(i = 0; i < 16; i++) {
944   - fprintf(logfile, " %02x", ldub(ptr + i));
945   - }
946   - fprintf(logfile, "\n");
947   - }
  937 + {
  938 + int i;
  939 + uint8_t *ptr;
  940 +
  941 + fprintf(logfile, " code=");
  942 + ptr = (uint8_t *)env->pc;
  943 + for(i = 0; i < 16; i++) {
  944 + fprintf(logfile, " %02x", ldub(ptr + i));
  945 + }
  946 + fprintf(logfile, "\n");
  947 + }
948 948 #endif
949   - count++;
  949 + count++;
950 950 }
951 951 #endif
952 952 #if !defined(CONFIG_USER_ONLY)
953 953 if (env->tl == MAXTL) {
954 954 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
955   - return;
  955 + return;
956 956 }
957 957 #endif
958 958 env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
959   - ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
  959 + ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
960 960 env->tpc[env->tl] = env->pc;
961 961 env->tnpc[env->tl] = env->npc;
962 962 env->tt[env->tl] = intno;
... ... @@ -971,11 +971,11 @@ void do_interrupt(int intno)
971 971 env->tbr &= ~0x7fffULL;
972 972 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
973 973 if (env->tl < MAXTL - 1) {
974   - env->tl++;
  974 + env->tl++;
975 975 } else {
976   - env->pstate |= PS_RED;
977   - if (env->tl != MAXTL)
978   - env->tl++;
  976 + env->pstate |= PS_RED;
  977 + if (env->tl != MAXTL)
  978 + env->tl++;
979 979 }
980 980 env->pc = env->tbr;
981 981 env->npc = env->pc + 4;
... ... @@ -988,32 +988,32 @@ void do_interrupt(int intno)
988 988  
989 989 #ifdef DEBUG_PCALL
990 990 if (loglevel & CPU_LOG_INT) {
991   - static int count;
992   - fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
  991 + static int count;
  992 + fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
993 993 count, intno,
994 994 env->pc,
995 995 env->npc, env->regwptr[6]);
996   - cpu_dump_state(env, logfile, fprintf, 0);
  996 + cpu_dump_state(env, logfile, fprintf, 0);
997 997 #if 0
998   - {
999   - int i;
1000   - uint8_t *ptr;
1001   -
1002   - fprintf(logfile, " code=");
1003   - ptr = (uint8_t *)env->pc;
1004   - for(i = 0; i < 16; i++) {
1005   - fprintf(logfile, " %02x", ldub(ptr + i));
1006   - }
1007   - fprintf(logfile, "\n");
1008   - }
  998 + {
  999 + int i;
  1000 + uint8_t *ptr;
  1001 +
  1002 + fprintf(logfile, " code=");
  1003 + ptr = (uint8_t *)env->pc;
  1004 + for(i = 0; i < 16; i++) {
  1005 + fprintf(logfile, " %02x", ldub(ptr + i));
  1006 + }
  1007 + fprintf(logfile, "\n");
  1008 + }
1009 1009 #endif
1010   - count++;
  1010 + count++;
1011 1011 }
1012 1012 #endif
1013 1013 #if !defined(CONFIG_USER_ONLY)
1014 1014 if (env->psret == 0) {
1015 1015 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
1016   - return;
  1016 + return;
1017 1017 }
1018 1018 #endif
1019 1019 env->psret = 0;
... ... @@ -1106,7 +1106,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1106 1106 saved_env = env;
1107 1107 env = cpu_single_env;
1108 1108 if (env->mmuregs[3]) /* Fault status register */
1109   - env->mmuregs[3] = 1; /* overflow (not read before another fault) */
  1109 + env->mmuregs[3] = 1; /* overflow (not read before another fault) */
1110 1110 if (is_asi)
1111 1111 env->mmuregs[3] |= 1 << 16;
1112 1112 if (env->psrs)
... ...
target-sparc/op_mem.h
  View file @0f8a249
... ... @@ -2,13 +2,13 @@
2 2 #define SPARC_LD_OP(name, qp) \
3 3 void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
4 4 { \
5   - T1 = (target_ulong)glue(qp, MEMSUFFIX)(T0); \
  5 + T1 = (target_ulong)glue(qp, MEMSUFFIX)(T0); \
6 6 }
7 7  
8   -#define SPARC_LD_OP_S(name, qp) \
9   - void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
10   - { \
11   - T1 = (target_long)glue(qp, MEMSUFFIX)(T0); \
  8 +#define SPARC_LD_OP_S(name, qp) \
  9 + void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
  10 + { \
  11 + T1 = (target_long)glue(qp, MEMSUFFIX)(T0); \
12 12 }
13 13  
14 14 #define SPARC_ST_OP(name, op) \
... ... @@ -85,7 +85,7 @@ void OPPROTO glue(op_cas, MEMSUFFIX)(void)
85 85 tmp = glue(ldl, MEMSUFFIX)(T0);
86 86 T2 &= 0xffffffffULL;
87 87 if (tmp == (T1 & 0xffffffffULL)) {
88   - glue(stl, MEMSUFFIX)(T0, T2);
  88 + glue(stl, MEMSUFFIX)(T0, T2);
89 89 }
90 90 T2 = tmp;
91 91 }
... ... @@ -98,7 +98,7 @@ void OPPROTO glue(op_casx, MEMSUFFIX)(void)
98 98 tmp = (uint64_t)glue(ldl, MEMSUFFIX)(T0) << 32;
99 99 tmp |= glue(ldl, MEMSUFFIX)(T0);
100 100 if (tmp == T1) {
101   - glue(stq, MEMSUFFIX)(T0, T2);
  101 + glue(stq, MEMSUFFIX)(T0, T2);
102 102 }
103 103 T2 = tmp;
104 104 }
... ...
target-sparc/translate.c
  View file @0f8a249
... ... @@ -45,8 +45,8 @@
45 45 according to jump_pc[T2] */
46 46  
47 47 typedef struct DisasContext {
48   - target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
49   - target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  48 + target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
  49 + target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
50 50 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
51 51 int is_br;
52 52 int mem_idx;
... ... @@ -359,57 +359,57 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
359 359 #define supervisor(dc) 0
360 360 #define hypervisor(dc) 0
361 361 #define gen_op_ldst(name) gen_op_##name##_raw()
362   -#define OP_LD_TABLE(width) \
  362 +#define OP_LD_TABLE(width) \
363 363 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
364   - { \
365   - int asi, offset; \
366   - \
367   - if (IS_IMM) { \
368   - offset = GET_FIELD(insn, 25, 31); \
369   - if (is_ld) \
370   - gen_op_ld_asi_reg(offset, size, sign); \
371   - else \
372   - gen_op_st_asi_reg(offset, size, sign); \
373   - return; \
374   - } \
375   - asi = GET_FIELD(insn, 19, 26); \
376   - switch (asi) { \
377   - case 0x80: /* Primary address space */ \
378   - gen_op_##width##_raw(); \
379   - break; \
380   - case 0x82: /* Primary address space, non-faulting load */ \
381   - gen_op_##width##_raw(); \
382   - break; \
383   - default: \
384   - break; \
385   - } \
  364 + { \
  365 + int asi, offset; \
  366 + \
  367 + if (IS_IMM) { \
  368 + offset = GET_FIELD(insn, 25, 31); \
  369 + if (is_ld) \
  370 + gen_op_ld_asi_reg(offset, size, sign); \
  371 + else \
  372 + gen_op_st_asi_reg(offset, size, sign); \
  373 + return; \
  374 + } \
  375 + asi = GET_FIELD(insn, 19, 26); \
  376 + switch (asi) { \
  377 + case 0x80: /* Primary address space */ \
  378 + gen_op_##width##_raw(); \
  379 + break; \
  380 + case 0x82: /* Primary address space, non-faulting load */ \
  381 + gen_op_##width##_raw(); \
  382 + break; \
  383 + default: \
  384 + break; \
  385 + } \
386 386 }
387 387  
388 388 #else
389 389 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
390   -#define OP_LD_TABLE(width) \
  390 +#define OP_LD_TABLE(width) \
391 391 static GenOpFunc * const gen_op_##width[] = { \
392   - &gen_op_##width##_user, \
393   - &gen_op_##width##_kernel, \
394   - }; \
395   - \
  392 + &gen_op_##width##_user, \
  393 + &gen_op_##width##_kernel, \
  394 + }; \
  395 + \
396 396 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
397   - { \
398   - int asi, offset; \
399   - \
400   - if (IS_IMM) { \
401   - offset = GET_FIELD(insn, 25, 31); \
402   - if (is_ld) \
403   - gen_op_ld_asi_reg(offset, size, sign); \
404   - else \
405   - gen_op_st_asi_reg(offset, size, sign); \
406   - return; \
407   - } \
408   - asi = GET_FIELD(insn, 19, 26); \
409   - if (is_ld) \
410   - gen_op_ld_asi(asi, size, sign); \
411   - else \
412   - gen_op_st_asi(asi, size, sign); \
  397 + { \
  398 + int asi, offset; \
  399 + \
  400 + if (IS_IMM) { \
  401 + offset = GET_FIELD(insn, 25, 31); \
  402 + if (is_ld) \
  403 + gen_op_ld_asi_reg(offset, size, sign); \
  404 + else \
  405 + gen_op_st_asi_reg(offset, size, sign); \
  406 + return; \
  407 + } \
  408 + asi = GET_FIELD(insn, 19, 26); \
  409 + if (is_ld) \
  410 + gen_op_ld_asi(asi, size, sign); \
  411 + else \
  412 + gen_op_st_asi(asi, size, sign); \
413 413 }
414 414  
415 415 #define supervisor(dc) (dc->mem_idx == 1)
... ... @@ -422,7 +422,7 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
422 422 #define supervisor(dc) 0
423 423 #else
424 424 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
425   -#define OP_LD_TABLE(width) \
  425 +#define OP_LD_TABLE(width) \
426 426 static GenOpFunc * const gen_op_##width[] = { \
427 427 &gen_op_##width##_user, \
428 428 &gen_op_##width##_kernel, \
... ... @@ -434,23 +434,23 @@ static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
434 434 \
435 435 asi = GET_FIELD(insn, 19, 26); \
436 436 switch (asi) { \
437   - case 10: /* User data access */ \
438   - gen_op_##width##_user(); \
439   - break; \
440   - case 11: /* Supervisor data access */ \
441   - gen_op_##width##_kernel(); \
442   - break; \
443   - case 0x20 ... 0x2f: /* MMU passthrough */ \
444   - if (is_ld) \
445   - gen_op_ld_asi(asi, size, sign); \
446   - else \
447   - gen_op_st_asi(asi, size, sign); \
448   - break; \
449   - default: \
450   - if (is_ld) \
451   - gen_op_ld_asi(asi, size, sign); \
452   - else \
453   - gen_op_st_asi(asi, size, sign); \
  437 + case 10: /* User data access */ \
  438 + gen_op_##width##_user(); \
  439 + break; \
  440 + case 11: /* Supervisor data access */ \
  441 + gen_op_##width##_kernel(); \
  442 + break; \
  443 + case 0x20 ... 0x2f: /* MMU passthrough */ \
  444 + if (is_ld) \
  445 + gen_op_ld_asi(asi, size, sign); \
  446 + else \
  447 + gen_op_st_asi(asi, size, sign); \
  448 + break; \
  449 + default: \
  450 + if (is_ld) \
  451 + gen_op_ld_asi(asi, size, sign); \
  452 + else \
  453 + gen_op_st_asi(asi, size, sign); \
454 454 break; \
455 455 } \
456 456 }
... ... @@ -518,9 +518,9 @@ static inline void gen_movl_simm_T0(int32_t val)
518 518 static inline void gen_movl_reg_TN(int reg, int t)
519 519 {
520 520 if (reg)
521   - gen_op_movl_reg_TN[t][reg] ();
  521 + gen_op_movl_reg_TN[t][reg] ();
522 522 else
523   - gen_movl_imm_TN(t, 0);
  523 + gen_movl_imm_TN(t, 0);
524 524 }
525 525  
526 526 static inline void gen_movl_reg_T0(int reg)
... ... @@ -541,7 +541,7 @@ static inline void gen_movl_reg_T2(int reg)
541 541 static inline void gen_movl_TN_reg(int reg, int t)
542 542 {
543 543 if (reg)
544   - gen_op_movl_TN_reg[t][reg] ();
  544 + gen_op_movl_TN_reg[t][reg] ();
545 545 }
546 546  
547 547 static inline void gen_movl_T0_reg(int reg)
... ... @@ -699,118 +699,118 @@ static inline void gen_mov_pc_npc(DisasContext * dc)
699 699  
700 700 static GenOpFunc * const gen_cond[2][16] = {
701 701 {
702   - gen_op_eval_bn,
703   - gen_op_eval_be,
704   - gen_op_eval_ble,
705   - gen_op_eval_bl,
706   - gen_op_eval_bleu,
707   - gen_op_eval_bcs,
708   - gen_op_eval_bneg,
709   - gen_op_eval_bvs,
710   - gen_op_eval_ba,
711   - gen_op_eval_bne,
712   - gen_op_eval_bg,
713   - gen_op_eval_bge,
714   - gen_op_eval_bgu,
715   - gen_op_eval_bcc,
716   - gen_op_eval_bpos,
717   - gen_op_eval_bvc,
  702 + gen_op_eval_bn,
  703 + gen_op_eval_be,
  704 + gen_op_eval_ble,
  705 + gen_op_eval_bl,
  706 + gen_op_eval_bleu,
  707 + gen_op_eval_bcs,
  708 + gen_op_eval_bneg,
  709 + gen_op_eval_bvs,
  710 + gen_op_eval_ba,
  711 + gen_op_eval_bne,
  712 + gen_op_eval_bg,
  713 + gen_op_eval_bge,
  714 + gen_op_eval_bgu,
  715 + gen_op_eval_bcc,
  716 + gen_op_eval_bpos,
  717 + gen_op_eval_bvc,
718 718 },
719 719 {
720 720 #ifdef TARGET_SPARC64
721   - gen_op_eval_bn,
722   - gen_op_eval_xbe,
723   - gen_op_eval_xble,
724   - gen_op_eval_xbl,
725   - gen_op_eval_xbleu,
726   - gen_op_eval_xbcs,
727   - gen_op_eval_xbneg,
728   - gen_op_eval_xbvs,
729   - gen_op_eval_ba,
730   - gen_op_eval_xbne,
731   - gen_op_eval_xbg,
732   - gen_op_eval_xbge,
733   - gen_op_eval_xbgu,
734   - gen_op_eval_xbcc,
735   - gen_op_eval_xbpos,
736   - gen_op_eval_xbvc,
  721 + gen_op_eval_bn,
  722 + gen_op_eval_xbe,
  723 + gen_op_eval_xble,
  724 + gen_op_eval_xbl,
  725 + gen_op_eval_xbleu,
  726 + gen_op_eval_xbcs,
  727 + gen_op_eval_xbneg,
  728 + gen_op_eval_xbvs,
  729 + gen_op_eval_ba,
  730 + gen_op_eval_xbne,
  731 + gen_op_eval_xbg,
  732 + gen_op_eval_xbge,
  733 + gen_op_eval_xbgu,
  734 + gen_op_eval_xbcc,
  735 + gen_op_eval_xbpos,
  736 + gen_op_eval_xbvc,
737 737 #endif
738 738 },
739 739 };
740 740  
741 741 static GenOpFunc * const gen_fcond[4][16] = {
742 742 {
743   - gen_op_eval_bn,
744   - gen_op_eval_fbne,
745   - gen_op_eval_fblg,
746   - gen_op_eval_fbul,
747   - gen_op_eval_fbl,
748   - gen_op_eval_fbug,
749   - gen_op_eval_fbg,
750   - gen_op_eval_fbu,
751   - gen_op_eval_ba,
752   - gen_op_eval_fbe,
753   - gen_op_eval_fbue,
754   - gen_op_eval_fbge,
755   - gen_op_eval_fbuge,
756   - gen_op_eval_fble,
757   - gen_op_eval_fbule,
758   - gen_op_eval_fbo,
  743 + gen_op_eval_bn,
  744 + gen_op_eval_fbne,
  745 + gen_op_eval_fblg,
  746 + gen_op_eval_fbul,
  747 + gen_op_eval_fbl,
  748 + gen_op_eval_fbug,
  749 + gen_op_eval_fbg,
  750 + gen_op_eval_fbu,
  751 + gen_op_eval_ba,
  752 + gen_op_eval_fbe,
  753 + gen_op_eval_fbue,
  754 + gen_op_eval_fbge,
  755 + gen_op_eval_fbuge,
  756 + gen_op_eval_fble,
  757 + gen_op_eval_fbule,
  758 + gen_op_eval_fbo,
759 759 },
760 760 #ifdef TARGET_SPARC64
761 761 {
762   - gen_op_eval_bn,
763   - gen_op_eval_fbne_fcc1,
764   - gen_op_eval_fblg_fcc1,
765   - gen_op_eval_fbul_fcc1,
766   - gen_op_eval_fbl_fcc1,
767   - gen_op_eval_fbug_fcc1,
768   - gen_op_eval_fbg_fcc1,
769   - gen_op_eval_fbu_fcc1,
770   - gen_op_eval_ba,
771   - gen_op_eval_fbe_fcc1,
772   - gen_op_eval_fbue_fcc1,
773   - gen_op_eval_fbge_fcc1,
774   - gen_op_eval_fbuge_fcc1,
775   - gen_op_eval_fble_fcc1,
776   - gen_op_eval_fbule_fcc1,
777   - gen_op_eval_fbo_fcc1,
  762 + gen_op_eval_bn,
  763 + gen_op_eval_fbne_fcc1,
  764 + gen_op_eval_fblg_fcc1,
  765 + gen_op_eval_fbul_fcc1,
  766 + gen_op_eval_fbl_fcc1,
  767 + gen_op_eval_fbug_fcc1,
  768 + gen_op_eval_fbg_fcc1,
  769 + gen_op_eval_fbu_fcc1,
  770 + gen_op_eval_ba,
  771 + gen_op_eval_fbe_fcc1,
  772 + gen_op_eval_fbue_fcc1,
  773 + gen_op_eval_fbge_fcc1,
  774 + gen_op_eval_fbuge_fcc1,
  775 + gen_op_eval_fble_fcc1,
  776 + gen_op_eval_fbule_fcc1,
  777 + gen_op_eval_fbo_fcc1,
778 778 },
779 779 {
780   - gen_op_eval_bn,
781   - gen_op_eval_fbne_fcc2,
782   - gen_op_eval_fblg_fcc2,
783   - gen_op_eval_fbul_fcc2,
784   - gen_op_eval_fbl_fcc2,
785   - gen_op_eval_fbug_fcc2,
786   - gen_op_eval_fbg_fcc2,
787   - gen_op_eval_fbu_fcc2,
788   - gen_op_eval_ba,
789   - gen_op_eval_fbe_fcc2,
790   - gen_op_eval_fbue_fcc2,
791   - gen_op_eval_fbge_fcc2,
792   - gen_op_eval_fbuge_fcc2,
793   - gen_op_eval_fble_fcc2,
794   - gen_op_eval_fbule_fcc2,
795   - gen_op_eval_fbo_fcc2,
  780 + gen_op_eval_bn,
  781 + gen_op_eval_fbne_fcc2,
  782 + gen_op_eval_fblg_fcc2,
  783 + gen_op_eval_fbul_fcc2,
  784 + gen_op_eval_fbl_fcc2,
  785 + gen_op_eval_fbug_fcc2,
  786 + gen_op_eval_fbg_fcc2,
  787 + gen_op_eval_fbu_fcc2,
  788 + gen_op_eval_ba,
  789 + gen_op_eval_fbe_fcc2,
  790 + gen_op_eval_fbue_fcc2,
  791 + gen_op_eval_fbge_fcc2,
  792 + gen_op_eval_fbuge_fcc2,
  793 + gen_op_eval_fble_fcc2,
  794 + gen_op_eval_fbule_fcc2,
  795 + gen_op_eval_fbo_fcc2,
796 796 },
797 797 {
798   - gen_op_eval_bn,
799   - gen_op_eval_fbne_fcc3,
800   - gen_op_eval_fblg_fcc3,
801   - gen_op_eval_fbul_fcc3,
802   - gen_op_eval_fbl_fcc3,
803   - gen_op_eval_fbug_fcc3,
804   - gen_op_eval_fbg_fcc3,
805   - gen_op_eval_fbu_fcc3,
806   - gen_op_eval_ba,
807   - gen_op_eval_fbe_fcc3,
808   - gen_op_eval_fbue_fcc3,
809   - gen_op_eval_fbge_fcc3,
810   - gen_op_eval_fbuge_fcc3,
811   - gen_op_eval_fble_fcc3,
812   - gen_op_eval_fbule_fcc3,
813   - gen_op_eval_fbo_fcc3,
  798 + gen_op_eval_bn,
  799 + gen_op_eval_fbne_fcc3,
  800 + gen_op_eval_fblg_fcc3,
  801 + gen_op_eval_fbul_fcc3,
  802 + gen_op_eval_fbl_fcc3,
  803 + gen_op_eval_fbug_fcc3,
  804 + gen_op_eval_fbg_fcc3,
  805 + gen_op_eval_fbu_fcc3,
  806 + gen_op_eval_ba,
  807 + gen_op_eval_fbe_fcc3,
  808 + gen_op_eval_fbue_fcc3,
  809 + gen_op_eval_fbge_fcc3,
  810 + gen_op_eval_fbuge_fcc3,
  811 + gen_op_eval_fble_fcc3,
  812 + gen_op_eval_fbule_fcc3,
  813 + gen_op_eval_fbo_fcc3,
814 814 },
815 815 #else
816 816 {}, {}, {},
... ... @@ -820,27 +820,27 @@ static GenOpFunc * const gen_fcond[4][16] = {
820 820 #ifdef TARGET_SPARC64
821 821 static void gen_cond_reg(int cond)
822 822 {
823   - switch (cond) {
824   - case 0x1:
825   - gen_op_eval_brz();
826   - break;
827   - case 0x2:
828   - gen_op_eval_brlez();
829   - break;
830   - case 0x3:
831   - gen_op_eval_brlz();
832   - break;
833   - case 0x5:
834   - gen_op_eval_brnz();
835   - break;
836   - case 0x6:
837   - gen_op_eval_brgz();
838   - break;
  823 + switch (cond) {
  824 + case 0x1:
  825 + gen_op_eval_brz();
  826 + break;
  827 + case 0x2:
  828 + gen_op_eval_brlez();
  829 + break;
  830 + case 0x3:
  831 + gen_op_eval_brlz();
  832 + break;
  833 + case 0x5:
  834 + gen_op_eval_brnz();
  835 + break;
  836 + case 0x6:
  837 + gen_op_eval_brgz();
  838 + break;
839 839 default:
840   - case 0x7:
841   - gen_op_eval_brgez();
842   - break;
843   - }
  840 + case 0x7:
  841 + gen_op_eval_brgez();
  842 + break;
  843 + }
844 844 }
845 845 #endif
846 846  
... ... @@ -851,35 +851,35 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
851 851 target_ulong target = dc->pc + offset;
852 852  
853 853 if (cond == 0x0) {
854   - /* unconditional not taken */
855   - if (a) {
856   - dc->pc = dc->npc + 4;
857   - dc->npc = dc->pc + 4;
858   - } else {
859   - dc->pc = dc->npc;
860   - dc->npc = dc->pc + 4;
861   - }
  854 + /* unconditional not taken */
  855 + if (a) {
  856 + dc->pc = dc->npc + 4;
  857 + dc->npc = dc->pc + 4;
  858 + } else {
  859 + dc->pc = dc->npc;
  860 + dc->npc = dc->pc + 4;
  861 + }
862 862 } else if (cond == 0x8) {
863   - /* unconditional taken */
864   - if (a) {
865   - dc->pc = target;
866   - dc->npc = dc->pc + 4;
867   - } else {
868   - dc->pc = dc->npc;
869   - dc->npc = target;
870   - }
  863 + /* unconditional taken */
  864 + if (a) {
  865 + dc->pc = target;
  866 + dc->npc = dc->pc + 4;
  867 + } else {
  868 + dc->pc = dc->npc;
  869 + dc->npc = target;
  870 + }
871 871 } else {
872 872 flush_T2(dc);
873 873 gen_cond[cc][cond]();
874   - if (a) {
875   - gen_branch_a(dc, target, dc->npc);
  874 + if (a) {
  875 + gen_branch_a(dc, target, dc->npc);
876 876 dc->is_br = 1;
877   - } else {
  877 + } else {
878 878 dc->pc = dc->npc;
879 879 dc->jump_pc[0] = target;
880 880 dc->jump_pc[1] = dc->npc + 4;
881 881 dc->npc = JUMP_PC;
882   - }
  882 + }
883 883 }
884 884 }
885 885  
... ... @@ -890,35 +890,35 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
890 890 target_ulong target = dc->pc + offset;
891 891  
892 892 if (cond == 0x0) {
893   - /* unconditional not taken */
894   - if (a) {
895   - dc->pc = dc->npc + 4;
896   - dc->npc = dc->pc + 4;
897   - } else {
898   - dc->pc = dc->npc;
899   - dc->npc = dc->pc + 4;
900   - }
  893 + /* unconditional not taken */
  894 + if (a) {
  895 + dc->pc = dc->npc + 4;
  896 + dc->npc = dc->pc + 4;
  897 + } else {
  898 + dc->pc = dc->npc;
  899 + dc->npc = dc->pc + 4;
  900 + }
901 901 } else if (cond == 0x8) {
902   - /* unconditional taken */
903   - if (a) {
904   - dc->pc = target;
905   - dc->npc = dc->pc + 4;
906   - } else {
907   - dc->pc = dc->npc;
908   - dc->npc = target;
909   - }
  902 + /* unconditional taken */
  903 + if (a) {
  904 + dc->pc = target;
  905 + dc->npc = dc->pc + 4;
  906 + } else {
  907 + dc->pc = dc->npc;
  908 + dc->npc = target;
  909 + }
910 910 } else {
911 911 flush_T2(dc);
912 912 gen_fcond[cc][cond]();
913   - if (a) {
914   - gen_branch_a(dc, target, dc->npc);
  913 + if (a) {
  914 + gen_branch_a(dc, target, dc->npc);
915 915 dc->is_br = 1;
916   - } else {
  916 + } else {
917 917 dc->pc = dc->npc;
918 918 dc->jump_pc[0] = target;
919 919 dc->jump_pc[1] = dc->npc + 4;
920 920 dc->npc = JUMP_PC;
921   - }
  921 + }
922 922 }
923 923 }
924 924  
... ... @@ -932,13 +932,13 @@ static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
932 932 flush_T2(dc);
933 933 gen_cond_reg(cond);
934 934 if (a) {
935   - gen_branch_a(dc, target, dc->npc);
936   - dc->is_br = 1;
  935 + gen_branch_a(dc, target, dc->npc);
  936 + dc->is_br = 1;
937 937 } else {
938   - dc->pc = dc->npc;
939   - dc->jump_pc[0] = target;
940   - dc->jump_pc[1] = dc->npc + 4;
941   - dc->npc = JUMP_PC;
  938 + dc->pc = dc->npc;
  939 + dc->jump_pc[0] = target;
  940 + dc->jump_pc[1] = dc->npc + 4;
  941 + dc->npc = JUMP_PC;
942 942 }
943 943 }
944 944  
... ... @@ -995,139 +995,139 @@ static void disas_sparc_insn(DisasContext * dc)
995 995  
996 996 rd = GET_FIELD(insn, 2, 6);
997 997 switch (opc) {
998   - case 0: /* branches/sethi */
999   - {
1000   - unsigned int xop = GET_FIELD(insn, 7, 9);
1001   - int32_t target;
1002   - switch (xop) {
  998 + case 0: /* branches/sethi */
  999 + {
  1000 + unsigned int xop = GET_FIELD(insn, 7, 9);
  1001 + int32_t target;
  1002 + switch (xop) {
1003 1003 #ifdef TARGET_SPARC64
1004   - case 0x1: /* V9 BPcc */
1005   - {
1006   - int cc;
1007   -
1008   - target = GET_FIELD_SP(insn, 0, 18);
1009   - target = sign_extend(target, 18);
1010   - target <<= 2;
1011   - cc = GET_FIELD_SP(insn, 20, 21);
1012   - if (cc == 0)
1013   - do_branch(dc, target, insn, 0);
1014   - else if (cc == 2)
1015   - do_branch(dc, target, insn, 1);
1016   - else
1017   - goto illegal_insn;
1018   - goto jmp_insn;
1019   - }
1020   - case 0x3: /* V9 BPr */
1021   - {
1022   - target = GET_FIELD_SP(insn, 0, 13) |
  1004 + case 0x1: /* V9 BPcc */
  1005 + {
  1006 + int cc;
  1007 +
  1008 + target = GET_FIELD_SP(insn, 0, 18);
  1009 + target = sign_extend(target, 18);
  1010 + target <<= 2;
  1011 + cc = GET_FIELD_SP(insn, 20, 21);
  1012 + if (cc == 0)
  1013 + do_branch(dc, target, insn, 0);
  1014 + else if (cc == 2)
  1015 + do_branch(dc, target, insn, 1);
  1016 + else
  1017 + goto illegal_insn;
  1018 + goto jmp_insn;
  1019 + }
  1020 + case 0x3: /* V9 BPr */
  1021 + {
  1022 + target = GET_FIELD_SP(insn, 0, 13) |
1023 1023 (GET_FIELD_SP(insn, 20, 21) << 14);
1024   - target = sign_extend(target, 16);
1025   - target <<= 2;
1026   - rs1 = GET_FIELD(insn, 13, 17);
1027   - gen_movl_reg_T0(rs1);
1028   - do_branch_reg(dc, target, insn);
1029   - goto jmp_insn;
1030   - }
1031   - case 0x5: /* V9 FBPcc */
1032   - {
1033   - int cc = GET_FIELD_SP(insn, 20, 21);
  1024 + target = sign_extend(target, 16);
  1025 + target <<= 2;
  1026 + rs1 = GET_FIELD(insn, 13, 17);
  1027 + gen_movl_reg_T0(rs1);
  1028 + do_branch_reg(dc, target, insn);
  1029 + goto jmp_insn;
  1030 + }
  1031 + case 0x5: /* V9 FBPcc */
  1032 + {
  1033 + int cc = GET_FIELD_SP(insn, 20, 21);
1034 1034 if (gen_trap_ifnofpu(dc))
1035 1035 goto jmp_insn;
1036   - target = GET_FIELD_SP(insn, 0, 18);
1037   - target = sign_extend(target, 19);
1038   - target <<= 2;
1039   - do_fbranch(dc, target, insn, cc);
1040   - goto jmp_insn;
1041   - }
  1036 + target = GET_FIELD_SP(insn, 0, 18);
  1037 + target = sign_extend(target, 19);
  1038 + target <<= 2;
  1039 + do_fbranch(dc, target, insn, cc);
  1040 + goto jmp_insn;
  1041 + }
1042 1042 #else
1043   - case 0x7: /* CBN+x */
1044   - {
1045   - goto ncp_insn;
1046   - }
1047   -#endif
1048   - case 0x2: /* BN+x */
1049   - {
1050   - target = GET_FIELD(insn, 10, 31);
1051   - target = sign_extend(target, 22);
1052   - target <<= 2;
1053   - do_branch(dc, target, insn, 0);
1054   - goto jmp_insn;
1055   - }
1056   - case 0x6: /* FBN+x */
1057   - {
  1043 + case 0x7: /* CBN+x */
  1044 + {
  1045 + goto ncp_insn;
  1046 + }
  1047 +#endif
  1048 + case 0x2: /* BN+x */
  1049 + {
  1050 + target = GET_FIELD(insn, 10, 31);
  1051 + target = sign_extend(target, 22);
  1052 + target <<= 2;
  1053 + do_branch(dc, target, insn, 0);
  1054 + goto jmp_insn;
  1055 + }
  1056 + case 0x6: /* FBN+x */
  1057 + {
1058 1058 if (gen_trap_ifnofpu(dc))
1059 1059 goto jmp_insn;
1060   - target = GET_FIELD(insn, 10, 31);
1061   - target = sign_extend(target, 22);
1062   - target <<= 2;
1063   - do_fbranch(dc, target, insn, 0);
1064   - goto jmp_insn;
1065   - }
1066   - case 0x4: /* SETHI */
  1060 + target = GET_FIELD(insn, 10, 31);
  1061 + target = sign_extend(target, 22);
  1062 + target <<= 2;
  1063 + do_fbranch(dc, target, insn, 0);
  1064 + goto jmp_insn;
  1065 + }
  1066 + case 0x4: /* SETHI */
1067 1067 #define OPTIM
1068 1068 #if defined(OPTIM)
1069   - if (rd) { // nop
  1069 + if (rd) { // nop
1070 1070 #endif
1071   - uint32_t value = GET_FIELD(insn, 10, 31);
1072   - gen_movl_imm_T0(value << 10);
1073   - gen_movl_T0_reg(rd);
  1071 + uint32_t value = GET_FIELD(insn, 10, 31);
  1072 + gen_movl_imm_T0(value << 10);
  1073 + gen_movl_T0_reg(rd);
1074 1074 #if defined(OPTIM)
1075   - }
  1075 + }
1076 1076 #endif
1077   - break;
1078   - case 0x0: /* UNIMPL */
1079   - default:
  1077 + break;
  1078 + case 0x0: /* UNIMPL */
  1079 + default:
1080 1080 goto illegal_insn;
1081   - }
1082   - break;
1083   - }
1084   - break;
  1081 + }
  1082 + break;
  1083 + }
  1084 + break;
1085 1085 case 1:
1086   - /*CALL*/ {
1087   - target_long target = GET_FIELDs(insn, 2, 31) << 2;
  1086 + /*CALL*/ {
  1087 + target_long target = GET_FIELDs(insn, 2, 31) << 2;
1088 1088  
1089 1089 #ifdef TARGET_SPARC64
1090   - if (dc->pc == (uint32_t)dc->pc) {
1091   - gen_op_movl_T0_im(dc->pc);
1092   - } else {
1093   - gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1094   - }
  1090 + if (dc->pc == (uint32_t)dc->pc) {
  1091 + gen_op_movl_T0_im(dc->pc);
  1092 + } else {
  1093 + gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
  1094 + }
1095 1095 #else
1096   - gen_op_movl_T0_im(dc->pc);
  1096 + gen_op_movl_T0_im(dc->pc);
1097 1097 #endif
1098   - gen_movl_T0_reg(15);
1099   - target += dc->pc;
  1098 + gen_movl_T0_reg(15);
  1099 + target += dc->pc;
1100 1100 gen_mov_pc_npc(dc);
1101   - dc->npc = target;
1102   - }
1103   - goto jmp_insn;
1104   - case 2: /* FPU & Logical Operations */
1105   - {
1106   - unsigned int xop = GET_FIELD(insn, 7, 12);
1107   - if (xop == 0x3a) { /* generate trap */
  1101 + dc->npc = target;
  1102 + }
  1103 + goto jmp_insn;
  1104 + case 2: /* FPU & Logical Operations */
  1105 + {
  1106 + unsigned int xop = GET_FIELD(insn, 7, 12);
  1107 + if (xop == 0x3a) { /* generate trap */
1108 1108 int cond;
1109 1109  
1110 1110 rs1 = GET_FIELD(insn, 13, 17);
1111 1111 gen_movl_reg_T0(rs1);
1112   - if (IS_IMM) {
1113   - rs2 = GET_FIELD(insn, 25, 31);
  1112 + if (IS_IMM) {
  1113 + rs2 = GET_FIELD(insn, 25, 31);
1114 1114 #if defined(OPTIM)
1115   - if (rs2 != 0) {
  1115 + if (rs2 != 0) {
1116 1116 #endif
1117   - gen_movl_simm_T1(rs2);
1118   - gen_op_add_T1_T0();
  1117 + gen_movl_simm_T1(rs2);
  1118 + gen_op_add_T1_T0();
1119 1119 #if defined(OPTIM)
1120   - }
  1120 + }
1121 1121 #endif
1122 1122 } else {
1123 1123 rs2 = GET_FIELD(insn, 27, 31);
1124 1124 #if defined(OPTIM)
1125   - if (rs2 != 0) {
  1125 + if (rs2 != 0) {
1126 1126 #endif
1127   - gen_movl_reg_T1(rs2);
1128   - gen_op_add_T1_T0();
  1127 + gen_movl_reg_T1(rs2);
  1128 + gen_op_add_T1_T0();
1129 1129 #if defined(OPTIM)
1130   - }
  1130 + }
1131 1131 #endif
1132 1132 }
1133 1133 cond = GET_FIELD(insn, 3, 6);
... ... @@ -1136,20 +1136,20 @@ static void disas_sparc_insn(DisasContext * dc)
1136 1136 gen_op_trap_T0();
1137 1137 } else if (cond != 0) {
1138 1138 #ifdef TARGET_SPARC64
1139   - /* V9 icc/xcc */
1140   - int cc = GET_FIELD_SP(insn, 11, 12);
1141   - flush_T2(dc);
  1139 + /* V9 icc/xcc */
  1140 + int cc = GET_FIELD_SP(insn, 11, 12);
  1141 + flush_T2(dc);
1142 1142 save_state(dc);
1143   - if (cc == 0)
1144   - gen_cond[0][cond]();
1145   - else if (cc == 2)
1146   - gen_cond[1][cond]();
1147   - else
1148   - goto illegal_insn;
  1143 + if (cc == 0)
  1144 + gen_cond[0][cond]();
  1145 + else if (cc == 2)
  1146 + gen_cond[1][cond]();
  1147 + else
  1148 + goto illegal_insn;
1149 1149 #else
1150   - flush_T2(dc);
  1150 + flush_T2(dc);
1151 1151 save_state(dc);
1152   - gen_cond[0][cond]();
  1152 + gen_cond[0][cond]();
1153 1153 #endif
1154 1154 gen_op_trapcc_T0();
1155 1155 }
... ... @@ -1176,56 +1176,56 @@ static void disas_sparc_insn(DisasContext * dc)
1176 1176 gen_movl_T0_reg(rd);
1177 1177 break;
1178 1178 #ifdef TARGET_SPARC64
1179   - case 0x2: /* V9 rdccr */
  1179 + case 0x2: /* V9 rdccr */
1180 1180 gen_op_rdccr();
1181 1181 gen_movl_T0_reg(rd);
1182 1182 break;
1183   - case 0x3: /* V9 rdasi */
1184   - gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
  1183 + case 0x3: /* V9 rdasi */
  1184 + gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1185 1185 gen_movl_T0_reg(rd);
1186 1186 break;
1187   - case 0x4: /* V9 rdtick */
  1187 + case 0x4: /* V9 rdtick */
1188 1188 gen_op_rdtick();
1189 1189 gen_movl_T0_reg(rd);
1190 1190 break;
1191   - case 0x5: /* V9 rdpc */
1192   - if (dc->pc == (uint32_t)dc->pc) {
1193   - gen_op_movl_T0_im(dc->pc);
1194   - } else {
1195   - gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1196   - }
1197   - gen_movl_T0_reg(rd);
1198   - break;
1199   - case 0x6: /* V9 rdfprs */
1200   - gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
  1191 + case 0x5: /* V9 rdpc */
  1192 + if (dc->pc == (uint32_t)dc->pc) {
  1193 + gen_op_movl_T0_im(dc->pc);
  1194 + } else {
  1195 + gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
  1196 + }
  1197 + gen_movl_T0_reg(rd);
  1198 + break;
  1199 + case 0x6: /* V9 rdfprs */
  1200 + gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1201 1201 gen_movl_T0_reg(rd);
1202 1202 break;
1203 1203 case 0xf: /* V9 membar */
1204 1204 break; /* no effect */
1205   - case 0x13: /* Graphics Status */
  1205 + case 0x13: /* Graphics Status */
1206 1206 if (gen_trap_ifnofpu(dc))
1207 1207 goto jmp_insn;
1208   - gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
  1208 + gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1209 1209 gen_movl_T0_reg(rd);
1210 1210 break;
1211   - case 0x17: /* Tick compare */
1212   - gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
  1211 + case 0x17: /* Tick compare */
  1212 + gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1213 1213 gen_movl_T0_reg(rd);
1214 1214 break;
1215   - case 0x18: /* System tick */
  1215 + case 0x18: /* System tick */
1216 1216 gen_op_rdstick();
1217 1217 gen_movl_T0_reg(rd);
1218 1218 break;
1219   - case 0x19: /* System tick compare */
1220   - gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
  1219 + case 0x19: /* System tick compare */
  1220 + gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1221 1221 gen_movl_T0_reg(rd);
1222 1222 break;
1223   - case 0x10: /* Performance Control */
1224   - case 0x11: /* Performance Instrumentation Counter */
1225   - case 0x12: /* Dispatch Control */
1226   - case 0x14: /* Softint set, WO */
1227   - case 0x15: /* Softint clear, WO */
1228   - case 0x16: /* Softint write */
  1223 + case 0x10: /* Performance Control */
  1224 + case 0x11: /* Performance Instrumentation Counter */
  1225 + case 0x12: /* Dispatch Control */
  1226 + case 0x14: /* Softint set, WO */
  1227 + case 0x15: /* Softint clear, WO */
  1228 + case 0x16: /* Softint write */
1229 1229 #endif
1230 1230 default:
1231 1231 goto illegal_insn;
... ... @@ -1233,8 +1233,8 @@ static void disas_sparc_insn(DisasContext * dc)
1233 1233 #if !defined(CONFIG_USER_ONLY)
1234 1234 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
1235 1235 #ifndef TARGET_SPARC64
1236   - if (!supervisor(dc))
1237   - goto priv_insn;
  1236 + if (!supervisor(dc))
  1237 + goto priv_insn;
1238 1238 gen_op_rdpsr();
1239 1239 #else
1240 1240 if (!hypervisor(dc))
... ... @@ -1266,56 +1266,56 @@ static void disas_sparc_insn(DisasContext * dc)
1266 1266 gen_movl_T0_reg(rd);
1267 1267 break;
1268 1268 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1269   - if (!supervisor(dc))
1270   - goto priv_insn;
  1269 + if (!supervisor(dc))
  1270 + goto priv_insn;
1271 1271 #ifdef TARGET_SPARC64
1272 1272 rs1 = GET_FIELD(insn, 13, 17);
1273   - switch (rs1) {
1274   - case 0: // tpc
1275   - gen_op_rdtpc();
1276   - break;
1277   - case 1: // tnpc
1278   - gen_op_rdtnpc();
1279   - break;
1280   - case 2: // tstate
1281   - gen_op_rdtstate();
1282   - break;
1283   - case 3: // tt
1284   - gen_op_rdtt();
1285   - break;
1286   - case 4: // tick
1287   - gen_op_rdtick();
1288   - break;
1289   - case 5: // tba
1290   - gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1291   - break;
1292   - case 6: // pstate
1293   - gen_op_rdpstate();
1294   - break;
1295   - case 7: // tl
1296   - gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1297   - break;
1298   - case 8: // pil
1299   - gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1300   - break;
1301   - case 9: // cwp
1302   - gen_op_rdcwp();
1303   - break;
1304   - case 10: // cansave
1305   - gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1306   - break;
1307   - case 11: // canrestore
1308   - gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1309   - break;
1310   - case 12: // cleanwin
1311   - gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1312   - break;
1313   - case 13: // otherwin
1314   - gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1315   - break;
1316   - case 14: // wstate
1317   - gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1318   - break;
  1273 + switch (rs1) {
  1274 + case 0: // tpc
  1275 + gen_op_rdtpc();
  1276 + break;
  1277 + case 1: // tnpc
  1278 + gen_op_rdtnpc();
  1279 + break;
  1280 + case 2: // tstate
  1281 + gen_op_rdtstate();
  1282 + break;
  1283 + case 3: // tt
  1284 + gen_op_rdtt();
  1285 + break;
  1286 + case 4: // tick
  1287 + gen_op_rdtick();
  1288 + break;
  1289 + case 5: // tba
  1290 + gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
  1291 + break;
  1292 + case 6: // pstate
  1293 + gen_op_rdpstate();
  1294 + break;
  1295 + case 7: // tl
  1296 + gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
  1297 + break;
  1298 + case 8: // pil
  1299 + gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
  1300 + break;
  1301 + case 9: // cwp
  1302 + gen_op_rdcwp();
  1303 + break;
  1304 + case 10: // cansave
  1305 + gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
  1306 + break;
  1307 + case 11: // canrestore
  1308 + gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
  1309 + break;
  1310 + case 12: // cleanwin
  1311 + gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
  1312 + break;
  1313 + case 13: // otherwin
  1314 + gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
  1315 + break;
  1316 + case 14: // wstate
  1317 + gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
  1318 + break;
1319 1319 case 16: // UA2005 gl
1320 1320 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1321 1321 break;
... ... @@ -1324,506 +1324,506 @@ static void disas_sparc_insn(DisasContext * dc)
1324 1324 goto priv_insn;
1325 1325 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1326 1326 break;
1327   - case 31: // ver
1328   - gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1329   - break;
1330   - case 15: // fq
1331   - default:
1332   - goto illegal_insn;
1333   - }
  1327 + case 31: // ver
  1328 + gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
  1329 + break;
  1330 + case 15: // fq
  1331 + default:
  1332 + goto illegal_insn;
  1333 + }
1334 1334 #else
1335   - gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
  1335 + gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1336 1336 #endif
1337 1337 gen_movl_T0_reg(rd);
1338 1338 break;
1339 1339 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1340 1340 #ifdef TARGET_SPARC64
1341   - gen_op_flushw();
  1341 + gen_op_flushw();
1342 1342 #else
1343   - if (!supervisor(dc))
1344   - goto priv_insn;
1345   - gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
  1343 + if (!supervisor(dc))
  1344 + goto priv_insn;
  1345 + gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1346 1346 gen_movl_T0_reg(rd);
1347 1347 #endif
1348 1348 break;
1349 1349 #endif
1350   - } else if (xop == 0x34) { /* FPU Operations */
  1350 + } else if (xop == 0x34) { /* FPU Operations */
1351 1351 if (gen_trap_ifnofpu(dc))
1352 1352 goto jmp_insn;
1353   - gen_op_clear_ieee_excp_and_FTT();
  1353 + gen_op_clear_ieee_excp_and_FTT();
1354 1354 rs1 = GET_FIELD(insn, 13, 17);
1355   - rs2 = GET_FIELD(insn, 27, 31);
1356   - xop = GET_FIELD(insn, 18, 26);
1357   - switch (xop) {
1358   - case 0x1: /* fmovs */
1359   - gen_op_load_fpr_FT0(rs2);
1360   - gen_op_store_FT0_fpr(rd);
1361   - break;
1362   - case 0x5: /* fnegs */
1363   - gen_op_load_fpr_FT1(rs2);
1364   - gen_op_fnegs();
1365   - gen_op_store_FT0_fpr(rd);
1366   - break;
1367   - case 0x9: /* fabss */
1368   - gen_op_load_fpr_FT1(rs2);
1369   - gen_op_fabss();
1370   - gen_op_store_FT0_fpr(rd);
1371   - break;
1372   - case 0x29: /* fsqrts */
1373   - gen_op_load_fpr_FT1(rs2);
1374   - gen_op_fsqrts();
1375   - gen_op_store_FT0_fpr(rd);
1376   - break;
1377   - case 0x2a: /* fsqrtd */
1378   - gen_op_load_fpr_DT1(DFPREG(rs2));
1379   - gen_op_fsqrtd();
1380   - gen_op_store_DT0_fpr(DFPREG(rd));
1381   - break;
1382   - case 0x2b: /* fsqrtq */
1383   - goto nfpu_insn;
1384   - case 0x41:
1385   - gen_op_load_fpr_FT0(rs1);
1386   - gen_op_load_fpr_FT1(rs2);
1387   - gen_op_fadds();
1388   - gen_op_store_FT0_fpr(rd);
1389   - break;
1390   - case 0x42:
1391   - gen_op_load_fpr_DT0(DFPREG(rs1));
1392   - gen_op_load_fpr_DT1(DFPREG(rs2));
1393   - gen_op_faddd();
1394   - gen_op_store_DT0_fpr(DFPREG(rd));
1395   - break;
1396   - case 0x43: /* faddq */
1397   - goto nfpu_insn;
1398   - case 0x45:
1399   - gen_op_load_fpr_FT0(rs1);
1400   - gen_op_load_fpr_FT1(rs2);
1401   - gen_op_fsubs();
1402   - gen_op_store_FT0_fpr(rd);
1403   - break;
1404   - case 0x46:
1405   - gen_op_load_fpr_DT0(DFPREG(rs1));
1406   - gen_op_load_fpr_DT1(DFPREG(rs2));
1407   - gen_op_fsubd();
1408   - gen_op_store_DT0_fpr(DFPREG(rd));
1409   - break;
1410   - case 0x47: /* fsubq */
1411   - goto nfpu_insn;
1412   - case 0x49:
1413   - gen_op_load_fpr_FT0(rs1);
1414   - gen_op_load_fpr_FT1(rs2);
1415   - gen_op_fmuls();
1416   - gen_op_store_FT0_fpr(rd);
1417   - break;
1418   - case 0x4a:
1419   - gen_op_load_fpr_DT0(DFPREG(rs1));
1420   - gen_op_load_fpr_DT1(DFPREG(rs2));
1421   - gen_op_fmuld();
1422   - gen_op_store_DT0_fpr(rd);
1423   - break;
1424   - case 0x4b: /* fmulq */
1425   - goto nfpu_insn;
1426   - case 0x4d:
1427   - gen_op_load_fpr_FT0(rs1);
1428   - gen_op_load_fpr_FT1(rs2);
1429   - gen_op_fdivs();
1430   - gen_op_store_FT0_fpr(rd);
1431   - break;
1432   - case 0x4e:
1433   - gen_op_load_fpr_DT0(DFPREG(rs1));
1434   - gen_op_load_fpr_DT1(DFPREG(rs2));
1435   - gen_op_fdivd();
1436   - gen_op_store_DT0_fpr(DFPREG(rd));
1437   - break;
1438   - case 0x4f: /* fdivq */
1439   - goto nfpu_insn;
1440   - case 0x69:
1441   - gen_op_load_fpr_FT0(rs1);
1442   - gen_op_load_fpr_FT1(rs2);
1443   - gen_op_fsmuld();
1444   - gen_op_store_DT0_fpr(DFPREG(rd));
1445   - break;
1446   - case 0x6e: /* fdmulq */
1447   - goto nfpu_insn;
1448   - case 0xc4:
1449   - gen_op_load_fpr_FT1(rs2);
1450   - gen_op_fitos();
1451   - gen_op_store_FT0_fpr(rd);
1452   - break;
1453   - case 0xc6:
1454   - gen_op_load_fpr_DT1(DFPREG(rs2));
1455   - gen_op_fdtos();
1456   - gen_op_store_FT0_fpr(rd);
1457   - break;
1458   - case 0xc7: /* fqtos */
1459   - goto nfpu_insn;
1460   - case 0xc8:
1461   - gen_op_load_fpr_FT1(rs2);
1462   - gen_op_fitod();
1463   - gen_op_store_DT0_fpr(DFPREG(rd));
1464   - break;
1465   - case 0xc9:
1466   - gen_op_load_fpr_FT1(rs2);
1467   - gen_op_fstod();
1468   - gen_op_store_DT0_fpr(DFPREG(rd));
1469   - break;
1470   - case 0xcb: /* fqtod */
1471   - goto nfpu_insn;
1472   - case 0xcc: /* fitoq */
1473   - goto nfpu_insn;
1474   - case 0xcd: /* fstoq */
1475   - goto nfpu_insn;
1476   - case 0xce: /* fdtoq */
1477   - goto nfpu_insn;
1478   - case 0xd1:
1479   - gen_op_load_fpr_FT1(rs2);
1480   - gen_op_fstoi();
1481   - gen_op_store_FT0_fpr(rd);
1482   - break;
1483   - case 0xd2:
1484   - gen_op_load_fpr_DT1(rs2);
1485   - gen_op_fdtoi();
1486   - gen_op_store_FT0_fpr(rd);
1487   - break;
1488   - case 0xd3: /* fqtoi */
1489   - goto nfpu_insn;
  1355 + rs2 = GET_FIELD(insn, 27, 31);
  1356 + xop = GET_FIELD(insn, 18, 26);
  1357 + switch (xop) {
  1358 + case 0x1: /* fmovs */
  1359 + gen_op_load_fpr_FT0(rs2);
  1360 + gen_op_store_FT0_fpr(rd);
  1361 + break;
  1362 + case 0x5: /* fnegs */
  1363 + gen_op_load_fpr_FT1(rs2);
  1364 + gen_op_fnegs();
  1365 + gen_op_store_FT0_fpr(rd);
  1366 + break;
  1367 + case 0x9: /* fabss */
  1368 + gen_op_load_fpr_FT1(rs2);
  1369 + gen_op_fabss();
  1370 + gen_op_store_FT0_fpr(rd);
  1371 + break;
  1372 + case 0x29: /* fsqrts */
  1373 + gen_op_load_fpr_FT1(rs2);
  1374 + gen_op_fsqrts();
  1375 + gen_op_store_FT0_fpr(rd);
  1376 + break;
  1377 + case 0x2a: /* fsqrtd */
  1378 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1379 + gen_op_fsqrtd();
  1380 + gen_op_store_DT0_fpr(DFPREG(rd));
  1381 + break;
  1382 + case 0x2b: /* fsqrtq */
  1383 + goto nfpu_insn;
  1384 + case 0x41:
  1385 + gen_op_load_fpr_FT0(rs1);
  1386 + gen_op_load_fpr_FT1(rs2);
  1387 + gen_op_fadds();
  1388 + gen_op_store_FT0_fpr(rd);
  1389 + break;
  1390 + case 0x42:
  1391 + gen_op_load_fpr_DT0(DFPREG(rs1));
  1392 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1393 + gen_op_faddd();
  1394 + gen_op_store_DT0_fpr(DFPREG(rd));
  1395 + break;
  1396 + case 0x43: /* faddq */
  1397 + goto nfpu_insn;
  1398 + case 0x45:
  1399 + gen_op_load_fpr_FT0(rs1);
  1400 + gen_op_load_fpr_FT1(rs2);
  1401 + gen_op_fsubs();
  1402 + gen_op_store_FT0_fpr(rd);
  1403 + break;
  1404 + case 0x46:
  1405 + gen_op_load_fpr_DT0(DFPREG(rs1));
  1406 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1407 + gen_op_fsubd();
  1408 + gen_op_store_DT0_fpr(DFPREG(rd));
  1409 + break;
  1410 + case 0x47: /* fsubq */
  1411 + goto nfpu_insn;
  1412 + case 0x49:
  1413 + gen_op_load_fpr_FT0(rs1);
  1414 + gen_op_load_fpr_FT1(rs2);
  1415 + gen_op_fmuls();
  1416 + gen_op_store_FT0_fpr(rd);
  1417 + break;
  1418 + case 0x4a:
  1419 + gen_op_load_fpr_DT0(DFPREG(rs1));
  1420 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1421 + gen_op_fmuld();
  1422 + gen_op_store_DT0_fpr(rd);
  1423 + break;
  1424 + case 0x4b: /* fmulq */
  1425 + goto nfpu_insn;
  1426 + case 0x4d:
  1427 + gen_op_load_fpr_FT0(rs1);
  1428 + gen_op_load_fpr_FT1(rs2);
  1429 + gen_op_fdivs();
  1430 + gen_op_store_FT0_fpr(rd);
  1431 + break;
  1432 + case 0x4e:
  1433 + gen_op_load_fpr_DT0(DFPREG(rs1));
  1434 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1435 + gen_op_fdivd();
  1436 + gen_op_store_DT0_fpr(DFPREG(rd));
  1437 + break;
  1438 + case 0x4f: /* fdivq */
  1439 + goto nfpu_insn;
  1440 + case 0x69:
  1441 + gen_op_load_fpr_FT0(rs1);
  1442 + gen_op_load_fpr_FT1(rs2);
  1443 + gen_op_fsmuld();
  1444 + gen_op_store_DT0_fpr(DFPREG(rd));
  1445 + break;
  1446 + case 0x6e: /* fdmulq */
  1447 + goto nfpu_insn;
  1448 + case 0xc4:
  1449 + gen_op_load_fpr_FT1(rs2);
  1450 + gen_op_fitos();
  1451 + gen_op_store_FT0_fpr(rd);
  1452 + break;
  1453 + case 0xc6:
  1454 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1455 + gen_op_fdtos();
  1456 + gen_op_store_FT0_fpr(rd);
  1457 + break;
  1458 + case 0xc7: /* fqtos */
  1459 + goto nfpu_insn;
  1460 + case 0xc8:
  1461 + gen_op_load_fpr_FT1(rs2);
  1462 + gen_op_fitod();
  1463 + gen_op_store_DT0_fpr(DFPREG(rd));
  1464 + break;
  1465 + case 0xc9:
  1466 + gen_op_load_fpr_FT1(rs2);
  1467 + gen_op_fstod();
  1468 + gen_op_store_DT0_fpr(DFPREG(rd));
  1469 + break;
  1470 + case 0xcb: /* fqtod */
  1471 + goto nfpu_insn;
  1472 + case 0xcc: /* fitoq */
  1473 + goto nfpu_insn;
  1474 + case 0xcd: /* fstoq */
  1475 + goto nfpu_insn;
  1476 + case 0xce: /* fdtoq */
  1477 + goto nfpu_insn;
  1478 + case 0xd1:
  1479 + gen_op_load_fpr_FT1(rs2);
  1480 + gen_op_fstoi();
  1481 + gen_op_store_FT0_fpr(rd);
  1482 + break;
  1483 + case 0xd2:
  1484 + gen_op_load_fpr_DT1(rs2);
  1485 + gen_op_fdtoi();
  1486 + gen_op_store_FT0_fpr(rd);
  1487 + break;
  1488 + case 0xd3: /* fqtoi */
  1489 + goto nfpu_insn;
1490 1490 #ifdef TARGET_SPARC64
1491   - case 0x2: /* V9 fmovd */
1492   - gen_op_load_fpr_DT0(DFPREG(rs2));
1493   - gen_op_store_DT0_fpr(DFPREG(rd));
1494   - break;
1495   - case 0x6: /* V9 fnegd */
1496   - gen_op_load_fpr_DT1(DFPREG(rs2));
1497   - gen_op_fnegd();
1498   - gen_op_store_DT0_fpr(DFPREG(rd));
1499   - break;
1500   - case 0xa: /* V9 fabsd */
1501   - gen_op_load_fpr_DT1(DFPREG(rs2));
1502   - gen_op_fabsd();
1503   - gen_op_store_DT0_fpr(DFPREG(rd));
1504   - break;
1505   - case 0x81: /* V9 fstox */
1506   - gen_op_load_fpr_FT1(rs2);
1507   - gen_op_fstox();
1508   - gen_op_store_DT0_fpr(DFPREG(rd));
1509   - break;
1510   - case 0x82: /* V9 fdtox */
1511   - gen_op_load_fpr_DT1(DFPREG(rs2));
1512   - gen_op_fdtox();
1513   - gen_op_store_DT0_fpr(DFPREG(rd));
1514   - break;
1515   - case 0x84: /* V9 fxtos */
1516   - gen_op_load_fpr_DT1(DFPREG(rs2));
1517   - gen_op_fxtos();
1518   - gen_op_store_FT0_fpr(rd);
1519   - break;
1520   - case 0x88: /* V9 fxtod */
1521   - gen_op_load_fpr_DT1(DFPREG(rs2));
1522   - gen_op_fxtod();
1523   - gen_op_store_DT0_fpr(DFPREG(rd));
1524   - break;
1525   - case 0x3: /* V9 fmovq */
1526   - case 0x7: /* V9 fnegq */
1527   - case 0xb: /* V9 fabsq */
1528   - case 0x83: /* V9 fqtox */
1529   - case 0x8c: /* V9 fxtoq */
1530   - goto nfpu_insn;
1531   -#endif
1532   - default:
1533   - goto illegal_insn;
1534   - }
1535   - } else if (xop == 0x35) { /* FPU Operations */
  1491 + case 0x2: /* V9 fmovd */
  1492 + gen_op_load_fpr_DT0(DFPREG(rs2));
  1493 + gen_op_store_DT0_fpr(DFPREG(rd));
  1494 + break;
  1495 + case 0x6: /* V9 fnegd */
  1496 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1497 + gen_op_fnegd();
  1498 + gen_op_store_DT0_fpr(DFPREG(rd));
  1499 + break;
  1500 + case 0xa: /* V9 fabsd */
  1501 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1502 + gen_op_fabsd();
  1503 + gen_op_store_DT0_fpr(DFPREG(rd));
  1504 + break;
  1505 + case 0x81: /* V9 fstox */
  1506 + gen_op_load_fpr_FT1(rs2);
  1507 + gen_op_fstox();
  1508 + gen_op_store_DT0_fpr(DFPREG(rd));
  1509 + break;
  1510 + case 0x82: /* V9 fdtox */
  1511 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1512 + gen_op_fdtox();
  1513 + gen_op_store_DT0_fpr(DFPREG(rd));
  1514 + break;
  1515 + case 0x84: /* V9 fxtos */
  1516 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1517 + gen_op_fxtos();
  1518 + gen_op_store_FT0_fpr(rd);
  1519 + break;
  1520 + case 0x88: /* V9 fxtod */
  1521 + gen_op_load_fpr_DT1(DFPREG(rs2));
  1522 + gen_op_fxtod();
  1523 + gen_op_store_DT0_fpr(DFPREG(rd));
  1524 + break;
  1525 + case 0x3: /* V9 fmovq */
  1526 + case 0x7: /* V9 fnegq */
  1527 + case 0xb: /* V9 fabsq */
  1528 + case 0x83: /* V9 fqtox */
  1529 + case 0x8c: /* V9 fxtoq */
  1530 + goto nfpu_insn;
  1531 +#endif
  1532 + default:
  1533 + goto illegal_insn;
  1534 + }
  1535 + } else if (xop == 0x35) { /* FPU Operations */
1536 1536 #ifdef TARGET_SPARC64
1537   - int cond;
  1537 + int cond;
1538 1538 #endif
1539 1539 if (gen_trap_ifnofpu(dc))
1540 1540 goto jmp_insn;
1541   - gen_op_clear_ieee_excp_and_FTT();
  1541 + gen_op_clear_ieee_excp_and_FTT();
1542 1542 rs1 = GET_FIELD(insn, 13, 17);
1543   - rs2 = GET_FIELD(insn, 27, 31);
1544   - xop = GET_FIELD(insn, 18, 26);
  1543 + rs2 = GET_FIELD(insn, 27, 31);
  1544 + xop = GET_FIELD(insn, 18, 26);
1545 1545 #ifdef TARGET_SPARC64
1546   - if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1547   - cond = GET_FIELD_SP(insn, 14, 17);
1548   - gen_op_load_fpr_FT0(rd);
1549   - gen_op_load_fpr_FT1(rs2);
1550   - rs1 = GET_FIELD(insn, 13, 17);
1551   - gen_movl_reg_T0(rs1);
1552   - flush_T2(dc);
1553   - gen_cond_reg(cond);
1554   - gen_op_fmovs_cc();
1555   - gen_op_store_FT0_fpr(rd);
1556   - break;
1557   - } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1558   - cond = GET_FIELD_SP(insn, 14, 17);
1559   - gen_op_load_fpr_DT0(rd);
1560   - gen_op_load_fpr_DT1(rs2);
1561   - flush_T2(dc);
1562   - rs1 = GET_FIELD(insn, 13, 17);
1563   - gen_movl_reg_T0(rs1);
1564   - gen_cond_reg(cond);
1565   - gen_op_fmovs_cc();
1566   - gen_op_store_DT0_fpr(rd);
1567   - break;
1568   - } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1569   - goto nfpu_insn;
1570   - }
1571   -#endif
1572   - switch (xop) {
  1546 + if ((xop & 0x11f) == 0x005) { // V9 fmovsr
  1547 + cond = GET_FIELD_SP(insn, 14, 17);
  1548 + gen_op_load_fpr_FT0(rd);
  1549 + gen_op_load_fpr_FT1(rs2);
  1550 + rs1 = GET_FIELD(insn, 13, 17);
  1551 + gen_movl_reg_T0(rs1);
  1552 + flush_T2(dc);
  1553 + gen_cond_reg(cond);
  1554 + gen_op_fmovs_cc();
  1555 + gen_op_store_FT0_fpr(rd);
  1556 + break;
  1557 + } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
  1558 + cond = GET_FIELD_SP(insn, 14, 17);
  1559 + gen_op_load_fpr_DT0(rd);
  1560 + gen_op_load_fpr_DT1(rs2);
  1561 + flush_T2(dc);
  1562 + rs1 = GET_FIELD(insn, 13, 17);
  1563 + gen_movl_reg_T0(rs1);
  1564 + gen_cond_reg(cond);
  1565 + gen_op_fmovs_cc();
  1566 + gen_op_store_DT0_fpr(rd);
  1567 + break;
  1568 + } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
  1569 + goto nfpu_insn;
  1570 + }
  1571 +#endif
  1572 + switch (xop) {
1573 1573 #ifdef TARGET_SPARC64
1574   - case 0x001: /* V9 fmovscc %fcc0 */
1575   - cond = GET_FIELD_SP(insn, 14, 17);
1576   - gen_op_load_fpr_FT0(rd);
1577   - gen_op_load_fpr_FT1(rs2);
1578   - flush_T2(dc);
1579   - gen_fcond[0][cond]();
1580   - gen_op_fmovs_cc();
1581   - gen_op_store_FT0_fpr(rd);
1582   - break;
1583   - case 0x002: /* V9 fmovdcc %fcc0 */
1584   - cond = GET_FIELD_SP(insn, 14, 17);
1585   - gen_op_load_fpr_DT0(rd);
1586   - gen_op_load_fpr_DT1(rs2);
1587   - flush_T2(dc);
1588   - gen_fcond[0][cond]();
1589   - gen_op_fmovd_cc();
1590   - gen_op_store_DT0_fpr(rd);
1591   - break;
1592   - case 0x003: /* V9 fmovqcc %fcc0 */
1593   - goto nfpu_insn;
1594   - case 0x041: /* V9 fmovscc %fcc1 */
1595   - cond = GET_FIELD_SP(insn, 14, 17);
1596   - gen_op_load_fpr_FT0(rd);
1597   - gen_op_load_fpr_FT1(rs2);
1598   - flush_T2(dc);
1599   - gen_fcond[1][cond]();
1600   - gen_op_fmovs_cc();
1601   - gen_op_store_FT0_fpr(rd);
1602   - break;
1603   - case 0x042: /* V9 fmovdcc %fcc1 */
1604   - cond = GET_FIELD_SP(insn, 14, 17);
1605   - gen_op_load_fpr_DT0(rd);
1606   - gen_op_load_fpr_DT1(rs2);
1607   - flush_T2(dc);
1608   - gen_fcond[1][cond]();
1609   - gen_op_fmovd_cc();
1610   - gen_op_store_DT0_fpr(rd);
1611   - break;
1612   - case 0x043: /* V9 fmovqcc %fcc1 */
1613   - goto nfpu_insn;
1614   - case 0x081: /* V9 fmovscc %fcc2 */
1615   - cond = GET_FIELD_SP(insn, 14, 17);
1616   - gen_op_load_fpr_FT0(rd);
1617   - gen_op_load_fpr_FT1(rs2);
1618   - flush_T2(dc);
1619   - gen_fcond[2][cond]();
1620   - gen_op_fmovs_cc();
1621   - gen_op_store_FT0_fpr(rd);
1622   - break;
1623   - case 0x082: /* V9 fmovdcc %fcc2 */
1624   - cond = GET_FIELD_SP(insn, 14, 17);
1625   - gen_op_load_fpr_DT0(rd);
1626   - gen_op_load_fpr_DT1(rs2);
1627   - flush_T2(dc);
1628   - gen_fcond[2][cond]();
1629   - gen_op_fmovd_cc();
1630   - gen_op_store_DT0_fpr(rd);
1631   - break;
1632   - case 0x083: /* V9 fmovqcc %fcc2 */
1633   - goto nfpu_insn;
1634   - case 0x0c1: /* V9 fmovscc %fcc3 */
1635   - cond = GET_FIELD_SP(insn, 14, 17);
1636   - gen_op_load_fpr_FT0(rd);
1637   - gen_op_load_fpr_FT1(rs2);
1638   - flush_T2(dc);
1639   - gen_fcond[3][cond]();
1640   - gen_op_fmovs_cc();
1641   - gen_op_store_FT0_fpr(rd);
1642   - break;
1643   - case 0x0c2: /* V9 fmovdcc %fcc3 */
1644   - cond = GET_FIELD_SP(insn, 14, 17);
1645   - gen_op_load_fpr_DT0(rd);
1646   - gen_op_load_fpr_DT1(rs2);
1647   - flush_T2(dc);
1648   - gen_fcond[3][cond]();
1649   - gen_op_fmovd_cc();
1650   - gen_op_store_DT0_fpr(rd);
1651   - break;
1652   - case 0x0c3: /* V9 fmovqcc %fcc3 */
1653   - goto nfpu_insn;
1654   - case 0x101: /* V9 fmovscc %icc */
1655   - cond = GET_FIELD_SP(insn, 14, 17);
1656   - gen_op_load_fpr_FT0(rd);
1657   - gen_op_load_fpr_FT1(rs2);
1658   - flush_T2(dc);
1659   - gen_cond[0][cond]();
1660   - gen_op_fmovs_cc();
1661   - gen_op_store_FT0_fpr(rd);
1662   - break;
1663   - case 0x102: /* V9 fmovdcc %icc */
1664   - cond = GET_FIELD_SP(insn, 14, 17);
1665   - gen_op_load_fpr_DT0(rd);
1666   - gen_op_load_fpr_DT1(rs2);
1667   - flush_T2(dc);
1668   - gen_cond[0][cond]();
1669   - gen_op_fmovd_cc();
1670   - gen_op_store_DT0_fpr(rd);
1671   - break;
1672   - case 0x103: /* V9 fmovqcc %icc */
1673   - goto nfpu_insn;
1674   - case 0x181: /* V9 fmovscc %xcc */
1675   - cond = GET_FIELD_SP(insn, 14, 17);
1676   - gen_op_load_fpr_FT0(rd);
1677   - gen_op_load_fpr_FT1(rs2);
1678   - flush_T2(dc);
1679   - gen_cond[1][cond]();
1680   - gen_op_fmovs_cc();
1681   - gen_op_store_FT0_fpr(rd);
1682   - break;
1683   - case 0x182: /* V9 fmovdcc %xcc */
1684   - cond = GET_FIELD_SP(insn, 14, 17);
1685   - gen_op_load_fpr_DT0(rd);
1686   - gen_op_load_fpr_DT1(rs2);
1687   - flush_T2(dc);
1688   - gen_cond[1][cond]();
1689   - gen_op_fmovd_cc();
1690   - gen_op_store_DT0_fpr(rd);
1691   - break;
1692   - case 0x183: /* V9 fmovqcc %xcc */
1693   - goto nfpu_insn;
1694   -#endif
1695   - case 0x51: /* V9 %fcc */
1696   - gen_op_load_fpr_FT0(rs1);
1697   - gen_op_load_fpr_FT1(rs2);
  1574 + case 0x001: /* V9 fmovscc %fcc0 */
  1575 + cond = GET_FIELD_SP(insn, 14, 17);
  1576 + gen_op_load_fpr_FT0(rd);
  1577 + gen_op_load_fpr_FT1(rs2);
  1578 + flush_T2(dc);
  1579 + gen_fcond[0][cond]();
  1580 + gen_op_fmovs_cc();
  1581 + gen_op_store_FT0_fpr(rd);
  1582 + break;
  1583 + case 0x002: /* V9 fmovdcc %fcc0 */
  1584 + cond = GET_FIELD_SP(insn, 14, 17);
  1585 + gen_op_load_fpr_DT0(rd);
  1586 + gen_op_load_fpr_DT1(rs2);
  1587 + flush_T2(dc);
  1588 + gen_fcond[0][cond]();
  1589 + gen_op_fmovd_cc();
  1590 + gen_op_store_DT0_fpr(rd);
  1591 + break;
  1592 + case 0x003: /* V9 fmovqcc %fcc0 */
  1593 + goto nfpu_insn;
  1594 + case 0x041: /* V9 fmovscc %fcc1 */
  1595 + cond = GET_FIELD_SP(insn, 14, 17);
  1596 + gen_op_load_fpr_FT0(rd);
  1597 + gen_op_load_fpr_FT1(rs2);
  1598 + flush_T2(dc);
  1599 + gen_fcond[1][cond]();
  1600 + gen_op_fmovs_cc();
  1601 + gen_op_store_FT0_fpr(rd);
  1602 + break;
  1603 + case 0x042: /* V9 fmovdcc %fcc1 */
  1604 + cond = GET_FIELD_SP(insn, 14, 17);
  1605 + gen_op_load_fpr_DT0(rd);
  1606 + gen_op_load_fpr_DT1(rs2);
  1607 + flush_T2(dc);
  1608 + gen_fcond[1][cond]();
  1609 + gen_op_fmovd_cc();
  1610 + gen_op_store_DT0_fpr(rd);
  1611 + break;
  1612 + case 0x043: /* V9 fmovqcc %fcc1 */
  1613 + goto nfpu_insn;
  1614 + case 0x081: /* V9 fmovscc %fcc2 */
  1615 + cond = GET_FIELD_SP(insn, 14, 17);
  1616 + gen_op_load_fpr_FT0(rd);
  1617 + gen_op_load_fpr_FT1(rs2);
  1618 + flush_T2(dc);
  1619 + gen_fcond[2][cond]();
  1620 + gen_op_fmovs_cc();
  1621 + gen_op_store_FT0_fpr(rd);
  1622 + break;
  1623 + case 0x082: /* V9 fmovdcc %fcc2 */
  1624 + cond = GET_FIELD_SP(insn, 14, 17);
  1625 + gen_op_load_fpr_DT0(rd);
  1626 + gen_op_load_fpr_DT1(rs2);
  1627 + flush_T2(dc);
  1628 + gen_fcond[2][cond]();
  1629 + gen_op_fmovd_cc();
  1630 + gen_op_store_DT0_fpr(rd);
  1631 + break;
  1632 + case 0x083: /* V9 fmovqcc %fcc2 */
  1633 + goto nfpu_insn;
  1634 + case 0x0c1: /* V9 fmovscc %fcc3 */
  1635 + cond = GET_FIELD_SP(insn, 14, 17);
  1636 + gen_op_load_fpr_FT0(rd);
  1637 + gen_op_load_fpr_FT1(rs2);
  1638 + flush_T2(dc);
  1639 + gen_fcond[3][cond]();
  1640 + gen_op_fmovs_cc();
  1641 + gen_op_store_FT0_fpr(rd);
  1642 + break;
  1643 + case 0x0c2: /* V9 fmovdcc %fcc3 */
  1644 + cond = GET_FIELD_SP(insn, 14, 17);
  1645 + gen_op_load_fpr_DT0(rd);
  1646 + gen_op_load_fpr_DT1(rs2);
  1647 + flush_T2(dc);
  1648 + gen_fcond[3][cond]();
  1649 + gen_op_fmovd_cc();
  1650 + gen_op_store_DT0_fpr(rd);
  1651 + break;
  1652 + case 0x0c3: /* V9 fmovqcc %fcc3 */
  1653 + goto nfpu_insn;
  1654 + case 0x101: /* V9 fmovscc %icc */
  1655 + cond = GET_FIELD_SP(insn, 14, 17);
  1656 + gen_op_load_fpr_FT0(rd);
  1657 + gen_op_load_fpr_FT1(rs2);
  1658 + flush_T2(dc);
  1659 + gen_cond[0][cond]();
  1660 + gen_op_fmovs_cc();
  1661 + gen_op_store_FT0_fpr(rd);
  1662 + break;
  1663 + case 0x102: /* V9 fmovdcc %icc */
  1664 + cond = GET_FIELD_SP(insn, 14, 17);
  1665 + gen_op_load_fpr_DT0(rd);
  1666 + gen_op_load_fpr_DT1(rs2);
  1667 + flush_T2(dc);
  1668 + gen_cond[0][cond]();
  1669 + gen_op_fmovd_cc();
  1670 + gen_op_store_DT0_fpr(rd);
  1671 + break;
  1672 + case 0x103: /* V9 fmovqcc %icc */
  1673 + goto nfpu_insn;
  1674 + case 0x181: /* V9 fmovscc %xcc */
  1675 + cond = GET_FIELD_SP(insn, 14, 17);
  1676 + gen_op_load_fpr_FT0(rd);
  1677 + gen_op_load_fpr_FT1(rs2);
  1678 + flush_T2(dc);
  1679 + gen_cond[1][cond]();
  1680 + gen_op_fmovs_cc();
  1681 + gen_op_store_FT0_fpr(rd);
  1682 + break;
  1683 + case 0x182: /* V9 fmovdcc %xcc */
  1684 + cond = GET_FIELD_SP(insn, 14, 17);
  1685 + gen_op_load_fpr_DT0(rd);
  1686 + gen_op_load_fpr_DT1(rs2);
  1687 + flush_T2(dc);
  1688 + gen_cond[1][cond]();
  1689 + gen_op_fmovd_cc();
  1690 + gen_op_store_DT0_fpr(rd);
  1691 + break;
  1692 + case 0x183: /* V9 fmovqcc %xcc */
  1693 + goto nfpu_insn;
  1694 +#endif
  1695 + case 0x51: /* V9 %fcc */
  1696 + gen_op_load_fpr_FT0(rs1);
  1697 + gen_op_load_fpr_FT1(rs2);
1698 1698 #ifdef TARGET_SPARC64
1699   - gen_fcmps[rd & 3]();
  1699 + gen_fcmps[rd & 3]();
1700 1700 #else
1701   - gen_op_fcmps();
  1701 + gen_op_fcmps();
1702 1702 #endif
1703   - break;
1704   - case 0x52: /* V9 %fcc */
1705   - gen_op_load_fpr_DT0(DFPREG(rs1));
1706   - gen_op_load_fpr_DT1(DFPREG(rs2));
  1703 + break;
  1704 + case 0x52: /* V9 %fcc */
  1705 + gen_op_load_fpr_DT0(DFPREG(rs1));
  1706 + gen_op_load_fpr_DT1(DFPREG(rs2));
1707 1707 #ifdef TARGET_SPARC64
1708   - gen_fcmpd[rd & 3]();
  1708 + gen_fcmpd[rd & 3]();
1709 1709 #else
1710   - gen_op_fcmpd();
1711   -#endif
1712   - break;
1713   - case 0x53: /* fcmpq */
1714   - goto nfpu_insn;
1715   - case 0x55: /* fcmpes, V9 %fcc */
1716   - gen_op_load_fpr_FT0(rs1);
1717   - gen_op_load_fpr_FT1(rs2);
  1710 + gen_op_fcmpd();
  1711 +#endif
  1712 + break;
  1713 + case 0x53: /* fcmpq */
  1714 + goto nfpu_insn;
  1715 + case 0x55: /* fcmpes, V9 %fcc */
  1716 + gen_op_load_fpr_FT0(rs1);
  1717 + gen_op_load_fpr_FT1(rs2);
1718 1718 #ifdef TARGET_SPARC64
1719   - gen_fcmpes[rd & 3]();
  1719 + gen_fcmpes[rd & 3]();
1720 1720 #else
1721   - gen_op_fcmpes();
  1721 + gen_op_fcmpes();
1722 1722 #endif
1723   - break;
1724   - case 0x56: /* fcmped, V9 %fcc */
1725   - gen_op_load_fpr_DT0(DFPREG(rs1));
1726   - gen_op_load_fpr_DT1(DFPREG(rs2));
  1723 + break;
  1724 + case 0x56: /* fcmped, V9 %fcc */
  1725 + gen_op_load_fpr_DT0(DFPREG(rs1));
  1726 + gen_op_load_fpr_DT1(DFPREG(rs2));
1727 1727 #ifdef TARGET_SPARC64
1728   - gen_fcmped[rd & 3]();
  1728 + gen_fcmped[rd & 3]();
1729 1729 #else
1730   - gen_op_fcmped();
1731   -#endif
1732   - break;
1733   - case 0x57: /* fcmpeq */
1734   - goto nfpu_insn;
1735   - default:
1736   - goto illegal_insn;
1737   - }
  1730 + gen_op_fcmped();
  1731 +#endif
  1732 + break;
  1733 + case 0x57: /* fcmpeq */
  1734 + goto nfpu_insn;
  1735 + default:
  1736 + goto illegal_insn;
  1737 + }
1738 1738 #if defined(OPTIM)
1739   - } else if (xop == 0x2) {
1740   - // clr/mov shortcut
  1739 + } else if (xop == 0x2) {
  1740 + // clr/mov shortcut
1741 1741  
1742 1742 rs1 = GET_FIELD(insn, 13, 17);
1743   - if (rs1 == 0) {
1744   - // or %g0, x, y -> mov T1, x; mov y, T1
1745   - if (IS_IMM) { /* immediate */
1746   - rs2 = GET_FIELDs(insn, 19, 31);
1747   - gen_movl_simm_T1(rs2);
1748   - } else { /* register */
1749   - rs2 = GET_FIELD(insn, 27, 31);
1750   - gen_movl_reg_T1(rs2);
1751   - }
1752   - gen_movl_T1_reg(rd);
1753   - } else {
1754   - gen_movl_reg_T0(rs1);
1755   - if (IS_IMM) { /* immediate */
1756   - // or x, #0, y -> mov T1, x; mov y, T1
1757   - rs2 = GET_FIELDs(insn, 19, 31);
1758   - if (rs2 != 0) {
1759   - gen_movl_simm_T1(rs2);
1760   - gen_op_or_T1_T0();
1761   - }
1762   - } else { /* register */
1763   - // or x, %g0, y -> mov T1, x; mov y, T1
1764   - rs2 = GET_FIELD(insn, 27, 31);
1765   - if (rs2 != 0) {
1766   - gen_movl_reg_T1(rs2);
1767   - gen_op_or_T1_T0();
1768   - }
1769   - }
1770   - gen_movl_T0_reg(rd);
1771   - }
  1743 + if (rs1 == 0) {
  1744 + // or %g0, x, y -> mov T1, x; mov y, T1
  1745 + if (IS_IMM) { /* immediate */
  1746 + rs2 = GET_FIELDs(insn, 19, 31);
  1747 + gen_movl_simm_T1(rs2);
  1748 + } else { /* register */
  1749 + rs2 = GET_FIELD(insn, 27, 31);
  1750 + gen_movl_reg_T1(rs2);
  1751 + }
  1752 + gen_movl_T1_reg(rd);
  1753 + } else {
  1754 + gen_movl_reg_T0(rs1);
  1755 + if (IS_IMM) { /* immediate */
  1756 + // or x, #0, y -> mov T1, x; mov y, T1
  1757 + rs2 = GET_FIELDs(insn, 19, 31);
  1758 + if (rs2 != 0) {
  1759 + gen_movl_simm_T1(rs2);
  1760 + gen_op_or_T1_T0();
  1761 + }
  1762 + } else { /* register */
  1763 + // or x, %g0, y -> mov T1, x; mov y, T1
  1764 + rs2 = GET_FIELD(insn, 27, 31);
  1765 + if (rs2 != 0) {
  1766 + gen_movl_reg_T1(rs2);
  1767 + gen_op_or_T1_T0();
  1768 + }
  1769 + }
  1770 + gen_movl_T0_reg(rd);
  1771 + }
1772 1772 #endif
1773 1773 #ifdef TARGET_SPARC64
1774   - } else if (xop == 0x25) { /* sll, V9 sllx */
  1774 + } else if (xop == 0x25) { /* sll, V9 sllx */
1775 1775 rs1 = GET_FIELD(insn, 13, 17);
1776   - gen_movl_reg_T0(rs1);
1777   - if (IS_IMM) { /* immediate */
  1776 + gen_movl_reg_T0(rs1);
  1777 + if (IS_IMM) { /* immediate */
1778 1778 rs2 = GET_FIELDs(insn, 20, 31);
1779 1779 gen_movl_simm_T1(rs2);
1780   - } else { /* register */
  1780 + } else { /* register */
1781 1781 rs2 = GET_FIELD(insn, 27, 31);
1782 1782 gen_movl_reg_T1(rs2);
1783 1783 }
1784   - if (insn & (1 << 12))
1785   - gen_op_sllx();
1786   - else
1787   - gen_op_sll();
1788   - gen_movl_T0_reg(rd);
1789   - } else if (xop == 0x26) { /* srl, V9 srlx */
  1784 + if (insn & (1 << 12))
  1785 + gen_op_sllx();
  1786 + else
  1787 + gen_op_sll();
  1788 + gen_movl_T0_reg(rd);
  1789 + } else if (xop == 0x26) { /* srl, V9 srlx */
1790 1790 rs1 = GET_FIELD(insn, 13, 17);
1791   - gen_movl_reg_T0(rs1);
1792   - if (IS_IMM) { /* immediate */
  1791 + gen_movl_reg_T0(rs1);
  1792 + if (IS_IMM) { /* immediate */
1793 1793 rs2 = GET_FIELDs(insn, 20, 31);
1794 1794 gen_movl_simm_T1(rs2);
1795   - } else { /* register */
  1795 + } else { /* register */
1796 1796 rs2 = GET_FIELD(insn, 27, 31);
1797 1797 gen_movl_reg_T1(rs2);
1798 1798 }
1799   - if (insn & (1 << 12))
1800   - gen_op_srlx();
1801   - else
1802   - gen_op_srl();
1803   - gen_movl_T0_reg(rd);
1804   - } else if (xop == 0x27) { /* sra, V9 srax */
  1799 + if (insn & (1 << 12))
  1800 + gen_op_srlx();
  1801 + else
  1802 + gen_op_srl();
  1803 + gen_movl_T0_reg(rd);
  1804 + } else if (xop == 0x27) { /* sra, V9 srax */
1805 1805 rs1 = GET_FIELD(insn, 13, 17);
1806   - gen_movl_reg_T0(rs1);
1807   - if (IS_IMM) { /* immediate */
  1806 + gen_movl_reg_T0(rs1);
  1807 + if (IS_IMM) { /* immediate */
1808 1808 rs2 = GET_FIELDs(insn, 20, 31);
1809 1809 gen_movl_simm_T1(rs2);
1810   - } else { /* register */
  1810 + } else { /* register */
1811 1811 rs2 = GET_FIELD(insn, 27, 31);
1812 1812 gen_movl_reg_T1(rs2);
1813 1813 }
1814   - if (insn & (1 << 12))
1815   - gen_op_srax();
1816   - else
1817   - gen_op_sra();
1818   - gen_movl_T0_reg(rd);
  1814 + if (insn & (1 << 12))
  1815 + gen_op_srax();
  1816 + else
  1817 + gen_op_sra();
  1818 + gen_movl_T0_reg(rd);
1819 1819 #endif
1820 1820 } else if (xop < 0x36) {
1821 1821 rs1 = GET_FIELD(insn, 13, 17);
1822   - gen_movl_reg_T0(rs1);
1823   - if (IS_IMM) { /* immediate */
  1822 + gen_movl_reg_T0(rs1);
  1823 + if (IS_IMM) { /* immediate */
1824 1824 rs2 = GET_FIELDs(insn, 19, 31);
1825 1825 gen_movl_simm_T1(rs2);
1826   - } else { /* register */
  1826 + } else { /* register */
1827 1827 rs2 = GET_FIELD(insn, 27, 31);
1828 1828 gen_movl_reg_T1(rs2);
1829 1829 }
... ... @@ -1841,10 +1841,10 @@ static void disas_sparc_insn(DisasContext * dc)
1841 1841 gen_op_logic_T0_cc();
1842 1842 break;
1843 1843 case 0x2:
1844   - gen_op_or_T1_T0();
1845   - if (xop & 0x10)
1846   - gen_op_logic_T0_cc();
1847   - break;
  1844 + gen_op_or_T1_T0();
  1845 + if (xop & 0x10)
  1846 + gen_op_logic_T0_cc();
  1847 + break;
1848 1848 case 0x3:
1849 1849 gen_op_xor_T1_T0();
1850 1850 if (xop & 0x10)
... ... @@ -1878,7 +1878,7 @@ static void disas_sparc_insn(DisasContext * dc)
1878 1878 gen_op_addx_T1_T0();
1879 1879 break;
1880 1880 #ifdef TARGET_SPARC64
1881   - case 0x9: /* V9 mulx */
  1881 + case 0x9: /* V9 mulx */
1882 1882 gen_op_mulx_T1_T0();
1883 1883 break;
1884 1884 #endif
... ... @@ -1899,7 +1899,7 @@ static void disas_sparc_insn(DisasContext * dc)
1899 1899 gen_op_subx_T1_T0();
1900 1900 break;
1901 1901 #ifdef TARGET_SPARC64
1902   - case 0xd: /* V9 udivx */
  1902 + case 0xd: /* V9 udivx */
1903 1903 gen_op_udivx_T1_T0();
1904 1904 break;
1905 1905 #endif
... ... @@ -1916,40 +1916,40 @@ static void disas_sparc_insn(DisasContext * dc)
1916 1916 default:
1917 1917 goto illegal_insn;
1918 1918 }
1919   - gen_movl_T0_reg(rd);
  1919 + gen_movl_T0_reg(rd);
1920 1920 } else {
1921 1921 switch (xop) {
1922   - case 0x20: /* taddcc */
1923   - gen_op_tadd_T1_T0_cc();
1924   - gen_movl_T0_reg(rd);
1925   - break;
1926   - case 0x21: /* tsubcc */
1927   - gen_op_tsub_T1_T0_cc();
1928   - gen_movl_T0_reg(rd);
1929   - break;
1930   - case 0x22: /* taddcctv */
1931   - gen_op_tadd_T1_T0_ccTV();
1932   - gen_movl_T0_reg(rd);
1933   - break;
1934   - case 0x23: /* tsubcctv */
1935   - gen_op_tsub_T1_T0_ccTV();
1936   - gen_movl_T0_reg(rd);
1937   - break;
  1922 + case 0x20: /* taddcc */
  1923 + gen_op_tadd_T1_T0_cc();
  1924 + gen_movl_T0_reg(rd);
  1925 + break;
  1926 + case 0x21: /* tsubcc */
  1927 + gen_op_tsub_T1_T0_cc();
  1928 + gen_movl_T0_reg(rd);
  1929 + break;
  1930 + case 0x22: /* taddcctv */
  1931 + gen_op_tadd_T1_T0_ccTV();
  1932 + gen_movl_T0_reg(rd);
  1933 + break;
  1934 + case 0x23: /* tsubcctv */
  1935 + gen_op_tsub_T1_T0_ccTV();
  1936 + gen_movl_T0_reg(rd);
  1937 + break;
1938 1938 case 0x24: /* mulscc */
1939 1939 gen_op_mulscc_T1_T0();
1940 1940 gen_movl_T0_reg(rd);
1941 1941 break;
1942 1942 #ifndef TARGET_SPARC64
1943   - case 0x25: /* sll */
1944   - gen_op_sll();
  1943 + case 0x25: /* sll */
  1944 + gen_op_sll();
1945 1945 gen_movl_T0_reg(rd);
1946 1946 break;
1947 1947 case 0x26: /* srl */
1948   - gen_op_srl();
  1948 + gen_op_srl();
1949 1949 gen_movl_T0_reg(rd);
1950 1950 break;
1951 1951 case 0x27: /* sra */
1952   - gen_op_sra();
  1952 + gen_op_sra();
1953 1953 gen_movl_T0_reg(rd);
1954 1954 break;
1955 1955 #endif
... ... @@ -1957,8 +1957,8 @@ static void disas_sparc_insn(DisasContext * dc)
1957 1957 {
1958 1958 switch(rd) {
1959 1959 case 0: /* wry */
1960   - gen_op_xor_T1_T0();
1961   - gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
  1960 + gen_op_xor_T1_T0();
  1961 + gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
1962 1962 break;
1963 1963 #ifndef TARGET_SPARC64
1964 1964 case 0x01 ... 0x0f: /* undefined in the
... ... @@ -1971,62 +1971,62 @@ static void disas_sparc_insn(DisasContext * dc)
1971 1971 microSPARC II */
1972 1972 break;
1973 1973 #else
1974   - case 0x2: /* V9 wrccr */
  1974 + case 0x2: /* V9 wrccr */
1975 1975 gen_op_wrccr();
1976   - break;
1977   - case 0x3: /* V9 wrasi */
1978   - gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1979   - break;
1980   - case 0x6: /* V9 wrfprs */
1981   - gen_op_xor_T1_T0();
1982   - gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
  1976 + break;
  1977 + case 0x3: /* V9 wrasi */
  1978 + gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
  1979 + break;
  1980 + case 0x6: /* V9 wrfprs */
  1981 + gen_op_xor_T1_T0();
  1982 + gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1983 1983 save_state(dc);
1984 1984 gen_op_next_insn();
1985 1985 gen_op_movl_T0_0();
1986 1986 gen_op_exit_tb();
1987 1987 dc->is_br = 1;
1988   - break;
1989   - case 0xf: /* V9 sir, nop if user */
  1988 + break;
  1989 + case 0xf: /* V9 sir, nop if user */
1990 1990 #if !defined(CONFIG_USER_ONLY)
1991   - if (supervisor(dc))
1992   - gen_op_sir();
  1991 + if (supervisor(dc))
  1992 + gen_op_sir();
1993 1993 #endif
1994   - break;
1995   - case 0x13: /* Graphics Status */
  1994 + break;
  1995 + case 0x13: /* Graphics Status */
1996 1996 if (gen_trap_ifnofpu(dc))
1997 1997 goto jmp_insn;
1998   - gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
1999   - break;
2000   - case 0x17: /* Tick compare */
  1998 + gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
  1999 + break;
  2000 + case 0x17: /* Tick compare */
2001 2001 #if !defined(CONFIG_USER_ONLY)
2002   - if (!supervisor(dc))
2003   - goto illegal_insn;
  2002 + if (!supervisor(dc))
  2003 + goto illegal_insn;
2004 2004 #endif
2005 2005 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
2006 2006 gen_op_wrtick_cmpr();
2007   - break;
2008   - case 0x18: /* System tick */
  2007 + break;
  2008 + case 0x18: /* System tick */
2009 2009 #if !defined(CONFIG_USER_ONLY)
2010   - if (!supervisor(dc))
2011   - goto illegal_insn;
  2010 + if (!supervisor(dc))
  2011 + goto illegal_insn;
2012 2012 #endif
2013 2013 gen_op_wrstick();
2014   - break;
2015   - case 0x19: /* System tick compare */
  2014 + break;
  2015 + case 0x19: /* System tick compare */
2016 2016 #if !defined(CONFIG_USER_ONLY)
2017   - if (!supervisor(dc))
2018   - goto illegal_insn;
  2017 + if (!supervisor(dc))
  2018 + goto illegal_insn;
2019 2019 #endif
2020 2020 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2021 2021 gen_op_wrstick_cmpr();
2022   - break;
  2022 + break;
2023 2023  
2024   - case 0x10: /* Performance Control */
2025   - case 0x11: /* Performance Instrumentation Counter */
2026   - case 0x12: /* Dispatch Control */
2027   - case 0x14: /* Softint set */
2028   - case 0x15: /* Softint clear */
2029   - case 0x16: /* Softint write */
  2024 + case 0x10: /* Performance Control */
  2025 + case 0x11: /* Performance Instrumentation Counter */
  2026 + case 0x12: /* Dispatch Control */
  2027 + case 0x14: /* Softint set */
  2028 + case 0x15: /* Softint clear */
  2029 + case 0x16: /* Softint write */
2030 2030 #endif
2031 2031 default:
2032 2032 goto illegal_insn;
... ... @@ -2036,22 +2036,22 @@ static void disas_sparc_insn(DisasContext * dc)
2036 2036 #if !defined(CONFIG_USER_ONLY)
2037 2037 case 0x31: /* wrpsr, V9 saved, restored */
2038 2038 {
2039   - if (!supervisor(dc))
2040   - goto priv_insn;
  2039 + if (!supervisor(dc))
  2040 + goto priv_insn;
2041 2041 #ifdef TARGET_SPARC64
2042   - switch (rd) {
2043   - case 0:
2044   - gen_op_saved();
2045   - break;
2046   - case 1:
2047   - gen_op_restored();
2048   - break;
  2042 + switch (rd) {
  2043 + case 0:
  2044 + gen_op_saved();
  2045 + break;
  2046 + case 1:
  2047 + gen_op_restored();
  2048 + break;
2049 2049 case 2: /* UA2005 allclean */
2050 2050 case 3: /* UA2005 otherw */
2051 2051 case 4: /* UA2005 normalw */
2052 2052 case 5: /* UA2005 invalw */
2053 2053 // XXX
2054   - default:
  2054 + default:
2055 2055 goto illegal_insn;
2056 2056 }
2057 2057 #else
... ... @@ -2059,69 +2059,69 @@ static void disas_sparc_insn(DisasContext * dc)
2059 2059 gen_op_wrpsr();
2060 2060 save_state(dc);
2061 2061 gen_op_next_insn();
2062   - gen_op_movl_T0_0();
2063   - gen_op_exit_tb();
2064   - dc->is_br = 1;
  2062 + gen_op_movl_T0_0();
  2063 + gen_op_exit_tb();
  2064 + dc->is_br = 1;
2065 2065 #endif
2066 2066 }
2067 2067 break;
2068 2068 case 0x32: /* wrwim, V9 wrpr */
2069 2069 {
2070   - if (!supervisor(dc))
2071   - goto priv_insn;
  2070 + if (!supervisor(dc))
  2071 + goto priv_insn;
2072 2072 gen_op_xor_T1_T0();
2073 2073 #ifdef TARGET_SPARC64
2074   - switch (rd) {
2075   - case 0: // tpc
2076   - gen_op_wrtpc();
2077   - break;
2078   - case 1: // tnpc
2079   - gen_op_wrtnpc();
2080   - break;
2081   - case 2: // tstate
2082   - gen_op_wrtstate();
2083   - break;
2084   - case 3: // tt
2085   - gen_op_wrtt();
2086   - break;
2087   - case 4: // tick
2088   - gen_op_wrtick();
2089   - break;
2090   - case 5: // tba
2091   - gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2092   - break;
2093   - case 6: // pstate
2094   - gen_op_wrpstate();
  2074 + switch (rd) {
  2075 + case 0: // tpc
  2076 + gen_op_wrtpc();
  2077 + break;
  2078 + case 1: // tnpc
  2079 + gen_op_wrtnpc();
  2080 + break;
  2081 + case 2: // tstate
  2082 + gen_op_wrtstate();
  2083 + break;
  2084 + case 3: // tt
  2085 + gen_op_wrtt();
  2086 + break;
  2087 + case 4: // tick
  2088 + gen_op_wrtick();
  2089 + break;
  2090 + case 5: // tba
  2091 + gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
  2092 + break;
  2093 + case 6: // pstate
  2094 + gen_op_wrpstate();
2095 2095 save_state(dc);
2096 2096 gen_op_next_insn();
2097 2097 gen_op_movl_T0_0();
2098 2098 gen_op_exit_tb();
2099 2099 dc->is_br = 1;
2100   - break;
2101   - case 7: // tl
2102   - gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2103   - break;
2104   - case 8: // pil
2105   - gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2106   - break;
2107   - case 9: // cwp
2108   - gen_op_wrcwp();
2109   - break;
2110   - case 10: // cansave
2111   - gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2112   - break;
2113   - case 11: // canrestore
2114   - gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2115   - break;
2116   - case 12: // cleanwin
2117   - gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2118   - break;
2119   - case 13: // otherwin
2120   - gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2121   - break;
2122   - case 14: // wstate
2123   - gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2124   - break;
  2100 + break;
  2101 + case 7: // tl
  2102 + gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
  2103 + break;
  2104 + case 8: // pil
  2105 + gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
  2106 + break;
  2107 + case 9: // cwp
  2108 + gen_op_wrcwp();
  2109 + break;
  2110 + case 10: // cansave
  2111 + gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
  2112 + break;
  2113 + case 11: // canrestore
  2114 + gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
  2115 + break;
  2116 + case 12: // cleanwin
  2117 + gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
  2118 + break;
  2119 + case 13: // otherwin
  2120 + gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
  2121 + break;
  2122 + case 14: // wstate
  2123 + gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
  2124 + break;
2125 2125 case 16: // UA2005 gl
2126 2126 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2127 2127 break;
... ... @@ -2130,19 +2130,19 @@ static void disas_sparc_insn(DisasContext * dc)
2130 2130 goto priv_insn;
2131 2131 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2132 2132 break;
2133   - default:
2134   - goto illegal_insn;
2135   - }
  2133 + default:
  2134 + goto illegal_insn;
  2135 + }
2136 2136 #else
2137   - gen_op_wrwim();
  2137 + gen_op_wrwim();
2138 2138 #endif
2139 2139 }
2140 2140 break;
2141 2141 case 0x33: /* wrtbr, UA2005 wrhpr */
2142 2142 {
2143 2143 #ifndef TARGET_SPARC64
2144   - if (!supervisor(dc))
2145   - goto priv_insn;
  2144 + if (!supervisor(dc))
  2145 + goto priv_insn;
2146 2146 gen_op_xor_T1_T0();
2147 2147 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2148 2148 #else
... ... @@ -2180,77 +2180,77 @@ static void disas_sparc_insn(DisasContext * dc)
2180 2180 break;
2181 2181 #endif
2182 2182 #ifdef TARGET_SPARC64
2183   - case 0x2c: /* V9 movcc */
2184   - {
2185   - int cc = GET_FIELD_SP(insn, 11, 12);
2186   - int cond = GET_FIELD_SP(insn, 14, 17);
2187   - if (IS_IMM) { /* immediate */
2188   - rs2 = GET_FIELD_SPs(insn, 0, 10);
2189   - gen_movl_simm_T1(rs2);
2190   - }
2191   - else {
2192   - rs2 = GET_FIELD_SP(insn, 0, 4);
2193   - gen_movl_reg_T1(rs2);
2194   - }
2195   - gen_movl_reg_T0(rd);
2196   - flush_T2(dc);
2197   - if (insn & (1 << 18)) {
2198   - if (cc == 0)
2199   - gen_cond[0][cond]();
2200   - else if (cc == 2)
2201   - gen_cond[1][cond]();
2202   - else
2203   - goto illegal_insn;
2204   - } else {
2205   - gen_fcond[cc][cond]();
2206   - }
2207   - gen_op_mov_cc();
2208   - gen_movl_T0_reg(rd);
2209   - break;
2210   - }
2211   - case 0x2d: /* V9 sdivx */
  2183 + case 0x2c: /* V9 movcc */
  2184 + {
  2185 + int cc = GET_FIELD_SP(insn, 11, 12);
  2186 + int cond = GET_FIELD_SP(insn, 14, 17);
  2187 + if (IS_IMM) { /* immediate */
  2188 + rs2 = GET_FIELD_SPs(insn, 0, 10);
  2189 + gen_movl_simm_T1(rs2);
  2190 + }
  2191 + else {
  2192 + rs2 = GET_FIELD_SP(insn, 0, 4);
  2193 + gen_movl_reg_T1(rs2);
  2194 + }
  2195 + gen_movl_reg_T0(rd);
  2196 + flush_T2(dc);
  2197 + if (insn & (1 << 18)) {
  2198 + if (cc == 0)
  2199 + gen_cond[0][cond]();
  2200 + else if (cc == 2)
  2201 + gen_cond[1][cond]();
  2202 + else
  2203 + goto illegal_insn;
  2204 + } else {
  2205 + gen_fcond[cc][cond]();
  2206 + }
  2207 + gen_op_mov_cc();
  2208 + gen_movl_T0_reg(rd);
  2209 + break;
  2210 + }
  2211 + case 0x2d: /* V9 sdivx */
2212 2212 gen_op_sdivx_T1_T0();
2213   - gen_movl_T0_reg(rd);
2214   - break;
2215   - case 0x2e: /* V9 popc */
2216   - {
2217   - if (IS_IMM) { /* immediate */
2218   - rs2 = GET_FIELD_SPs(insn, 0, 12);
2219   - gen_movl_simm_T1(rs2);
2220   - // XXX optimize: popc(constant)
2221   - }
2222   - else {
2223   - rs2 = GET_FIELD_SP(insn, 0, 4);
2224   - gen_movl_reg_T1(rs2);
2225   - }
2226   - gen_op_popc();
2227   - gen_movl_T0_reg(rd);
2228   - }
2229   - case 0x2f: /* V9 movr */
2230   - {
2231   - int cond = GET_FIELD_SP(insn, 10, 12);
2232   - rs1 = GET_FIELD(insn, 13, 17);
2233   - flush_T2(dc);
2234   - gen_movl_reg_T0(rs1);
2235   - gen_cond_reg(cond);
2236   - if (IS_IMM) { /* immediate */
2237   - rs2 = GET_FIELD_SPs(insn, 0, 9);
2238   - gen_movl_simm_T1(rs2);
2239   - }
2240   - else {
2241   - rs2 = GET_FIELD_SP(insn, 0, 4);
2242   - gen_movl_reg_T1(rs2);
2243   - }
2244   - gen_movl_reg_T0(rd);
2245   - gen_op_mov_cc();
2246   - gen_movl_T0_reg(rd);
2247   - break;
2248   - }
2249   -#endif
2250   - default:
2251   - goto illegal_insn;
2252   - }
2253   - }
  2213 + gen_movl_T0_reg(rd);
  2214 + break;
  2215 + case 0x2e: /* V9 popc */
  2216 + {
  2217 + if (IS_IMM) { /* immediate */
  2218 + rs2 = GET_FIELD_SPs(insn, 0, 12);
  2219 + gen_movl_simm_T1(rs2);
  2220 + // XXX optimize: popc(constant)
  2221 + }
  2222 + else {
  2223 + rs2 = GET_FIELD_SP(insn, 0, 4);
  2224 + gen_movl_reg_T1(rs2);
  2225 + }
  2226 + gen_op_popc();
  2227 + gen_movl_T0_reg(rd);
  2228 + }
  2229 + case 0x2f: /* V9 movr */
  2230 + {
  2231 + int cond = GET_FIELD_SP(insn, 10, 12);
  2232 + rs1 = GET_FIELD(insn, 13, 17);
  2233 + flush_T2(dc);
  2234 + gen_movl_reg_T0(rs1);
  2235 + gen_cond_reg(cond);
  2236 + if (IS_IMM) { /* immediate */
  2237 + rs2 = GET_FIELD_SPs(insn, 0, 9);
  2238 + gen_movl_simm_T1(rs2);
  2239 + }
  2240 + else {
  2241 + rs2 = GET_FIELD_SP(insn, 0, 4);
  2242 + gen_movl_reg_T1(rs2);
  2243 + }
  2244 + gen_movl_reg_T0(rd);
  2245 + gen_op_mov_cc();
  2246 + gen_movl_T0_reg(rd);
  2247 + break;
  2248 + }
  2249 +#endif
  2250 + default:
  2251 + goto illegal_insn;
  2252 + }
  2253 + }
2254 2254 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2255 2255 #ifdef TARGET_SPARC64
2256 2256 int opf = GET_FIELD_SP(insn, 5, 13);
... ... @@ -2647,75 +2647,75 @@ static void disas_sparc_insn(DisasContext * dc)
2647 2647 goto illegal_insn;
2648 2648 }
2649 2649 #else
2650   - goto ncp_insn;
  2650 + goto ncp_insn;
2651 2651 #endif
2652 2652 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
2653 2653 #ifdef TARGET_SPARC64
2654   - goto illegal_insn;
  2654 + goto illegal_insn;
2655 2655 #else
2656   - goto ncp_insn;
  2656 + goto ncp_insn;
2657 2657 #endif
2658 2658 #ifdef TARGET_SPARC64
2659   - } else if (xop == 0x39) { /* V9 return */
  2659 + } else if (xop == 0x39) { /* V9 return */
2660 2660 rs1 = GET_FIELD(insn, 13, 17);
2661 2661 save_state(dc);
2662   - gen_movl_reg_T0(rs1);
2663   - if (IS_IMM) { /* immediate */
2664   - rs2 = GET_FIELDs(insn, 19, 31);
  2662 + gen_movl_reg_T0(rs1);
  2663 + if (IS_IMM) { /* immediate */
  2664 + rs2 = GET_FIELDs(insn, 19, 31);
2665 2665 #if defined(OPTIM)
2666   - if (rs2) {
  2666 + if (rs2) {
2667 2667 #endif
2668   - gen_movl_simm_T1(rs2);
2669   - gen_op_add_T1_T0();
  2668 + gen_movl_simm_T1(rs2);
  2669 + gen_op_add_T1_T0();
2670 2670 #if defined(OPTIM)
2671   - }
  2671 + }
2672 2672 #endif
2673   - } else { /* register */
  2673 + } else { /* register */
2674 2674 rs2 = GET_FIELD(insn, 27, 31);
2675 2675 #if defined(OPTIM)
2676   - if (rs2) {
  2676 + if (rs2) {
2677 2677 #endif
2678   - gen_movl_reg_T1(rs2);
2679   - gen_op_add_T1_T0();
  2678 + gen_movl_reg_T1(rs2);
  2679 + gen_op_add_T1_T0();
2680 2680 #if defined(OPTIM)
2681   - }
  2681 + }
2682 2682 #endif
2683 2683 }
2684   - gen_op_restore();
2685   - gen_mov_pc_npc(dc);
  2684 + gen_op_restore();
  2685 + gen_mov_pc_npc(dc);
2686 2686 gen_op_check_align_T0_3();
2687   - gen_op_movl_npc_T0();
2688   - dc->npc = DYNAMIC_PC;
2689   - goto jmp_insn;
  2687 + gen_op_movl_npc_T0();
  2688 + dc->npc = DYNAMIC_PC;
  2689 + goto jmp_insn;
2690 2690 #endif
2691   - } else {
  2691 + } else {
2692 2692 rs1 = GET_FIELD(insn, 13, 17);
2693   - gen_movl_reg_T0(rs1);
2694   - if (IS_IMM) { /* immediate */
2695   - rs2 = GET_FIELDs(insn, 19, 31);
  2693 + gen_movl_reg_T0(rs1);
  2694 + if (IS_IMM) { /* immediate */
  2695 + rs2 = GET_FIELDs(insn, 19, 31);
2696 2696 #if defined(OPTIM)
2697   - if (rs2) {
  2697 + if (rs2) {
2698 2698 #endif
2699   - gen_movl_simm_T1(rs2);
2700   - gen_op_add_T1_T0();
  2699 + gen_movl_simm_T1(rs2);
  2700 + gen_op_add_T1_T0();
2701 2701 #if defined(OPTIM)
2702   - }
  2702 + }
2703 2703 #endif
2704   - } else { /* register */
  2704 + } else { /* register */
2705 2705 rs2 = GET_FIELD(insn, 27, 31);
2706 2706 #if defined(OPTIM)
2707   - if (rs2) {
  2707 + if (rs2) {
2708 2708 #endif
2709   - gen_movl_reg_T1(rs2);
2710   - gen_op_add_T1_T0();
  2709 + gen_movl_reg_T1(rs2);
  2710 + gen_op_add_T1_T0();
2711 2711 #if defined(OPTIM)
2712   - }
  2712 + }
2713 2713 #endif
2714 2714 }
2715   - switch (xop) {
2716   - case 0x38: /* jmpl */
2717   - {
2718   - if (rd != 0) {
  2715 + switch (xop) {
  2716 + case 0x38: /* jmpl */
  2717 + {
  2718 + if (rd != 0) {
2719 2719 #ifdef TARGET_SPARC64
2720 2720 if (dc->pc == (uint32_t)dc->pc) {
2721 2721 gen_op_movl_T1_im(dc->pc);
... ... @@ -2723,250 +2723,250 @@ static void disas_sparc_insn(DisasContext * dc)
2723 2723 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2724 2724 }
2725 2725 #else
2726   - gen_op_movl_T1_im(dc->pc);
  2726 + gen_op_movl_T1_im(dc->pc);
2727 2727 #endif
2728   - gen_movl_T1_reg(rd);
2729   - }
  2728 + gen_movl_T1_reg(rd);
  2729 + }
2730 2730 gen_mov_pc_npc(dc);
2731 2731 gen_op_check_align_T0_3();
2732   - gen_op_movl_npc_T0();
2733   - dc->npc = DYNAMIC_PC;
2734   - }
2735   - goto jmp_insn;
  2732 + gen_op_movl_npc_T0();
  2733 + dc->npc = DYNAMIC_PC;
  2734 + }
  2735 + goto jmp_insn;
2736 2736 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2737   - case 0x39: /* rett, V9 return */
2738   - {
2739   - if (!supervisor(dc))
2740   - goto priv_insn;
  2737 + case 0x39: /* rett, V9 return */
  2738 + {
  2739 + if (!supervisor(dc))
  2740 + goto priv_insn;
2741 2741 gen_mov_pc_npc(dc);
2742 2742 gen_op_check_align_T0_3();
2743   - gen_op_movl_npc_T0();
2744   - dc->npc = DYNAMIC_PC;
2745   - gen_op_rett();
2746   - }
2747   - goto jmp_insn;
2748   -#endif
2749   - case 0x3b: /* flush */
2750   - gen_op_flush_T0();
2751   - break;
2752   - case 0x3c: /* save */
2753   - save_state(dc);
2754   - gen_op_save();
2755   - gen_movl_T0_reg(rd);
2756   - break;
2757   - case 0x3d: /* restore */
2758   - save_state(dc);
2759   - gen_op_restore();
2760   - gen_movl_T0_reg(rd);
2761   - break;
  2743 + gen_op_movl_npc_T0();
  2744 + dc->npc = DYNAMIC_PC;
  2745 + gen_op_rett();
  2746 + }
  2747 + goto jmp_insn;
  2748 +#endif
  2749 + case 0x3b: /* flush */
  2750 + gen_op_flush_T0();
  2751 + break;
  2752 + case 0x3c: /* save */
  2753 + save_state(dc);
  2754 + gen_op_save();
  2755 + gen_movl_T0_reg(rd);
  2756 + break;
  2757 + case 0x3d: /* restore */
  2758 + save_state(dc);
  2759 + gen_op_restore();
  2760 + gen_movl_T0_reg(rd);
  2761 + break;
2762 2762 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
2763   - case 0x3e: /* V9 done/retry */
2764   - {
2765   - switch (rd) {
2766   - case 0:
2767   - if (!supervisor(dc))
2768   - goto priv_insn;
2769   - dc->npc = DYNAMIC_PC;
2770   - dc->pc = DYNAMIC_PC;
2771   - gen_op_done();
2772   - goto jmp_insn;
2773   - case 1:
2774   - if (!supervisor(dc))
2775   - goto priv_insn;
2776   - dc->npc = DYNAMIC_PC;
2777   - dc->pc = DYNAMIC_PC;
2778   - gen_op_retry();
2779   - goto jmp_insn;
2780   - default:
2781   - goto illegal_insn;
2782   - }
2783   - }
2784   - break;
2785   -#endif
2786   - default:
2787   - goto illegal_insn;
2788   - }
  2763 + case 0x3e: /* V9 done/retry */
  2764 + {
  2765 + switch (rd) {
  2766 + case 0:
  2767 + if (!supervisor(dc))
  2768 + goto priv_insn;
  2769 + dc->npc = DYNAMIC_PC;
  2770 + dc->pc = DYNAMIC_PC;
  2771 + gen_op_done();
  2772 + goto jmp_insn;
  2773 + case 1:
  2774 + if (!supervisor(dc))
  2775 + goto priv_insn;
  2776 + dc->npc = DYNAMIC_PC;
  2777 + dc->pc = DYNAMIC_PC;
  2778 + gen_op_retry();
  2779 + goto jmp_insn;
  2780 + default:
  2781 + goto illegal_insn;
  2782 + }
  2783 + }
  2784 + break;
  2785 +#endif
  2786 + default:
  2787 + goto illegal_insn;
  2788 + }
2789 2789 }
2790   - break;
2791   - }
2792   - break;
2793   - case 3: /* load/store instructions */
2794   - {
2795   - unsigned int xop = GET_FIELD(insn, 7, 12);
2796   - rs1 = GET_FIELD(insn, 13, 17);
  2790 + break;
  2791 + }
  2792 + break;
  2793 + case 3: /* load/store instructions */
  2794 + {
  2795 + unsigned int xop = GET_FIELD(insn, 7, 12);
  2796 + rs1 = GET_FIELD(insn, 13, 17);
2797 2797 save_state(dc);
2798   - gen_movl_reg_T0(rs1);
2799   - if (IS_IMM) { /* immediate */
2800   - rs2 = GET_FIELDs(insn, 19, 31);
  2798 + gen_movl_reg_T0(rs1);
  2799 + if (IS_IMM) { /* immediate */
  2800 + rs2 = GET_FIELDs(insn, 19, 31);
2801 2801 #if defined(OPTIM)
2802   - if (rs2 != 0) {
  2802 + if (rs2 != 0) {
2803 2803 #endif
2804   - gen_movl_simm_T1(rs2);
2805   - gen_op_add_T1_T0();
  2804 + gen_movl_simm_T1(rs2);
  2805 + gen_op_add_T1_T0();
2806 2806 #if defined(OPTIM)
2807   - }
  2807 + }
2808 2808 #endif
2809   - } else { /* register */
2810   - rs2 = GET_FIELD(insn, 27, 31);
  2809 + } else { /* register */
  2810 + rs2 = GET_FIELD(insn, 27, 31);
2811 2811 #if defined(OPTIM)
2812   - if (rs2 != 0) {
  2812 + if (rs2 != 0) {
2813 2813 #endif
2814   - gen_movl_reg_T1(rs2);
2815   - gen_op_add_T1_T0();
  2814 + gen_movl_reg_T1(rs2);
  2815 + gen_op_add_T1_T0();
2816 2816 #if defined(OPTIM)
2817   - }
  2817 + }
2818 2818 #endif
2819   - }
  2819 + }
2820 2820 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
2821 2821 (xop > 0x17 && xop <= 0x1d ) ||
2822 2822 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
2823   - switch (xop) {
2824   - case 0x0: /* load word */
  2823 + switch (xop) {
  2824 + case 0x0: /* load word */
2825 2825 #ifdef CONFIG_USER_ONLY
2826 2826 gen_op_check_align_T0_3();
2827 2827 #endif
2828 2828 #ifndef TARGET_SPARC64
2829   - gen_op_ldst(ld);
  2829 + gen_op_ldst(ld);
2830 2830 #else
2831 2831 gen_op_ldst(lduw);
2832 2832 #endif
2833   - break;
2834   - case 0x1: /* load unsigned byte */
2835   - gen_op_ldst(ldub);
2836   - break;
2837   - case 0x2: /* load unsigned halfword */
  2833 + break;
  2834 + case 0x1: /* load unsigned byte */
  2835 + gen_op_ldst(ldub);
  2836 + break;
  2837 + case 0x2: /* load unsigned halfword */
2838 2838 #ifdef CONFIG_USER_ONLY
2839 2839 gen_op_check_align_T0_1();
2840 2840 #endif
2841   - gen_op_ldst(lduh);
2842   - break;
2843   - case 0x3: /* load double word */
  2841 + gen_op_ldst(lduh);
  2842 + break;
  2843 + case 0x3: /* load double word */
2844 2844 gen_op_check_align_T0_7();
2845   - if (rd & 1)
  2845 + if (rd & 1)
2846 2846 goto illegal_insn;
2847   - gen_op_ldst(ldd);
2848   - gen_movl_T0_reg(rd + 1);
2849   - break;
2850   - case 0x9: /* load signed byte */
2851   - gen_op_ldst(ldsb);
2852   - break;
2853   - case 0xa: /* load signed halfword */
  2847 + gen_op_ldst(ldd);
  2848 + gen_movl_T0_reg(rd + 1);
  2849 + break;
  2850 + case 0x9: /* load signed byte */
  2851 + gen_op_ldst(ldsb);
  2852 + break;
  2853 + case 0xa: /* load signed halfword */
2854 2854 #ifdef CONFIG_USER_ONLY
2855 2855 gen_op_check_align_T0_1();
2856 2856 #endif
2857   - gen_op_ldst(ldsh);
2858   - break;
2859   - case 0xd: /* ldstub -- XXX: should be atomically */
2860   - gen_op_ldst(ldstub);
2861   - break;
2862   - case 0x0f: /* swap register with memory. Also atomically */
  2857 + gen_op_ldst(ldsh);
  2858 + break;
  2859 + case 0xd: /* ldstub -- XXX: should be atomically */
  2860 + gen_op_ldst(ldstub);
  2861 + break;
  2862 + case 0x0f: /* swap register with memory. Also atomically */
2863 2863 #ifdef CONFIG_USER_ONLY
2864 2864 gen_op_check_align_T0_3();
2865 2865 #endif
2866   - gen_movl_reg_T1(rd);
2867   - gen_op_ldst(swap);
2868   - break;
  2866 + gen_movl_reg_T1(rd);
  2867 + gen_op_ldst(swap);
  2868 + break;
2869 2869 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2870   - case 0x10: /* load word alternate */
  2870 + case 0x10: /* load word alternate */
2871 2871 #ifndef TARGET_SPARC64
2872   - if (IS_IMM)
2873   - goto illegal_insn;
2874   - if (!supervisor(dc))
2875   - goto priv_insn;
  2872 + if (IS_IMM)
  2873 + goto illegal_insn;
  2874 + if (!supervisor(dc))
  2875 + goto priv_insn;
2876 2876 #ifdef CONFIG_USER_ONLY
2877 2877 gen_op_check_align_T0_3();
2878 2878 #endif
2879   - gen_op_lda(insn, 1, 4, 0);
  2879 + gen_op_lda(insn, 1, 4, 0);
2880 2880 #else
2881 2881 #ifdef CONFIG_USER_ONLY
2882 2882 gen_op_check_align_T0_3();
2883 2883 #endif
2884 2884 gen_op_lduwa(insn, 1, 4, 0);
2885 2885 #endif
2886   - break;
2887   - case 0x11: /* load unsigned byte alternate */
  2886 + break;
  2887 + case 0x11: /* load unsigned byte alternate */
2888 2888 #ifndef TARGET_SPARC64
2889   - if (IS_IMM)
2890   - goto illegal_insn;
2891   - if (!supervisor(dc))
2892   - goto priv_insn;
2893   -#endif
2894   - gen_op_lduba(insn, 1, 1, 0);
2895   - break;
2896   - case 0x12: /* load unsigned halfword alternate */
  2889 + if (IS_IMM)
  2890 + goto illegal_insn;
  2891 + if (!supervisor(dc))
  2892 + goto priv_insn;
  2893 +#endif
  2894 + gen_op_lduba(insn, 1, 1, 0);
  2895 + break;
  2896 + case 0x12: /* load unsigned halfword alternate */
2897 2897 #ifndef TARGET_SPARC64
2898   - if (IS_IMM)
2899   - goto illegal_insn;
2900   - if (!supervisor(dc))
2901   - goto priv_insn;
  2898 + if (IS_IMM)
  2899 + goto illegal_insn;
  2900 + if (!supervisor(dc))
  2901 + goto priv_insn;
2902 2902 #endif
2903 2903 #ifdef CONFIG_USER_ONLY
2904 2904 gen_op_check_align_T0_1();
2905 2905 #endif
2906   - gen_op_lduha(insn, 1, 2, 0);
2907   - break;
2908   - case 0x13: /* load double word alternate */
  2906 + gen_op_lduha(insn, 1, 2, 0);
  2907 + break;
  2908 + case 0x13: /* load double word alternate */
2909 2909 #ifndef TARGET_SPARC64
2910   - if (IS_IMM)
2911   - goto illegal_insn;
2912   - if (!supervisor(dc))
2913   - goto priv_insn;
  2910 + if (IS_IMM)
  2911 + goto illegal_insn;
  2912 + if (!supervisor(dc))
  2913 + goto priv_insn;
2914 2914 #endif
2915   - if (rd & 1)
  2915 + if (rd & 1)
2916 2916 goto illegal_insn;
2917 2917 gen_op_check_align_T0_7();
2918   - gen_op_ldda(insn, 1, 8, 0);
2919   - gen_movl_T0_reg(rd + 1);
2920   - break;
2921   - case 0x19: /* load signed byte alternate */
  2918 + gen_op_ldda(insn, 1, 8, 0);
  2919 + gen_movl_T0_reg(rd + 1);
  2920 + break;
  2921 + case 0x19: /* load signed byte alternate */
2922 2922 #ifndef TARGET_SPARC64
2923   - if (IS_IMM)
2924   - goto illegal_insn;
2925   - if (!supervisor(dc))
2926   - goto priv_insn;
2927   -#endif
2928   - gen_op_ldsba(insn, 1, 1, 1);
2929   - break;
2930   - case 0x1a: /* load signed halfword alternate */
  2923 + if (IS_IMM)
  2924 + goto illegal_insn;
  2925 + if (!supervisor(dc))
  2926 + goto priv_insn;
  2927 +#endif
  2928 + gen_op_ldsba(insn, 1, 1, 1);
  2929 + break;
  2930 + case 0x1a: /* load signed halfword alternate */
2931 2931 #ifndef TARGET_SPARC64
2932   - if (IS_IMM)
2933   - goto illegal_insn;
2934   - if (!supervisor(dc))
2935   - goto priv_insn;
  2932 + if (IS_IMM)
  2933 + goto illegal_insn;
  2934 + if (!supervisor(dc))
  2935 + goto priv_insn;
2936 2936 #endif
2937 2937 #ifdef CONFIG_USER_ONLY
2938 2938 gen_op_check_align_T0_1();
2939 2939 #endif
2940   - gen_op_ldsha(insn, 1, 2 ,1);
2941   - break;
2942   - case 0x1d: /* ldstuba -- XXX: should be atomically */
  2940 + gen_op_ldsha(insn, 1, 2 ,1);
  2941 + break;
  2942 + case 0x1d: /* ldstuba -- XXX: should be atomically */
2943 2943 #ifndef TARGET_SPARC64
2944   - if (IS_IMM)
2945   - goto illegal_insn;
2946   - if (!supervisor(dc))
2947   - goto priv_insn;
2948   -#endif
2949   - gen_op_ldstuba(insn, 1, 1, 0);
2950   - break;
2951   - case 0x1f: /* swap reg with alt. memory. Also atomically */
  2944 + if (IS_IMM)
  2945 + goto illegal_insn;
  2946 + if (!supervisor(dc))
  2947 + goto priv_insn;
  2948 +#endif
  2949 + gen_op_ldstuba(insn, 1, 1, 0);
  2950 + break;
  2951 + case 0x1f: /* swap reg with alt. memory. Also atomically */
2952 2952 #ifndef TARGET_SPARC64
2953   - if (IS_IMM)
2954   - goto illegal_insn;
2955   - if (!supervisor(dc))
2956   - goto priv_insn;
  2953 + if (IS_IMM)
  2954 + goto illegal_insn;
  2955 + if (!supervisor(dc))
  2956 + goto priv_insn;
2957 2957 #endif
2958   - gen_movl_reg_T1(rd);
  2958 + gen_movl_reg_T1(rd);
2959 2959 #ifdef CONFIG_USER_ONLY
2960 2960 gen_op_check_align_T0_3();
2961 2961 #endif
2962   - gen_op_swapa(insn, 1, 4, 0);
2963   - break;
  2962 + gen_op_swapa(insn, 1, 4, 0);
  2963 + break;
2964 2964  
2965 2965 #ifndef TARGET_SPARC64
2966   - case 0x30: /* ldc */
2967   - case 0x31: /* ldcsr */
2968   - case 0x33: /* lddc */
2969   - goto ncp_insn;
  2966 + case 0x30: /* ldc */
  2967 + case 0x31: /* ldcsr */
  2968 + case 0x33: /* lddc */
  2969 + goto ncp_insn;
2970 2970 /* avoid warnings */
2971 2971 (void) &gen_op_stfa;
2972 2972 (void) &gen_op_stdfa;
... ... @@ -2975,260 +2975,260 @@ static void disas_sparc_insn(DisasContext * dc)
2975 2975 #else
2976 2976 (void) &gen_op_lda;
2977 2977 #if !defined(CONFIG_USER_ONLY)
2978   - (void) &gen_op_cas;
2979   - (void) &gen_op_casx;
  2978 + (void) &gen_op_cas;
  2979 + (void) &gen_op_casx;
2980 2980 #endif
2981 2981 #endif
2982 2982 #endif
2983 2983 #ifdef TARGET_SPARC64
2984   - case 0x08: /* V9 ldsw */
  2984 + case 0x08: /* V9 ldsw */
2985 2985 #ifdef CONFIG_USER_ONLY
2986 2986 gen_op_check_align_T0_3();
2987 2987 #endif
2988   - gen_op_ldst(ldsw);
2989   - break;
2990   - case 0x0b: /* V9 ldx */
  2988 + gen_op_ldst(ldsw);
  2989 + break;
  2990 + case 0x0b: /* V9 ldx */
2991 2991 gen_op_check_align_T0_7();
2992   - gen_op_ldst(ldx);
2993   - break;
2994   - case 0x18: /* V9 ldswa */
  2992 + gen_op_ldst(ldx);
  2993 + break;
  2994 + case 0x18: /* V9 ldswa */
2995 2995 #ifdef CONFIG_USER_ONLY
2996 2996 gen_op_check_align_T0_3();
2997 2997 #endif
2998   - gen_op_ldswa(insn, 1, 4, 1);
2999   - break;
3000   - case 0x1b: /* V9 ldxa */
  2998 + gen_op_ldswa(insn, 1, 4, 1);
  2999 + break;
  3000 + case 0x1b: /* V9 ldxa */
3001 3001 gen_op_check_align_T0_7();
3002   - gen_op_ldxa(insn, 1, 8, 0);
3003   - break;
3004   - case 0x2d: /* V9 prefetch, no effect */
3005   - goto skip_move;
3006   - case 0x30: /* V9 ldfa */
  3002 + gen_op_ldxa(insn, 1, 8, 0);
  3003 + break;
  3004 + case 0x2d: /* V9 prefetch, no effect */
  3005 + goto skip_move;
  3006 + case 0x30: /* V9 ldfa */
3007 3007 #ifdef CONFIG_USER_ONLY
3008 3008 gen_op_check_align_T0_3();
3009 3009 #endif
3010   - gen_op_ldfa(insn, 1, 8, 0); // XXX
3011   - break;
3012   - case 0x33: /* V9 lddfa */
  3010 + gen_op_ldfa(insn, 1, 8, 0); // XXX
  3011 + break;
  3012 + case 0x33: /* V9 lddfa */
3013 3013 gen_op_check_align_T0_7();
3014   - gen_op_lddfa(insn, 1, 8, 0); // XXX
3015   -
3016   - break;
3017   - case 0x3d: /* V9 prefetcha, no effect */
3018   - goto skip_move;
3019   - case 0x32: /* V9 ldqfa */
3020   - goto nfpu_insn;
3021   -#endif
3022   - default:
3023   - goto illegal_insn;
3024   - }
3025   - gen_movl_T1_reg(rd);
  3014 + gen_op_lddfa(insn, 1, 8, 0); // XXX
  3015 +
  3016 + break;
  3017 + case 0x3d: /* V9 prefetcha, no effect */
  3018 + goto skip_move;
  3019 + case 0x32: /* V9 ldqfa */
  3020 + goto nfpu_insn;
  3021 +#endif
  3022 + default:
  3023 + goto illegal_insn;
  3024 + }
  3025 + gen_movl_T1_reg(rd);
3026 3026 #ifdef TARGET_SPARC64
3027   - skip_move: ;
  3027 + skip_move: ;
3028 3028 #endif
3029   - } else if (xop >= 0x20 && xop < 0x24) {
  3029 + } else if (xop >= 0x20 && xop < 0x24) {
3030 3030 if (gen_trap_ifnofpu(dc))
3031 3031 goto jmp_insn;
3032   - switch (xop) {
3033   - case 0x20: /* load fpreg */
  3032 + switch (xop) {
  3033 + case 0x20: /* load fpreg */
3034 3034 #ifdef CONFIG_USER_ONLY
3035 3035 gen_op_check_align_T0_3();
3036 3036 #endif
3037   - gen_op_ldst(ldf);
3038   - gen_op_store_FT0_fpr(rd);
3039   - break;
3040   - case 0x21: /* load fsr */
  3037 + gen_op_ldst(ldf);
  3038 + gen_op_store_FT0_fpr(rd);
  3039 + break;
  3040 + case 0x21: /* load fsr */
3041 3041 #ifdef CONFIG_USER_ONLY
3042 3042 gen_op_check_align_T0_3();
3043 3043 #endif
3044   - gen_op_ldst(ldf);
3045   - gen_op_ldfsr();
3046   - break;
3047   - case 0x22: /* load quad fpreg */
3048   - goto nfpu_insn;
3049   - case 0x23: /* load double fpreg */
  3044 + gen_op_ldst(ldf);
  3045 + gen_op_ldfsr();
  3046 + break;
  3047 + case 0x22: /* load quad fpreg */
  3048 + goto nfpu_insn;
  3049 + case 0x23: /* load double fpreg */
3050 3050 gen_op_check_align_T0_7();
3051   - gen_op_ldst(lddf);
3052   - gen_op_store_DT0_fpr(DFPREG(rd));
3053   - break;
3054   - default:
3055   - goto illegal_insn;
3056   - }
3057   - } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
3058   - xop == 0xe || xop == 0x1e) {
3059   - gen_movl_reg_T1(rd);
3060   - switch (xop) {
3061   - case 0x4:
  3051 + gen_op_ldst(lddf);
  3052 + gen_op_store_DT0_fpr(DFPREG(rd));
  3053 + break;
  3054 + default:
  3055 + goto illegal_insn;
  3056 + }
  3057 + } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
  3058 + xop == 0xe || xop == 0x1e) {
  3059 + gen_movl_reg_T1(rd);
  3060 + switch (xop) {
  3061 + case 0x4:
3062 3062 #ifdef CONFIG_USER_ONLY
3063 3063 gen_op_check_align_T0_3();
3064 3064 #endif
3065   - gen_op_ldst(st);
3066   - break;
3067   - case 0x5:
3068   - gen_op_ldst(stb);
3069   - break;
3070   - case 0x6:
  3065 + gen_op_ldst(st);
  3066 + break;
  3067 + case 0x5:
  3068 + gen_op_ldst(stb);
  3069 + break;
  3070 + case 0x6:
3071 3071 #ifdef CONFIG_USER_ONLY
3072 3072 gen_op_check_align_T0_1();
3073 3073 #endif
3074   - gen_op_ldst(sth);
3075   - break;
3076   - case 0x7:
3077   - if (rd & 1)
  3074 + gen_op_ldst(sth);
  3075 + break;
  3076 + case 0x7:
  3077 + if (rd & 1)
3078 3078 goto illegal_insn;
3079 3079 gen_op_check_align_T0_7();
3080 3080 flush_T2(dc);
3081   - gen_movl_reg_T2(rd + 1);
3082   - gen_op_ldst(std);
3083   - break;
  3081 + gen_movl_reg_T2(rd + 1);
  3082 + gen_op_ldst(std);
  3083 + break;
3084 3084 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3085   - case 0x14:
  3085 + case 0x14:
3086 3086 #ifndef TARGET_SPARC64
3087   - if (IS_IMM)
3088   - goto illegal_insn;
3089   - if (!supervisor(dc))
3090   - goto priv_insn;
  3087 + if (IS_IMM)
  3088 + goto illegal_insn;
  3089 + if (!supervisor(dc))
  3090 + goto priv_insn;
3091 3091 #endif
3092 3092 #ifdef CONFIG_USER_ONLY
3093 3093 gen_op_check_align_T0_3();
3094 3094 #endif
3095   - gen_op_sta(insn, 0, 4, 0);
  3095 + gen_op_sta(insn, 0, 4, 0);
3096 3096 break;
3097   - case 0x15:
  3097 + case 0x15:
3098 3098 #ifndef TARGET_SPARC64
3099   - if (IS_IMM)
3100   - goto illegal_insn;
3101   - if (!supervisor(dc))
3102   - goto priv_insn;
  3099 + if (IS_IMM)
  3100 + goto illegal_insn;
  3101 + if (!supervisor(dc))
  3102 + goto priv_insn;
3103 3103 #endif
3104   - gen_op_stba(insn, 0, 1, 0);
  3104 + gen_op_stba(insn, 0, 1, 0);
3105 3105 break;
3106   - case 0x16:
  3106 + case 0x16:
3107 3107 #ifndef TARGET_SPARC64
3108   - if (IS_IMM)
3109   - goto illegal_insn;
3110   - if (!supervisor(dc))
3111   - goto priv_insn;
  3108 + if (IS_IMM)
  3109 + goto illegal_insn;
  3110 + if (!supervisor(dc))
  3111 + goto priv_insn;
3112 3112 #endif
3113 3113 #ifdef CONFIG_USER_ONLY
3114 3114 gen_op_check_align_T0_1();
3115 3115 #endif
3116   - gen_op_stha(insn, 0, 2, 0);
  3116 + gen_op_stha(insn, 0, 2, 0);
3117 3117 break;
3118   - case 0x17:
  3118 + case 0x17:
3119 3119 #ifndef TARGET_SPARC64
3120   - if (IS_IMM)
3121   - goto illegal_insn;
3122   - if (!supervisor(dc))
3123   - goto priv_insn;
  3120 + if (IS_IMM)
  3121 + goto illegal_insn;
  3122 + if (!supervisor(dc))
  3123 + goto priv_insn;
3124 3124 #endif
3125   - if (rd & 1)
  3125 + if (rd & 1)
3126 3126 goto illegal_insn;
3127 3127 gen_op_check_align_T0_7();
3128 3128 flush_T2(dc);
3129   - gen_movl_reg_T2(rd + 1);
3130   - gen_op_stda(insn, 0, 8, 0);
  3129 + gen_movl_reg_T2(rd + 1);
  3130 + gen_op_stda(insn, 0, 8, 0);
3131 3131 break;
3132 3132 #endif
3133 3133 #ifdef TARGET_SPARC64
3134   - case 0x0e: /* V9 stx */
  3134 + case 0x0e: /* V9 stx */
3135 3135 gen_op_check_align_T0_7();
3136   - gen_op_ldst(stx);
3137   - break;
3138   - case 0x1e: /* V9 stxa */
  3136 + gen_op_ldst(stx);
  3137 + break;
  3138 + case 0x1e: /* V9 stxa */
3139 3139 gen_op_check_align_T0_7();
3140   - gen_op_stxa(insn, 0, 8, 0); // XXX
3141   - break;
  3140 + gen_op_stxa(insn, 0, 8, 0); // XXX
  3141 + break;
3142 3142 #endif
3143   - default:
3144   - goto illegal_insn;
3145   - }
3146   - } else if (xop > 0x23 && xop < 0x28) {
  3143 + default:
  3144 + goto illegal_insn;
  3145 + }
  3146 + } else if (xop > 0x23 && xop < 0x28) {
3147 3147 if (gen_trap_ifnofpu(dc))
3148 3148 goto jmp_insn;
3149   - switch (xop) {
3150   - case 0x24:
  3149 + switch (xop) {
  3150 + case 0x24:
3151 3151 #ifdef CONFIG_USER_ONLY
3152 3152 gen_op_check_align_T0_3();
3153 3153 #endif
3154 3154 gen_op_load_fpr_FT0(rd);
3155   - gen_op_ldst(stf);
3156   - break;
3157   - case 0x25: /* stfsr, V9 stxfsr */
  3155 + gen_op_ldst(stf);
  3156 + break;
  3157 + case 0x25: /* stfsr, V9 stxfsr */
3158 3158 #ifdef CONFIG_USER_ONLY
3159 3159 gen_op_check_align_T0_3();
3160 3160 #endif
3161   - gen_op_stfsr();
3162   - gen_op_ldst(stf);
3163   - break;
  3161 + gen_op_stfsr();
  3162 + gen_op_ldst(stf);
  3163 + break;
3164 3164 #if !defined(CONFIG_USER_ONLY)
3165   - case 0x26: /* stdfq */
3166   - if (!supervisor(dc))
3167   - goto priv_insn;
3168   - if (gen_trap_ifnofpu(dc))
3169   - goto jmp_insn;
3170   - goto nfq_insn;
3171   -#endif
3172   - case 0x27:
  3165 + case 0x26: /* stdfq */
  3166 + if (!supervisor(dc))
  3167 + goto priv_insn;
  3168 + if (gen_trap_ifnofpu(dc))
  3169 + goto jmp_insn;
  3170 + goto nfq_insn;
  3171 +#endif
  3172 + case 0x27:
3173 3173 gen_op_check_align_T0_7();
3174 3174 gen_op_load_fpr_DT0(DFPREG(rd));
3175   - gen_op_ldst(stdf);
3176   - break;
3177   - default:
3178   - goto illegal_insn;
3179   - }
3180   - } else if (xop > 0x33 && xop < 0x3f) {
3181   - switch (xop) {
  3175 + gen_op_ldst(stdf);
  3176 + break;
  3177 + default:
  3178 + goto illegal_insn;
  3179 + }
  3180 + } else if (xop > 0x33 && xop < 0x3f) {
  3181 + switch (xop) {
3182 3182 #ifdef TARGET_SPARC64
3183   - case 0x34: /* V9 stfa */
  3183 + case 0x34: /* V9 stfa */
3184 3184 #ifdef CONFIG_USER_ONLY
3185 3185 gen_op_check_align_T0_3();
3186 3186 #endif
3187   - gen_op_stfa(insn, 0, 0, 0); // XXX
3188   - break;
3189   - case 0x37: /* V9 stdfa */
  3187 + gen_op_stfa(insn, 0, 0, 0); // XXX
  3188 + break;
  3189 + case 0x37: /* V9 stdfa */
3190 3190 gen_op_check_align_T0_7();
3191   - gen_op_stdfa(insn, 0, 0, 0); // XXX
3192   - break;
3193   - case 0x3c: /* V9 casa */
  3191 + gen_op_stdfa(insn, 0, 0, 0); // XXX
  3192 + break;
  3193 + case 0x3c: /* V9 casa */
3194 3194 #ifdef CONFIG_USER_ONLY
3195 3195 gen_op_check_align_T0_3();
3196 3196 #endif
3197   - gen_op_casa(insn, 0, 4, 0); // XXX
3198   - break;
3199   - case 0x3e: /* V9 casxa */
  3197 + gen_op_casa(insn, 0, 4, 0); // XXX
  3198 + break;
  3199 + case 0x3e: /* V9 casxa */
3200 3200 gen_op_check_align_T0_7();
3201   - gen_op_casxa(insn, 0, 8, 0); // XXX
3202   - break;
3203   - case 0x36: /* V9 stqfa */
3204   - goto nfpu_insn;
  3201 + gen_op_casxa(insn, 0, 8, 0); // XXX
  3202 + break;
  3203 + case 0x36: /* V9 stqfa */
  3204 + goto nfpu_insn;
3205 3205 #else
3206   - case 0x34: /* stc */
3207   - case 0x35: /* stcsr */
3208   - case 0x36: /* stdcq */
3209   - case 0x37: /* stdc */
3210   - goto ncp_insn;
3211   -#endif
3212   - default:
3213   - goto illegal_insn;
3214   - }
  3206 + case 0x34: /* stc */
  3207 + case 0x35: /* stcsr */
  3208 + case 0x36: /* stdcq */
  3209 + case 0x37: /* stdc */
  3210 + goto ncp_insn;
  3211 +#endif
  3212 + default:
  3213 + goto illegal_insn;
  3214 + }
3215 3215 }
3216   - else
3217   - goto illegal_insn;
3218   - }
3219   - break;
  3216 + else
  3217 + goto illegal_insn;
  3218 + }
  3219 + break;
3220 3220 }
3221 3221 /* default case for non jump instructions */
3222 3222 if (dc->npc == DYNAMIC_PC) {
3223   - dc->pc = DYNAMIC_PC;
3224   - gen_op_next_insn();
  3223 + dc->pc = DYNAMIC_PC;
  3224 + gen_op_next_insn();
3225 3225 } else if (dc->npc == JUMP_PC) {
3226 3226 /* we can do a static jump */
3227 3227 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
3228 3228 dc->is_br = 1;
3229 3229 } else {
3230   - dc->pc = dc->npc;
3231   - dc->npc = dc->npc + 4;
  3230 + dc->pc = dc->npc;
  3231 + dc->npc = dc->npc + 4;
3232 3232 }
3233 3233 jmp_insn:
3234 3234 return;
... ... @@ -3266,7 +3266,7 @@ static void disas_sparc_insn(DisasContext * dc)
3266 3266 }
3267 3267  
3268 3268 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3269   - int spc, CPUSPARCState *env)
  3269 + int spc, CPUSPARCState *env)
3270 3270 {
3271 3271 target_ulong pc_start, last_pc;
3272 3272 uint16_t *gen_opc_end;
... ... @@ -3299,12 +3299,12 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3299 3299 if (env->nb_breakpoints > 0) {
3300 3300 for(j = 0; j < env->nb_breakpoints; j++) {
3301 3301 if (env->breakpoints[j] == dc->pc) {
3302   - if (dc->pc != pc_start)
3303   - save_state(dc);
  3302 + if (dc->pc != pc_start)
  3303 + save_state(dc);
3304 3304 gen_op_debug();
3305   - gen_op_movl_T0_0();
3306   - gen_op_exit_tb();
3307   - dc->is_br = 1;
  3305 + gen_op_movl_T0_0();
  3306 + gen_op_exit_tb();
  3307 + dc->is_br = 1;
3308 3308 goto exit_gen_loop;
3309 3309 }
3310 3310 }
... ... @@ -3322,14 +3322,14 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3322 3322 gen_opc_instr_start[lj] = 1;
3323 3323 }
3324 3324 }
3325   - last_pc = dc->pc;
3326   - disas_sparc_insn(dc);
3327   -
3328   - if (dc->is_br)
3329   - break;
3330   - /* if the next PC is different, we abort now */
3331   - if (dc->pc != (last_pc + 4))
3332   - break;
  3325 + last_pc = dc->pc;
  3326 + disas_sparc_insn(dc);
  3327 +
  3328 + if (dc->is_br)
  3329 + break;
  3330 + /* if the next PC is different, we abort now */
  3331 + if (dc->pc != (last_pc + 4))
  3332 + break;
3333 3333 /* if we reach a page boundary, we stop generation so that the
3334 3334 PC of a TT_TFAULT exception is always in the right page */
3335 3335 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
... ... @@ -3343,7 +3343,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3343 3343 break;
3344 3344 }
3345 3345 } while ((gen_opc_ptr < gen_opc_end) &&
3346   - (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
  3346 + (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
3347 3347  
3348 3348 exit_gen_loop:
3349 3349 if (!dc->is_br) {
... ... @@ -3377,10 +3377,10 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3377 3377 }
3378 3378 #ifdef DEBUG_DISAS
3379 3379 if (loglevel & CPU_LOG_TB_IN_ASM) {
3380   - fprintf(logfile, "--------------\n");
3381   - fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3382   - target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3383   - fprintf(logfile, "\n");
  3380 + fprintf(logfile, "--------------\n");
  3381 + fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
  3382 + target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
  3383 + fprintf(logfile, "\n");
3384 3384 if (loglevel & CPU_LOG_TB_OP) {
3385 3385 fprintf(logfile, "OP:\n");
3386 3386 dump_ops(gen_opc_buf, gen_opparam_buf);
... ... @@ -3438,7 +3438,7 @@ CPUSPARCState *cpu_sparc_init(void)
3438 3438  
3439 3439 env = qemu_mallocz(sizeof(CPUSPARCState));
3440 3440 if (!env)
3441   - return NULL;
  3441 + return NULL;
3442 3442 cpu_exec_init(env);
3443 3443 cpu_reset(env);
3444 3444 return (env);
... ... @@ -3539,22 +3539,22 @@ void cpu_dump_state(CPUState *env, FILE *f,
3539 3539 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
3540 3540 cpu_fprintf(f, "General Registers:\n");
3541 3541 for (i = 0; i < 4; i++)
3542   - cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
  3542 + cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3543 3543 cpu_fprintf(f, "\n");
3544 3544 for (; i < 8; i++)
3545   - cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
  3545 + cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3546 3546 cpu_fprintf(f, "\nCurrent Register Window:\n");
3547 3547 for (x = 0; x < 3; x++) {
3548   - for (i = 0; i < 4; i++)
3549   - cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3550   - (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
3551   - env->regwptr[i + x * 8]);
3552   - cpu_fprintf(f, "\n");
3553   - for (; i < 8; i++)
3554   - cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3555   - (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
3556   - env->regwptr[i + x * 8]);
3557   - cpu_fprintf(f, "\n");
  3548 + for (i = 0; i < 4; i++)
  3549 + cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
  3550 + (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
  3551 + env->regwptr[i + x * 8]);
  3552 + cpu_fprintf(f, "\n");
  3553 + for (; i < 8; i++)
  3554 + cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
  3555 + (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
  3556 + env->regwptr[i + x * 8]);
  3557 + cpu_fprintf(f, "\n");
3558 3558 }
3559 3559 cpu_fprintf(f, "\nFloating Point Registers:\n");
3560 3560 for (i = 0; i < 32; i++) {
... ... @@ -3566,16 +3566,16 @@ void cpu_dump_state(CPUState *env, FILE *f,
3566 3566 }
3567 3567 #ifdef TARGET_SPARC64
3568 3568 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
3569   - env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
  3569 + env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
3570 3570 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3571   - env->cansave, env->canrestore, env->otherwin, env->wstate,
3572   - env->cleanwin, NWINDOWS - 1 - env->cwp);
  3571 + env->cansave, env->canrestore, env->otherwin, env->wstate,
  3572 + env->cleanwin, NWINDOWS - 1 - env->cwp);
3573 3573 #else
3574 3574 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
3575   - GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
3576   - GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
3577   - env->psrs?'S':'-', env->psrps?'P':'-',
3578   - env->psret?'E':'-', env->wim);
  3575 + GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
  3576 + GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
  3577 + env->psrs?'S':'-', env->psrps?'P':'-',
  3578 + env->psret?'E':'-', env->wim);
3579 3579 #endif
3580 3580 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
3581 3581 }
... ...