Commit 0cfe11ea5fff6a62dd28f116ec5d227d682b08e7

Authored by aurel32
1 parent ef7ec1c1

target-ppc: improve mfcr/mtcrf

- use ctz32 instead of ffs - 1
- small optimisation of mtcrf
- add the name of both opcodes

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc/translate.c
@@ -28,6 +28,7 @@ @@ -28,6 +28,7 @@
28 #include "disas.h" 28 #include "disas.h"
29 #include "tcg-op.h" 29 #include "tcg-op.h"
30 #include "qemu-common.h" 30 #include "qemu-common.h"
  31 +#include "host-utils.h"
31 32
32 #include "helper.h" 33 #include "helper.h"
33 #define GEN_HELPER 1 34 #define GEN_HELPER 1
@@ -3836,7 +3837,7 @@ GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC) @@ -3836,7 +3837,7 @@ GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3836 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA)); 3837 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3837 } 3838 }
3838 3839
3839 -/* mfcr */ 3840 +/* mfcr mfocrf */
3840 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC) 3841 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3841 { 3842 {
3842 uint32_t crm, crn; 3843 uint32_t crm, crn;
@@ -3844,7 +3845,7 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC) @@ -3844,7 +3845,7 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3844 if (likely(ctx->opcode & 0x00100000)) { 3845 if (likely(ctx->opcode & 0x00100000)) {
3845 crm = CRM(ctx->opcode); 3846 crm = CRM(ctx->opcode);
3846 if (likely(crm && ((crm & (crm - 1)) == 0))) { 3847 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3847 - crn = ffs (crm) - 1; 3848 + crn = ctz32 (crm);
3848 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 3849 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3849 tcg_gen_shli_i32(cpu_gpr[rD(ctx->opcode)], 3850 tcg_gen_shli_i32(cpu_gpr[rD(ctx->opcode)],
3850 cpu_gpr[rD(ctx->opcode)], crn * 4); 3851 cpu_gpr[rD(ctx->opcode)], crn * 4);
@@ -3931,7 +3932,7 @@ GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB) @@ -3931,7 +3932,7 @@ GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3931 gen_op_mfspr(ctx); 3932 gen_op_mfspr(ctx);
3932 } 3933 }
3933 3934
3934 -/* mtcrf */ 3935 +/* mtcrf mtocrf*/
3935 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) 3936 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3936 { 3937 {
3937 uint32_t crm, crn; 3938 uint32_t crm, crn;
@@ -3940,10 +3941,10 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) @@ -3940,10 +3941,10 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3940 if (likely((ctx->opcode & 0x00100000))) { 3941 if (likely((ctx->opcode & 0x00100000))) {
3941 if (crm && ((crm & (crm - 1)) == 0)) { 3942 if (crm && ((crm & (crm - 1)) == 0)) {
3942 TCGv_i32 temp = tcg_temp_new_i32(); 3943 TCGv_i32 temp = tcg_temp_new_i32();
3943 - crn = ffs (crm) - 1; 3944 + crn = ctz32 (crm);
3944 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 3945 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3945 - tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);  
3946 - tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 3946 + tcg_gen_shri_i32(temp, temp, crn * 4);
  3947 + tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3947 tcg_temp_free_i32(temp); 3948 tcg_temp_free_i32(temp);
3948 } 3949 }
3949 } else { 3950 } else {
target-ppc/translate_init.c
@@ -24,7 +24,6 @@ @@ -24,7 +24,6 @@
24 */ 24 */
25 25
26 #include "dis-asm.h" 26 #include "dis-asm.h"
27 -#include "host-utils.h"  
28 #include "gdbstub.h" 27 #include "gdbstub.h"
29 28
30 //#define PPC_DUMP_CPU 29 //#define PPC_DUMP_CPU