gwj / at91sam9263 · Commits

Commit ef7ec1c16d184c6b7296d681aaa7e4f37cb57c6c

Authored by aurel32
1 parent 8dd640e4

clean build: Fix remaining sh4 warnings 

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6668 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 4 changed files with 9 additions and 28 deletions
hw/shix.c
  View file @ef7ec1c
... ... @@ -45,21 +45,6 @@ void pic_info(void)
45 45 /* XXXXX */
46 46 }
47 47  
48   -void vga_update_display(void)
49   -{
50   - /* XXXXX */
51   -}
52   -
53   -void vga_invalidate_display(void)
54   -{
55   - /* XXXXX */
56   -}
57   -
58   -void vga_screen_dump(const char *filename)
59   -{
60   - /* XXXXX */
61   -}
62   -
63 48 static void shix_init(ram_addr_t ram_size, int vga_ram_size,
64 49 const char *boot_device,
65 50 const char *kernel_filename, const char *kernel_cmdline,
... ...
target-sh4/cpu.h
  View file @ef7ec1c
... ... @@ -165,6 +165,8 @@ static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
165 165 env->gbr = newtls;
166 166 }
167 167  
  168 +void cpu_load_tlb(CPUSH4State * env);
  169 +
168 170 #include "softfloat.h"
169 171  
170 172 #define CPUState CPUSH4State
... ...
target-sh4/exec.h
  View file @ef7ec1c
... ... @@ -53,10 +53,4 @@ static inline void env_to_regs(void)
53 53 /* XXXXX */
54 54 }
55 55  
56   -void cpu_load_tlb(CPUState * env);
57   -
58   -int find_itlb_entry(CPUState * env, target_ulong address,
59   - int use_asid, int update);
60   -int find_utlb_entry(CPUState * env, target_ulong address, int use_asid);
61   -
62 56 #endif /* _EXEC_SH4_H */
... ...
target-sh4/helper.c
  View file @ef7ec1c
... ... @@ -313,8 +313,8 @@ static void increment_urc(CPUState * env)
313 313 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
314 314 Update the itlb from utlb if update is not 0
315 315 */
316   -int find_itlb_entry(CPUState * env, target_ulong address,
317   - int use_asid, int update)
  316 +static int find_itlb_entry(CPUState * env, target_ulong address,
  317 + int use_asid, int update)
318 318 {
319 319 int e, n;
320 320  
... ... @@ -344,7 +344,7 @@ int find_itlb_entry(CPUState * env, target_ulong address,
344 344  
345 345 /* Find utlb entry
346 346 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
347   -int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
  347 +static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
348 348 {
349 349 /* per utlb access */
350 350 increment_urc(env);
... ... @@ -418,9 +418,9 @@ static int get_mmu_address(CPUState * env, target_ulong * physical,
418 418 return n;
419 419 }
420 420  
421   -int get_physical_address(CPUState * env, target_ulong * physical,
422   - int *prot, target_ulong address,
423   - int rw, int access_type)
  421 +static int get_physical_address(CPUState * env, target_ulong * physical,
  422 + int *prot, target_ulong address,
  423 + int rw, int access_type)
424 424 {
425 425 /* P1, P2 and P4 areas do not use translation */
426 426 if ((address >= 0x80000000 && address < 0xc0000000) ||
... ... @@ -525,7 +525,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
525 525 return physical;
526 526 }
527 527  
528   -void cpu_load_tlb(CPUState * env)
  528 +void cpu_load_tlb(CPUSH4State * env)
529 529 {
530 530 int n = cpu_mmucr_urc(env->mmucr);
531 531 tlb_t * entry = &env->utlb[n];
... ...