Commit 0637b04ff18065fa24765b22c44fa16dae62c114
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5439c95c
Compile script improved.
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virtual_lab/compileme.sh
| 1 | -arm-none-eabi-gcc -mcpu=arm926ej-s -nostdlib main.c -o main.elf | |
| 2 | -gdb-multiarch main.elf | |
| 1 | +arm-none-eabi-gcc -E -I include -D__ASSEMBLY__ cstartup.S > cstartup_pre.S | |
| 2 | +arm-none-eabi-gcc -g -mcpu=arm926ej-s -c cstartup_pre.S -o cstartup.o | |
| 3 | +arm-none-eabi-gcc -g -mcpu=arm926ej-s -I include lowlevel.c main.c cstartup.o -o main.elf -Ttext 0x20000000 -Tdata 0x300000 -T script.lds | |
| 4 | +# -Wl,--verbose | |
| 5 | + | |
| 6 | +#gdb-multiarch main.elf | ... | ... |
virtual_lab/cstartup.S
0 → 100644
| 1 | +/* ---------------------------------------------------------------------------- | |
| 2 | + * ATMEL Microcontroller Software Support - ROUSSET - | |
| 3 | + * ---------------------------------------------------------------------------- | |
| 4 | + * Copyright (c) 2006, Atmel Corporation | |
| 5 | + | |
| 6 | + * All rights reserved. | |
| 7 | + * | |
| 8 | + * Redistribution and use in source and binary forms, with or without | |
| 9 | + * modification, are permitted provided that the following conditions are met: | |
| 10 | + * | |
| 11 | + * - Redistributions of source code must retain the above copyright notice, | |
| 12 | + * this list of conditions and the disclaimer below. | |
| 13 | + * | |
| 14 | + * - Redistributions in binary form must reproduce the above copyright notice, | |
| 15 | + * this list of conditions and the disclaimer below in the documentation and/or | |
| 16 | + * other materials provided with the distribution. | |
| 17 | + * | |
| 18 | + * Atmel's name may not be used to endorse or promote products derived from | |
| 19 | + * this software without specific prior written permission. | |
| 20 | + * | |
| 21 | + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR | |
| 22 | + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
| 23 | + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE | |
| 24 | + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, | |
| 25 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 26 | + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, | |
| 27 | + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
| 28 | + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
| 29 | + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, | |
| 30 | + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | + * ---------------------------------------------------------------------------- | |
| 32 | + * File Name : cstartup.S | |
| 33 | + * Object : | |
| 34 | + * Creation : FDy Nov 10th 2006 | |
| 35 | + * Updates : ODi Nov 20th 2006 Cleanup | |
| 36 | + *----------------------------------------------------------------------------- | |
| 37 | + */ | |
| 38 | + | |
| 39 | +#include "project.h" | |
| 40 | + | |
| 41 | +#define TOP_OF_MEMORY (AT91C_IRAM + AT91C_IRAM_SIZE) | |
| 42 | +#define ABT_STACK_SIZE 8*3*4 | |
| 43 | +#define IRQ_STACK_SIZE 8*3*4 | |
| 44 | + | |
| 45 | +#define ARM_MODE_ABT 0x17 | |
| 46 | +#define ARM_MODE_FIQ 0x11 | |
| 47 | +#define ARM_MODE_IRQ 0x12 | |
| 48 | +#define ARM_MODE_SVC 0x13 | |
| 49 | + | |
| 50 | +#define I_BIT 0x80 | |
| 51 | +#define F_BIT 0x40 | |
| 52 | + | |
| 53 | + | |
| 54 | +/* Application startup entry point */ | |
| 55 | + .globl reset_handler | |
| 56 | + .align 4 | |
| 57 | + | |
| 58 | +.section .vectors | |
| 59 | +.arm | |
| 60 | + | |
| 61 | + | |
| 62 | +/* Exception vectors (should be a branch to be detected as a valid code by the rom */ | |
| 63 | +_exception_vectors: | |
| 64 | +reset_vector: | |
| 65 | + ldr pc, =reset_handler | |
| 66 | +undef_vector: | |
| 67 | + b undef_vector /* Undefined Instruction */ | |
| 68 | +swi_vector: | |
| 69 | + b swi_vector /* Software Interrupt */ | |
| 70 | +pabt_vector: | |
| 71 | + ldr pc, =pabt_handler /* Prefetch Abort */ | |
| 72 | +dabt_vector: | |
| 73 | + ldr pc, =dabt_handler /* Data Abort */ | |
| 74 | +rsvd_vector: | |
| 75 | + b rsvd_vector /* reserved */ | |
| 76 | +irq_vector: | |
| 77 | + b irq_handler /* IRQ : read the AIC */ | |
| 78 | +fiq_vector: | |
| 79 | +/*------------------------------------------------------------------------------ | |
| 80 | + *- Function : fiq_handler | |
| 81 | + *- Treatments : FIQ Interrupt Handler. | |
| 82 | + *- Called Functions : | |
| 83 | + *------------------------------------------------------------------------------*/ | |
| 84 | +fiq_handler: | |
| 85 | + b fiq_handler | |
| 86 | + | |
| 87 | +/*------------------------------------------------------------------------------ | |
| 88 | + *- Function : irq_handler | |
| 89 | + *- Treatments : IRQ Controller Interrupt Handler. | |
| 90 | + *- Called Functions : AIC_IVR[interrupt] | |
| 91 | + *------------------------------------------------------------------------------*/ | |
| 92 | +irq_handler: | |
| 93 | +/*- Manage Exception Entry */ | |
| 94 | +/*- Adjust and save LR_irq in IRQ stack */ | |
| 95 | + sub lr, lr, #4 | |
| 96 | + stmfd sp!, {lr} | |
| 97 | +/*- Save r0 and SPSR in IRQ stack */ | |
| 98 | + mrs r14, SPSR | |
| 99 | + stmfd sp!, {r0,r14} | |
| 100 | + | |
| 101 | +/*- Write in the IVR to support Protect Mode */ | |
| 102 | +/*- No effect in Normal Mode */ | |
| 103 | +/*- De-assert the NIRQ and clear the source in Protect Mode */ | |
| 104 | + ldr r14, =AT91C_BASE_AIC | |
| 105 | + ldr r0 , [r14, #AIC_IVR] | |
| 106 | + str r14, [r14, #AIC_IVR] | |
| 107 | + | |
| 108 | +/*- Enable Interrupt and Switch in Supervisor Mode */ | |
| 109 | + msr CPSR_c, #ARM_MODE_SVC | |
| 110 | + | |
| 111 | +/*- Save scratch/used registers and LR in User Stack */ | |
| 112 | + stmfd sp!, {r1-r3, r12, r14} | |
| 113 | + | |
| 114 | +/*- Branch to the routine pointed by the AIC_IVR */ | |
| 115 | + mov r14, pc | |
| 116 | + bx r0 | |
| 117 | + | |
| 118 | +/*- Restore scratch/used registers and LR from User Stack */ | |
| 119 | + ldmia sp!, {r1-r3, r12, r14} | |
| 120 | + | |
| 121 | +/*- Disable Interrupt and switch back in IRQ mode */ | |
| 122 | + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | |
| 123 | + | |
| 124 | +/*- Mark the End of Interrupt on the AIC */ | |
| 125 | + ldr r14, =AT91C_BASE_AIC | |
| 126 | + str r14, [r14, #AIC_EOICR] | |
| 127 | + | |
| 128 | +/*- Restore SPSR_irq and r0 from IRQ stack */ | |
| 129 | + ldmia sp!, {r0,r14} | |
| 130 | + msr SPSR_cxsf, r14 | |
| 131 | + | |
| 132 | +/*- Restore adjusted LR_irq from IRQ stack directly in the PC */ | |
| 133 | + ldmia sp!, {pc}^ | |
| 134 | + | |
| 135 | +/*------------------------------------------------------------------------------ | |
| 136 | + *- Function : reset_handler | |
| 137 | + *- Treatments : Reset Interrupt Handler. | |
| 138 | + *- Called Functions : lowlevel_init | |
| 139 | + * main | |
| 140 | + *------------------------------------------------------------------------------*/ | |
| 141 | +.section .text | |
| 142 | +reset_handler: | |
| 143 | + ldr pc, =_low_level_init | |
| 144 | + | |
| 145 | +/*------------------------------------------------------------------------------ | |
| 146 | + *- Low level Init is performed in a C function: lowlevel_init | |
| 147 | + *- Init Stack Pointer to a valid memory area before calling lowlevel_init | |
| 148 | + *------------------------------------------------------------------------------*/ | |
| 149 | +/*- Temporary stack in internal RAM for Low Level Init execution */ | |
| 150 | +_low_level_init: | |
| 151 | + ldr r2, =_lp_ll_init | |
| 152 | + ldmia r2, {r0, r1} | |
| 153 | + mov sp, r1 | |
| 154 | + mov lr, pc | |
| 155 | + bx r0 /* Branch on C function (interworking) */ | |
| 156 | + | |
| 157 | +/*------------------------------------------------------------------------------ | |
| 158 | + *- Setup the stack for each mode | |
| 159 | + *------------------------------------------------------------------------------*/ | |
| 160 | +_stack_init: | |
| 161 | + ldr r2, =_lp_stack_init | |
| 162 | + ldmia r2, {r0, r1, r2} | |
| 163 | + | |
| 164 | +/*- Set up Abort Mode and set ABT Mode Stack */ | |
| 165 | + msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT | |
| 166 | + mov sp, r0 | |
| 167 | + sub r0, r0, r1 | |
| 168 | + | |
| 169 | +/*- Set up Interrupt Mode and set IRQ Mode Stack */ | |
| 170 | + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT | |
| 171 | + mov sp, r0 | |
| 172 | + sub r0, r0, r2 | |
| 173 | + | |
| 174 | +/*- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack */ | |
| 175 | + msr CPSR_c, #ARM_MODE_SVC | F_BIT | |
| 176 | + mov sp, r0 | |
| 177 | + | |
| 178 | +/*------------------------------------------------------------------------------ | |
| 179 | + *- Segments initialization | |
| 180 | + *------------------------------------------------------------------------------*/ | |
| 181 | +/* Copy the data section in RAM at 0x0000 */ | |
| 182 | +_init_data: | |
| 183 | + ldr r2, =_lp_data | |
| 184 | + ldmia r2, {r1, r3, r4} | |
| 185 | +1: | |
| 186 | + cmp r3, r4 | |
| 187 | + ldrcc r2, [r1], #4 | |
| 188 | + strcc r2, [r3], #4 | |
| 189 | + bcc 1b | |
| 190 | + | |
| 191 | +/* Clear the bss segment */ | |
| 192 | +_init_bss: | |
| 193 | + ldr r2, =_lp_bss | |
| 194 | + ldmia r2, {r3, r4} | |
| 195 | + mov r2, #0 | |
| 196 | +1: | |
| 197 | + cmp r3, r4 | |
| 198 | + strcc r2, [r3], #4 | |
| 199 | + bcc 1b | |
| 200 | + | |
| 201 | +/*------------------------------------------------------------------------------ | |
| 202 | + *- Branch to the main | |
| 203 | + *------------------------------------------------------------------------------*/ | |
| 204 | +_branch_main: | |
| 205 | + ldr r0, =main | |
| 206 | + mov lr, pc | |
| 207 | + bx r0 | |
| 208 | + | |
| 209 | +/*------------------------------------------------------------------------------ | |
| 210 | + *- Litteral pools | |
| 211 | + *------------------------------------------------------------------------------*/ | |
| 212 | +_lp_ll_init: | |
| 213 | + .word lowlevel_init | |
| 214 | + .word TOP_OF_MEMORY /* Default SVC stack after power up */ | |
| 215 | + | |
| 216 | +_lp_stack_init: | |
| 217 | + .word TOP_OF_MEMORY /* Top of the stack */ | |
| 218 | + .word ABT_STACK_SIZE /* ABT stack size */ | |
| 219 | + .word IRQ_STACK_SIZE /* IRQ stack size */ | |
| 220 | + | |
| 221 | +_lp_bss: | |
| 222 | + .word _sbss | |
| 223 | + .word _ebss | |
| 224 | + | |
| 225 | +_lp_data: | |
| 226 | + .word _etext | |
| 227 | + .word _sdata | |
| 228 | + .word _edata | |
| 229 | + | ... | ... |
virtual_lab/gdbinit
virtual_lab/include/AT91SAM9263-EK.h
0 → 100644
| 1 | +/* ---------------------------------------------------------------------------- | |
| 2 | + * ATMEL Microcontroller Software Support - ROUSSET - | |
| 3 | + * ---------------------------------------------------------------------------- | |
| 4 | + * Copyright (c) 2006, Atmel Corporation | |
| 5 | + * | |
| 6 | + * All rights reserved. | |
| 7 | + * | |
| 8 | + * Redistribution and use in source and binary forms, with or without | |
| 9 | + * modification, are permitted provided that the following conditions are met: | |
| 10 | + * | |
| 11 | + * - Redistributions of source code must retain the above copyright notice, | |
| 12 | + * this list of conditions and the disclaiimer below. | |
| 13 | + * | |
| 14 | + * - Redistributions in binary form must reproduce the above copyright notice, | |
| 15 | + * this list of conditions and the disclaimer below in the documentation and/or | |
| 16 | + * other materials provided with the distribution. | |
| 17 | + * | |
| 18 | + * Atmel's name may not be used to endorse or promote products derived from | |
| 19 | + * this software without specific prior written permission. | |
| 20 | + * | |
| 21 | + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR | |
| 22 | + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
| 23 | + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE | |
| 24 | + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, | |
| 25 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 26 | + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, | |
| 27 | + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
| 28 | + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
| 29 | + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, | |
| 30 | + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | + * ---------------------------------------------------------------------------- | |
| 32 | + */ | |
| 33 | +/*----------------------------------------------------------------------------- | |
| 34 | + * File Name : AT91SAM9263-EK.h | |
| 35 | + * Object : AT91SAM9263-EK Evaluation Board Features Definition File | |
| 36 | + * Creation : FDy 10-Nov-2006 | |
| 37 | + *----------------------------------------------------------------------------- | |
| 38 | + */ | |
| 39 | +#ifndef AT91SAM9263_EK_H | |
| 40 | +#define AT91SAM9263_EK_H | |
| 41 | + | |
| 42 | + | |
| 43 | +/*-----------------*/ | |
| 44 | +/* LEDs Definition */ | |
| 45 | +/*-----------------*/ | |
| 46 | +#define AT91B_LED1 AT91C_PIO_PB8 /* DS1 */ | |
| 47 | +#define AT91B_LED2 AT91C_PIO_PC29 /* DS2 */ | |
| 48 | +#define AT91B_NB_LEB 2 | |
| 49 | +#define AT91D_BASE_PIO_LED1 (AT91C_BASE_PIOB) | |
| 50 | +#define AT91D_BASE_PIO_LED2 (AT91C_BASE_PIOC) | |
| 51 | +#define AT91D_ID_PIO_LED1 (AT91C_ID_PIOB) | |
| 52 | +#define AT91D_ID_PIO_LED2 (AT91C_ID_PIOC) | |
| 53 | + | |
| 54 | +/*-------------------------------*/ | |
| 55 | +/* Push Button Definition */ | |
| 56 | +/*-------------------------------*/ | |
| 57 | +#define AT91B_BP1 AT91C_PIO_PC5 // Left click | |
| 58 | +#define AT91B_BP2 AT91C_PIO_PC4 // Right clic | |
| 59 | +#define AT91D_BASE_PIO_BP AT91C_BASE_PIOC | |
| 60 | +#define AT91D_ID_PIO_BP AT91C_ID_PIOCDE | |
| 61 | + | |
| 62 | +/*-------------------------------*/ | |
| 63 | +/* Push Button Definition */ | |
| 64 | +/*-------------------------------*/ | |
| 65 | +#define AT91D_ID_TC AT91C_ID_TC012 | |
| 66 | + | |
| 67 | + | |
| 68 | + | |
| 69 | +#define AT91B_DBGU_BAUD_RATE 115200 | |
| 70 | + | |
| 71 | +/*---------------*/ | |
| 72 | +/* SPI interface */ | |
| 73 | +/*---------------*/ | |
| 74 | +/* MN5 SERIAL DATAFLASH AT45DB642E | |
| 75 | + SPI Name : Port | |
| 76 | + SPI SCK PA14 / SPI_SPCK | |
| 77 | + CS PA11 / SPI_NPCS0 | |
| 78 | + SO PA12 /SPI_MISO | |
| 79 | + SI PA13 /SPI_MOSI | |
| 80 | +*/ | |
| 81 | +#define DATAFLASH_PERI Peripheral_A | |
| 82 | +#define DATAFLASH_SI AT91C_PA13_MOSI | |
| 83 | +#define DATAFLASH_SO AT91C_PA12_MISO | |
| 84 | +#define DATAFLASH_CS AT91C_PA11_NPCS0 | |
| 85 | +#define DATAFLASH_SCK AT91C_PA14_SPCK | |
| 86 | + | |
| 87 | +/*---------------*/ | |
| 88 | +/* Clocks */ | |
| 89 | +/*--------------*/ | |
| 90 | +#define AT91B_MAIN_OSC 16367660 // Main Oscillator MAINCK | |
| 91 | +#define AT91B_MCK ((16367660*110/9)/2) // Output PLLA Clock / 2 (~100 MHz) | |
| 92 | +#define AT91B_MASTER_CLOCK AT91B_MCK | |
| 93 | +#define AT91B_SLOW_CLOCK 32768 | |
| 94 | + | |
| 95 | + | |
| 96 | +#endif /* AT91SAM9263-EK_H */ | ... | ... |