gwj / at91sam9263 · Commits

Commit 0637b04ff18065fa24765b22c44fa16dae62c114

Authored by Grzegorz Jabłoński
1 parent 5439c95c

Compile script improved.

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Showing 9 changed files with 6566 additions and 6 deletions
virtual_lab/compileme.sh
  View file @0637b04
1   -arm-none-eabi-gcc -mcpu=arm926ej-s -nostdlib main.c -o main.elf
2   -gdb-multiarch main.elf
  1 +arm-none-eabi-gcc -E -I include -D__ASSEMBLY__ cstartup.S > cstartup_pre.S
  2 +arm-none-eabi-gcc -g -mcpu=arm926ej-s -c cstartup_pre.S -o cstartup.o
  3 +arm-none-eabi-gcc -g -mcpu=arm926ej-s -I include lowlevel.c main.c cstartup.o -o main.elf -Ttext 0x20000000 -Tdata 0x300000 -T script.lds
  4 +# -Wl,--verbose
  5 +
  6 +#gdb-multiarch main.elf
... ...
virtual_lab/cstartup.S 0 → 100644
  View file @0637b04
  1 +/* ----------------------------------------------------------------------------
  2 + * ATMEL Microcontroller Software Support - ROUSSET -
  3 + * ----------------------------------------------------------------------------
  4 + * Copyright (c) 2006, Atmel Corporation
  5 +
  6 + * All rights reserved.
  7 + *
  8 + * Redistribution and use in source and binary forms, with or without
  9 + * modification, are permitted provided that the following conditions are met:
  10 + *
  11 + * - Redistributions of source code must retain the above copyright notice,
  12 + * this list of conditions and the disclaimer below.
  13 + *
  14 + * - Redistributions in binary form must reproduce the above copyright notice,
  15 + * this list of conditions and the disclaimer below in the documentation and/or
  16 + * other materials provided with the distribution.
  17 + *
  18 + * Atmel's name may not be used to endorse or promote products derived from
  19 + * this software without specific prior written permission.
  20 + *
  21 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  22 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  24 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  25 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  27 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  28 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  29 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31 + * ----------------------------------------------------------------------------
  32 + * File Name : cstartup.S
  33 + * Object :
  34 + * Creation : FDy Nov 10th 2006
  35 + * Updates : ODi Nov 20th 2006 Cleanup
  36 + *-----------------------------------------------------------------------------
  37 + */
  38 +
  39 +#include "project.h"
  40 +
  41 +#define TOP_OF_MEMORY (AT91C_IRAM + AT91C_IRAM_SIZE)
  42 +#define ABT_STACK_SIZE 8*3*4
  43 +#define IRQ_STACK_SIZE 8*3*4
  44 +
  45 +#define ARM_MODE_ABT 0x17
  46 +#define ARM_MODE_FIQ 0x11
  47 +#define ARM_MODE_IRQ 0x12
  48 +#define ARM_MODE_SVC 0x13
  49 +
  50 +#define I_BIT 0x80
  51 +#define F_BIT 0x40
  52 +
  53 +
  54 +/* Application startup entry point */
  55 + .globl reset_handler
  56 + .align 4
  57 +
  58 +.section .vectors
  59 +.arm
  60 +
  61 +
  62 +/* Exception vectors (should be a branch to be detected as a valid code by the rom */
  63 +_exception_vectors:
  64 +reset_vector:
  65 + ldr pc, =reset_handler
  66 +undef_vector:
  67 + b undef_vector /* Undefined Instruction */
  68 +swi_vector:
  69 + b swi_vector /* Software Interrupt */
  70 +pabt_vector:
  71 + ldr pc, =pabt_handler /* Prefetch Abort */
  72 +dabt_vector:
  73 + ldr pc, =dabt_handler /* Data Abort */
  74 +rsvd_vector:
  75 + b rsvd_vector /* reserved */
  76 +irq_vector:
  77 + b irq_handler /* IRQ : read the AIC */
  78 +fiq_vector:
  79 +/*------------------------------------------------------------------------------
  80 + *- Function : fiq_handler
  81 + *- Treatments : FIQ Interrupt Handler.
  82 + *- Called Functions :
  83 + *------------------------------------------------------------------------------*/
  84 +fiq_handler:
  85 + b fiq_handler
  86 +
  87 +/*------------------------------------------------------------------------------
  88 + *- Function : irq_handler
  89 + *- Treatments : IRQ Controller Interrupt Handler.
  90 + *- Called Functions : AIC_IVR[interrupt]
  91 + *------------------------------------------------------------------------------*/
  92 +irq_handler:
  93 +/*- Manage Exception Entry */
  94 +/*- Adjust and save LR_irq in IRQ stack */
  95 + sub lr, lr, #4
  96 + stmfd sp!, {lr}
  97 +/*- Save r0 and SPSR in IRQ stack */
  98 + mrs r14, SPSR
  99 + stmfd sp!, {r0,r14}
  100 +
  101 +/*- Write in the IVR to support Protect Mode */
  102 +/*- No effect in Normal Mode */
  103 +/*- De-assert the NIRQ and clear the source in Protect Mode */
  104 + ldr r14, =AT91C_BASE_AIC
  105 + ldr r0 , [r14, #AIC_IVR]
  106 + str r14, [r14, #AIC_IVR]
  107 +
  108 +/*- Enable Interrupt and Switch in Supervisor Mode */
  109 + msr CPSR_c, #ARM_MODE_SVC
  110 +
  111 +/*- Save scratch/used registers and LR in User Stack */
  112 + stmfd sp!, {r1-r3, r12, r14}
  113 +
  114 +/*- Branch to the routine pointed by the AIC_IVR */
  115 + mov r14, pc
  116 + bx r0
  117 +
  118 +/*- Restore scratch/used registers and LR from User Stack */
  119 + ldmia sp!, {r1-r3, r12, r14}
  120 +
  121 +/*- Disable Interrupt and switch back in IRQ mode */
  122 + msr CPSR_c, #ARM_MODE_IRQ | I_BIT
  123 +
  124 +/*- Mark the End of Interrupt on the AIC */
  125 + ldr r14, =AT91C_BASE_AIC
  126 + str r14, [r14, #AIC_EOICR]
  127 +
  128 +/*- Restore SPSR_irq and r0 from IRQ stack */
  129 + ldmia sp!, {r0,r14}
  130 + msr SPSR_cxsf, r14
  131 +
  132 +/*- Restore adjusted LR_irq from IRQ stack directly in the PC */
  133 + ldmia sp!, {pc}^
  134 +
  135 +/*------------------------------------------------------------------------------
  136 + *- Function : reset_handler
  137 + *- Treatments : Reset Interrupt Handler.
  138 + *- Called Functions : lowlevel_init
  139 + * main
  140 + *------------------------------------------------------------------------------*/
  141 +.section .text
  142 +reset_handler:
  143 + ldr pc, =_low_level_init
  144 +
  145 +/*------------------------------------------------------------------------------
  146 + *- Low level Init is performed in a C function: lowlevel_init
  147 + *- Init Stack Pointer to a valid memory area before calling lowlevel_init
  148 + *------------------------------------------------------------------------------*/
  149 +/*- Temporary stack in internal RAM for Low Level Init execution */
  150 +_low_level_init:
  151 + ldr r2, =_lp_ll_init
  152 + ldmia r2, {r0, r1}
  153 + mov sp, r1
  154 + mov lr, pc
  155 + bx r0 /* Branch on C function (interworking) */
  156 +
  157 +/*------------------------------------------------------------------------------
  158 + *- Setup the stack for each mode
  159 + *------------------------------------------------------------------------------*/
  160 +_stack_init:
  161 + ldr r2, =_lp_stack_init
  162 + ldmia r2, {r0, r1, r2}
  163 +
  164 +/*- Set up Abort Mode and set ABT Mode Stack */
  165 + msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT
  166 + mov sp, r0
  167 + sub r0, r0, r1
  168 +
  169 +/*- Set up Interrupt Mode and set IRQ Mode Stack */
  170 + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
  171 + mov sp, r0
  172 + sub r0, r0, r2
  173 +
  174 +/*- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack */
  175 + msr CPSR_c, #ARM_MODE_SVC | F_BIT
  176 + mov sp, r0
  177 +
  178 +/*------------------------------------------------------------------------------
  179 + *- Segments initialization
  180 + *------------------------------------------------------------------------------*/
  181 +/* Copy the data section in RAM at 0x0000 */
  182 +_init_data:
  183 + ldr r2, =_lp_data
  184 + ldmia r2, {r1, r3, r4}
  185 +1:
  186 + cmp r3, r4
  187 + ldrcc r2, [r1], #4
  188 + strcc r2, [r3], #4
  189 + bcc 1b
  190 +
  191 +/* Clear the bss segment */
  192 +_init_bss:
  193 + ldr r2, =_lp_bss
  194 + ldmia r2, {r3, r4}
  195 + mov r2, #0
  196 +1:
  197 + cmp r3, r4
  198 + strcc r2, [r3], #4
  199 + bcc 1b
  200 +
  201 +/*------------------------------------------------------------------------------
  202 + *- Branch to the main
  203 + *------------------------------------------------------------------------------*/
  204 +_branch_main:
  205 + ldr r0, =main
  206 + mov lr, pc
  207 + bx r0
  208 +
  209 +/*------------------------------------------------------------------------------
  210 + *- Litteral pools
  211 + *------------------------------------------------------------------------------*/
  212 +_lp_ll_init:
  213 + .word lowlevel_init
  214 + .word TOP_OF_MEMORY /* Default SVC stack after power up */
  215 +
  216 +_lp_stack_init:
  217 + .word TOP_OF_MEMORY /* Top of the stack */
  218 + .word ABT_STACK_SIZE /* ABT stack size */
  219 + .word IRQ_STACK_SIZE /* IRQ stack size */
  220 +
  221 +_lp_bss:
  222 + .word _sbss
  223 + .word _ebss
  224 +
  225 +_lp_data:
  226 + .word _etext
  227 + .word _sdata
  228 + .word _edata
  229 +
... ...
virtual_lab/gdbinit
  View file @0637b04
... ... @@ -3,7 +3,7 @@ ni
3 3 disass $pc,+16
4 4 end
5 5  
6   -define ssii
  6 +define ssi
7 7 si
8 8 disass $pc,+16
9 9 end
... ...
virtual_lab/include/AT91SAM9263-EK.h 0 → 100644
  View file @0637b04
  1 +/* ----------------------------------------------------------------------------
  2 + * ATMEL Microcontroller Software Support - ROUSSET -
  3 + * ----------------------------------------------------------------------------
  4 + * Copyright (c) 2006, Atmel Corporation
  5 + *
  6 + * All rights reserved.
  7 + *
  8 + * Redistribution and use in source and binary forms, with or without
  9 + * modification, are permitted provided that the following conditions are met:
  10 + *
  11 + * - Redistributions of source code must retain the above copyright notice,
  12 + * this list of conditions and the disclaiimer below.
  13 + *
  14 + * - Redistributions in binary form must reproduce the above copyright notice,
  15 + * this list of conditions and the disclaimer below in the documentation and/or
  16 + * other materials provided with the distribution.
  17 + *
  18 + * Atmel's name may not be used to endorse or promote products derived from
  19 + * this software without specific prior written permission.
  20 + *
  21 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  22 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  24 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  25 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  27 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  28 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  29 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31 + * ----------------------------------------------------------------------------
  32 + */
  33 +/*-----------------------------------------------------------------------------
  34 + * File Name : AT91SAM9263-EK.h
  35 + * Object : AT91SAM9263-EK Evaluation Board Features Definition File
  36 + * Creation : FDy 10-Nov-2006
  37 + *-----------------------------------------------------------------------------
  38 + */
  39 +#ifndef AT91SAM9263_EK_H
  40 +#define AT91SAM9263_EK_H
  41 +
  42 +
  43 +/*-----------------*/
  44 +/* LEDs Definition */
  45 +/*-----------------*/
  46 +#define AT91B_LED1 AT91C_PIO_PB8 /* DS1 */
  47 +#define AT91B_LED2 AT91C_PIO_PC29 /* DS2 */
  48 +#define AT91B_NB_LEB 2
  49 +#define AT91D_BASE_PIO_LED1 (AT91C_BASE_PIOB)
  50 +#define AT91D_BASE_PIO_LED2 (AT91C_BASE_PIOC)
  51 +#define AT91D_ID_PIO_LED1 (AT91C_ID_PIOB)
  52 +#define AT91D_ID_PIO_LED2 (AT91C_ID_PIOC)
  53 +
  54 +/*-------------------------------*/
  55 +/* Push Button Definition */
  56 +/*-------------------------------*/
  57 +#define AT91B_BP1 AT91C_PIO_PC5 // Left click
  58 +#define AT91B_BP2 AT91C_PIO_PC4 // Right clic
  59 +#define AT91D_BASE_PIO_BP AT91C_BASE_PIOC
  60 +#define AT91D_ID_PIO_BP AT91C_ID_PIOCDE
  61 +
  62 +/*-------------------------------*/
  63 +/* Push Button Definition */
  64 +/*-------------------------------*/
  65 +#define AT91D_ID_TC AT91C_ID_TC012
  66 +
  67 +
  68 +
  69 +#define AT91B_DBGU_BAUD_RATE 115200
  70 +
  71 +/*---------------*/
  72 +/* SPI interface */
  73 +/*---------------*/
  74 +/* MN5 SERIAL DATAFLASH AT45DB642E
  75 + SPI Name : Port
  76 + SPI SCK PA14 / SPI_SPCK
  77 + CS PA11 / SPI_NPCS0
  78 + SO PA12 /SPI_MISO
  79 + SI PA13 /SPI_MOSI
  80 +*/
  81 +#define DATAFLASH_PERI Peripheral_A
  82 +#define DATAFLASH_SI AT91C_PA13_MOSI
  83 +#define DATAFLASH_SO AT91C_PA12_MISO
  84 +#define DATAFLASH_CS AT91C_PA11_NPCS0
  85 +#define DATAFLASH_SCK AT91C_PA14_SPCK
  86 +
  87 +/*---------------*/
  88 +/* Clocks */
  89 +/*--------------*/
  90 +#define AT91B_MAIN_OSC 16367660 // Main Oscillator MAINCK
  91 +#define AT91B_MCK ((16367660*110/9)/2) // Output PLLA Clock / 2 (~100 MHz)
  92 +#define AT91B_MASTER_CLOCK AT91B_MCK
  93 +#define AT91B_SLOW_CLOCK 32768
  94 +
  95 +
  96 +#endif /* AT91SAM9263-EK_H */
... ...
virtual_lab/include/AT91SAM9263.h 0 → 100644
  View file @0637b04
Changes suppressed. Click to show.
  1 +// ----------------------------------------------------------------------------
  2 +// ATMEL Microcontroller Software Support - ROUSSET -
  3 +// ----------------------------------------------------------------------------
  4 +// Copyright (c) 2006, Atmel Corporation
  5 +//
  6 +// All rights reserved.
  7 +//
  8 +// Redistribution and use in source and binary forms, with or without
  9 +// modification, are permitted provided that the following conditions are met:
  10 +//
  11 +// - Redistributions of source code must retain the above copyright notice,
  12 +// this list of conditions and the disclaimer below.
  13 +//
  14 +// - Redistributions in binary form must reproduce the above copyright notice,
  15 +// this list of conditions and the disclaimer below in the documentation and/or
  16 +// other materials provided with the distribution.
  17 +//
  18 +// Atmel's name may not be used to endorse or promote products derived from
  19 +// this software without specific prior written permission.
  20 +//
  21 +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  22 +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23 +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  24 +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  25 +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26 +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  27 +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  28 +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  29 +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30 +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31 +// ----------------------------------------------------------------------------
  32 +// File Name : AT91SAM9263.h
  33 +// Object : AT91SAM9263 definitions
  34 +// Generated : AT91 SW Application Group 12/07/2006 (13:32:18)
  35 +//
  36 +// CVS Reference : /AT91SAM9263.pl/1.2/Fri Nov 10 12:56:00 2006//
  37 +// CVS Reference : /SYS_SAM9262.pl/1.4/Tue Jan 18 17:06:33 2005//
  38 +// CVS Reference : /HMATRIX1_SAM9262.pl/1.10/Thu Oct 13 12:44:26 2005//
  39 +// CVS Reference : /CCR_SAM9262.pl/1.7/Fri Nov 10 13:23:00 2006//
  40 +// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005//
  41 +// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//
  42 +// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
  43 +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
  44 +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
  45 +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
  46 +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
  47 +// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//
  48 +// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004//
  49 +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
  50 +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
  51 +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
  52 +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
  53 +// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005//
  54 +// CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006//
  55 +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
  56 +// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005//
  57 +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
  58 +// CVS Reference : /AC97C_XXXX.pl/1.3/Tue Feb 22 17:08:27 2005//
  59 +// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
  60 +// CVS Reference : /PWM_6044D.pl/1.2/Tue May 10 12:39:09 2005//
  61 +// CVS Reference : /LCDC_6063A.pl/1.3/Fri Dec 9 10:59:26 2005//
  62 +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
  63 +// CVS Reference : /DMA_XXXX.pl/1.6/Tue Jan 11 09:40:44 2005//
  64 +// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//
  65 +// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
  66 +// CVS Reference : /TBOX_XXXX.pl/1.15/Thu Jun 9 07:05:57 2005//
  67 +// CVS Reference : /EBI_nadia2.pl/1.1/Wed Dec 29 11:28:03 2004//
  68 +// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005//
  69 +// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005//
  70 +// ----------------------------------------------------------------------------
  71 +
  72 +#ifndef AT91SAM9263_H
  73 +#define AT91SAM9263_H
  74 +
  75 +#ifndef __ASSEMBLY__
  76 +typedef volatile unsigned int AT91_REG;// Hardware register definition
  77 +#define AT91_CAST(a) (a)
  78 +#else
  79 +#define AT91_CAST(a)
  80 +#endif
  81 +
  82 +// *****************************************************************************
  83 +// SOFTWARE API DEFINITION FOR System Peripherals
  84 +// *****************************************************************************
  85 +#ifndef __ASSEMBLY__
  86 +typedef struct _AT91S_SYS {
  87 + AT91_REG SYS_ECC0; // ECC 0
  88 + AT91_REG Reserved0[127]; //
  89 + AT91_REG SYS_SDRAMC0_MR; // SDRAM Controller Mode Register
  90 + AT91_REG SYS_SDRAMC0_TR; // SDRAM Controller Refresh Timer Register
  91 + AT91_REG SYS_SDRAMC0_CR; // SDRAM Controller Configuration Register
  92 + AT91_REG SYS_SDRAMC0_HSR; // SDRAM Controller High Speed Register
  93 + AT91_REG SYS_SDRAMC0_LPR; // SDRAM Controller Low Power Register
  94 + AT91_REG SYS_SDRAMC0_IER; // SDRAM Controller Interrupt Enable Register
  95 + AT91_REG SYS_SDRAMC0_IDR; // SDRAM Controller Interrupt Disable Register
  96 + AT91_REG SYS_SDRAMC0_IMR; // SDRAM Controller Interrupt Mask Register
  97 + AT91_REG SYS_SDRAMC0_ISR; // SDRAM Controller Interrupt Mask Register
  98 + AT91_REG SYS_SDRAMC0_MDR; // SDRAM Memory Device Register
  99 + AT91_REG Reserved1[118]; //
  100 + AT91_REG SYS_SMC0_SETUP0; // Setup Register for CS 0
  101 + AT91_REG SYS_SMC0_PULSE0; // Pulse Register for CS 0
  102 + AT91_REG SYS_SMC0_CYCLE0; // Cycle Register for CS 0
  103 + AT91_REG SYS_SMC0_CTRL0; // Control Register for CS 0
  104 + AT91_REG SYS_SMC0_SETUP1; // Setup Register for CS 1
  105 + AT91_REG SYS_SMC0_PULSE1; // Pulse Register for CS 1
  106 + AT91_REG SYS_SMC0_CYCLE1; // Cycle Register for CS 1
  107 + AT91_REG SYS_SMC0_CTRL1; // Control Register for CS 1
  108 + AT91_REG SYS_SMC0_SETUP2; // Setup Register for CS 2
  109 + AT91_REG SYS_SMC0_PULSE2; // Pulse Register for CS 2
  110 + AT91_REG SYS_SMC0_CYCLE2; // Cycle Register for CS 2
  111 + AT91_REG SYS_SMC0_CTRL2; // Control Register for CS 2
  112 + AT91_REG SYS_SMC0_SETUP3; // Setup Register for CS 3
  113 + AT91_REG SYS_SMC0_PULSE3; // Pulse Register for CS 3
  114 + AT91_REG SYS_SMC0_CYCLE3; // Cycle Register for CS 3
  115 + AT91_REG SYS_SMC0_CTRL3; // Control Register for CS 3
  116 + AT91_REG SYS_SMC0_SETUP4; // Setup Register for CS 4
  117 + AT91_REG SYS_SMC0_PULSE4; // Pulse Register for CS 4
  118 + AT91_REG SYS_SMC0_CYCLE4; // Cycle Register for CS 4
  119 + AT91_REG SYS_SMC0_CTRL4; // Control Register for CS 4
  120 + AT91_REG SYS_SMC0_SETUP5; // Setup Register for CS 5
  121 + AT91_REG SYS_SMC0_PULSE5; // Pulse Register for CS 5
  122 + AT91_REG SYS_SMC0_CYCLE5; // Cycle Register for CS 5
  123 + AT91_REG SYS_SMC0_CTRL5; // Control Register for CS 5
  124 + AT91_REG SYS_SMC0_SETUP6; // Setup Register for CS 6
  125 + AT91_REG SYS_SMC0_PULSE6; // Pulse Register for CS 6
  126 + AT91_REG SYS_SMC0_CYCLE6; // Cycle Register for CS 6
  127 + AT91_REG SYS_SMC0_CTRL6; // Control Register for CS 6
  128 + AT91_REG SYS_SMC0_SETUP7; // Setup Register for CS 7
  129 + AT91_REG SYS_SMC0_PULSE7; // Pulse Register for CS 7
  130 + AT91_REG SYS_SMC0_CYCLE7; // Cycle Register for CS 7
  131 + AT91_REG SYS_SMC0_CTRL7; // Control Register for CS 7
  132 + AT91_REG Reserved2[96]; //
  133 + AT91_REG SYS_ECC1; // ECC 0
  134 + AT91_REG Reserved3[127]; //
  135 + AT91_REG SYS_SDRAMC1_MR; // SDRAM Controller Mode Register
  136 + AT91_REG SYS_SDRAMC1_TR; // SDRAM Controller Refresh Timer Register
  137 + AT91_REG SYS_SDRAMC1_CR; // SDRAM Controller Configuration Register
  138 + AT91_REG SYS_SDRAMC1_HSR; // SDRAM Controller High Speed Register
  139 + AT91_REG SYS_SDRAMC1_LPR; // SDRAM Controller Low Power Register
  140 + AT91_REG SYS_SDRAMC1_IER; // SDRAM Controller Interrupt Enable Register
  141 + AT91_REG SYS_SDRAMC1_IDR; // SDRAM Controller Interrupt Disable Register
  142 + AT91_REG SYS_SDRAMC1_IMR; // SDRAM Controller Interrupt Mask Register
  143 + AT91_REG SYS_SDRAMC1_ISR; // SDRAM Controller Interrupt Mask Register
  144 + AT91_REG SYS_SDRAMC1_MDR; // SDRAM Memory Device Register
  145 + AT91_REG Reserved4[118]; //
  146 + AT91_REG SYS_SMC1_SETUP0; // Setup Register for CS 0
  147 + AT91_REG SYS_SMC1_PULSE0; // Pulse Register for CS 0
  148 + AT91_REG SYS_SMC1_CYCLE0; // Cycle Register for CS 0
  149 + AT91_REG SYS_SMC1_CTRL0; // Control Register for CS 0
  150 + AT91_REG SYS_SMC1_SETUP1; // Setup Register for CS 1
  151 + AT91_REG SYS_SMC1_PULSE1; // Pulse Register for CS 1
  152 + AT91_REG SYS_SMC1_CYCLE1; // Cycle Register for CS 1
  153 + AT91_REG SYS_SMC1_CTRL1; // Control Register for CS 1
  154 + AT91_REG SYS_SMC1_SETUP2; // Setup Register for CS 2
  155 + AT91_REG SYS_SMC1_PULSE2; // Pulse Register for CS 2
  156 + AT91_REG SYS_SMC1_CYCLE2; // Cycle Register for CS 2
  157 + AT91_REG SYS_SMC1_CTRL2; // Control Register for CS 2
  158 + AT91_REG SYS_SMC1_SETUP3; // Setup Register for CS 3
  159 + AT91_REG SYS_SMC1_PULSE3; // Pulse Register for CS 3
  160 + AT91_REG SYS_SMC1_CYCLE3; // Cycle Register for CS 3
  161 + AT91_REG SYS_SMC1_CTRL3; // Control Register for CS 3
  162 + AT91_REG SYS_SMC1_SETUP4; // Setup Register for CS 4
  163 + AT91_REG SYS_SMC1_PULSE4; // Pulse Register for CS 4
  164 + AT91_REG SYS_SMC1_CYCLE4; // Cycle Register for CS 4
  165 + AT91_REG SYS_SMC1_CTRL4; // Control Register for CS 4
  166 + AT91_REG SYS_SMC1_SETUP5; // Setup Register for CS 5
  167 + AT91_REG SYS_SMC1_PULSE5; // Pulse Register for CS 5
  168 + AT91_REG SYS_SMC1_CYCLE5; // Cycle Register for CS 5
  169 + AT91_REG SYS_SMC1_CTRL5; // Control Register for CS 5
  170 + AT91_REG SYS_SMC1_SETUP6; // Setup Register for CS 6
  171 + AT91_REG SYS_SMC1_PULSE6; // Pulse Register for CS 6
  172 + AT91_REG SYS_SMC1_CYCLE6; // Cycle Register for CS 6
  173 + AT91_REG SYS_SMC1_CTRL6; // Control Register for CS 6
  174 + AT91_REG SYS_SMC1_SETUP7; // Setup Register for CS 7
  175 + AT91_REG SYS_SMC1_PULSE7; // Pulse Register for CS 7
  176 + AT91_REG SYS_SMC1_CYCLE7; // Cycle Register for CS 7
  177 + AT91_REG SYS_SMC1_CTRL7; // Control Register for CS 7
  178 + AT91_REG Reserved5[96]; //
  179 + AT91_REG SYS_MATRIX_MCFG0; // Master Configuration Register 0
  180 + AT91_REG SYS_MATRIX_MCFG1; // Master Configuration Register 1
  181 + AT91_REG SYS_MATRIX_MCFG2; // Master Configuration Register 2
  182 + AT91_REG SYS_MATRIX_MCFG3; // Master Configuration Register 3
  183 + AT91_REG SYS_MATRIX_MCFG4; // Master Configuration Register 4
  184 + AT91_REG SYS_MATRIX_MCFG5; // Master Configuration Register 5
  185 + AT91_REG SYS_MATRIX_MCFG6; // Master Configuration Register 6
  186 + AT91_REG SYS_MATRIX_MCFG7; // Master Configuration Register 7
  187 + AT91_REG SYS_MATRIX_MCFG8; // Master Configuration Register 8
  188 + AT91_REG Reserved6[7]; //
  189 + AT91_REG SYS_MATRIX_SCFG0; // Slave Configuration Register 0
  190 + AT91_REG SYS_MATRIX_SCFG1; // Slave Configuration Register 1
  191 + AT91_REG SYS_MATRIX_SCFG2; // Slave Configuration Register 2
  192 + AT91_REG SYS_MATRIX_SCFG3; // Slave Configuration Register 3
  193 + AT91_REG SYS_MATRIX_SCFG4; // Slave Configuration Register 4
  194 + AT91_REG SYS_MATRIX_SCFG5; // Slave Configuration Register 5
  195 + AT91_REG SYS_MATRIX_SCFG6; // Slave Configuration Register 6
  196 + AT91_REG SYS_MATRIX_SCFG7; // Slave Configuration Register 7
  197 + AT91_REG Reserved7[8]; //
  198 + AT91_REG SYS_MATRIX_PRAS0; // PRAS0
  199 + AT91_REG SYS_MATRIX_PRBS0; // PRBS0
  200 + AT91_REG SYS_MATRIX_PRAS1; // PRAS1
  201 + AT91_REG SYS_MATRIX_PRBS1; // PRBS1
  202 + AT91_REG SYS_MATRIX_PRAS2; // PRAS2
  203 + AT91_REG SYS_MATRIX_PRBS2; // PRBS2
  204 + AT91_REG SYS_MATRIX_PRAS3; // PRAS3
  205 + AT91_REG SYS_MATRIX_PRBS3; // PRBS3
  206 + AT91_REG SYS_MATRIX_PRAS4; // PRAS4
  207 + AT91_REG SYS_MATRIX_PRBS4; // PRBS4
  208 + AT91_REG SYS_MATRIX_PRAS5; // PRAS5
  209 + AT91_REG SYS_MATRIX_PRBS5; // PRBS5
  210 + AT91_REG SYS_MATRIX_PRAS6; // PRAS6
  211 + AT91_REG SYS_MATRIX_PRBS6; // PRBS6
  212 + AT91_REG SYS_MATRIX_PRAS7; // PRAS7
  213 + AT91_REG SYS_MATRIX_PRBS7; // PRBS7
  214 + AT91_REG Reserved8[16]; //
  215 + AT91_REG SYS_MATRIX_MRCR; // Master Remp Control Register
  216 + AT91_REG Reserved9[63]; //
  217 + AT91_REG SYS_DBGU_CR; // Control Register
  218 + AT91_REG SYS_DBGU_MR; // Mode Register
  219 + AT91_REG SYS_DBGU_IER; // Interrupt Enable Register
  220 + AT91_REG SYS_DBGU_IDR; // Interrupt Disable Register
  221 + AT91_REG SYS_DBGU_IMR; // Interrupt Mask Register
  222 + AT91_REG SYS_DBGU_CSR; // Channel Status Register
  223 + AT91_REG SYS_DBGU_RHR; // Receiver Holding Register
  224 + AT91_REG SYS_DBGU_THR; // Transmitter Holding Register
  225 + AT91_REG SYS_DBGU_BRGR; // Baud Rate Generator Register
  226 + AT91_REG Reserved10[7]; //
  227 + AT91_REG SYS_DBGU_CIDR; // Chip ID Register
  228 + AT91_REG SYS_DBGU_EXID; // Chip ID Extension Register
  229 + AT91_REG SYS_DBGU_FNTR; // Force NTRST Register
  230 + AT91_REG Reserved11[45]; //
  231 + AT91_REG SYS_DBGU_RPR; // Receive Pointer Register
  232 + AT91_REG SYS_DBGU_RCR; // Receive Counter Register
  233 + AT91_REG SYS_DBGU_TPR; // Transmit Pointer Register
  234 + AT91_REG SYS_DBGU_TCR; // Transmit Counter Register
  235 + AT91_REG SYS_DBGU_RNPR; // Receive Next Pointer Register
  236 + AT91_REG SYS_DBGU_RNCR; // Receive Next Counter Register
  237 + AT91_REG SYS_DBGU_TNPR; // Transmit Next Pointer Register
  238 + AT91_REG SYS_DBGU_TNCR; // Transmit Next Counter Register
  239 + AT91_REG SYS_DBGU_PTCR; // PDC Transfer Control Register
  240 + AT91_REG SYS_DBGU_PTSR; // PDC Transfer Status Register
  241 + AT91_REG Reserved12[54]; //
  242 + AT91_REG SYS_AIC_SMR[32]; // Source Mode Register
  243 + AT91_REG SYS_AIC_SVR[32]; // Source Vector Register
  244 + AT91_REG SYS_AIC_IVR; // IRQ Vector Register
  245 + AT91_REG SYS_AIC_FVR; // FIQ Vector Register
  246 + AT91_REG SYS_AIC_ISR; // Interrupt Status Register
  247 + AT91_REG SYS_AIC_IPR; // Interrupt Pending Register
  248 + AT91_REG SYS_AIC_IMR; // Interrupt Mask Register
  249 + AT91_REG SYS_AIC_CISR; // Core Interrupt Status Register
  250 + AT91_REG Reserved13[2]; //
  251 + AT91_REG SYS_AIC_IECR; // Interrupt Enable Command Register
  252 + AT91_REG SYS_AIC_IDCR; // Interrupt Disable Command Register
  253 + AT91_REG SYS_AIC_ICCR; // Interrupt Clear Command Register
  254 + AT91_REG SYS_AIC_ISCR; // Interrupt Set Command Register
  255 + AT91_REG SYS_AIC_EOICR; // End of Interrupt Command Register
  256 + AT91_REG SYS_AIC_SPU; // Spurious Vector Register
  257 + AT91_REG SYS_AIC_DCR; // Debug Control Register (Protect)
  258 + AT91_REG Reserved14[1]; //
  259 + AT91_REG SYS_AIC_FFER; // Fast Forcing Enable Register
  260 + AT91_REG SYS_AIC_FFDR; // Fast Forcing Disable Register
  261 + AT91_REG SYS_AIC_FFSR; // Fast Forcing Status Register
  262 + AT91_REG Reserved15[45]; //
  263 + AT91_REG SYS_PIOA_PER; // PIO Enable Register
  264 + AT91_REG SYS_PIOA_PDR; // PIO Disable Register
  265 + AT91_REG SYS_PIOA_PSR; // PIO Status Register
  266 + AT91_REG Reserved16[1]; //
  267 + AT91_REG SYS_PIOA_OER; // Output Enable Register
  268 + AT91_REG SYS_PIOA_ODR; // Output Disable Registerr
  269 + AT91_REG SYS_PIOA_OSR; // Output Status Register
  270 + AT91_REG Reserved17[1]; //
  271 + AT91_REG SYS_PIOA_IFER; // Input Filter Enable Register
  272 + AT91_REG SYS_PIOA_IFDR; // Input Filter Disable Register
  273 + AT91_REG SYS_PIOA_IFSR; // Input Filter Status Register
  274 + AT91_REG Reserved18[1]; //
  275 + AT91_REG SYS_PIOA_SODR; // Set Output Data Register
  276 + AT91_REG SYS_PIOA_CODR; // Clear Output Data Register
  277 + AT91_REG SYS_PIOA_ODSR; // Output Data Status Register
  278 + AT91_REG SYS_PIOA_PDSR; // Pin Data Status Register
  279 + AT91_REG SYS_PIOA_IER; // Interrupt Enable Register
  280 + AT91_REG SYS_PIOA_IDR; // Interrupt Disable Register
  281 + AT91_REG SYS_PIOA_IMR; // Interrupt Mask Register
  282 + AT91_REG SYS_PIOA_ISR; // Interrupt Status Register
  283 + AT91_REG SYS_PIOA_MDER; // Multi-driver Enable Register
  284 + AT91_REG SYS_PIOA_MDDR; // Multi-driver Disable Register
  285 + AT91_REG SYS_PIOA_MDSR; // Multi-driver Status Register
  286 + AT91_REG Reserved19[1]; //
  287 + AT91_REG SYS_PIOA_PPUDR; // Pull-up Disable Register
  288 + AT91_REG SYS_PIOA_PPUER; // Pull-up Enable Register
  289 + AT91_REG SYS_PIOA_PPUSR; // Pull-up Status Register
  290 + AT91_REG Reserved20[1]; //
  291 + AT91_REG SYS_PIOA_ASR; // Select A Register
  292 + AT91_REG SYS_PIOA_BSR; // Select B Register
  293 + AT91_REG SYS_PIOA_ABSR; // AB Select Status Register
  294 + AT91_REG Reserved21[9]; //
  295 + AT91_REG SYS_PIOA_OWER; // Output Write Enable Register
  296 + AT91_REG SYS_PIOA_OWDR; // Output Write Disable Register
  297 + AT91_REG SYS_PIOA_OWSR; // Output Write Status Register
  298 + AT91_REG Reserved22[85]; //
  299 + AT91_REG SYS_PIOB_PER; // PIO Enable Register
  300 + AT91_REG SYS_PIOB_PDR; // PIO Disable Register
  301 + AT91_REG SYS_PIOB_PSR; // PIO Status Register
  302 + AT91_REG Reserved23[1]; //
  303 + AT91_REG SYS_PIOB_OER; // Output Enable Register
  304 + AT91_REG SYS_PIOB_ODR; // Output Disable Registerr
  305 + AT91_REG SYS_PIOB_OSR; // Output Status Register
  306 + AT91_REG Reserved24[1]; //
  307 + AT91_REG SYS_PIOB_IFER; // Input Filter Enable Register
  308 + AT91_REG SYS_PIOB_IFDR; // Input Filter Disable Register
  309 + AT91_REG SYS_PIOB_IFSR; // Input Filter Status Register
  310 + AT91_REG Reserved25[1]; //
  311 + AT91_REG SYS_PIOB_SODR; // Set Output Data Register
  312 + AT91_REG SYS_PIOB_CODR; // Clear Output Data Register
  313 + AT91_REG SYS_PIOB_ODSR; // Output Data Status Register
  314 + AT91_REG SYS_PIOB_PDSR; // Pin Data Status Register
  315 + AT91_REG SYS_PIOB_IER; // Interrupt Enable Register
  316 + AT91_REG SYS_PIOB_IDR; // Interrupt Disable Register
  317 + AT91_REG SYS_PIOB_IMR; // Interrupt Mask Register
  318 + AT91_REG SYS_PIOB_ISR; // Interrupt Status Register
  319 + AT91_REG SYS_PIOB_MDER; // Multi-driver Enable Register
  320 + AT91_REG SYS_PIOB_MDDR; // Multi-driver Disable Register
  321 + AT91_REG SYS_PIOB_MDSR; // Multi-driver Status Register
  322 + AT91_REG Reserved26[1]; //
  323 + AT91_REG SYS_PIOB_PPUDR; // Pull-up Disable Register
  324 + AT91_REG SYS_PIOB_PPUER; // Pull-up Enable Register
  325 + AT91_REG SYS_PIOB_PPUSR; // Pull-up Status Register
  326 + AT91_REG Reserved27[1]; //
  327 + AT91_REG SYS_PIOB_ASR; // Select A Register
  328 + AT91_REG SYS_PIOB_BSR; // Select B Register
  329 + AT91_REG SYS_PIOB_ABSR; // AB Select Status Register
  330 + AT91_REG Reserved28[9]; //
  331 + AT91_REG SYS_PIOB_OWER; // Output Write Enable Register
  332 + AT91_REG SYS_PIOB_OWDR; // Output Write Disable Register
  333 + AT91_REG SYS_PIOB_OWSR; // Output Write Status Register
  334 + AT91_REG Reserved29[85]; //
  335 + AT91_REG SYS_PIOC_PER; // PIO Enable Register
  336 + AT91_REG SYS_PIOC_PDR; // PIO Disable Register
  337 + AT91_REG SYS_PIOC_PSR; // PIO Status Register
  338 + AT91_REG Reserved30[1]; //
  339 + AT91_REG SYS_PIOC_OER; // Output Enable Register
  340 + AT91_REG SYS_PIOC_ODR; // Output Disable Registerr
  341 + AT91_REG SYS_PIOC_OSR; // Output Status Register
  342 + AT91_REG Reserved31[1]; //
  343 + AT91_REG SYS_PIOC_IFER; // Input Filter Enable Register
  344 + AT91_REG SYS_PIOC_IFDR; // Input Filter Disable Register
  345 + AT91_REG SYS_PIOC_IFSR; // Input Filter Status Register
  346 + AT91_REG Reserved32[1]; //
  347 + AT91_REG SYS_PIOC_SODR; // Set Output Data Register
  348 + AT91_REG SYS_PIOC_CODR; // Clear Output Data Register
  349 + AT91_REG SYS_PIOC_ODSR; // Output Data Status Register
  350 + AT91_REG SYS_PIOC_PDSR; // Pin Data Status Register
  351 + AT91_REG SYS_PIOC_IER; // Interrupt Enable Register
  352 + AT91_REG SYS_PIOC_IDR; // Interrupt Disable Register
  353 + AT91_REG SYS_PIOC_IMR; // Interrupt Mask Register
  354 + AT91_REG SYS_PIOC_ISR; // Interrupt Status Register
  355 + AT91_REG SYS_PIOC_MDER; // Multi-driver Enable Register
  356 + AT91_REG SYS_PIOC_MDDR; // Multi-driver Disable Register
  357 + AT91_REG SYS_PIOC_MDSR; // Multi-driver Status Register
  358 + AT91_REG Reserved33[1]; //
  359 + AT91_REG SYS_PIOC_PPUDR; // Pull-up Disable Register
  360 + AT91_REG SYS_PIOC_PPUER; // Pull-up Enable Register
  361 + AT91_REG SYS_PIOC_PPUSR; // Pull-up Status Register
  362 + AT91_REG Reserved34[1]; //
  363 + AT91_REG SYS_PIOC_ASR; // Select A Register
  364 + AT91_REG SYS_PIOC_BSR; // Select B Register
  365 + AT91_REG SYS_PIOC_ABSR; // AB Select Status Register
  366 + AT91_REG Reserved35[9]; //
  367 + AT91_REG SYS_PIOC_OWER; // Output Write Enable Register
  368 + AT91_REG SYS_PIOC_OWDR; // Output Write Disable Register
  369 + AT91_REG SYS_PIOC_OWSR; // Output Write Status Register
  370 + AT91_REG Reserved36[85]; //
  371 + AT91_REG SYS_PIOD_PER; // PIO Enable Register
  372 + AT91_REG SYS_PIOD_PDR; // PIO Disable Register
  373 + AT91_REG SYS_PIOD_PSR; // PIO Status Register
  374 + AT91_REG Reserved37[1]; //
  375 + AT91_REG SYS_PIOD_OER; // Output Enable Register
  376 + AT91_REG SYS_PIOD_ODR; // Output Disable Registerr
  377 + AT91_REG SYS_PIOD_OSR; // Output Status Register
  378 + AT91_REG Reserved38[1]; //
  379 + AT91_REG SYS_PIOD_IFER; // Input Filter Enable Register
  380 + AT91_REG SYS_PIOD_IFDR; // Input Filter Disable Register
  381 + AT91_REG SYS_PIOD_IFSR; // Input Filter Status Register
  382 + AT91_REG Reserved39[1]; //
  383 + AT91_REG SYS_PIOD_SODR; // Set Output Data Register
  384 + AT91_REG SYS_PIOD_CODR; // Clear Output Data Register
  385 + AT91_REG SYS_PIOD_ODSR; // Output Data Status Register
  386 + AT91_REG SYS_PIOD_PDSR; // Pin Data Status Register
  387 + AT91_REG SYS_PIOD_IER; // Interrupt Enable Register
  388 + AT91_REG SYS_PIOD_IDR; // Interrupt Disable Register
  389 + AT91_REG SYS_PIOD_IMR; // Interrupt Mask Register
  390 + AT91_REG SYS_PIOD_ISR; // Interrupt Status Register
  391 + AT91_REG SYS_PIOD_MDER; // Multi-driver Enable Register
  392 + AT91_REG SYS_PIOD_MDDR; // Multi-driver Disable Register
  393 + AT91_REG SYS_PIOD_MDSR; // Multi-driver Status Register
  394 + AT91_REG Reserved40[1]; //
  395 + AT91_REG SYS_PIOD_PPUDR; // Pull-up Disable Register
  396 + AT91_REG SYS_PIOD_PPUER; // Pull-up Enable Register
  397 + AT91_REG SYS_PIOD_PPUSR; // Pull-up Status Register
  398 + AT91_REG Reserved41[1]; //
  399 + AT91_REG SYS_PIOD_ASR; // Select A Register
  400 + AT91_REG SYS_PIOD_BSR; // Select B Register
  401 + AT91_REG SYS_PIOD_ABSR; // AB Select Status Register
  402 + AT91_REG Reserved42[9]; //
  403 + AT91_REG SYS_PIOD_OWER; // Output Write Enable Register
  404 + AT91_REG SYS_PIOD_OWDR; // Output Write Disable Register
  405 + AT91_REG SYS_PIOD_OWSR; // Output Write Status Register
  406 + AT91_REG Reserved43[85]; //
  407 + AT91_REG SYS_PIOE_PER; // PIO Enable Register
  408 + AT91_REG SYS_PIOE_PDR; // PIO Disable Register
  409 + AT91_REG SYS_PIOE_PSR; // PIO Status Register
  410 + AT91_REG Reserved44[1]; //
  411 + AT91_REG SYS_PIOE_OER; // Output Enable Register
  412 + AT91_REG SYS_PIOE_ODR; // Output Disable Registerr
  413 + AT91_REG SYS_PIOE_OSR; // Output Status Register
  414 + AT91_REG Reserved45[1]; //
  415 + AT91_REG SYS_PIOE_IFER; // Input Filter Enable Register
  416 + AT91_REG SYS_PIOE_IFDR; // Input Filter Disable Register
  417 + AT91_REG SYS_PIOE_IFSR; // Input Filter Status Register
  418 + AT91_REG Reserved46[1]; //
  419 + AT91_REG SYS_PIOE_SODR; // Set Output Data Register
  420 + AT91_REG SYS_PIOE_CODR; // Clear Output Data Register
  421 + AT91_REG SYS_PIOE_ODSR; // Output Data Status Register
  422 + AT91_REG SYS_PIOE_PDSR; // Pin Data Status Register
  423 + AT91_REG SYS_PIOE_IER; // Interrupt Enable Register
  424 + AT91_REG SYS_PIOE_IDR; // Interrupt Disable Register
  425 + AT91_REG SYS_PIOE_IMR; // Interrupt Mask Register
  426 + AT91_REG SYS_PIOE_ISR; // Interrupt Status Register
  427 + AT91_REG SYS_PIOE_MDER; // Multi-driver Enable Register
  428 + AT91_REG SYS_PIOE_MDDR; // Multi-driver Disable Register
  429 + AT91_REG SYS_PIOE_MDSR; // Multi-driver Status Register
  430 + AT91_REG Reserved47[1]; //
  431 + AT91_REG SYS_PIOE_PPUDR; // Pull-up Disable Register
  432 + AT91_REG SYS_PIOE_PPUER; // Pull-up Enable Register
  433 + AT91_REG SYS_PIOE_PPUSR; // Pull-up Status Register
  434 + AT91_REG Reserved48[1]; //
  435 + AT91_REG SYS_PIOE_ASR; // Select A Register
  436 + AT91_REG SYS_PIOE_BSR; // Select B Register
  437 + AT91_REG SYS_PIOE_ABSR; // AB Select Status Register
  438 + AT91_REG Reserved49[9]; //
  439 + AT91_REG SYS_PIOE_OWER; // Output Write Enable Register
  440 + AT91_REG SYS_PIOE_OWDR; // Output Write Disable Register
  441 + AT91_REG SYS_PIOE_OWSR; // Output Write Status Register
  442 + AT91_REG Reserved50[85]; //
  443 + AT91_REG SYS_PMC_SCER; // System Clock Enable Register
  444 + AT91_REG SYS_PMC_SCDR; // System Clock Disable Register
  445 + AT91_REG SYS_PMC_SCSR; // System Clock Status Register
  446 + AT91_REG Reserved51[1]; //
  447 + AT91_REG SYS_PMC_PCER; // Peripheral Clock Enable Register
  448 + AT91_REG SYS_PMC_PCDR; // Peripheral Clock Disable Register
  449 + AT91_REG SYS_PMC_PCSR; // Peripheral Clock Status Register
  450 + AT91_REG Reserved52[1]; //
  451 + AT91_REG SYS_PMC_MOR; // Main Oscillator Register
  452 + AT91_REG SYS_PMC_MCFR; // Main Clock Frequency Register
  453 + AT91_REG SYS_PMC_PLLAR; // PLL A Register
  454 + AT91_REG SYS_PMC_PLLBR; // PLL B Register
  455 + AT91_REG SYS_PMC_MCKR; // Master Clock Register
  456 + AT91_REG Reserved53[3]; //
  457 + AT91_REG SYS_PMC_PCKR[8]; // Programmable Clock Register
  458 + AT91_REG SYS_PMC_IER; // Interrupt Enable Register
  459 + AT91_REG SYS_PMC_IDR; // Interrupt Disable Register
  460 + AT91_REG SYS_PMC_SR; // Status Register
  461 + AT91_REG SYS_PMC_IMR; // Interrupt Mask Register
  462 + AT91_REG Reserved54[36]; //
  463 + AT91_REG SYS_RSTC_RCR; // Reset Control Register
  464 + AT91_REG SYS_RSTC_RSR; // Reset Status Register
  465 + AT91_REG SYS_RSTC_RMR; // Reset Mode Register
  466 + AT91_REG Reserved55[1]; //
  467 + AT91_REG SYS_SHDWC_SHCR; // Shut Down Control Register
  468 + AT91_REG SYS_SHDWC_SHMR; // Shut Down Mode Register
  469 + AT91_REG SYS_SHDWC_SHSR; // Shut Down Status Register
  470 + AT91_REG Reserved56[1]; //
  471 + AT91_REG SYS_RTTC0_RTMR; // Real-time Mode Register
  472 + AT91_REG SYS_RTTC0_RTAR; // Real-time Alarm Register
  473 + AT91_REG SYS_RTTC0_RTVR; // Real-time Value Register
  474 + AT91_REG SYS_RTTC0_RTSR; // Real-time Status Register
  475 + AT91_REG SYS_PITC_PIMR; // Period Interval Mode Register
  476 + AT91_REG SYS_PITC_PISR; // Period Interval Status Register
  477 + AT91_REG SYS_PITC_PIVR; // Period Interval Value Register
  478 + AT91_REG SYS_PITC_PIIR; // Period Interval Image Register
  479 + AT91_REG SYS_WDTC_WDCR; // Watchdog Control Register
  480 + AT91_REG SYS_WDTC_WDMR; // Watchdog Mode Register
  481 + AT91_REG SYS_WDTC_WDSR; // Watchdog Status Register
  482 + AT91_REG Reserved57[1]; //
  483 + AT91_REG SYS_RTTC1_RTMR; // Real-time Mode Register
  484 + AT91_REG SYS_RTTC1_RTAR; // Real-time Alarm Register
  485 + AT91_REG SYS_RTTC1_RTVR; // Real-time Value Register
  486 + AT91_REG SYS_RTTC1_RTSR; // Real-time Status Register
  487 + AT91_REG SYS_GPBR[20]; // General Purpose Register
  488 +} AT91S_SYS, *AT91PS_SYS;
  489 +#else
  490 +#define ECC0 (AT91_CAST(AT91_REG *) 0x00000000) // (ECC0) ECC 0
  491 +#define ECC1 (AT91_CAST(AT91_REG *) 0x00000600) // (ECC1) ECC 0
  492 +#define GPBR (AT91_CAST(AT91_REG *) 0x00001D60) // (GPBR) General Purpose Register
  493 +
  494 +#endif
  495 +// -------- GPBR : (SYS Offset: 0x1d60) GPBR General Purpose Register --------
  496 +#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value
  497 +
  498 +// *****************************************************************************
  499 +// SOFTWARE API DEFINITION FOR External Bus Interface 0
  500 +// *****************************************************************************
  501 +#ifndef __ASSEMBLY__
  502 +typedef struct _AT91S_EBI0 {
  503 + AT91_REG EBI0_DUMMY; // Dummy register - Do not use
  504 +} AT91S_EBI0, *AT91PS_EBI0;
  505 +#else
  506 +#define EBI0_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI0_DUMMY) Dummy register - Do not use
  507 +
  508 +#endif
  509 +
  510 +// *****************************************************************************
  511 +// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
  512 +// *****************************************************************************
  513 +#ifndef __ASSEMBLY__
  514 +typedef struct _AT91S_SDRAMC {
  515 + AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
  516 + AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
  517 + AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
  518 + AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
  519 + AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
  520 + AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
  521 + AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
  522 + AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
  523 + AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
  524 + AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
  525 +} AT91S_SDRAMC, *AT91PS_SDRAMC;
  526 +#else
  527 +#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
  528 +#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
  529 +#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
  530 +#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
  531 +#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
  532 +#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
  533 +#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
  534 +#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
  535 +#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
  536 +#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
  537 +
  538 +#endif
  539 +// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
  540 +#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode
  541 +#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
  542 +#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
  543 +#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
  544 +#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
  545 +#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
  546 +#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
  547 +#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
  548 +// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
  549 +#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
  550 +// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
  551 +#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
  552 +#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
  553 +#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
  554 +#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
  555 +#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
  556 +#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
  557 +#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
  558 +#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
  559 +#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
  560 +#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
  561 +#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
  562 +#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
  563 +#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
  564 +#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
  565 +#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
  566 +#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
  567 +#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
  568 +#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
  569 +#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
  570 +#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
  571 +#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
  572 +#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
  573 +#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
  574 +#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
  575 +#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
  576 +#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
  577 +#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
  578 +#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
  579 +#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
  580 +#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
  581 +#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
  582 +#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
  583 +#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
  584 +#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
  585 +#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
  586 +#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
  587 +#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
  588 +#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
  589 +#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2
  590 +#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3
  591 +#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4
  592 +#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5
  593 +#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6
  594 +#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7
  595 +#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8
  596 +#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9
  597 +#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10
  598 +#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11
  599 +#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12
  600 +#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13
  601 +#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14
  602 +#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15
  603 +#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
  604 +#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0
  605 +#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1
  606 +#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2
  607 +#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3
  608 +#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4
  609 +#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5
  610 +#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6
  611 +#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7
  612 +#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8
  613 +#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9
  614 +#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10
  615 +#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11
  616 +#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12
  617 +#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13
  618 +#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14
  619 +#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15
  620 +#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
  621 +#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0
  622 +#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1
  623 +#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2
  624 +#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3
  625 +#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4
  626 +#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5
  627 +#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6
  628 +#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7
  629 +#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8
  630 +#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9
  631 +#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10
  632 +#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11
  633 +#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12
  634 +#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13
  635 +#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14
  636 +#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15
  637 +#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
  638 +#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0
  639 +#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1
  640 +#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2
  641 +#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3
  642 +#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4
  643 +#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5
  644 +#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6
  645 +#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7
  646 +#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8
  647 +#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9
  648 +#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10
  649 +#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11
  650 +#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12
  651 +#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13
  652 +#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14
  653 +#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15
  654 +#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
  655 +#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0
  656 +#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1
  657 +#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2
  658 +#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3
  659 +#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4
  660 +#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5
  661 +#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6
  662 +#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7
  663 +#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8
  664 +#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9
  665 +#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10
  666 +#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11
  667 +#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12
  668 +#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13
  669 +#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14
  670 +#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15
  671 +// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
  672 +#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit
  673 +#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle
  674 +#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle
  675 +// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
  676 +#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations
  677 +#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features
  678 +#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH
  679 +#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN
  680 +#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
  681 +#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
  682 +#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
  683 +#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
  684 +#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
  685 +#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
  686 +#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
  687 +#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
  688 +// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
  689 +#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status
  690 +// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
  691 +// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
  692 +// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
  693 +// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
  694 +#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type
  695 +#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode
  696 +#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode
  697 +
  698 +// *****************************************************************************
  699 +// SOFTWARE API DEFINITION FOR Static Memory Controller Interface
  700 +// *****************************************************************************
  701 +#ifndef __ASSEMBLY__
  702 +typedef struct _AT91S_SMC {
  703 + AT91_REG SMC_SETUP0; // Setup Register for CS 0
  704 + AT91_REG SMC_PULSE0; // Pulse Register for CS 0
  705 + AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
  706 + AT91_REG SMC_CTRL0; // Control Register for CS 0
  707 + AT91_REG SMC_SETUP1; // Setup Register for CS 1
  708 + AT91_REG SMC_PULSE1; // Pulse Register for CS 1
  709 + AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
  710 + AT91_REG SMC_CTRL1; // Control Register for CS 1
  711 + AT91_REG SMC_SETUP2; // Setup Register for CS 2
  712 + AT91_REG SMC_PULSE2; // Pulse Register for CS 2
  713 + AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
  714 + AT91_REG SMC_CTRL2; // Control Register for CS 2
  715 + AT91_REG SMC_SETUP3; // Setup Register for CS 3
  716 + AT91_REG SMC_PULSE3; // Pulse Register for CS 3
  717 + AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
  718 + AT91_REG SMC_CTRL3; // Control Register for CS 3
  719 + AT91_REG SMC_SETUP4; // Setup Register for CS 4
  720 + AT91_REG SMC_PULSE4; // Pulse Register for CS 4
  721 + AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
  722 + AT91_REG SMC_CTRL4; // Control Register for CS 4
  723 + AT91_REG SMC_SETUP5; // Setup Register for CS 5
  724 + AT91_REG SMC_PULSE5; // Pulse Register for CS 5
  725 + AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
  726 + AT91_REG SMC_CTRL5; // Control Register for CS 5
  727 + AT91_REG SMC_SETUP6; // Setup Register for CS 6
  728 + AT91_REG SMC_PULSE6; // Pulse Register for CS 6
  729 + AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
  730 + AT91_REG SMC_CTRL6; // Control Register for CS 6
  731 + AT91_REG SMC_SETUP7; // Setup Register for CS 7
  732 + AT91_REG SMC_PULSE7; // Pulse Register for CS 7
  733 + AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
  734 + AT91_REG SMC_CTRL7; // Control Register for CS 7
  735 +} AT91S_SMC, *AT91PS_SMC;
  736 +#else
  737 +#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0
  738 +#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0
  739 +#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0
  740 +#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0
  741 +#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1
  742 +#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1
  743 +#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1
  744 +#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1
  745 +#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2
  746 +#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2
  747 +#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2
  748 +#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2
  749 +#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3
  750 +#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3
  751 +#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3
  752 +#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3
  753 +#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4
  754 +#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4
  755 +#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4
  756 +#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4
  757 +#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5
  758 +#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5
  759 +#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5
  760 +#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5
  761 +#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6
  762 +#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6
  763 +#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6
  764 +#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6
  765 +#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7
  766 +#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7
  767 +#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7
  768 +#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7
  769 +
  770 +#endif
  771 +// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
  772 +#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length
  773 +#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access
  774 +#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length
  775 +#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
  776 +// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
  777 +#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length
  778 +#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access
  779 +#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length
  780 +#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
  781 +// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
  782 +#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length
  783 +#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length
  784 +// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
  785 +#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode
  786 +#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode
  787 +#define AT91C_SMC_NWAITM (0x3 << 5) // (SMC) NWAIT Mode
  788 +#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) // (SMC) External NWAIT disabled.
  789 +#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) // (SMC) External NWAIT enabled in frozen mode.
  790 +#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) // (SMC) External NWAIT enabled in ready mode.
  791 +#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type
  792 +#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
  793 +#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
  794 +#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width
  795 +#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.
  796 +#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.
  797 +#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
  798 +#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.
  799 +#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.
  800 +#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.
  801 +#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size
  802 +#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.
  803 +#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.
  804 +#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.
  805 +#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
  806 +// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
  807 +// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
  808 +// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
  809 +// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
  810 +// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
  811 +// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
  812 +// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
  813 +// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
  814 +// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
  815 +// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
  816 +// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
  817 +// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
  818 +// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
  819 +// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
  820 +// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
  821 +// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
  822 +// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
  823 +// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
  824 +// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
  825 +// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
  826 +// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
  827 +// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
  828 +// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
  829 +// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
  830 +// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
  831 +// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
  832 +// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
  833 +// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
  834 +
  835 +// *****************************************************************************
  836 +// SOFTWARE API DEFINITION FOR External Bus Interface 1
  837 +// *****************************************************************************
  838 +#ifndef __ASSEMBLY__
  839 +typedef struct _AT91S_EBI1 {
  840 + AT91_REG EBI1_DUMMY; // Dummy register - Do not use
  841 +} AT91S_EBI1, *AT91PS_EBI1;
  842 +#else
  843 +#define EBI1_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI1_DUMMY) Dummy register - Do not use
  844 +
  845 +#endif
  846 +
  847 +// *****************************************************************************
  848 +// SOFTWARE API DEFINITION FOR AHB Matrix Interface
  849 +// *****************************************************************************
  850 +#ifndef __ASSEMBLY__
  851 +typedef struct _AT91S_MATRIX {
  852 + AT91_REG MATRIX_MCFG0; // Master Configuration Register 0
  853 + AT91_REG MATRIX_MCFG1; // Master Configuration Register 1
  854 + AT91_REG MATRIX_MCFG2; // Master Configuration Register 2
  855 + AT91_REG MATRIX_MCFG3; // Master Configuration Register 3
  856 + AT91_REG MATRIX_MCFG4; // Master Configuration Register 4
  857 + AT91_REG MATRIX_MCFG5; // Master Configuration Register 5
  858 + AT91_REG MATRIX_MCFG6; // Master Configuration Register 6
  859 + AT91_REG MATRIX_MCFG7; // Master Configuration Register 7
  860 + AT91_REG MATRIX_MCFG8; // Master Configuration Register 8
  861 + AT91_REG Reserved0[7]; //
  862 + AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0
  863 + AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1
  864 + AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2
  865 + AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3
  866 + AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4
  867 + AT91_REG MATRIX_SCFG5; // Slave Configuration Register 5
  868 + AT91_REG MATRIX_SCFG6; // Slave Configuration Register 6
  869 + AT91_REG MATRIX_SCFG7; // Slave Configuration Register 7
  870 + AT91_REG Reserved1[8]; //
  871 + AT91_REG MATRIX_PRAS0; // PRAS0
  872 + AT91_REG MATRIX_PRBS0; // PRBS0
  873 + AT91_REG MATRIX_PRAS1; // PRAS1
  874 + AT91_REG MATRIX_PRBS1; // PRBS1
  875 + AT91_REG MATRIX_PRAS2; // PRAS2
  876 + AT91_REG MATRIX_PRBS2; // PRBS2
  877 + AT91_REG MATRIX_PRAS3; // PRAS3
  878 + AT91_REG MATRIX_PRBS3; // PRBS3
  879 + AT91_REG MATRIX_PRAS4; // PRAS4
  880 + AT91_REG MATRIX_PRBS4; // PRBS4
  881 + AT91_REG MATRIX_PRAS5; // PRAS5
  882 + AT91_REG MATRIX_PRBS5; // PRBS5
  883 + AT91_REG MATRIX_PRAS6; // PRAS6
  884 + AT91_REG MATRIX_PRBS6; // PRBS6
  885 + AT91_REG MATRIX_PRAS7; // PRAS7
  886 + AT91_REG MATRIX_PRBS7; // PRBS7
  887 + AT91_REG Reserved2[16]; //
  888 + AT91_REG MATRIX_MRCR; // Master Remp Control Register
  889 +} AT91S_MATRIX, *AT91PS_MATRIX;
  890 +#else
  891 +#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0
  892 +#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1
  893 +#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2
  894 +#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3
  895 +#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4
  896 +#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5
  897 +#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6
  898 +#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7
  899 +#define MATRIX_MCFG8 (AT91_CAST(AT91_REG *) 0x00000020) // (MATRIX_MCFG8) Master Configuration Register 8
  900 +#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0
  901 +#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1
  902 +#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2
  903 +#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3
  904 +#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4
  905 +#define MATRIX_SCFG5 (AT91_CAST(AT91_REG *) 0x00000054) // (MATRIX_SCFG5) Slave Configuration Register 5
  906 +#define MATRIX_SCFG6 (AT91_CAST(AT91_REG *) 0x00000058) // (MATRIX_SCFG6) Slave Configuration Register 6
  907 +#define MATRIX_SCFG7 (AT91_CAST(AT91_REG *) 0x0000005C) // (MATRIX_SCFG7) Slave Configuration Register 7
  908 +#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0
  909 +#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0
  910 +#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1
  911 +#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1
  912 +#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2
  913 +#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2
  914 +#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3
  915 +#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3
  916 +#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4
  917 +#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4
  918 +#define MATRIX_PRAS5 (AT91_CAST(AT91_REG *) 0x000000A8) // (MATRIX_PRAS5) PRAS5
  919 +#define MATRIX_PRBS5 (AT91_CAST(AT91_REG *) 0x000000AC) // (MATRIX_PRBS5) PRBS5
  920 +#define MATRIX_PRAS6 (AT91_CAST(AT91_REG *) 0x000000B0) // (MATRIX_PRAS6) PRAS6
  921 +#define MATRIX_PRBS6 (AT91_CAST(AT91_REG *) 0x000000B4) // (MATRIX_PRBS6) PRBS6
  922 +#define MATRIX_PRAS7 (AT91_CAST(AT91_REG *) 0x000000B8) // (MATRIX_PRAS7) PRAS7
  923 +#define MATRIX_PRBS7 (AT91_CAST(AT91_REG *) 0x000000BC) // (MATRIX_PRBS7) PRBS7
  924 +#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register
  925 +
  926 +#endif
  927 +// -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0) Master Configuration Register rom --------
  928 +#define AT91C_MATRIX_ULBT (0x7 << 0) // (MATRIX) Undefined Length Burst Type
  929 +// -------- MATRIX_MCFG1 : (MATRIX Offset: 0x4) Master Configuration Register htcm --------
  930 +// -------- MATRIX_MCFG2 : (MATRIX Offset: 0x8) Master Configuration Register gps_tcm --------
  931 +// -------- MATRIX_MCFG3 : (MATRIX Offset: 0xc) Master Configuration Register hperiphs --------
  932 +// -------- MATRIX_MCFG4 : (MATRIX Offset: 0x10) Master Configuration Register ebi0 --------
  933 +// -------- MATRIX_MCFG5 : (MATRIX Offset: 0x14) Master Configuration Register ebi1 --------
  934 +// -------- MATRIX_MCFG6 : (MATRIX Offset: 0x18) Master Configuration Register bridge --------
  935 +// -------- MATRIX_MCFG7 : (MATRIX Offset: 0x1c) Master Configuration Register gps --------
  936 +// -------- MATRIX_MCFG8 : (MATRIX Offset: 0x20) Master Configuration Register gps --------
  937 +// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 --------
  938 +#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
  939 +#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
  940 +#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
  941 +#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
  942 +#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
  943 +#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
  944 +#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
  945 +#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
  946 +#define AT91C_MATRIX_FIXED_DEFMSTR0_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
  947 +#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
  948 +#define AT91C_MATRIX_FIXED_DEFMSTR0_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master
  949 +#define AT91C_MATRIX_FIXED_DEFMSTR0_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master
  950 +#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
  951 +#define AT91C_MATRIX_FIXED_DEFMSTR0_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master
  952 +#define AT91C_MATRIX_FIXED_DEFMSTR0_USB (0x8 << 18) // (MATRIX) USB Master is Default Master
  953 +#define AT91C_MATRIX_ARBT (0x3 << 24) // (MATRIX) Arbitration Type
  954 +// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 --------
  955 +#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
  956 +#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
  957 +#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
  958 +#define AT91C_MATRIX_FIXED_DEFMSTR1_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
  959 +#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
  960 +#define AT91C_MATRIX_FIXED_DEFMSTR1_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master
  961 +#define AT91C_MATRIX_FIXED_DEFMSTR1_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master
  962 +#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
  963 +#define AT91C_MATRIX_FIXED_DEFMSTR1_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master
  964 +#define AT91C_MATRIX_FIXED_DEFMSTR1_USB (0x8 << 18) // (MATRIX) USB Master is Default Master
  965 +// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 --------
  966 +#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
  967 +#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
  968 +#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
  969 +#define AT91C_MATRIX_FIXED_DEFMSTR2_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
  970 +// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 --------
  971 +#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
  972 +#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
  973 +#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
  974 +#define AT91C_MATRIX_FIXED_DEFMSTR3_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
  975 +#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
  976 +#define AT91C_MATRIX_FIXED_DEFMSTR3_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master
  977 +#define AT91C_MATRIX_FIXED_DEFMSTR3_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master
  978 +#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
  979 +#define AT91C_MATRIX_FIXED_DEFMSTR3_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master
  980 +#define AT91C_MATRIX_FIXED_DEFMSTR3_USB (0x8 << 18) // (MATRIX) USB Master is Default Master
  981 +// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 --------
  982 +#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
  983 +#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
  984 +#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
  985 +#define AT91C_MATRIX_FIXED_DEFMSTR4_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
  986 +// -------- MATRIX_SCFG5 : (MATRIX Offset: 0x54) Slave Configuration Register 5 --------
  987 +#define AT91C_MATRIX_FIXED_DEFMSTR5 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
  988 +#define AT91C_MATRIX_FIXED_DEFMSTR5_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
  989 +#define AT91C_MATRIX_FIXED_DEFMSTR5_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
  990 +#define AT91C_MATRIX_FIXED_DEFMSTR5_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
  991 +#define AT91C_MATRIX_FIXED_DEFMSTR5_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
  992 +#define AT91C_MATRIX_FIXED_DEFMSTR5_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master
  993 +#define AT91C_MATRIX_FIXED_DEFMSTR5_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master
  994 +#define AT91C_MATRIX_FIXED_DEFMSTR5_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
  995 +#define AT91C_MATRIX_FIXED_DEFMSTR5_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master
  996 +#define AT91C_MATRIX_FIXED_DEFMSTR5_USB (0x8 << 18) // (MATRIX) USB Master is Default Master
  997 +// -------- MATRIX_SCFG6 : (MATRIX Offset: 0x58) Slave Configuration Register 6 --------
  998 +#define AT91C_MATRIX_FIXED_DEFMSTR6 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
  999 +#define AT91C_MATRIX_FIXED_DEFMSTR6_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
  1000 +#define AT91C_MATRIX_FIXED_DEFMSTR6_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
  1001 +#define AT91C_MATRIX_FIXED_DEFMSTR6_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
  1002 +#define AT91C_MATRIX_FIXED_DEFMSTR6_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
  1003 +#define AT91C_MATRIX_FIXED_DEFMSTR6_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master
  1004 +#define AT91C_MATRIX_FIXED_DEFMSTR6_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master
  1005 +#define AT91C_MATRIX_FIXED_DEFMSTR6_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
  1006 +#define AT91C_MATRIX_FIXED_DEFMSTR6_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master
  1007 +#define AT91C_MATRIX_FIXED_DEFMSTR6_USB (0x8 << 18) // (MATRIX) USB Master is Default Master
  1008 +// -------- MATRIX_SCFG7 : (MATRIX Offset: 0x5c) Slave Configuration Register 7 --------
  1009 +#define AT91C_MATRIX_FIXED_DEFMSTR7 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
  1010 +#define AT91C_MATRIX_FIXED_DEFMSTR7_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
  1011 +#define AT91C_MATRIX_FIXED_DEFMSTR7_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
  1012 +#define AT91C_MATRIX_FIXED_DEFMSTR7_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
  1013 +#define AT91C_MATRIX_FIXED_DEFMSTR7_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
  1014 +// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register --------
  1015 +#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority
  1016 +#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority
  1017 +#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority
  1018 +#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority
  1019 +#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority
  1020 +#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority
  1021 +#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority
  1022 +#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority
  1023 +// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register --------
  1024 +#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority
  1025 +// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register --------
  1026 +// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register --------
  1027 +// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register --------
  1028 +// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register --------
  1029 +// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register --------
  1030 +// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register --------
  1031 +// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register --------
  1032 +// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register --------
  1033 +// -------- MATRIX_PRAS5 : (MATRIX Offset: 0xa8) PRAS5 Register --------
  1034 +// -------- MATRIX_PRBS5 : (MATRIX Offset: 0xac) PRBS5 Register --------
  1035 +// -------- MATRIX_PRAS6 : (MATRIX Offset: 0xb0) PRAS6 Register --------
  1036 +// -------- MATRIX_PRBS6 : (MATRIX Offset: 0xb4) PRBS6 Register --------
  1037 +// -------- MATRIX_PRAS7 : (MATRIX Offset: 0xb8) PRAS7 Register --------
  1038 +// -------- MATRIX_PRBS7 : (MATRIX Offset: 0xbc) PRBS7 Register --------
  1039 +// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
  1040 +#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command Bit for ARM926EJ-S Instruction
  1041 +#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command Bit for ARM926EJ-S Data
  1042 +#define AT91C_MATRIX_RCB2 (0x1 << 2) // (MATRIX) Remap Command Bit for PDC
  1043 +#define AT91C_MATRIX_RCB3 (0x1 << 3) // (MATRIX) Remap Command Bit for LCD
  1044 +#define AT91C_MATRIX_RCB4 (0x1 << 4) // (MATRIX) Remap Command Bit for 2DGC
  1045 +#define AT91C_MATRIX_RCB5 (0x1 << 5) // (MATRIX) Remap Command Bit for ISI
  1046 +#define AT91C_MATRIX_RCB6 (0x1 << 6) // (MATRIX) Remap Command Bit for DMA
  1047 +#define AT91C_MATRIX_RCB7 (0x1 << 7) // (MATRIX) Remap Command Bit for EMAC
  1048 +#define AT91C_MATRIX_RCB8 (0x1 << 8) // (MATRIX) Remap Command Bit for USB
  1049 +
  1050 +// *****************************************************************************
  1051 +// SOFTWARE API DEFINITION FOR AHB CCFG Interface
  1052 +// *****************************************************************************
  1053 +#ifndef __ASSEMBLY__
  1054 +typedef struct _AT91S_CCFG {
  1055 + AT91_REG Reserved0[1]; //
  1056 + AT91_REG CCFG_TCMR; // TCM configuration
  1057 + AT91_REG Reserved1[2]; //
  1058 + AT91_REG CCFG_EBI0CSA; // EBI0 Chip Select Assignement Register
  1059 + AT91_REG CCFG_EBI1CSA; // EBI1 Chip Select Assignement Register
  1060 + AT91_REG Reserved2[53]; //
  1061 + AT91_REG CCFG_MATRIXVERSION; // Version Register
  1062 +} AT91S_CCFG, *AT91PS_CCFG;
  1063 +#else
  1064 +#define CCFG_TCMR (AT91_CAST(AT91_REG *) 0x00000004) // (CCFG_TCMR) TCM configuration
  1065 +#define CCFG_EBI0CSA (AT91_CAST(AT91_REG *) 0x00000010) // (CCFG_EBI0CSA) EBI0 Chip Select Assignement Register
  1066 +#define CCFG_EBI1CSA (AT91_CAST(AT91_REG *) 0x00000014) // (CCFG_EBI1CSA) EBI1 Chip Select Assignement Register
  1067 +#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register
  1068 +
  1069 +#endif
  1070 +// -------- CCFG_TCMR : (CCFG Offset: 0x4) TCM Configuration --------
  1071 +#define AT91C_CCFG_ITCM_SIZE (0xF << 0) // (CCFG) Size of ITCM enabled memory block
  1072 +#define AT91C_CCFG_ITCM_SIZE_0KB (0x0) // (CCFG) 0 KB (No ITCM Memory)
  1073 +#define AT91C_CCFG_ITCM_SIZE_16KB (0x5) // (CCFG) 16 KB
  1074 +#define AT91C_CCFG_ITCM_SIZE_32KB (0x6) // (CCFG) 32 KB
  1075 +#define AT91C_CCFG_DTCM_SIZE (0xF << 4) // (CCFG) Size of DTCM enabled memory block
  1076 +#define AT91C_CCFG_DTCM_SIZE_0KB (0x0 << 4) // (CCFG) 0 KB (No DTCM Memory)
  1077 +#define AT91C_CCFG_DTCM_SIZE_16KB (0x5 << 4) // (CCFG) 16 KB
  1078 +#define AT91C_CCFG_DTCM_SIZE_32KB (0x6 << 4) // (CCFG) 32 KB
  1079 +#define AT91C_CCFG_RM (0xF << 8) // (CCFG) Read Margin registers
  1080 +// -------- CCFG_EBI0CSA : (CCFG Offset: 0x10) EBI0 Chip Select Assignment Register --------
  1081 +#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment
  1082 +#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
  1083 +#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
  1084 +#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment
  1085 +#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
  1086 +#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
  1087 +#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment
  1088 +#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
  1089 +#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
  1090 +#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment
  1091 +#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
  1092 +#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
  1093 +#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration
  1094 +// -------- CCFG_EBI1CSA : (CCFG Offset: 0x14) EBI1 Chip Select Assignement Register --------
  1095 +#define AT91C_EBI_CS2A (0x1 << 3) // (CCFG) EBI1 Chip Select 2 Assignment
  1096 +#define AT91C_EBI_CS2A_SMC (0x0 << 3) // (CCFG) Chip Select 2 is assigned to the Static Memory Controller.
  1097 +#define AT91C_EBI_CS2A_SM (0x1 << 3) // (CCFG) Chip Select 2 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
  1098 +
  1099 +// *****************************************************************************
  1100 +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
  1101 +// *****************************************************************************
  1102 +#ifndef __ASSEMBLY__
  1103 +typedef struct _AT91S_PDC {
  1104 + AT91_REG PDC_RPR; // Receive Pointer Register
  1105 + AT91_REG PDC_RCR; // Receive Counter Register
  1106 + AT91_REG PDC_TPR; // Transmit Pointer Register
  1107 + AT91_REG PDC_TCR; // Transmit Counter Register
  1108 + AT91_REG PDC_RNPR; // Receive Next Pointer Register
  1109 + AT91_REG PDC_RNCR; // Receive Next Counter Register
  1110 + AT91_REG PDC_TNPR; // Transmit Next Pointer Register
  1111 + AT91_REG PDC_TNCR; // Transmit Next Counter Register
  1112 + AT91_REG PDC_PTCR; // PDC Transfer Control Register
  1113 + AT91_REG PDC_PTSR; // PDC Transfer Status Register
  1114 +} AT91S_PDC, *AT91PS_PDC;
  1115 +#else
  1116 +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
  1117 +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
  1118 +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
  1119 +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
  1120 +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
  1121 +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
  1122 +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
  1123 +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
  1124 +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
  1125 +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
  1126 +
  1127 +#endif
  1128 +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
  1129 +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
  1130 +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
  1131 +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
  1132 +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
  1133 +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
  1134 +
  1135 +// *****************************************************************************
  1136 +// SOFTWARE API DEFINITION FOR Debug Unit
  1137 +// *****************************************************************************
  1138 +#ifndef __ASSEMBLY__
  1139 +typedef struct _AT91S_DBGU {
  1140 + AT91_REG DBGU_CR; // Control Register
  1141 + AT91_REG DBGU_MR; // Mode Register
  1142 + AT91_REG DBGU_IER; // Interrupt Enable Register
  1143 + AT91_REG DBGU_IDR; // Interrupt Disable Register
  1144 + AT91_REG DBGU_IMR; // Interrupt Mask Register
  1145 + AT91_REG DBGU_CSR; // Channel Status Register
  1146 + AT91_REG DBGU_RHR; // Receiver Holding Register
  1147 + AT91_REG DBGU_THR; // Transmitter Holding Register
  1148 + AT91_REG DBGU_BRGR; // Baud Rate Generator Register
  1149 + AT91_REG Reserved0[7]; //
  1150 + AT91_REG DBGU_CIDR; // Chip ID Register
  1151 + AT91_REG DBGU_EXID; // Chip ID Extension Register
  1152 + AT91_REG DBGU_FNTR; // Force NTRST Register
  1153 + AT91_REG Reserved1[45]; //
  1154 + AT91_REG DBGU_RPR; // Receive Pointer Register
  1155 + AT91_REG DBGU_RCR; // Receive Counter Register
  1156 + AT91_REG DBGU_TPR; // Transmit Pointer Register
  1157 + AT91_REG DBGU_TCR; // Transmit Counter Register
  1158 + AT91_REG DBGU_RNPR; // Receive Next Pointer Register
  1159 + AT91_REG DBGU_RNCR; // Receive Next Counter Register
  1160 + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
  1161 + AT91_REG DBGU_TNCR; // Transmit Next Counter Register
  1162 + AT91_REG DBGU_PTCR; // PDC Transfer Control Register
  1163 + AT91_REG DBGU_PTSR; // PDC Transfer Status Register
  1164 +} AT91S_DBGU, *AT91PS_DBGU;
  1165 +#else
  1166 +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
  1167 +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
  1168 +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
  1169 +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
  1170 +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
  1171 +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
  1172 +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
  1173 +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
  1174 +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
  1175 +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
  1176 +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
  1177 +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
  1178 +
  1179 +#endif
  1180 +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
  1181 +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
  1182 +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
  1183 +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
  1184 +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
  1185 +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
  1186 +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
  1187 +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
  1188 +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
  1189 +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
  1190 +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
  1191 +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
  1192 +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
  1193 +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
  1194 +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
  1195 +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
  1196 +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
  1197 +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
  1198 +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
  1199 +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
  1200 +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
  1201 +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
  1202 +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
  1203 +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
  1204 +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
  1205 +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
  1206 +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
  1207 +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
  1208 +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
  1209 +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
  1210 +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
  1211 +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
  1212 +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
  1213 +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
  1214 +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
  1215 +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
  1216 +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
  1217 +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
  1218 +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
  1219 +
  1220 +// *****************************************************************************
  1221 +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
  1222 +// *****************************************************************************
  1223 +#ifndef __ASSEMBLY__
  1224 +typedef struct _AT91S_AIC {
  1225 + AT91_REG AIC_SMR[32]; // Source Mode Register
  1226 + AT91_REG AIC_SVR[32]; // Source Vector Register
  1227 + AT91_REG AIC_IVR; // IRQ Vector Register
  1228 + AT91_REG AIC_FVR; // FIQ Vector Register
  1229 + AT91_REG AIC_ISR; // Interrupt Status Register
  1230 + AT91_REG AIC_IPR; // Interrupt Pending Register
  1231 + AT91_REG AIC_IMR; // Interrupt Mask Register
  1232 + AT91_REG AIC_CISR; // Core Interrupt Status Register
  1233 + AT91_REG Reserved0[2]; //
  1234 + AT91_REG AIC_IECR; // Interrupt Enable Command Register
  1235 + AT91_REG AIC_IDCR; // Interrupt Disable Command Register
  1236 + AT91_REG AIC_ICCR; // Interrupt Clear Command Register
  1237 + AT91_REG AIC_ISCR; // Interrupt Set Command Register
  1238 + AT91_REG AIC_EOICR; // End of Interrupt Command Register
  1239 + AT91_REG AIC_SPU; // Spurious Vector Register
  1240 + AT91_REG AIC_DCR; // Debug Control Register (Protect)
  1241 + AT91_REG Reserved1[1]; //
  1242 + AT91_REG AIC_FFER; // Fast Forcing Enable Register
  1243 + AT91_REG AIC_FFDR; // Fast Forcing Disable Register
  1244 + AT91_REG AIC_FFSR; // Fast Forcing Status Register
  1245 +} AT91S_AIC, *AT91PS_AIC;
  1246 +#else
  1247 +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
  1248 +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
  1249 +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
  1250 +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
  1251 +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
  1252 +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
  1253 +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
  1254 +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
  1255 +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
  1256 +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
  1257 +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
  1258 +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
  1259 +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
  1260 +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
  1261 +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
  1262 +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
  1263 +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
  1264 +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
  1265 +
  1266 +#endif
  1267 +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
  1268 +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
  1269 +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
  1270 +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
  1271 +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
  1272 +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
  1273 +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
  1274 +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
  1275 +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
  1276 +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
  1277 +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
  1278 +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
  1279 +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
  1280 +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
  1281 +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
  1282 +
  1283 +// *****************************************************************************
  1284 +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
  1285 +// *****************************************************************************
  1286 +#ifndef __ASSEMBLY__
  1287 +typedef struct _AT91S_PIO {
  1288 + AT91_REG PIO_PER; // PIO Enable Register
  1289 + AT91_REG PIO_PDR; // PIO Disable Register
  1290 + AT91_REG PIO_PSR; // PIO Status Register
  1291 + AT91_REG Reserved0[1]; //
  1292 + AT91_REG PIO_OER; // Output Enable Register
  1293 + AT91_REG PIO_ODR; // Output Disable Registerr
  1294 + AT91_REG PIO_OSR; // Output Status Register
  1295 + AT91_REG Reserved1[1]; //
  1296 + AT91_REG PIO_IFER; // Input Filter Enable Register
  1297 + AT91_REG PIO_IFDR; // Input Filter Disable Register
  1298 + AT91_REG PIO_IFSR; // Input Filter Status Register
  1299 + AT91_REG Reserved2[1]; //
  1300 + AT91_REG PIO_SODR; // Set Output Data Register
  1301 + AT91_REG PIO_CODR; // Clear Output Data Register
  1302 + AT91_REG PIO_ODSR; // Output Data Status Register
  1303 + AT91_REG PIO_PDSR; // Pin Data Status Register
  1304 + AT91_REG PIO_IER; // Interrupt Enable Register
  1305 + AT91_REG PIO_IDR; // Interrupt Disable Register
  1306 + AT91_REG PIO_IMR; // Interrupt Mask Register
  1307 + AT91_REG PIO_ISR; // Interrupt Status Register
  1308 + AT91_REG PIO_MDER; // Multi-driver Enable Register
  1309 + AT91_REG PIO_MDDR; // Multi-driver Disable Register
  1310 + AT91_REG PIO_MDSR; // Multi-driver Status Register
  1311 + AT91_REG Reserved3[1]; //
  1312 + AT91_REG PIO_PPUDR; // Pull-up Disable Register
  1313 + AT91_REG PIO_PPUER; // Pull-up Enable Register
  1314 + AT91_REG PIO_PPUSR; // Pull-up Status Register
  1315 + AT91_REG Reserved4[1]; //
  1316 + AT91_REG PIO_ASR; // Select A Register
  1317 + AT91_REG PIO_BSR; // Select B Register
  1318 + AT91_REG PIO_ABSR; // AB Select Status Register
  1319 + AT91_REG Reserved5[9]; //
  1320 + AT91_REG PIO_OWER; // Output Write Enable Register
  1321 + AT91_REG PIO_OWDR; // Output Write Disable Register
  1322 + AT91_REG PIO_OWSR; // Output Write Status Register
  1323 +} AT91S_PIO, *AT91PS_PIO;
  1324 +#else
  1325 +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
  1326 +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
  1327 +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
  1328 +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
  1329 +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
  1330 +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
  1331 +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
  1332 +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
  1333 +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
  1334 +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
  1335 +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
  1336 +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
  1337 +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
  1338 +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
  1339 +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
  1340 +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
  1341 +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
  1342 +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
  1343 +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
  1344 +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
  1345 +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
  1346 +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
  1347 +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
  1348 +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
  1349 +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
  1350 +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
  1351 +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
  1352 +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
  1353 +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
  1354 +
  1355 +#endif
  1356 +
  1357 +// *****************************************************************************
  1358 +// SOFTWARE API DEFINITION FOR Clock Generator Controler
  1359 +// *****************************************************************************
  1360 +#ifndef __ASSEMBLY__
  1361 +typedef struct _AT91S_CKGR {
  1362 + AT91_REG CKGR_MOR; // Main Oscillator Register
  1363 + AT91_REG CKGR_MCFR; // Main Clock Frequency Register
  1364 + AT91_REG CKGR_PLLAR; // PLL A Register
  1365 + AT91_REG CKGR_PLLBR; // PLL B Register
  1366 +} AT91S_CKGR, *AT91PS_CKGR;
  1367 +#else
  1368 +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
  1369 +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
  1370 +#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register
  1371 +#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register
  1372 +
  1373 +#endif
  1374 +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
  1375 +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
  1376 +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
  1377 +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
  1378 +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
  1379 +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
  1380 +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
  1381 +// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
  1382 +#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected
  1383 +#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0
  1384 +#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed
  1385 +#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter
  1386 +#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range
  1387 +#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
  1388 +#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
  1389 +#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
  1390 +#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
  1391 +#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier
  1392 +#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR)
  1393 +// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
  1394 +#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected
  1395 +#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0
  1396 +#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed
  1397 +#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter
  1398 +#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range
  1399 +#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
  1400 +#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
  1401 +#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
  1402 +#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
  1403 +#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier
  1404 +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
  1405 +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
  1406 +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
  1407 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
  1408 +
  1409 +// *****************************************************************************
  1410 +// SOFTWARE API DEFINITION FOR Power Management Controler
  1411 +// *****************************************************************************
  1412 +#ifndef __ASSEMBLY__
  1413 +typedef struct _AT91S_PMC {
  1414 + AT91_REG PMC_SCER; // System Clock Enable Register
  1415 + AT91_REG PMC_SCDR; // System Clock Disable Register
  1416 + AT91_REG PMC_SCSR; // System Clock Status Register
  1417 + AT91_REG Reserved0[1]; //
  1418 + AT91_REG PMC_PCER; // Peripheral Clock Enable Register
  1419 + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
  1420 + AT91_REG PMC_PCSR; // Peripheral Clock Status Register
  1421 + AT91_REG Reserved1[1]; //
  1422 + AT91_REG PMC_MOR; // Main Oscillator Register
  1423 + AT91_REG PMC_MCFR; // Main Clock Frequency Register
  1424 + AT91_REG PMC_PLLAR; // PLL A Register
  1425 + AT91_REG PMC_PLLBR; // PLL B Register
  1426 + AT91_REG PMC_MCKR; // Master Clock Register
  1427 + AT91_REG Reserved2[3]; //
  1428 + AT91_REG PMC_PCKR[8]; // Programmable Clock Register
  1429 + AT91_REG PMC_IER; // Interrupt Enable Register
  1430 + AT91_REG PMC_IDR; // Interrupt Disable Register
  1431 + AT91_REG PMC_SR; // Status Register
  1432 + AT91_REG PMC_IMR; // Interrupt Mask Register
  1433 +} AT91S_PMC, *AT91PS_PMC;
  1434 +#else
  1435 +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
  1436 +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
  1437 +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
  1438 +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
  1439 +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
  1440 +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
  1441 +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
  1442 +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
  1443 +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
  1444 +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
  1445 +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
  1446 +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
  1447 +
  1448 +#endif
  1449 +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
  1450 +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
  1451 +#define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock
  1452 +#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock
  1453 +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
  1454 +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
  1455 +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
  1456 +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
  1457 +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
  1458 +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
  1459 +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
  1460 +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
  1461 +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
  1462 +// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
  1463 +// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
  1464 +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
  1465 +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
  1466 +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
  1467 +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
  1468 +#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected
  1469 +#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected
  1470 +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
  1471 +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
  1472 +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
  1473 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
  1474 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
  1475 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
  1476 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
  1477 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
  1478 +#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division
  1479 +#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same
  1480 +#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
  1481 +#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock
  1482 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
  1483 +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
  1484 +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
  1485 +#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
  1486 +#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
  1487 +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask
  1488 +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
  1489 +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
  1490 +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
  1491 +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
  1492 +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
  1493 +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
  1494 +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
  1495 +
  1496 +// *****************************************************************************
  1497 +// SOFTWARE API DEFINITION FOR Reset Controller Interface
  1498 +// *****************************************************************************
  1499 +#ifndef __ASSEMBLY__
  1500 +typedef struct _AT91S_RSTC {
  1501 + AT91_REG RSTC_RCR; // Reset Control Register
  1502 + AT91_REG RSTC_RSR; // Reset Status Register
  1503 + AT91_REG RSTC_RMR; // Reset Mode Register
  1504 +} AT91S_RSTC, *AT91PS_RSTC;
  1505 +#else
  1506 +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
  1507 +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
  1508 +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
  1509 +
  1510 +#endif
  1511 +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
  1512 +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
  1513 +#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
  1514 +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
  1515 +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
  1516 +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
  1517 +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
  1518 +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
  1519 +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
  1520 +#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
  1521 +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
  1522 +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
  1523 +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
  1524 +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
  1525 +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
  1526 +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
  1527 +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
  1528 +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
  1529 +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
  1530 +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
  1531 +
  1532 +// *****************************************************************************
  1533 +// SOFTWARE API DEFINITION FOR Shut Down Controller Interface
  1534 +// *****************************************************************************
  1535 +#ifndef __ASSEMBLY__
  1536 +typedef struct _AT91S_SHDWC {
  1537 + AT91_REG SHDWC_SHCR; // Shut Down Control Register
  1538 + AT91_REG SHDWC_SHMR; // Shut Down Mode Register
  1539 + AT91_REG SHDWC_SHSR; // Shut Down Status Register
  1540 +} AT91S_SHDWC, *AT91PS_SHDWC;
  1541 +#else
  1542 +#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register
  1543 +#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
  1544 +#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register
  1545 +
  1546 +#endif
  1547 +// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
  1548 +#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset
  1549 +#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password
  1550 +// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
  1551 +#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection
  1552 +#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.
  1553 +#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.
  1554 +#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.
  1555 +#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.
  1556 +#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0
  1557 +#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
  1558 +// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
  1559 +#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status
  1560 +#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up
  1561 +
  1562 +// *****************************************************************************
  1563 +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
  1564 +// *****************************************************************************
  1565 +#ifndef __ASSEMBLY__
  1566 +typedef struct _AT91S_RTTC {
  1567 + AT91_REG RTTC_RTMR; // Real-time Mode Register
  1568 + AT91_REG RTTC_RTAR; // Real-time Alarm Register
  1569 + AT91_REG RTTC_RTVR; // Real-time Value Register
  1570 + AT91_REG RTTC_RTSR; // Real-time Status Register
  1571 +} AT91S_RTTC, *AT91PS_RTTC;
  1572 +#else
  1573 +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
  1574 +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
  1575 +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
  1576 +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
  1577 +
  1578 +#endif
  1579 +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
  1580 +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
  1581 +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
  1582 +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
  1583 +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
  1584 +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
  1585 +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
  1586 +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
  1587 +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
  1588 +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
  1589 +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
  1590 +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
  1591 +
  1592 +// *****************************************************************************
  1593 +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
  1594 +// *****************************************************************************
  1595 +#ifndef __ASSEMBLY__
  1596 +typedef struct _AT91S_PITC {
  1597 + AT91_REG PITC_PIMR; // Period Interval Mode Register
  1598 + AT91_REG PITC_PISR; // Period Interval Status Register
  1599 + AT91_REG PITC_PIVR; // Period Interval Value Register
  1600 + AT91_REG PITC_PIIR; // Period Interval Image Register
  1601 +} AT91S_PITC, *AT91PS_PITC;
  1602 +#else
  1603 +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
  1604 +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
  1605 +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
  1606 +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
  1607 +
  1608 +#endif
  1609 +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
  1610 +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
  1611 +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
  1612 +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
  1613 +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
  1614 +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
  1615 +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
  1616 +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
  1617 +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
  1618 +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
  1619 +
  1620 +// *****************************************************************************
  1621 +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
  1622 +// *****************************************************************************
  1623 +#ifndef __ASSEMBLY__
  1624 +typedef struct _AT91S_WDTC {
  1625 + AT91_REG WDTC_WDCR; // Watchdog Control Register
  1626 + AT91_REG WDTC_WDMR; // Watchdog Mode Register
  1627 + AT91_REG WDTC_WDSR; // Watchdog Status Register
  1628 +} AT91S_WDTC, *AT91PS_WDTC;
  1629 +#else
  1630 +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
  1631 +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
  1632 +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
  1633 +
  1634 +#endif
  1635 +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
  1636 +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
  1637 +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
  1638 +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
  1639 +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
  1640 +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
  1641 +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
  1642 +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
  1643 +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
  1644 +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
  1645 +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
  1646 +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
  1647 +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
  1648 +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
  1649 +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
  1650 +
  1651 +// *****************************************************************************
  1652 +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
  1653 +// *****************************************************************************
  1654 +#ifndef __ASSEMBLY__
  1655 +typedef struct _AT91S_TC {
  1656 + AT91_REG TC_CCR; // Channel Control Register
  1657 + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
  1658 + AT91_REG Reserved0[2]; //
  1659 + AT91_REG TC_CV; // Counter Value
  1660 + AT91_REG TC_RA; // Register A
  1661 + AT91_REG TC_RB; // Register B
  1662 + AT91_REG TC_RC; // Register C
  1663 + AT91_REG TC_SR; // Status Register
  1664 + AT91_REG TC_IER; // Interrupt Enable Register
  1665 + AT91_REG TC_IDR; // Interrupt Disable Register
  1666 + AT91_REG TC_IMR; // Interrupt Mask Register
  1667 +} AT91S_TC, *AT91PS_TC;
  1668 +#else
  1669 +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
  1670 +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
  1671 +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
  1672 +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
  1673 +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
  1674 +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
  1675 +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
  1676 +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
  1677 +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
  1678 +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
  1679 +
  1680 +#endif
  1681 +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
  1682 +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
  1683 +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
  1684 +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
  1685 +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
  1686 +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
  1687 +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
  1688 +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
  1689 +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
  1690 +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
  1691 +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
  1692 +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
  1693 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
  1694 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
  1695 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
  1696 +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
  1697 +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
  1698 +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
  1699 +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
  1700 +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
  1701 +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
  1702 +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
  1703 +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
  1704 +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
  1705 +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
  1706 +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
  1707 +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
  1708 +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
  1709 +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
  1710 +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
  1711 +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
  1712 +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
  1713 +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
  1714 +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
  1715 +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
  1716 +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
  1717 +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
  1718 +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
  1719 +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
  1720 +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
  1721 +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
  1722 +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
  1723 +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
  1724 +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
  1725 +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
  1726 +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
  1727 +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
  1728 +#define AT91C_TC_WAVE (0x1 << 15) // (TC)
  1729 +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
  1730 +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
  1731 +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
  1732 +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
  1733 +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
  1734 +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
  1735 +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
  1736 +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
  1737 +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
  1738 +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
  1739 +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
  1740 +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
  1741 +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
  1742 +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
  1743 +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
  1744 +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
  1745 +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
  1746 +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
  1747 +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
  1748 +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
  1749 +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
  1750 +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
  1751 +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
  1752 +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
  1753 +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
  1754 +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
  1755 +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
  1756 +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
  1757 +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
  1758 +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
  1759 +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
  1760 +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
  1761 +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
  1762 +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
  1763 +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
  1764 +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
  1765 +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
  1766 +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
  1767 +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
  1768 +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
  1769 +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
  1770 +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
  1771 +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
  1772 +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
  1773 +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
  1774 +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
  1775 +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
  1776 +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
  1777 +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
  1778 +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
  1779 +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
  1780 +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
  1781 +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
  1782 +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
  1783 +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
  1784 +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
  1785 +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
  1786 +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
  1787 +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
  1788 +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
  1789 +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
  1790 +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
  1791 +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
  1792 +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
  1793 +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
  1794 +
  1795 +// *****************************************************************************
  1796 +// SOFTWARE API DEFINITION FOR Timer Counter Interface
  1797 +// *****************************************************************************
  1798 +#ifndef __ASSEMBLY__
  1799 +typedef struct _AT91S_TCB {
  1800 + AT91S_TC TCB_TC0; // TC Channel 0
  1801 + AT91_REG Reserved0[4]; //
  1802 + AT91S_TC TCB_TC1; // TC Channel 1
  1803 + AT91_REG Reserved1[4]; //
  1804 + AT91S_TC TCB_TC2; // TC Channel 2
  1805 + AT91_REG Reserved2[4]; //
  1806 + AT91_REG TCB_BCR; // TC Block Control Register
  1807 + AT91_REG TCB_BMR; // TC Block Mode Register
  1808 +} AT91S_TCB, *AT91PS_TCB;
  1809 +#else
  1810 +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
  1811 +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
  1812 +
  1813 +#endif
  1814 +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
  1815 +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
  1816 +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
  1817 +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
  1818 +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
  1819 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
  1820 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
  1821 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
  1822 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
  1823 +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
  1824 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
  1825 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
  1826 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
  1827 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
  1828 +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
  1829 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
  1830 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
  1831 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
  1832 +
  1833 +// *****************************************************************************
  1834 +// SOFTWARE API DEFINITION FOR Multimedia Card Interface
  1835 +// *****************************************************************************
  1836 +#ifndef __ASSEMBLY__
  1837 +typedef struct _AT91S_MCI {
  1838 + AT91_REG MCI_CR; // MCI Control Register
  1839 + AT91_REG MCI_MR; // MCI Mode Register
  1840 + AT91_REG MCI_DTOR; // MCI Data Timeout Register
  1841 + AT91_REG MCI_SDCR; // MCI SD Card Register
  1842 + AT91_REG MCI_ARGR; // MCI Argument Register
  1843 + AT91_REG MCI_CMDR; // MCI Command Register
  1844 + AT91_REG MCI_BLKR; // MCI Block Register
  1845 + AT91_REG Reserved0[1]; //
  1846 + AT91_REG MCI_RSPR[4]; // MCI Response Register
  1847 + AT91_REG MCI_RDR; // MCI Receive Data Register
  1848 + AT91_REG MCI_TDR; // MCI Transmit Data Register
  1849 + AT91_REG Reserved1[2]; //
  1850 + AT91_REG MCI_SR; // MCI Status Register
  1851 + AT91_REG MCI_IER; // MCI Interrupt Enable Register
  1852 + AT91_REG MCI_IDR; // MCI Interrupt Disable Register
  1853 + AT91_REG MCI_IMR; // MCI Interrupt Mask Register
  1854 + AT91_REG Reserved2[43]; //
  1855 + AT91_REG MCI_VR; // MCI Version Register
  1856 + AT91_REG MCI_RPR; // Receive Pointer Register
  1857 + AT91_REG MCI_RCR; // Receive Counter Register
  1858 + AT91_REG MCI_TPR; // Transmit Pointer Register
  1859 + AT91_REG MCI_TCR; // Transmit Counter Register
  1860 + AT91_REG MCI_RNPR; // Receive Next Pointer Register
  1861 + AT91_REG MCI_RNCR; // Receive Next Counter Register
  1862 + AT91_REG MCI_TNPR; // Transmit Next Pointer Register
  1863 + AT91_REG MCI_TNCR; // Transmit Next Counter Register
  1864 + AT91_REG MCI_PTCR; // PDC Transfer Control Register
  1865 + AT91_REG MCI_PTSR; // PDC Transfer Status Register
  1866 +} AT91S_MCI, *AT91PS_MCI;
  1867 +#else
  1868 +#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register
  1869 +#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register
  1870 +#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register
  1871 +#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register
  1872 +#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register
  1873 +#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register
  1874 +#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register
  1875 +#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register
  1876 +#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register
  1877 +#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register
  1878 +#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register
  1879 +#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register
  1880 +#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
  1881 +#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
  1882 +#define MCI_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VR) MCI Version Register
  1883 +
  1884 +#endif
  1885 +// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
  1886 +#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable
  1887 +#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable
  1888 +#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable
  1889 +#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable
  1890 +#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset
  1891 +// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
  1892 +#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider
  1893 +#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider
  1894 +#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable
  1895 +#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable
  1896 +#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer
  1897 +#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value
  1898 +#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode
  1899 +#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length
  1900 +// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
  1901 +#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number
  1902 +#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier
  1903 +#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1
  1904 +#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16
  1905 +#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128
  1906 +#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256
  1907 +#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024
  1908 +#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096
  1909 +#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536
  1910 +#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576
  1911 +// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
  1912 +#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector
  1913 +#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width
  1914 +// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
  1915 +#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number
  1916 +#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type
  1917 +#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response
  1918 +#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response
  1919 +#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response
  1920 +#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD
  1921 +#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD
  1922 +#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD
  1923 +#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD
  1924 +#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command
  1925 +#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response
  1926 +#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command
  1927 +#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond
  1928 +#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD
  1929 +#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer
  1930 +#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer
  1931 +#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer
  1932 +#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction
  1933 +#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type
  1934 +#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
  1935 +#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
  1936 +#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type
  1937 +#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type
  1938 +#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type
  1939 +#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command
  1940 +#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command
  1941 +#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command
  1942 +#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command
  1943 +// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register --------
  1944 +#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
  1945 +// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
  1946 +#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag
  1947 +#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag
  1948 +#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag
  1949 +#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag
  1950 +#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag
  1951 +#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag
  1952 +#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag
  1953 +#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag
  1954 +#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A
  1955 +#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B
  1956 +#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
  1957 +#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
  1958 +#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag
  1959 +#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag
  1960 +#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag
  1961 +#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag
  1962 +#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag
  1963 +#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag
  1964 +#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag
  1965 +#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag
  1966 +#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag
  1967 +#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag
  1968 +#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag
  1969 +// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
  1970 +// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
  1971 +// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
  1972 +
  1973 +// *****************************************************************************
  1974 +// SOFTWARE API DEFINITION FOR Two-wire Interface
  1975 +// *****************************************************************************
  1976 +#ifndef __ASSEMBLY__
  1977 +typedef struct _AT91S_TWI {
  1978 + AT91_REG TWI_CR; // Control Register
  1979 + AT91_REG TWI_MMR; // Master Mode Register
  1980 + AT91_REG TWI_SMR; // Slave Mode Register
  1981 + AT91_REG TWI_IADR; // Internal Address Register
  1982 + AT91_REG TWI_CWGR; // Clock Waveform Generator Register
  1983 + AT91_REG Reserved0[3]; //
  1984 + AT91_REG TWI_SR; // Status Register
  1985 + AT91_REG TWI_IER; // Interrupt Enable Register
  1986 + AT91_REG TWI_IDR; // Interrupt Disable Register
  1987 + AT91_REG TWI_IMR; // Interrupt Mask Register
  1988 + AT91_REG TWI_RHR; // Receive Holding Register
  1989 + AT91_REG TWI_THR; // Transmit Holding Register
  1990 + AT91_REG Reserved1[50]; //
  1991 + AT91_REG TWI_RPR; // Receive Pointer Register
  1992 + AT91_REG TWI_RCR; // Receive Counter Register
  1993 + AT91_REG TWI_TPR; // Transmit Pointer Register
  1994 + AT91_REG TWI_TCR; // Transmit Counter Register
  1995 + AT91_REG TWI_RNPR; // Receive Next Pointer Register
  1996 + AT91_REG TWI_RNCR; // Receive Next Counter Register
  1997 + AT91_REG TWI_TNPR; // Transmit Next Pointer Register
  1998 + AT91_REG TWI_TNCR; // Transmit Next Counter Register
  1999 + AT91_REG TWI_PTCR; // PDC Transfer Control Register
  2000 + AT91_REG TWI_PTSR; // PDC Transfer Status Register
  2001 +} AT91S_TWI, *AT91PS_TWI;
  2002 +#else
  2003 +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
  2004 +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
  2005 +#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register
  2006 +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
  2007 +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
  2008 +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
  2009 +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
  2010 +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
  2011 +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
  2012 +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
  2013 +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
  2014 +
  2015 +#endif
  2016 +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
  2017 +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
  2018 +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
  2019 +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
  2020 +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
  2021 +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled
  2022 +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled
  2023 +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
  2024 +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
  2025 +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
  2026 +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
  2027 +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
  2028 +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
  2029 +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
  2030 +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
  2031 +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
  2032 +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
  2033 +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address
  2034 +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
  2035 +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
  2036 +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
  2037 +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
  2038 +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
  2039 +#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed
  2040 +#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed
  2041 +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
  2042 +#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY
  2043 +#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY
  2044 +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode)
  2045 +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode)
  2046 +#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode)
  2047 +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
  2048 +#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged
  2049 +#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged
  2050 +#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode)
  2051 +#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
  2052 +#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
  2053 +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer
  2054 +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer
  2055 +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt
  2056 +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt
  2057 +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
  2058 +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
  2059 +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
  2060 +
  2061 +// *****************************************************************************
  2062 +// SOFTWARE API DEFINITION FOR Usart
  2063 +// *****************************************************************************
  2064 +#ifndef __ASSEMBLY__
  2065 +typedef struct _AT91S_USART {
  2066 + AT91_REG US_CR; // Control Register
  2067 + AT91_REG US_MR; // Mode Register
  2068 + AT91_REG US_IER; // Interrupt Enable Register
  2069 + AT91_REG US_IDR; // Interrupt Disable Register
  2070 + AT91_REG US_IMR; // Interrupt Mask Register
  2071 + AT91_REG US_CSR; // Channel Status Register
  2072 + AT91_REG US_RHR; // Receiver Holding Register
  2073 + AT91_REG US_THR; // Transmitter Holding Register
  2074 + AT91_REG US_BRGR; // Baud Rate Generator Register
  2075 + AT91_REG US_RTOR; // Receiver Time-out Register
  2076 + AT91_REG US_TTGR; // Transmitter Time-guard Register
  2077 + AT91_REG Reserved0[5]; //
  2078 + AT91_REG US_FIDI; // FI_DI_Ratio Register
  2079 + AT91_REG US_NER; // Nb Errors Register
  2080 + AT91_REG Reserved1[1]; //
  2081 + AT91_REG US_IF; // IRDA_FILTER Register
  2082 + AT91_REG Reserved2[44]; //
  2083 + AT91_REG US_RPR; // Receive Pointer Register
  2084 + AT91_REG US_RCR; // Receive Counter Register
  2085 + AT91_REG US_TPR; // Transmit Pointer Register
  2086 + AT91_REG US_TCR; // Transmit Counter Register
  2087 + AT91_REG US_RNPR; // Receive Next Pointer Register
  2088 + AT91_REG US_RNCR; // Receive Next Counter Register
  2089 + AT91_REG US_TNPR; // Transmit Next Pointer Register
  2090 + AT91_REG US_TNCR; // Transmit Next Counter Register
  2091 + AT91_REG US_PTCR; // PDC Transfer Control Register
  2092 + AT91_REG US_PTSR; // PDC Transfer Status Register
  2093 +} AT91S_USART, *AT91PS_USART;
  2094 +#else
  2095 +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
  2096 +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
  2097 +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
  2098 +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
  2099 +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
  2100 +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
  2101 +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
  2102 +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
  2103 +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
  2104 +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
  2105 +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
  2106 +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
  2107 +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
  2108 +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
  2109 +
  2110 +#endif
  2111 +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
  2112 +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
  2113 +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
  2114 +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
  2115 +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
  2116 +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
  2117 +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
  2118 +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
  2119 +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
  2120 +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
  2121 +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
  2122 +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
  2123 +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
  2124 +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
  2125 +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
  2126 +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
  2127 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
  2128 +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
  2129 +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
  2130 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
  2131 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
  2132 +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
  2133 +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
  2134 +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
  2135 +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
  2136 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
  2137 +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
  2138 +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
  2139 +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
  2140 +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
  2141 +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
  2142 +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
  2143 +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
  2144 +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
  2145 +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
  2146 +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
  2147 +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
  2148 +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
  2149 +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
  2150 +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
  2151 +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
  2152 +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
  2153 +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
  2154 +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
  2155 +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
  2156 +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
  2157 +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
  2158 +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
  2159 +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
  2160 +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
  2161 +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
  2162 +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
  2163 +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
  2164 +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
  2165 +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
  2166 +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
  2167 +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
  2168 +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
  2169 +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
  2170 +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
  2171 +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
  2172 +
  2173 +// *****************************************************************************
  2174 +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
  2175 +// *****************************************************************************
  2176 +#ifndef __ASSEMBLY__
  2177 +typedef struct _AT91S_SSC {
  2178 + AT91_REG SSC_CR; // Control Register
  2179 + AT91_REG SSC_CMR; // Clock Mode Register
  2180 + AT91_REG Reserved0[2]; //
  2181 + AT91_REG SSC_RCMR; // Receive Clock ModeRegister
  2182 + AT91_REG SSC_RFMR; // Receive Frame Mode Register
  2183 + AT91_REG SSC_TCMR; // Transmit Clock Mode Register
  2184 + AT91_REG SSC_TFMR; // Transmit Frame Mode Register
  2185 + AT91_REG SSC_RHR; // Receive Holding Register
  2186 + AT91_REG SSC_THR; // Transmit Holding Register
  2187 + AT91_REG Reserved1[2]; //
  2188 + AT91_REG SSC_RSHR; // Receive Sync Holding Register
  2189 + AT91_REG SSC_TSHR; // Transmit Sync Holding Register
  2190 + AT91_REG Reserved2[2]; //
  2191 + AT91_REG SSC_SR; // Status Register
  2192 + AT91_REG SSC_IER; // Interrupt Enable Register
  2193 + AT91_REG SSC_IDR; // Interrupt Disable Register
  2194 + AT91_REG SSC_IMR; // Interrupt Mask Register
  2195 + AT91_REG Reserved3[44]; //
  2196 + AT91_REG SSC_RPR; // Receive Pointer Register
  2197 + AT91_REG SSC_RCR; // Receive Counter Register
  2198 + AT91_REG SSC_TPR; // Transmit Pointer Register
  2199 + AT91_REG SSC_TCR; // Transmit Counter Register
  2200 + AT91_REG SSC_RNPR; // Receive Next Pointer Register
  2201 + AT91_REG SSC_RNCR; // Receive Next Counter Register
  2202 + AT91_REG SSC_TNPR; // Transmit Next Pointer Register
  2203 + AT91_REG SSC_TNCR; // Transmit Next Counter Register
  2204 + AT91_REG SSC_PTCR; // PDC Transfer Control Register
  2205 + AT91_REG SSC_PTSR; // PDC Transfer Status Register
  2206 +} AT91S_SSC, *AT91PS_SSC;
  2207 +#else
  2208 +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
  2209 +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
  2210 +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
  2211 +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
  2212 +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
  2213 +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
  2214 +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
  2215 +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
  2216 +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
  2217 +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
  2218 +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
  2219 +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
  2220 +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
  2221 +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
  2222 +
  2223 +#endif
  2224 +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
  2225 +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
  2226 +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
  2227 +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
  2228 +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
  2229 +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
  2230 +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
  2231 +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
  2232 +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
  2233 +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
  2234 +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
  2235 +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
  2236 +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
  2237 +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
  2238 +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
  2239 +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
  2240 +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
  2241 +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
  2242 +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
  2243 +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
  2244 +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
  2245 +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
  2246 +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
  2247 +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
  2248 +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
  2249 +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
  2250 +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
  2251 +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
  2252 +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
  2253 +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
  2254 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection
  2255 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
  2256 +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
  2257 +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
  2258 +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
  2259 +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
  2260 +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
  2261 +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
  2262 +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
  2263 +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
  2264 +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
  2265 +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
  2266 +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
  2267 +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
  2268 +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
  2269 +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
  2270 +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
  2271 +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
  2272 +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
  2273 +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
  2274 +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
  2275 +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
  2276 +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
  2277 +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
  2278 +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
  2279 +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
  2280 +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
  2281 +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
  2282 +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
  2283 +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
  2284 +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0
  2285 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1
  2286 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
  2287 +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
  2288 +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
  2289 +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
  2290 +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
  2291 +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
  2292 +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
  2293 +
  2294 +// *****************************************************************************
  2295 +// SOFTWARE API DEFINITION FOR AC97 Controller Interface
  2296 +// *****************************************************************************
  2297 +#ifndef __ASSEMBLY__
  2298 +typedef struct _AT91S_AC97C {
  2299 + AT91_REG Reserved0[2]; //
  2300 + AT91_REG AC97C_MR; // Mode Register
  2301 + AT91_REG Reserved1[1]; //
  2302 + AT91_REG AC97C_ICA; // Input Channel AssignementRegister
  2303 + AT91_REG AC97C_OCA; // Output Channel Assignement Register
  2304 + AT91_REG Reserved2[2]; //
  2305 + AT91_REG AC97C_CARHR; // Channel A Receive Holding Register
  2306 + AT91_REG AC97C_CATHR; // Channel A Transmit Holding Register
  2307 + AT91_REG AC97C_CASR; // Channel A Status Register
  2308 + AT91_REG AC97C_CAMR; // Channel A Mode Register
  2309 + AT91_REG AC97C_CBRHR; // Channel B Receive Holding Register (optional)
  2310 + AT91_REG AC97C_CBTHR; // Channel B Transmit Holding Register (optional)
  2311 + AT91_REG AC97C_CBSR; // Channel B Status Register
  2312 + AT91_REG AC97C_CBMR; // Channel B Mode Register
  2313 + AT91_REG AC97C_CORHR; // COdec Transmit Holding Register
  2314 + AT91_REG AC97C_COTHR; // COdec Transmit Holding Register
  2315 + AT91_REG AC97C_COSR; // CODEC Status Register
  2316 + AT91_REG AC97C_COMR; // CODEC Mask Status Register
  2317 + AT91_REG AC97C_SR; // Status Register
  2318 + AT91_REG AC97C_IER; // Interrupt Enable Register
  2319 + AT91_REG AC97C_IDR; // Interrupt Disable Register
  2320 + AT91_REG AC97C_IMR; // Interrupt Mask Register
  2321 + AT91_REG Reserved3[39]; //
  2322 + AT91_REG AC97C_VERSION; // Version Register
  2323 + AT91_REG AC97C_RPR; // Receive Pointer Register
  2324 + AT91_REG AC97C_RCR; // Receive Counter Register
  2325 + AT91_REG AC97C_TPR; // Transmit Pointer Register
  2326 + AT91_REG AC97C_TCR; // Transmit Counter Register
  2327 + AT91_REG AC97C_RNPR; // Receive Next Pointer Register
  2328 + AT91_REG AC97C_RNCR; // Receive Next Counter Register
  2329 + AT91_REG AC97C_TNPR; // Transmit Next Pointer Register
  2330 + AT91_REG AC97C_TNCR; // Transmit Next Counter Register
  2331 + AT91_REG AC97C_PTCR; // PDC Transfer Control Register
  2332 + AT91_REG AC97C_PTSR; // PDC Transfer Status Register
  2333 +} AT91S_AC97C, *AT91PS_AC97C;
  2334 +#else
  2335 +#define AC97C_MR (AT91_CAST(AT91_REG *) 0x00000008) // (AC97C_MR) Mode Register
  2336 +#define AC97C_ICA (AT91_CAST(AT91_REG *) 0x00000010) // (AC97C_ICA) Input Channel AssignementRegister
  2337 +#define AC97C_OCA (AT91_CAST(AT91_REG *) 0x00000014) // (AC97C_OCA) Output Channel Assignement Register
  2338 +#define AC97C_CARHR (AT91_CAST(AT91_REG *) 0x00000020) // (AC97C_CARHR) Channel A Receive Holding Register
  2339 +#define AC97C_CATHR (AT91_CAST(AT91_REG *) 0x00000024) // (AC97C_CATHR) Channel A Transmit Holding Register
  2340 +#define AC97C_CASR (AT91_CAST(AT91_REG *) 0x00000028) // (AC97C_CASR) Channel A Status Register
  2341 +#define AC97C_CAMR (AT91_CAST(AT91_REG *) 0x0000002C) // (AC97C_CAMR) Channel A Mode Register
  2342 +#define AC97C_CBRHR (AT91_CAST(AT91_REG *) 0x00000030) // (AC97C_CBRHR) Channel B Receive Holding Register (optional)
  2343 +#define AC97C_CBTHR (AT91_CAST(AT91_REG *) 0x00000034) // (AC97C_CBTHR) Channel B Transmit Holding Register (optional)
  2344 +#define AC97C_CBSR (AT91_CAST(AT91_REG *) 0x00000038) // (AC97C_CBSR) Channel B Status Register
  2345 +#define AC97C_CBMR (AT91_CAST(AT91_REG *) 0x0000003C) // (AC97C_CBMR) Channel B Mode Register
  2346 +#define AC97C_CORHR (AT91_CAST(AT91_REG *) 0x00000040) // (AC97C_CORHR) COdec Transmit Holding Register
  2347 +#define AC97C_COTHR (AT91_CAST(AT91_REG *) 0x00000044) // (AC97C_COTHR) COdec Transmit Holding Register
  2348 +#define AC97C_COSR (AT91_CAST(AT91_REG *) 0x00000048) // (AC97C_COSR) CODEC Status Register
  2349 +#define AC97C_COMR (AT91_CAST(AT91_REG *) 0x0000004C) // (AC97C_COMR) CODEC Mask Status Register
  2350 +#define AC97C_SR (AT91_CAST(AT91_REG *) 0x00000050) // (AC97C_SR) Status Register
  2351 +#define AC97C_IER (AT91_CAST(AT91_REG *) 0x00000054) // (AC97C_IER) Interrupt Enable Register
  2352 +#define AC97C_IDR (AT91_CAST(AT91_REG *) 0x00000058) // (AC97C_IDR) Interrupt Disable Register
  2353 +#define AC97C_IMR (AT91_CAST(AT91_REG *) 0x0000005C) // (AC97C_IMR) Interrupt Mask Register
  2354 +#define AC97C_VERSION (AT91_CAST(AT91_REG *) 0x000000FC) // (AC97C_VERSION) Version Register
  2355 +
  2356 +#endif
  2357 +// -------- AC97C_MR : (AC97C Offset: 0x8) AC97C Mode Register --------
  2358 +#define AT91C_AC97C_ENA (0x1 << 0) // (AC97C) AC97 Controller Global Enable
  2359 +#define AT91C_AC97C_WRST (0x1 << 1) // (AC97C) Warm Reset
  2360 +#define AT91C_AC97C_VRA (0x1 << 2) // (AC97C) Variable RAte (for Data Slots)
  2361 +// -------- AC97C_ICA : (AC97C Offset: 0x10) AC97C Input Channel Assignement Register --------
  2362 +#define AT91C_AC97C_CHID3 (0x7 << 0) // (AC97C) Channel Id for the input slot 3
  2363 +#define AT91C_AC97C_CHID3_NONE (0x0) // (AC97C) No data will be transmitted during this slot
  2364 +#define AT91C_AC97C_CHID3_CA (0x1) // (AC97C) Channel A data will be transmitted during this slot
  2365 +#define AT91C_AC97C_CHID3_CB (0x2) // (AC97C) Channel B data will be transmitted during this slot
  2366 +#define AT91C_AC97C_CHID3_CC (0x3) // (AC97C) Channel C data will be transmitted during this slot
  2367 +#define AT91C_AC97C_CHID4 (0x7 << 3) // (AC97C) Channel Id for the input slot 4
  2368 +#define AT91C_AC97C_CHID4_NONE (0x0 << 3) // (AC97C) No data will be transmitted during this slot
  2369 +#define AT91C_AC97C_CHID4_CA (0x1 << 3) // (AC97C) Channel A data will be transmitted during this slot
  2370 +#define AT91C_AC97C_CHID4_CB (0x2 << 3) // (AC97C) Channel B data will be transmitted during this slot
  2371 +#define AT91C_AC97C_CHID4_CC (0x3 << 3) // (AC97C) Channel C data will be transmitted during this slot
  2372 +#define AT91C_AC97C_CHID5 (0x7 << 6) // (AC97C) Channel Id for the input slot 5
  2373 +#define AT91C_AC97C_CHID5_NONE (0x0 << 6) // (AC97C) No data will be transmitted during this slot
  2374 +#define AT91C_AC97C_CHID5_CA (0x1 << 6) // (AC97C) Channel A data will be transmitted during this slot
  2375 +#define AT91C_AC97C_CHID5_CB (0x2 << 6) // (AC97C) Channel B data will be transmitted during this slot
  2376 +#define AT91C_AC97C_CHID5_CC (0x3 << 6) // (AC97C) Channel C data will be transmitted during this slot
  2377 +#define AT91C_AC97C_CHID6 (0x7 << 9) // (AC97C) Channel Id for the input slot 6
  2378 +#define AT91C_AC97C_CHID6_NONE (0x0 << 9) // (AC97C) No data will be transmitted during this slot
  2379 +#define AT91C_AC97C_CHID6_CA (0x1 << 9) // (AC97C) Channel A data will be transmitted during this slot
  2380 +#define AT91C_AC97C_CHID6_CB (0x2 << 9) // (AC97C) Channel B data will be transmitted during this slot
  2381 +#define AT91C_AC97C_CHID6_CC (0x3 << 9) // (AC97C) Channel C data will be transmitted during this slot
  2382 +#define AT91C_AC97C_CHID7 (0x7 << 12) // (AC97C) Channel Id for the input slot 7
  2383 +#define AT91C_AC97C_CHID7_NONE (0x0 << 12) // (AC97C) No data will be transmitted during this slot
  2384 +#define AT91C_AC97C_CHID7_CA (0x1 << 12) // (AC97C) Channel A data will be transmitted during this slot
  2385 +#define AT91C_AC97C_CHID7_CB (0x2 << 12) // (AC97C) Channel B data will be transmitted during this slot
  2386 +#define AT91C_AC97C_CHID7_CC (0x3 << 12) // (AC97C) Channel C data will be transmitted during this slot
  2387 +#define AT91C_AC97C_CHID8 (0x7 << 15) // (AC97C) Channel Id for the input slot 8
  2388 +#define AT91C_AC97C_CHID8_NONE (0x0 << 15) // (AC97C) No data will be transmitted during this slot
  2389 +#define AT91C_AC97C_CHID8_CA (0x1 << 15) // (AC97C) Channel A data will be transmitted during this slot
  2390 +#define AT91C_AC97C_CHID8_CB (0x2 << 15) // (AC97C) Channel B data will be transmitted during this slot
  2391 +#define AT91C_AC97C_CHID8_CC (0x3 << 15) // (AC97C) Channel C data will be transmitted during this slot
  2392 +#define AT91C_AC97C_CHID9 (0x7 << 18) // (AC97C) Channel Id for the input slot 9
  2393 +#define AT91C_AC97C_CHID9_NONE (0x0 << 18) // (AC97C) No data will be transmitted during this slot
  2394 +#define AT91C_AC97C_CHID9_CA (0x1 << 18) // (AC97C) Channel A data will be transmitted during this slot
  2395 +#define AT91C_AC97C_CHID9_CB (0x2 << 18) // (AC97C) Channel B data will be transmitted during this slot
  2396 +#define AT91C_AC97C_CHID9_CC (0x3 << 18) // (AC97C) Channel C data will be transmitted during this slot
  2397 +#define AT91C_AC97C_CHID10 (0x7 << 21) // (AC97C) Channel Id for the input slot 10
  2398 +#define AT91C_AC97C_CHID10_NONE (0x0 << 21) // (AC97C) No data will be transmitted during this slot
  2399 +#define AT91C_AC97C_CHID10_CA (0x1 << 21) // (AC97C) Channel A data will be transmitted during this slot
  2400 +#define AT91C_AC97C_CHID10_CB (0x2 << 21) // (AC97C) Channel B data will be transmitted during this slot
  2401 +#define AT91C_AC97C_CHID10_CC (0x3 << 21) // (AC97C) Channel C data will be transmitted during this slot
  2402 +#define AT91C_AC97C_CHID11 (0x7 << 24) // (AC97C) Channel Id for the input slot 11
  2403 +#define AT91C_AC97C_CHID11_NONE (0x0 << 24) // (AC97C) No data will be transmitted during this slot
  2404 +#define AT91C_AC97C_CHID11_CA (0x1 << 24) // (AC97C) Channel A data will be transmitted during this slot
  2405 +#define AT91C_AC97C_CHID11_CB (0x2 << 24) // (AC97C) Channel B data will be transmitted during this slot
  2406 +#define AT91C_AC97C_CHID11_CC (0x3 << 24) // (AC97C) Channel C data will be transmitted during this slot
  2407 +#define AT91C_AC97C_CHID12 (0x7 << 27) // (AC97C) Channel Id for the input slot 12
  2408 +#define AT91C_AC97C_CHID12_NONE (0x0 << 27) // (AC97C) No data will be transmitted during this slot
  2409 +#define AT91C_AC97C_CHID12_CA (0x1 << 27) // (AC97C) Channel A data will be transmitted during this slot
  2410 +#define AT91C_AC97C_CHID12_CB (0x2 << 27) // (AC97C) Channel B data will be transmitted during this slot
  2411 +#define AT91C_AC97C_CHID12_CC (0x3 << 27) // (AC97C) Channel C data will be transmitted during this slot
  2412 +// -------- AC97C_OCA : (AC97C Offset: 0x14) AC97C Output Channel Assignement Register --------
  2413 +// -------- AC97C_CARHR : (AC97C Offset: 0x20) AC97C Channel A Receive Holding Register --------
  2414 +#define AT91C_AC97C_RDATA (0xFFFFF << 0) // (AC97C) Receive data
  2415 +// -------- AC97C_CATHR : (AC97C Offset: 0x24) AC97C Channel A Transmit Holding Register --------
  2416 +#define AT91C_AC97C_TDATA (0xFFFFF << 0) // (AC97C) Transmit data
  2417 +// -------- AC97C_CASR : (AC97C Offset: 0x28) AC97C Channel A Status Register --------
  2418 +#define AT91C_AC97C_TXRDY (0x1 << 0) // (AC97C)
  2419 +#define AT91C_AC97C_TXEMPTY (0x1 << 1) // (AC97C)
  2420 +#define AT91C_AC97C_UNRUN (0x1 << 2) // (AC97C)
  2421 +#define AT91C_AC97C_RXRDY (0x1 << 4) // (AC97C)
  2422 +#define AT91C_AC97C_OVRUN (0x1 << 5) // (AC97C)
  2423 +#define AT91C_AC97C_ENDTX (0x1 << 10) // (AC97C)
  2424 +#define AT91C_AC97C_TXBUFE (0x1 << 11) // (AC97C)
  2425 +#define AT91C_AC97C_ENDRX (0x1 << 14) // (AC97C)
  2426 +#define AT91C_AC97C_RXBUFF (0x1 << 15) // (AC97C)
  2427 +// -------- AC97C_CAMR : (AC97C Offset: 0x2c) AC97C Channel A Mode Register --------
  2428 +#define AT91C_AC97C_SIZE (0x3 << 16) // (AC97C)
  2429 +#define AT91C_AC97C_SIZE_20_BITS (0x0 << 16) // (AC97C) Data size is 20 bits
  2430 +#define AT91C_AC97C_SIZE_18_BITS (0x1 << 16) // (AC97C) Data size is 18 bits
  2431 +#define AT91C_AC97C_SIZE_16_BITS (0x2 << 16) // (AC97C) Data size is 16 bits
  2432 +#define AT91C_AC97C_SIZE_10_BITS (0x3 << 16) // (AC97C) Data size is 10 bits
  2433 +#define AT91C_AC97C_CEM (0x1 << 18) // (AC97C)
  2434 +#define AT91C_AC97C_CEN (0x1 << 21) // (AC97C)
  2435 +#define AT91C_AC97C_PDCEN (0x1 << 22) // (AC97C)
  2436 +// -------- AC97C_CBRHR : (AC97C Offset: 0x30) AC97C Channel B Receive Holding Register --------
  2437 +// -------- AC97C_CBTHR : (AC97C Offset: 0x34) AC97C Channel B Transmit Holding Register --------
  2438 +// -------- AC97C_CBSR : (AC97C Offset: 0x38) AC97C Channel B Status Register --------
  2439 +// -------- AC97C_CBMR : (AC97C Offset: 0x3c) AC97C Channel B Mode Register --------
  2440 +// -------- AC97C_CORHR : (AC97C Offset: 0x40) AC97C Codec Channel Receive Holding Register --------
  2441 +#define AT91C_AC97C_SDATA (0xFFFF << 0) // (AC97C) Status Data
  2442 +// -------- AC97C_COTHR : (AC97C Offset: 0x44) AC97C Codec Channel Transmit Holding Register --------
  2443 +#define AT91C_AC97C_CDATA (0xFFFF << 0) // (AC97C) Command Data
  2444 +#define AT91C_AC97C_CADDR (0x7F << 16) // (AC97C) COdec control register index
  2445 +#define AT91C_AC97C_READ (0x1 << 23) // (AC97C) Read/Write command
  2446 +// -------- AC97C_COSR : (AC97C Offset: 0x48) AC97C CODEC Status Register --------
  2447 +// -------- AC97C_COMR : (AC97C Offset: 0x4c) AC97C CODEC Mode Register --------
  2448 +// -------- AC97C_SR : (AC97C Offset: 0x50) AC97C Status Register --------
  2449 +#define AT91C_AC97C_SOF (0x1 << 0) // (AC97C)
  2450 +#define AT91C_AC97C_WKUP (0x1 << 1) // (AC97C)
  2451 +#define AT91C_AC97C_COEVT (0x1 << 2) // (AC97C)
  2452 +#define AT91C_AC97C_CAEVT (0x1 << 3) // (AC97C)
  2453 +#define AT91C_AC97C_CBEVT (0x1 << 4) // (AC97C)
  2454 +// -------- AC97C_IER : (AC97C Offset: 0x54) AC97C Interrupt Enable Register --------
  2455 +// -------- AC97C_IDR : (AC97C Offset: 0x58) AC97C Interrupt Disable Register --------
  2456 +// -------- AC97C_IMR : (AC97C Offset: 0x5c) AC97C Interrupt Mask Register --------
  2457 +
  2458 +// *****************************************************************************
  2459 +// SOFTWARE API DEFINITION FOR Serial Parallel Interface
  2460 +// *****************************************************************************
  2461 +#ifndef __ASSEMBLY__
  2462 +typedef struct _AT91S_SPI {
  2463 + AT91_REG SPI_CR; // Control Register
  2464 + AT91_REG SPI_MR; // Mode Register
  2465 + AT91_REG SPI_RDR; // Receive Data Register
  2466 + AT91_REG SPI_TDR; // Transmit Data Register
  2467 + AT91_REG SPI_SR; // Status Register
  2468 + AT91_REG SPI_IER; // Interrupt Enable Register
  2469 + AT91_REG SPI_IDR; // Interrupt Disable Register
  2470 + AT91_REG SPI_IMR; // Interrupt Mask Register
  2471 + AT91_REG Reserved0[4]; //
  2472 + AT91_REG SPI_CSR[4]; // Chip Select Register
  2473 + AT91_REG Reserved1[48]; //
  2474 + AT91_REG SPI_RPR; // Receive Pointer Register
  2475 + AT91_REG SPI_RCR; // Receive Counter Register
  2476 + AT91_REG SPI_TPR; // Transmit Pointer Register
  2477 + AT91_REG SPI_TCR; // Transmit Counter Register
  2478 + AT91_REG SPI_RNPR; // Receive Next Pointer Register
  2479 + AT91_REG SPI_RNCR; // Receive Next Counter Register
  2480 + AT91_REG SPI_TNPR; // Transmit Next Pointer Register
  2481 + AT91_REG SPI_TNCR; // Transmit Next Counter Register
  2482 + AT91_REG SPI_PTCR; // PDC Transfer Control Register
  2483 + AT91_REG SPI_PTSR; // PDC Transfer Status Register
  2484 +} AT91S_SPI, *AT91PS_SPI;
  2485 +#else
  2486 +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
  2487 +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
  2488 +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
  2489 +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
  2490 +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
  2491 +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
  2492 +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
  2493 +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
  2494 +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
  2495 +
  2496 +#endif
  2497 +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
  2498 +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
  2499 +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
  2500 +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
  2501 +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
  2502 +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
  2503 +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
  2504 +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
  2505 +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
  2506 +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
  2507 +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
  2508 +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
  2509 +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
  2510 +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
  2511 +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
  2512 +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
  2513 +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
  2514 +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
  2515 +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
  2516 +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
  2517 +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
  2518 +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
  2519 +// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
  2520 +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
  2521 +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
  2522 +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
  2523 +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
  2524 +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
  2525 +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
  2526 +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
  2527 +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
  2528 +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
  2529 +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
  2530 +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
  2531 +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
  2532 +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
  2533 +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
  2534 +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
  2535 +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
  2536 +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
  2537 +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
  2538 +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
  2539 +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
  2540 +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
  2541 +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
  2542 +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
  2543 +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
  2544 +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
  2545 +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
  2546 +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
  2547 +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
  2548 +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
  2549 +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
  2550 +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
  2551 +
  2552 +// *****************************************************************************
  2553 +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
  2554 +// *****************************************************************************
  2555 +#ifndef __ASSEMBLY__
  2556 +typedef struct _AT91S_CAN_MB {
  2557 + AT91_REG CAN_MB_MMR; // MailBox Mode Register
  2558 + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
  2559 + AT91_REG CAN_MB_MID; // MailBox ID Register
  2560 + AT91_REG CAN_MB_MFID; // MailBox Family ID Register
  2561 + AT91_REG CAN_MB_MSR; // MailBox Status Register
  2562 + AT91_REG CAN_MB_MDL; // MailBox Data Low Register
  2563 + AT91_REG CAN_MB_MDH; // MailBox Data High Register
  2564 + AT91_REG CAN_MB_MCR; // MailBox Control Register
  2565 +} AT91S_CAN_MB, *AT91PS_CAN_MB;
  2566 +#else
  2567 +#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register
  2568 +#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register
  2569 +#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register
  2570 +#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register
  2571 +#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register
  2572 +#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register
  2573 +#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register
  2574 +#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register
  2575 +
  2576 +#endif
  2577 +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
  2578 +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
  2579 +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
  2580 +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
  2581 +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
  2582 +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
  2583 +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
  2584 +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
  2585 +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
  2586 +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
  2587 +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
  2588 +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
  2589 +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
  2590 +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
  2591 +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
  2592 +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
  2593 +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
  2594 +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
  2595 +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
  2596 +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
  2597 +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
  2598 +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
  2599 +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
  2600 +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
  2601 +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
  2602 +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
  2603 +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
  2604 +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
  2605 +
  2606 +// *****************************************************************************
  2607 +// SOFTWARE API DEFINITION FOR Control Area Network Interface
  2608 +// *****************************************************************************
  2609 +#ifndef __ASSEMBLY__
  2610 +typedef struct _AT91S_CAN {
  2611 + AT91_REG CAN_MR; // Mode Register
  2612 + AT91_REG CAN_IER; // Interrupt Enable Register
  2613 + AT91_REG CAN_IDR; // Interrupt Disable Register
  2614 + AT91_REG CAN_IMR; // Interrupt Mask Register
  2615 + AT91_REG CAN_SR; // Status Register
  2616 + AT91_REG CAN_BR; // Baudrate Register
  2617 + AT91_REG CAN_TIM; // Timer Register
  2618 + AT91_REG CAN_TIMESTP; // Time Stamp Register
  2619 + AT91_REG CAN_ECR; // Error Counter Register
  2620 + AT91_REG CAN_TCR; // Transfer Command Register
  2621 + AT91_REG CAN_ACR; // Abort Command Register
  2622 + AT91_REG Reserved0[52]; //
  2623 + AT91_REG CAN_VR; // Version Register
  2624 + AT91_REG Reserved1[64]; //
  2625 + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
  2626 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
  2627 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
  2628 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
  2629 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
  2630 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
  2631 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
  2632 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
  2633 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
  2634 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
  2635 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
  2636 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
  2637 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
  2638 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
  2639 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
  2640 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
  2641 +} AT91S_CAN, *AT91PS_CAN;
  2642 +#else
  2643 +#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register
  2644 +#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register
  2645 +#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register
  2646 +#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register
  2647 +#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register
  2648 +#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register
  2649 +#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register
  2650 +#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register
  2651 +#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register
  2652 +#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register
  2653 +#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register
  2654 +#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register
  2655 +
  2656 +#endif
  2657 +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
  2658 +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
  2659 +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
  2660 +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
  2661 +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
  2662 +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
  2663 +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
  2664 +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
  2665 +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
  2666 +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
  2667 +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
  2668 +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
  2669 +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
  2670 +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
  2671 +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
  2672 +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
  2673 +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
  2674 +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
  2675 +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
  2676 +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
  2677 +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
  2678 +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
  2679 +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
  2680 +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
  2681 +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
  2682 +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
  2683 +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
  2684 +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
  2685 +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
  2686 +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
  2687 +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
  2688 +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
  2689 +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
  2690 +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
  2691 +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
  2692 +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
  2693 +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
  2694 +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
  2695 +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
  2696 +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
  2697 +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
  2698 +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
  2699 +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
  2700 +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
  2701 +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
  2702 +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
  2703 +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
  2704 +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
  2705 +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
  2706 +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
  2707 +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
  2708 +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
  2709 +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
  2710 +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
  2711 +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
  2712 +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
  2713 +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
  2714 +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
  2715 +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
  2716 +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
  2717 +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
  2718 +
  2719 +// *****************************************************************************
  2720 +// SOFTWARE API DEFINITION FOR PWMC Channel Interface
  2721 +// *****************************************************************************
  2722 +#ifndef __ASSEMBLY__
  2723 +typedef struct _AT91S_PWMC_CH {
  2724 + AT91_REG PWMC_CMR; // Channel Mode Register
  2725 + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
  2726 + AT91_REG PWMC_CPRDR; // Channel Period Register
  2727 + AT91_REG PWMC_CCNTR; // Channel Counter Register
  2728 + AT91_REG PWMC_CUPDR; // Channel Update Register
  2729 + AT91_REG PWMC_Reserved[3]; // Reserved
  2730 +} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
  2731 +#else
  2732 +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register
  2733 +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
  2734 +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register
  2735 +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register
  2736 +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register
  2737 +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved
  2738 +
  2739 +#endif
  2740 +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
  2741 +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
  2742 +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
  2743 +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
  2744 +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
  2745 +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
  2746 +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
  2747 +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
  2748 +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
  2749 +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
  2750 +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
  2751 +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
  2752 +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
  2753 +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
  2754 +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
  2755 +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
  2756 +
  2757 +// *****************************************************************************
  2758 +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
  2759 +// *****************************************************************************
  2760 +#ifndef __ASSEMBLY__
  2761 +typedef struct _AT91S_PWMC {
  2762 + AT91_REG PWMC_MR; // PWMC Mode Register
  2763 + AT91_REG PWMC_ENA; // PWMC Enable Register
  2764 + AT91_REG PWMC_DIS; // PWMC Disable Register
  2765 + AT91_REG PWMC_SR; // PWMC Status Register
  2766 + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
  2767 + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
  2768 + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
  2769 + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
  2770 + AT91_REG Reserved0[55]; //
  2771 + AT91_REG PWMC_VR; // PWMC Version Register
  2772 + AT91_REG Reserved1[64]; //
  2773 + AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel
  2774 +} AT91S_PWMC, *AT91PS_PWMC;
  2775 +#else
  2776 +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register
  2777 +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register
  2778 +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register
  2779 +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register
  2780 +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
  2781 +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
  2782 +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
  2783 +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
  2784 +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register
  2785 +
  2786 +#endif
  2787 +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
  2788 +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
  2789 +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
  2790 +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
  2791 +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
  2792 +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
  2793 +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
  2794 +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
  2795 +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
  2796 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
  2797 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
  2798 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
  2799 +#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4
  2800 +#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5
  2801 +#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6
  2802 +#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7
  2803 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
  2804 +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
  2805 +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
  2806 +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
  2807 +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
  2808 +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
  2809 +
  2810 +// *****************************************************************************
  2811 +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
  2812 +// *****************************************************************************
  2813 +#ifndef __ASSEMBLY__
  2814 +typedef struct _AT91S_EMAC {
  2815 + AT91_REG EMAC_NCR; // Network Control Register
  2816 + AT91_REG EMAC_NCFGR; // Network Configuration Register
  2817 + AT91_REG EMAC_NSR; // Network Status Register
  2818 + AT91_REG Reserved0[2]; //
  2819 + AT91_REG EMAC_TSR; // Transmit Status Register
  2820 + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
  2821 + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
  2822 + AT91_REG EMAC_RSR; // Receive Status Register
  2823 + AT91_REG EMAC_ISR; // Interrupt Status Register
  2824 + AT91_REG EMAC_IER; // Interrupt Enable Register
  2825 + AT91_REG EMAC_IDR; // Interrupt Disable Register
  2826 + AT91_REG EMAC_IMR; // Interrupt Mask Register
  2827 + AT91_REG EMAC_MAN; // PHY Maintenance Register
  2828 + AT91_REG EMAC_PTR; // Pause Time Register
  2829 + AT91_REG EMAC_PFR; // Pause Frames received Register
  2830 + AT91_REG EMAC_FTO; // Frames Transmitted OK Register
  2831 + AT91_REG EMAC_SCF; // Single Collision Frame Register
  2832 + AT91_REG EMAC_MCF; // Multiple Collision Frame Register
  2833 + AT91_REG EMAC_FRO; // Frames Received OK Register
  2834 + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
  2835 + AT91_REG EMAC_ALE; // Alignment Error Register
  2836 + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
  2837 + AT91_REG EMAC_LCOL; // Late Collision Register
  2838 + AT91_REG EMAC_ECOL; // Excessive Collision Register
  2839 + AT91_REG EMAC_TUND; // Transmit Underrun Error Register
  2840 + AT91_REG EMAC_CSE; // Carrier Sense Error Register
  2841 + AT91_REG EMAC_RRE; // Receive Ressource Error Register
  2842 + AT91_REG EMAC_ROV; // Receive Overrun Errors Register
  2843 + AT91_REG EMAC_RSE; // Receive Symbol Errors Register
  2844 + AT91_REG EMAC_ELE; // Excessive Length Errors Register
  2845 + AT91_REG EMAC_RJA; // Receive Jabbers Register
  2846 + AT91_REG EMAC_USF; // Undersize Frames Register
  2847 + AT91_REG EMAC_STE; // SQE Test Error Register
  2848 + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
  2849 + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
  2850 + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
  2851 + AT91_REG EMAC_HRT; // Hash Address Top[63:32]
  2852 + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
  2853 + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
  2854 + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
  2855 + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
  2856 + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
  2857 + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
  2858 + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
  2859 + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
  2860 + AT91_REG EMAC_TID; // Type ID Checking Register
  2861 + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
  2862 + AT91_REG EMAC_USRIO; // USER Input/Output Register
  2863 + AT91_REG EMAC_WOL; // Wake On LAN Register
  2864 + AT91_REG Reserved1[13]; //
  2865 + AT91_REG EMAC_REV; // Revision Register
  2866 +} AT91S_EMAC, *AT91PS_EMAC;
  2867 +#else
  2868 +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register
  2869 +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register
  2870 +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register
  2871 +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register
  2872 +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
  2873 +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
  2874 +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register
  2875 +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register
  2876 +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register
  2877 +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register
  2878 +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register
  2879 +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register
  2880 +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register
  2881 +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register
  2882 +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
  2883 +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register
  2884 +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
  2885 +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register
  2886 +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
  2887 +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register
  2888 +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
  2889 +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register
  2890 +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register
  2891 +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
  2892 +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register
  2893 +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
  2894 +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
  2895 +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
  2896 +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register
  2897 +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register
  2898 +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register
  2899 +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register
  2900 +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
  2901 +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
  2902 +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
  2903 +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
  2904 +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
  2905 +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
  2906 +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
  2907 +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
  2908 +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
  2909 +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
  2910 +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
  2911 +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
  2912 +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register
  2913 +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
  2914 +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register
  2915 +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register
  2916 +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register
  2917 +
  2918 +#endif
  2919 +// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
  2920 +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
  2921 +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
  2922 +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
  2923 +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
  2924 +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
  2925 +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
  2926 +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
  2927 +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
  2928 +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
  2929 +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
  2930 +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
  2931 +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
  2932 +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
  2933 +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
  2934 +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
  2935 +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
  2936 +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
  2937 +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
  2938 +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
  2939 +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
  2940 +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
  2941 +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
  2942 +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
  2943 +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
  2944 +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
  2945 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
  2946 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
  2947 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
  2948 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
  2949 +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
  2950 +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
  2951 +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
  2952 +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
  2953 +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
  2954 +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
  2955 +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
  2956 +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
  2957 +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
  2958 +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
  2959 +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
  2960 +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
  2961 +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
  2962 +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
  2963 +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
  2964 +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
  2965 +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
  2966 +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
  2967 +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
  2968 +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
  2969 +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
  2970 +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
  2971 +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
  2972 +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
  2973 +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
  2974 +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
  2975 +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
  2976 +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
  2977 +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
  2978 +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
  2979 +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
  2980 +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
  2981 +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
  2982 +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
  2983 +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
  2984 +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
  2985 +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
  2986 +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
  2987 +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
  2988 +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
  2989 +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
  2990 +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
  2991 +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
  2992 +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
  2993 +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
  2994 +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
  2995 +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
  2996 +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
  2997 +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
  2998 +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
  2999 +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
  3000 +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
  3001 +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable
  3002 +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
  3003 +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
  3004 +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
  3005 +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
  3006 +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
  3007 +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
  3008 +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
  3009 +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
  3010 +
  3011 +// *****************************************************************************
  3012 +// SOFTWARE API DEFINITION FOR LCD Controller
  3013 +// *****************************************************************************
  3014 +#ifndef __ASSEMBLY__
  3015 +typedef struct _AT91S_LCDC {
  3016 + AT91_REG LCDC_BA1; // DMA Base Address Register 1
  3017 + AT91_REG LCDC_BA2; // DMA Base Address Register 2
  3018 + AT91_REG LCDC_FRMP1; // DMA Frame Pointer Register 1
  3019 + AT91_REG LCDC_FRMP2; // DMA Frame Pointer Register 2
  3020 + AT91_REG LCDC_FRMA1; // DMA Frame Address Register 1
  3021 + AT91_REG LCDC_FRMA2; // DMA Frame Address Register 2
  3022 + AT91_REG LCDC_FRMCFG; // DMA Frame Configuration Register
  3023 + AT91_REG LCDC_DMACON; // DMA Control Register
  3024 + AT91_REG LCDC_DMA2DCFG; // DMA 2D addressing configuration
  3025 + AT91_REG Reserved0[503]; //
  3026 + AT91_REG LCDC_LCDCON1; // LCD Control 1 Register
  3027 + AT91_REG LCDC_LCDCON2; // LCD Control 2 Register
  3028 + AT91_REG LCDC_TIM1; // LCD Timing Config 1 Register
  3029 + AT91_REG LCDC_TIM2; // LCD Timing Config 2 Register
  3030 + AT91_REG LCDC_LCDFRCFG; // LCD Frame Config Register
  3031 + AT91_REG LCDC_FIFO; // LCD FIFO Register
  3032 + AT91_REG LCDC_MVAL; // LCD Mode Toggle Rate Value Register
  3033 + AT91_REG LCDC_DP1_2; // Dithering Pattern DP1_2 Register
  3034 + AT91_REG LCDC_DP4_7; // Dithering Pattern DP4_7 Register
  3035 + AT91_REG LCDC_DP3_5; // Dithering Pattern DP3_5 Register
  3036 + AT91_REG LCDC_DP2_3; // Dithering Pattern DP2_3 Register
  3037 + AT91_REG LCDC_DP5_7; // Dithering Pattern DP5_7 Register
  3038 + AT91_REG LCDC_DP3_4; // Dithering Pattern DP3_4 Register
  3039 + AT91_REG LCDC_DP4_5; // Dithering Pattern DP4_5 Register
  3040 + AT91_REG LCDC_DP6_7; // Dithering Pattern DP6_7 Register
  3041 + AT91_REG LCDC_PWRCON; // Power Control Register
  3042 + AT91_REG LCDC_CTRSTCON; // Contrast Control Register
  3043 + AT91_REG LCDC_CTRSTVAL; // Contrast Value Register
  3044 + AT91_REG LCDC_IER; // Interrupt Enable Register
  3045 + AT91_REG LCDC_IDR; // Interrupt Disable Register
  3046 + AT91_REG LCDC_IMR; // Interrupt Mask Register
  3047 + AT91_REG LCDC_ISR; // Interrupt Enable Register
  3048 + AT91_REG LCDC_ICR; // Interrupt Clear Register
  3049 + AT91_REG LCDC_GPR; // General Purpose Register
  3050 + AT91_REG LCDC_ITR; // Interrupts Test Register
  3051 + AT91_REG LCDC_IRR; // Interrupts Raw Status Register
  3052 + AT91_REG Reserved1[230]; //
  3053 + AT91_REG LCDC_LUT_ENTRY[256]; // LUT Entries Register
  3054 +} AT91S_LCDC, *AT91PS_LCDC;
  3055 +#else
  3056 +#define LCDC_BA1 (AT91_CAST(AT91_REG *) 0x00000000) // (LCDC_BA1) DMA Base Address Register 1
  3057 +#define LCDC_BA2 (AT91_CAST(AT91_REG *) 0x00000004) // (LCDC_BA2) DMA Base Address Register 2
  3058 +#define LCDC_FRMP1 (AT91_CAST(AT91_REG *) 0x00000008) // (LCDC_FRMP1) DMA Frame Pointer Register 1
  3059 +#define LCDC_FRMP2 (AT91_CAST(AT91_REG *) 0x0000000C) // (LCDC_FRMP2) DMA Frame Pointer Register 2
  3060 +#define LCDC_FRMA1 (AT91_CAST(AT91_REG *) 0x00000010) // (LCDC_FRMA1) DMA Frame Address Register 1
  3061 +#define LCDC_FRMA2 (AT91_CAST(AT91_REG *) 0x00000014) // (LCDC_FRMA2) DMA Frame Address Register 2
  3062 +#define LCDC_FRMCFG (AT91_CAST(AT91_REG *) 0x00000018) // (LCDC_FRMCFG) DMA Frame Configuration Register
  3063 +#define LCDC_DMACON (AT91_CAST(AT91_REG *) 0x0000001C) // (LCDC_DMACON) DMA Control Register
  3064 +#define LCDC_DMA2DCFG (AT91_CAST(AT91_REG *) 0x00000020) // (LCDC_DMA2DCFG) DMA 2D addressing configuration
  3065 +#define LCDC_LCDCON1 (AT91_CAST(AT91_REG *) 0x00000800) // (LCDC_LCDCON1) LCD Control 1 Register
  3066 +#define LCDC_LCDCON2 (AT91_CAST(AT91_REG *) 0x00000804) // (LCDC_LCDCON2) LCD Control 2 Register
  3067 +#define LCDC_TIM1 (AT91_CAST(AT91_REG *) 0x00000808) // (LCDC_TIM1) LCD Timing Config 1 Register
  3068 +#define LCDC_TIM2 (AT91_CAST(AT91_REG *) 0x0000080C) // (LCDC_TIM2) LCD Timing Config 2 Register
  3069 +#define LCDC_LCDFRCFG (AT91_CAST(AT91_REG *) 0x00000810) // (LCDC_LCDFRCFG) LCD Frame Config Register
  3070 +#define LCDC_FIFO (AT91_CAST(AT91_REG *) 0x00000814) // (LCDC_FIFO) LCD FIFO Register
  3071 +#define LCDC_MVAL (AT91_CAST(AT91_REG *) 0x00000818) // (LCDC_MVAL) LCD Mode Toggle Rate Value Register
  3072 +#define LCDC_DP1_2 (AT91_CAST(AT91_REG *) 0x0000081C) // (LCDC_DP1_2) Dithering Pattern DP1_2 Register
  3073 +#define LCDC_DP4_7 (AT91_CAST(AT91_REG *) 0x00000820) // (LCDC_DP4_7) Dithering Pattern DP4_7 Register
  3074 +#define LCDC_DP3_5 (AT91_CAST(AT91_REG *) 0x00000824) // (LCDC_DP3_5) Dithering Pattern DP3_5 Register
  3075 +#define LCDC_DP2_3 (AT91_CAST(AT91_REG *) 0x00000828) // (LCDC_DP2_3) Dithering Pattern DP2_3 Register
  3076 +#define LCDC_DP5_7 (AT91_CAST(AT91_REG *) 0x0000082C) // (LCDC_DP5_7) Dithering Pattern DP5_7 Register
  3077 +#define LCDC_DP3_4 (AT91_CAST(AT91_REG *) 0x00000830) // (LCDC_DP3_4) Dithering Pattern DP3_4 Register
  3078 +#define LCDC_DP4_5 (AT91_CAST(AT91_REG *) 0x00000834) // (LCDC_DP4_5) Dithering Pattern DP4_5 Register
  3079 +#define LCDC_DP6_7 (AT91_CAST(AT91_REG *) 0x00000838) // (LCDC_DP6_7) Dithering Pattern DP6_7 Register
  3080 +#define LCDC_PWRCON (AT91_CAST(AT91_REG *) 0x0000083C) // (LCDC_PWRCON) Power Control Register
  3081 +#define LCDC_CTRSTCON (AT91_CAST(AT91_REG *) 0x00000840) // (LCDC_CTRSTCON) Contrast Control Register
  3082 +#define LCDC_CTRSTVAL (AT91_CAST(AT91_REG *) 0x00000844) // (LCDC_CTRSTVAL) Contrast Value Register
  3083 +#define LCDC_IER (AT91_CAST(AT91_REG *) 0x00000848) // (LCDC_IER) Interrupt Enable Register
  3084 +#define LCDC_IDR (AT91_CAST(AT91_REG *) 0x0000084C) // (LCDC_IDR) Interrupt Disable Register
  3085 +#define LCDC_IMR (AT91_CAST(AT91_REG *) 0x00000850) // (LCDC_IMR) Interrupt Mask Register
  3086 +#define LCDC_ISR (AT91_CAST(AT91_REG *) 0x00000854) // (LCDC_ISR) Interrupt Enable Register
  3087 +#define LCDC_ICR (AT91_CAST(AT91_REG *) 0x00000858) // (LCDC_ICR) Interrupt Clear Register
  3088 +#define LCDC_GPR (AT91_CAST(AT91_REG *) 0x0000085C) // (LCDC_GPR) General Purpose Register
  3089 +#define LCDC_ITR (AT91_CAST(AT91_REG *) 0x00000860) // (LCDC_ITR) Interrupts Test Register
  3090 +#define LCDC_IRR (AT91_CAST(AT91_REG *) 0x00000864) // (LCDC_IRR) Interrupts Raw Status Register
  3091 +#define LCDC_LUT_ENTRY (AT91_CAST(AT91_REG *) 0x00000C00) // (LCDC_LUT_ENTRY) LUT Entries Register
  3092 +
  3093 +#endif
  3094 +// -------- LCDC_FRMP1 : (LCDC Offset: 0x8) DMA Frame Pointer 1 Register --------
  3095 +#define AT91C_LCDC_FRMPT1 (0x3FFFFF << 0) // (LCDC) Frame Pointer Address 1
  3096 +// -------- LCDC_FRMP2 : (LCDC Offset: 0xc) DMA Frame Pointer 2 Register --------
  3097 +#define AT91C_LCDC_FRMPT2 (0x1FFFFF << 0) // (LCDC) Frame Pointer Address 2
  3098 +// -------- LCDC_FRMCFG : (LCDC Offset: 0x18) DMA Frame Config Register --------
  3099 +#define AT91C_LCDC_FRSIZE (0x3FFFFF << 0) // (LCDC) FRAME SIZE
  3100 +#define AT91C_LCDC_BLENGTH (0xF << 24) // (LCDC) BURST LENGTH
  3101 +// -------- LCDC_DMACON : (LCDC Offset: 0x1c) DMA Control Register --------
  3102 +#define AT91C_LCDC_DMAEN (0x1 << 0) // (LCDC) DAM Enable
  3103 +#define AT91C_LCDC_DMARST (0x1 << 1) // (LCDC) DMA Reset (WO)
  3104 +#define AT91C_LCDC_DMABUSY (0x1 << 2) // (LCDC) DMA Reset (WO)
  3105 +#define AT91C_LCDC_DMAUPDT (0x1 << 3) // (LCDC) DMA Configuration Update
  3106 +#define AT91C_LCDC_DMA2DEN (0x1 << 4) // (LCDC) 2D Addressing Enable
  3107 +// -------- LCDC_DMA2DCFG : (LCDC Offset: 0x20) DMA 2D addressing configuration Register --------
  3108 +#define AT91C_LCDC_ADDRINC (0xFFFF << 0) // (LCDC) Number of 32b words that the DMA must jump when going to the next line
  3109 +#define AT91C_LCDC_PIXELOFF (0x1F << 24) // (LCDC) Offset (in bits) of the first pixel of the screen in the memory word which contain it
  3110 +// -------- LCDC_LCDCON1 : (LCDC Offset: 0x800) LCD Control 1 Register --------
  3111 +#define AT91C_LCDC_BYPASS (0x1 << 0) // (LCDC) Bypass lcd_pccklk divider
  3112 +#define AT91C_LCDC_CLKVAL (0x1FF << 12) // (LCDC) 9-bit Divider for pixel clock frequency
  3113 +#define AT91C_LCDC_LINCNT (0x7FF << 21) // (LCDC) Line Counter (RO)
  3114 +// -------- LCDC_LCDCON2 : (LCDC Offset: 0x804) LCD Control 2 Register --------
  3115 +#define AT91C_LCDC_DISTYPE (0x3 << 0) // (LCDC) Display Type
  3116 +#define AT91C_LCDC_DISTYPE_STNMONO (0x0) // (LCDC) STN Mono
  3117 +#define AT91C_LCDC_DISTYPE_STNCOLOR (0x1) // (LCDC) STN Color
  3118 +#define AT91C_LCDC_DISTYPE_TFT (0x2) // (LCDC) TFT
  3119 +#define AT91C_LCDC_SCANMOD (0x1 << 2) // (LCDC) Scan Mode
  3120 +#define AT91C_LCDC_SCANMOD_SINGLESCAN (0x0 << 2) // (LCDC) Single Scan
  3121 +#define AT91C_LCDC_SCANMOD_DUALSCAN (0x1 << 2) // (LCDC) Dual Scan
  3122 +#define AT91C_LCDC_IFWIDTH (0x3 << 3) // (LCDC) Interface Width
  3123 +#define AT91C_LCDC_IFWIDTH_FOURBITSWIDTH (0x0 << 3) // (LCDC) 4 Bits
  3124 +#define AT91C_LCDC_IFWIDTH_EIGTHBITSWIDTH (0x1 << 3) // (LCDC) 8 Bits
  3125 +#define AT91C_LCDC_IFWIDTH_SIXTEENBITSWIDTH (0x2 << 3) // (LCDC) 16 Bits
  3126 +#define AT91C_LCDC_PIXELSIZE (0x7 << 5) // (LCDC) Bits per pixel
  3127 +#define AT91C_LCDC_PIXELSIZE_ONEBITSPERPIXEL (0x0 << 5) // (LCDC) 1 Bits
  3128 +#define AT91C_LCDC_PIXELSIZE_TWOBITSPERPIXEL (0x1 << 5) // (LCDC) 2 Bits
  3129 +#define AT91C_LCDC_PIXELSIZE_FOURBITSPERPIXEL (0x2 << 5) // (LCDC) 4 Bits
  3130 +#define AT91C_LCDC_PIXELSIZE_EIGTHBITSPERPIXEL (0x3 << 5) // (LCDC) 8 Bits
  3131 +#define AT91C_LCDC_PIXELSIZE_SIXTEENBITSPERPIXEL (0x4 << 5) // (LCDC) 16 Bits
  3132 +#define AT91C_LCDC_PIXELSIZE_TWENTYFOURBITSPERPIXEL (0x5 << 5) // (LCDC) 24 Bits
  3133 +#define AT91C_LCDC_INVVD (0x1 << 8) // (LCDC) lcd datas polarity
  3134 +#define AT91C_LCDC_INVVD_NORMALPOL (0x0 << 8) // (LCDC) Normal Polarity
  3135 +#define AT91C_LCDC_INVVD_INVERTEDPOL (0x1 << 8) // (LCDC) Inverted Polarity
  3136 +#define AT91C_LCDC_INVFRAME (0x1 << 9) // (LCDC) lcd vsync polarity
  3137 +#define AT91C_LCDC_INVFRAME_NORMALPOL (0x0 << 9) // (LCDC) Normal Polarity
  3138 +#define AT91C_LCDC_INVFRAME_INVERTEDPOL (0x1 << 9) // (LCDC) Inverted Polarity
  3139 +#define AT91C_LCDC_INVLINE (0x1 << 10) // (LCDC) lcd hsync polarity
  3140 +#define AT91C_LCDC_INVLINE_NORMALPOL (0x0 << 10) // (LCDC) Normal Polarity
  3141 +#define AT91C_LCDC_INVLINE_INVERTEDPOL (0x1 << 10) // (LCDC) Inverted Polarity
  3142 +#define AT91C_LCDC_INVCLK (0x1 << 11) // (LCDC) lcd pclk polarity
  3143 +#define AT91C_LCDC_INVCLK_NORMALPOL (0x0 << 11) // (LCDC) Normal Polarity
  3144 +#define AT91C_LCDC_INVCLK_INVERTEDPOL (0x1 << 11) // (LCDC) Inverted Polarity
  3145 +#define AT91C_LCDC_INVDVAL (0x1 << 12) // (LCDC) lcd dval polarity
  3146 +#define AT91C_LCDC_INVDVAL_NORMALPOL (0x0 << 12) // (LCDC) Normal Polarity
  3147 +#define AT91C_LCDC_INVDVAL_INVERTEDPOL (0x1 << 12) // (LCDC) Inverted Polarity
  3148 +#define AT91C_LCDC_CLKMOD (0x1 << 15) // (LCDC) lcd pclk Mode
  3149 +#define AT91C_LCDC_CLKMOD_ACTIVEONLYDISP (0x0 << 15) // (LCDC) Active during display period
  3150 +#define AT91C_LCDC_CLKMOD_ALWAYSACTIVE (0x1 << 15) // (LCDC) Always Active
  3151 +#define AT91C_LCDC_MEMOR (0x1 << 31) // (LCDC) lcd pclk Mode
  3152 +#define AT91C_LCDC_MEMOR_BIGIND (0x0 << 31) // (LCDC) Big Endian
  3153 +#define AT91C_LCDC_MEMOR_LITTLEIND (0x1 << 31) // (LCDC) Little Endian
  3154 +// -------- LCDC_TIM1 : (LCDC Offset: 0x808) LCDC Timing Config 1 Register --------
  3155 +#define AT91C_LCDC_VFP (0xFF << 0) // (LCDC) Vertical Front Porch
  3156 +#define AT91C_LCDC_VBP (0xFF << 8) // (LCDC) Vertical Back Porch
  3157 +#define AT91C_LCDC_VPW (0x3F << 16) // (LCDC) Vertical Synchronization Pulse Width
  3158 +#define AT91C_LCDC_VHDLY (0xF << 24) // (LCDC) Vertical to Horizontal Delay
  3159 +// -------- LCDC_TIM2 : (LCDC Offset: 0x80c) LCDC Timing Config 2 Register --------
  3160 +#define AT91C_LCDC_HBP (0xFF << 0) // (LCDC) Horizontal Back Porch
  3161 +#define AT91C_LCDC_HPW (0x3F << 8) // (LCDC) Horizontal Synchronization Pulse Width
  3162 +#define AT91C_LCDC_HFP (0x3FF << 22) // (LCDC) Horizontal Front Porch
  3163 +// -------- LCDC_LCDFRCFG : (LCDC Offset: 0x810) LCD Frame Config Register --------
  3164 +#define AT91C_LCDC_LINEVAL (0x7FF << 0) // (LCDC) Vertical Size of LCD Module
  3165 +#define AT91C_LCDC_HOZVAL (0x7FF << 21) // (LCDC) Horizontal Size of LCD Module
  3166 +// -------- LCDC_FIFO : (LCDC Offset: 0x814) LCD FIFO Register --------
  3167 +#define AT91C_LCDC_FIFOTH (0xFFFF << 0) // (LCDC) FIFO Threshold
  3168 +// -------- LCDC_MVAL : (LCDC Offset: 0x818) LCD Mode Toggle Rate Value Register --------
  3169 +#define AT91C_LCDC_MVALUE (0xFF << 0) // (LCDC) Toggle Rate Value
  3170 +#define AT91C_LCDC_MMODE (0x1 << 31) // (LCDC) Toggle Rate Sel
  3171 +#define AT91C_LCDC_MMODE_EACHFRAME (0x0 << 31) // (LCDC) Each Frame
  3172 +#define AT91C_LCDC_MMODE_MVALDEFINED (0x1 << 31) // (LCDC) Defined by MVAL
  3173 +// -------- LCDC_DP1_2 : (LCDC Offset: 0x81c) Dithering Pattern 1/2 --------
  3174 +#define AT91C_LCDC_DP1_2_FIELD (0xFF << 0) // (LCDC) Ratio
  3175 +// -------- LCDC_DP4_7 : (LCDC Offset: 0x820) Dithering Pattern 4/7 --------
  3176 +#define AT91C_LCDC_DP4_7_FIELD (0xFFFFFFF << 0) // (LCDC) Ratio
  3177 +// -------- LCDC_DP3_5 : (LCDC Offset: 0x824) Dithering Pattern 3/5 --------
  3178 +#define AT91C_LCDC_DP3_5_FIELD (0xFFFFF << 0) // (LCDC) Ratio
  3179 +// -------- LCDC_DP2_3 : (LCDC Offset: 0x828) Dithering Pattern 2/3 --------
  3180 +#define AT91C_LCDC_DP2_3_FIELD (0xFFF << 0) // (LCDC) Ratio
  3181 +// -------- LCDC_DP5_7 : (LCDC Offset: 0x82c) Dithering Pattern 5/7 --------
  3182 +#define AT91C_LCDC_DP5_7_FIELD (0xFFFFFFF << 0) // (LCDC) Ratio
  3183 +// -------- LCDC_DP3_4 : (LCDC Offset: 0x830) Dithering Pattern 3/4 --------
  3184 +#define AT91C_LCDC_DP3_4_FIELD (0xFFFF << 0) // (LCDC) Ratio
  3185 +// -------- LCDC_DP4_5 : (LCDC Offset: 0x834) Dithering Pattern 4/5 --------
  3186 +#define AT91C_LCDC_DP4_5_FIELD (0xFFFFF << 0) // (LCDC) Ratio
  3187 +// -------- LCDC_DP6_7 : (LCDC Offset: 0x838) Dithering Pattern 6/7 --------
  3188 +#define AT91C_LCDC_DP6_7_FIELD (0xFFFFFFF << 0) // (LCDC) Ratio
  3189 +// -------- LCDC_PWRCON : (LCDC Offset: 0x83c) LCDC Power Control Register --------
  3190 +#define AT91C_LCDC_PWR (0x1 << 0) // (LCDC) LCD Module Power Control
  3191 +#define AT91C_LCDC_GUARDT (0x7F << 1) // (LCDC) Delay in Frame Period
  3192 +#define AT91C_LCDC_BUSY (0x1 << 31) // (LCDC) Read Only : 1 indicates that LCDC is busy
  3193 +#define AT91C_LCDC_BUSY_LCDNOTBUSY (0x0 << 31) // (LCDC) LCD is Not Busy
  3194 +#define AT91C_LCDC_BUSY_LCDBUSY (0x1 << 31) // (LCDC) LCD is Busy
  3195 +// -------- LCDC_CTRSTCON : (LCDC Offset: 0x840) LCDC Contrast Control Register --------
  3196 +#define AT91C_LCDC_PS (0x3 << 0) // (LCDC) LCD Contrast Counter Prescaler
  3197 +#define AT91C_LCDC_PS_NOTDIVIDED (0x0) // (LCDC) Counter Freq is System Freq.
  3198 +#define AT91C_LCDC_PS_DIVIDEDBYTWO (0x1) // (LCDC) Counter Freq is System Freq divided by 2.
  3199 +#define AT91C_LCDC_PS_DIVIDEDBYFOUR (0x2) // (LCDC) Counter Freq is System Freq divided by 4.
  3200 +#define AT91C_LCDC_PS_DIVIDEDBYEIGHT (0x3) // (LCDC) Counter Freq is System Freq divided by 8.
  3201 +#define AT91C_LCDC_POL (0x1 << 2) // (LCDC) Polarity of output Pulse
  3202 +#define AT91C_LCDC_POL_NEGATIVEPULSE (0x0 << 2) // (LCDC) Negative Pulse
  3203 +#define AT91C_LCDC_POL_POSITIVEPULSE (0x1 << 2) // (LCDC) Positive Pulse
  3204 +#define AT91C_LCDC_ENA (0x1 << 3) // (LCDC) PWM generator Control
  3205 +#define AT91C_LCDC_ENA_PWMGEMDISABLED (0x0 << 3) // (LCDC) PWM Generator Disabled
  3206 +#define AT91C_LCDC_ENA_PWMGEMENABLED (0x1 << 3) // (LCDC) PWM Generator Disabled
  3207 +// -------- LCDC_CTRSTVAL : (LCDC Offset: 0x844) Contrast Value Register --------
  3208 +#define AT91C_LCDC_CVAL (0xFF << 0) // (LCDC) PWM Compare Value
  3209 +// -------- LCDC_IER : (LCDC Offset: 0x848) LCDC Interrupt Enable Register --------
  3210 +#define AT91C_LCDC_LNI (0x1 << 0) // (LCDC) Line Interrupt
  3211 +#define AT91C_LCDC_LSTLNI (0x1 << 1) // (LCDC) Last Line Interrupt
  3212 +#define AT91C_LCDC_EOFI (0x1 << 2) // (LCDC) End Of Frame Interrupt
  3213 +#define AT91C_LCDC_UFLWI (0x1 << 4) // (LCDC) FIFO Underflow Interrupt
  3214 +#define AT91C_LCDC_OWRI (0x1 << 5) // (LCDC) Over Write Interrupt
  3215 +#define AT91C_LCDC_MERI (0x1 << 6) // (LCDC) Memory Error Interrupt
  3216 +// -------- LCDC_IDR : (LCDC Offset: 0x84c) LCDC Interrupt Disable Register --------
  3217 +// -------- LCDC_IMR : (LCDC Offset: 0x850) LCDC Interrupt Mask Register --------
  3218 +// -------- LCDC_ISR : (LCDC Offset: 0x854) LCDC Interrupt Status Register --------
  3219 +// -------- LCDC_ICR : (LCDC Offset: 0x858) LCDC Interrupt Clear Register --------
  3220 +// -------- LCDC_GPR : (LCDC Offset: 0x85c) LCDC General Purpose Register --------
  3221 +#define AT91C_LCDC_GPRBUS (0xFF << 0) // (LCDC) 8 bits available
  3222 +// -------- LCDC_ITR : (LCDC Offset: 0x860) Interrupts Test Register --------
  3223 +// -------- LCDC_IRR : (LCDC Offset: 0x864) Interrupts Raw Status Register --------
  3224 +
  3225 +// *****************************************************************************
  3226 +// SOFTWARE API DEFINITION FOR DMA controller from Synopsys
  3227 +// *****************************************************************************
  3228 +#ifndef __ASSEMBLY__
  3229 +typedef struct _AT91S_DMA {
  3230 + AT91_REG DMA_SAR0; // Source Address Register for channel 0
  3231 + AT91_REG Reserved0[1]; //
  3232 + AT91_REG DMA_DAR0; // Destination Address Register for channel 0
  3233 + AT91_REG Reserved1[1]; //
  3234 + AT91_REG DMA_LLP0; // Linked List Pointer Register for channel 0
  3235 + AT91_REG Reserved2[1]; //
  3236 + AT91_REG DMA_CTL0l; // Control Register for channel 0 - low
  3237 + AT91_REG DMA_CTL0h; // Control Register for channel 0 - high
  3238 + AT91_REG DMA_SSTAT0; // Source Status Register for channel 0
  3239 + AT91_REG Reserved3[1]; //
  3240 + AT91_REG DMA_DSTAT0; // Destination Status Register for channel 0
  3241 + AT91_REG Reserved4[1]; //
  3242 + AT91_REG DMA_SSTATAR0; // Source Status Adress Register for channel 0
  3243 + AT91_REG Reserved5[1]; //
  3244 + AT91_REG DMA_DSTATAR0; // Destination Status Adress Register for channel 0
  3245 + AT91_REG Reserved6[1]; //
  3246 + AT91_REG DMA_CFG0l; // Configuration Register for channel 0 - low
  3247 + AT91_REG DMA_CFG0h; // Configuration Register for channel 0 - high
  3248 + AT91_REG DMA_SGR0; // Source Gather Register for channel 0
  3249 + AT91_REG Reserved7[1]; //
  3250 + AT91_REG DMA_DSR0; // Destination Scatter Register for channel 0
  3251 + AT91_REG Reserved8[1]; //
  3252 + AT91_REG DMA_SAR1; // Source Address Register for channel 1
  3253 + AT91_REG Reserved9[1]; //
  3254 + AT91_REG DMA_DAR1; // Destination Address Register for channel 1
  3255 + AT91_REG Reserved10[1]; //
  3256 + AT91_REG DMA_LLP1; // Linked List Pointer Register for channel 1
  3257 + AT91_REG Reserved11[1]; //
  3258 + AT91_REG DMA_CTL1l; // Control Register for channel 1 - low
  3259 + AT91_REG DMA_CTL1h; // Control Register for channel 1 - high
  3260 + AT91_REG DMA_SSTAT1; // Source Status Register for channel 1
  3261 + AT91_REG Reserved12[1]; //
  3262 + AT91_REG DMA_DSTAT1; // Destination Status Register for channel 1
  3263 + AT91_REG Reserved13[1]; //
  3264 + AT91_REG DMA_SSTATAR1; // Source Status Adress Register for channel 1
  3265 + AT91_REG Reserved14[1]; //
  3266 + AT91_REG DMA_DSTATAR1; // Destination Status Adress Register for channel 1
  3267 + AT91_REG Reserved15[1]; //
  3268 + AT91_REG DMA_CFG1l; // Configuration Register for channel 1 - low
  3269 + AT91_REG DMA_CFG1h; // Configuration Register for channel 1 - high
  3270 + AT91_REG DMA_SGR1; // Source Gather Register for channel 1
  3271 + AT91_REG Reserved16[1]; //
  3272 + AT91_REG DMA_DSR1; // Destination Scatter Register for channel 1
  3273 + AT91_REG Reserved17[133]; //
  3274 + AT91_REG DMA_RAWTFR; // Raw Status for IntTfr Interrupt
  3275 + AT91_REG Reserved18[1]; //
  3276 + AT91_REG DMA_RAWBLOCK; // Raw Status for IntBlock Interrupt
  3277 + AT91_REG Reserved19[1]; //
  3278 + AT91_REG DMA_RAWSRCTRAN; // Raw Status for IntSrcTran Interrupt
  3279 + AT91_REG Reserved20[1]; //
  3280 + AT91_REG DMA_RAWDSTTRAN; // Raw Status for IntDstTran Interrupt
  3281 + AT91_REG Reserved21[1]; //
  3282 + AT91_REG DMA_RAWERR; // Raw Status for IntErr Interrupt
  3283 + AT91_REG Reserved22[1]; //
  3284 + AT91_REG DMA_STATUSTFR; // Status for IntTfr Interrupt
  3285 + AT91_REG Reserved23[1]; //
  3286 + AT91_REG DMA_STATUSBLOCK; // Status for IntBlock Interrupt
  3287 + AT91_REG Reserved24[1]; //
  3288 + AT91_REG DMA_STATUSSRCTRAN; // Status for IntSrcTran Interrupt
  3289 + AT91_REG Reserved25[1]; //
  3290 + AT91_REG DMA_STATUSDSTTRAN; // Status for IntDstTran IInterrupt
  3291 + AT91_REG Reserved26[1]; //
  3292 + AT91_REG DMA_STATUSERR; // Status for IntErr IInterrupt
  3293 + AT91_REG Reserved27[1]; //
  3294 + AT91_REG DMA_MASKTFR; // Mask for IntTfr Interrupt
  3295 + AT91_REG Reserved28[1]; //
  3296 + AT91_REG DMA_MASKBLOCK; // Mask for IntBlock Interrupt
  3297 + AT91_REG Reserved29[1]; //
  3298 + AT91_REG DMA_MASKSRCTRAN; // Mask for IntSrcTran Interrupt
  3299 + AT91_REG Reserved30[1]; //
  3300 + AT91_REG DMA_MASKDSTTRAN; // Mask for IntDstTran Interrupt
  3301 + AT91_REG Reserved31[1]; //
  3302 + AT91_REG DMA_MASKERR; // Mask for IntErr Interrupt
  3303 + AT91_REG Reserved32[1]; //
  3304 + AT91_REG DMA_CLEARTFR; // Clear for IntTfr Interrupt
  3305 + AT91_REG Reserved33[1]; //
  3306 + AT91_REG DMA_CLEARBLOCK; // Clear for IntBlock Interrupt
  3307 + AT91_REG Reserved34[1]; //
  3308 + AT91_REG DMA_CLEARSRCTRAN; // Clear for IntSrcTran Interrupt
  3309 + AT91_REG Reserved35[1]; //
  3310 + AT91_REG DMA_CLEARDSTTRAN; // Clear for IntDstTran IInterrupt
  3311 + AT91_REG Reserved36[1]; //
  3312 + AT91_REG DMA_CLEARERR; // Clear for IntErr Interrupt
  3313 + AT91_REG Reserved37[1]; //
  3314 + AT91_REG DMA_STATUSINT; // Status for each Interrupt Type
  3315 + AT91_REG Reserved38[1]; //
  3316 + AT91_REG DMA_REQSRCREG; // Source Software Transaction Request Register
  3317 + AT91_REG Reserved39[1]; //
  3318 + AT91_REG DMA_REQDSTREG; // Destination Software Transaction Request Register
  3319 + AT91_REG Reserved40[1]; //
  3320 + AT91_REG DMA_SGLREQSRCREG; // Single Source Software Transaction Request Register
  3321 + AT91_REG Reserved41[1]; //
  3322 + AT91_REG DMA_SGLREQDSTREG; // Single Destination Software Transaction Request Register
  3323 + AT91_REG Reserved42[1]; //
  3324 + AT91_REG DMA_LSTREQSRCREG; // Last Source Software Transaction Request Register
  3325 + AT91_REG Reserved43[1]; //
  3326 + AT91_REG DMA_LSTREQDSTREG; // Last Destination Software Transaction Request Register
  3327 + AT91_REG Reserved44[1]; //
  3328 + AT91_REG DMA_DMACFGREG; // DW_ahb_dmac Configuration Register
  3329 + AT91_REG Reserved45[1]; //
  3330 + AT91_REG DMA_CHENREG; // DW_ahb_dmac Channel Enable Register
  3331 + AT91_REG Reserved46[1]; //
  3332 + AT91_REG DMA_DMAIDREG; // DW_ahb_dmac ID Register
  3333 + AT91_REG Reserved47[1]; //
  3334 + AT91_REG DMA_DMATESTREG; // DW_ahb_dmac Test Register
  3335 + AT91_REG Reserved48[1]; //
  3336 + AT91_REG DMA_VERSIONID; // DW_ahb_dmac Version ID Register
  3337 +} AT91S_DMA, *AT91PS_DMA;
  3338 +#else
  3339 +#define DMA_SAR0 (AT91_CAST(AT91_REG *) 0x00000000) // (DMA_SAR0) Source Address Register for channel 0
  3340 +#define DMA_DAR0 (AT91_CAST(AT91_REG *) 0x00000008) // (DMA_DAR0) Destination Address Register for channel 0
  3341 +#define DMA_LLP0 (AT91_CAST(AT91_REG *) 0x00000010) // (DMA_LLP0) Linked List Pointer Register for channel 0
  3342 +#define DMA_CTL0l (AT91_CAST(AT91_REG *) 0x00000018) // (DMA_CTL0l) Control Register for channel 0 - low
  3343 +#define DMA_CTL0h (AT91_CAST(AT91_REG *) 0x0000001C) // (DMA_CTL0h) Control Register for channel 0 - high
  3344 +#define DMA_SSTAT0 (AT91_CAST(AT91_REG *) 0x00000020) // (DMA_SSTAT0) Source Status Register for channel 0
  3345 +#define DMA_DSTAT0 (AT91_CAST(AT91_REG *) 0x00000028) // (DMA_DSTAT0) Destination Status Register for channel 0
  3346 +#define DMA_SSTATAR0 (AT91_CAST(AT91_REG *) 0x00000030) // (DMA_SSTATAR0) Source Status Adress Register for channel 0
  3347 +#define DMA_DSTATAR0 (AT91_CAST(AT91_REG *) 0x00000038) // (DMA_DSTATAR0) Destination Status Adress Register for channel 0
  3348 +#define DMA_CFG0l (AT91_CAST(AT91_REG *) 0x00000040) // (DMA_CFG0l) Configuration Register for channel 0 - low
  3349 +#define DMA_CFG0h (AT91_CAST(AT91_REG *) 0x00000044) // (DMA_CFG0h) Configuration Register for channel 0 - high
  3350 +#define DMA_SGR0 (AT91_CAST(AT91_REG *) 0x00000048) // (DMA_SGR0) Source Gather Register for channel 0
  3351 +#define DMA_DSR0 (AT91_CAST(AT91_REG *) 0x00000050) // (DMA_DSR0) Destination Scatter Register for channel 0
  3352 +#define DMA_SAR1 (AT91_CAST(AT91_REG *) 0x00000058) // (DMA_SAR1) Source Address Register for channel 1
  3353 +#define DMA_DAR1 (AT91_CAST(AT91_REG *) 0x00000060) // (DMA_DAR1) Destination Address Register for channel 1
  3354 +#define DMA_LLP1 (AT91_CAST(AT91_REG *) 0x00000068) // (DMA_LLP1) Linked List Pointer Register for channel 1
  3355 +#define DMA_CTL1l (AT91_CAST(AT91_REG *) 0x00000070) // (DMA_CTL1l) Control Register for channel 1 - low
  3356 +#define DMA_CTL1h (AT91_CAST(AT91_REG *) 0x00000074) // (DMA_CTL1h) Control Register for channel 1 - high
  3357 +#define DMA_SSTAT1 (AT91_CAST(AT91_REG *) 0x00000078) // (DMA_SSTAT1) Source Status Register for channel 1
  3358 +#define DMA_DSTAT1 (AT91_CAST(AT91_REG *) 0x00000080) // (DMA_DSTAT1) Destination Status Register for channel 1
  3359 +#define DMA_SSTATAR1 (AT91_CAST(AT91_REG *) 0x00000088) // (DMA_SSTATAR1) Source Status Adress Register for channel 1
  3360 +#define DMA_DSTATAR1 (AT91_CAST(AT91_REG *) 0x00000090) // (DMA_DSTATAR1) Destination Status Adress Register for channel 1
  3361 +#define DMA_CFG1l (AT91_CAST(AT91_REG *) 0x00000098) // (DMA_CFG1l) Configuration Register for channel 1 - low
  3362 +#define DMA_CFG1h (AT91_CAST(AT91_REG *) 0x0000009C) // (DMA_CFG1h) Configuration Register for channel 1 - high
  3363 +#define DMA_SGR1 (AT91_CAST(AT91_REG *) 0x000000A0) // (DMA_SGR1) Source Gather Register for channel 1
  3364 +#define DMA_DSR1 (AT91_CAST(AT91_REG *) 0x000000A8) // (DMA_DSR1) Destination Scatter Register for channel 1
  3365 +#define DMA_RAWTFR (AT91_CAST(AT91_REG *) 0x000002C0) // (DMA_RAWTFR) Raw Status for IntTfr Interrupt
  3366 +#define DMA_RAWBLOCK (AT91_CAST(AT91_REG *) 0x000002C8) // (DMA_RAWBLOCK) Raw Status for IntBlock Interrupt
  3367 +#define DMA_RAWSRCTRAN (AT91_CAST(AT91_REG *) 0x000002D0) // (DMA_RAWSRCTRAN) Raw Status for IntSrcTran Interrupt
  3368 +#define DMA_RAWDSTTRAN (AT91_CAST(AT91_REG *) 0x000002D8) // (DMA_RAWDSTTRAN) Raw Status for IntDstTran Interrupt
  3369 +#define DMA_RAWERR (AT91_CAST(AT91_REG *) 0x000002E0) // (DMA_RAWERR) Raw Status for IntErr Interrupt
  3370 +#define DMA_STATUSTFR (AT91_CAST(AT91_REG *) 0x000002E8) // (DMA_STATUSTFR) Status for IntTfr Interrupt
  3371 +#define DMA_STATUSBLOCK (AT91_CAST(AT91_REG *) 0x000002F0) // (DMA_STATUSBLOCK) Status for IntBlock Interrupt
  3372 +#define DMA_STATUSSRCTRAN (AT91_CAST(AT91_REG *) 0x000002F8) // (DMA_STATUSSRCTRAN) Status for IntSrcTran Interrupt
  3373 +#define DMA_STATUSDSTTRAN (AT91_CAST(AT91_REG *) 0x00000300) // (DMA_STATUSDSTTRAN) Status for IntDstTran IInterrupt
  3374 +#define DMA_STATUSERR (AT91_CAST(AT91_REG *) 0x00000308) // (DMA_STATUSERR) Status for IntErr IInterrupt
  3375 +#define DMA_MASKTFR (AT91_CAST(AT91_REG *) 0x00000310) // (DMA_MASKTFR) Mask for IntTfr Interrupt
  3376 +#define DMA_MASKBLOCK (AT91_CAST(AT91_REG *) 0x00000318) // (DMA_MASKBLOCK) Mask for IntBlock Interrupt
  3377 +#define DMA_MASKSRCTRAN (AT91_CAST(AT91_REG *) 0x00000320) // (DMA_MASKSRCTRAN) Mask for IntSrcTran Interrupt
  3378 +#define DMA_MASKDSTTRAN (AT91_CAST(AT91_REG *) 0x00000328) // (DMA_MASKDSTTRAN) Mask for IntDstTran Interrupt
  3379 +#define DMA_MASKERR (AT91_CAST(AT91_REG *) 0x00000330) // (DMA_MASKERR) Mask for IntErr Interrupt
  3380 +#define DMA_CLEARTFR (AT91_CAST(AT91_REG *) 0x00000338) // (DMA_CLEARTFR) Clear for IntTfr Interrupt
  3381 +#define DMA_CLEARBLOCK (AT91_CAST(AT91_REG *) 0x00000340) // (DMA_CLEARBLOCK) Clear for IntBlock Interrupt
  3382 +#define DMA_CLEARSRCTRAN (AT91_CAST(AT91_REG *) 0x00000348) // (DMA_CLEARSRCTRAN) Clear for IntSrcTran Interrupt
  3383 +#define DMA_CLEARDSTTRAN (AT91_CAST(AT91_REG *) 0x00000350) // (DMA_CLEARDSTTRAN) Clear for IntDstTran IInterrupt
  3384 +#define DMA_CLEARERR (AT91_CAST(AT91_REG *) 0x00000358) // (DMA_CLEARERR) Clear for IntErr Interrupt
  3385 +#define DMA_STATUSINT (AT91_CAST(AT91_REG *) 0x00000360) // (DMA_STATUSINT) Status for each Interrupt Type
  3386 +#define DMA_REQSRCREG (AT91_CAST(AT91_REG *) 0x00000368) // (DMA_REQSRCREG) Source Software Transaction Request Register
  3387 +#define DMA_REQDSTREG (AT91_CAST(AT91_REG *) 0x00000370) // (DMA_REQDSTREG) Destination Software Transaction Request Register
  3388 +#define DMA_SGLREQSRCREG (AT91_CAST(AT91_REG *) 0x00000378) // (DMA_SGLREQSRCREG) Single Source Software Transaction Request Register
  3389 +#define DMA_SGLREQDSTREG (AT91_CAST(AT91_REG *) 0x00000380) // (DMA_SGLREQDSTREG) Single Destination Software Transaction Request Register
  3390 +#define DMA_LSTREQSRCREG (AT91_CAST(AT91_REG *) 0x00000388) // (DMA_LSTREQSRCREG) Last Source Software Transaction Request Register
  3391 +#define DMA_LSTREQDSTREG (AT91_CAST(AT91_REG *) 0x00000390) // (DMA_LSTREQDSTREG) Last Destination Software Transaction Request Register
  3392 +#define DMA_DMACFGREG (AT91_CAST(AT91_REG *) 0x00000398) // (DMA_DMACFGREG) DW_ahb_dmac Configuration Register
  3393 +#define DMA_CHENREG (AT91_CAST(AT91_REG *) 0x000003A0) // (DMA_CHENREG) DW_ahb_dmac Channel Enable Register
  3394 +#define DMA_DMAIDREG (AT91_CAST(AT91_REG *) 0x000003A8) // (DMA_DMAIDREG) DW_ahb_dmac ID Register
  3395 +#define DMA_DMATESTREG (AT91_CAST(AT91_REG *) 0x000003B0) // (DMA_DMATESTREG) DW_ahb_dmac Test Register
  3396 +#define DMA_VERSIONID (AT91_CAST(AT91_REG *) 0x000003B8) // (DMA_VERSIONID) DW_ahb_dmac Version ID Register
  3397 +
  3398 +#endif
  3399 +// -------- DMA_SAR : (DMA Offset: 0x0) --------
  3400 +#define AT91C_DMA_SADD (0x0 << 0) // (DMA) Source Address of DMA Transfer
  3401 +// -------- DMA_DAR : (DMA Offset: 0x8) --------
  3402 +#define AT91C_DMA_DADD (0x0 << 0) // (DMA) Destination Address of DMA Transfer
  3403 +// -------- DMA_LLP : (DMA Offset: 0x10) --------
  3404 +#define AT91C_DMA_LOC (0x0 << 0) // (DMA) Address of the Next LLI
  3405 +// -------- DMA_CTLl : (DMA Offset: 0x18) --------
  3406 +#define AT91C_DMA_INT_EN (0x1 << 0) // (DMA) Interrupt Enable Bit
  3407 +#define AT91C_DMA_DST_TR_WIDTH (0x7 << 1) // (DMA) Destination Transfer Width
  3408 +#define AT91C_DMA_SRC_TR_WIDTH (0x7 << 4) // (DMA) Source Transfer Width
  3409 +#define AT91C_DMA_DINC (0x3 << 7) // (DMA) Destination Address Increment
  3410 +#define AT91C_DMA_SINC (0x3 << 9) // (DMA) Source Address Increment
  3411 +#define AT91C_DMA_DEST_MSIZE (0x7 << 11) // (DMA) Destination Burst Transaction Length
  3412 +#define AT91C_DMA_SRC_MSIZE (0x7 << 14) // (DMA) Source Burst Transaction Length
  3413 +#define AT91C_DMA_S_GATH_EN (0x1 << 17) // (DMA) Source Gather Enable Bit
  3414 +#define AT91C_DMA_D_SCAT_EN (0x1 << 18) // (DMA) Destination Scatter Enable Bit
  3415 +#define AT91C_DMA_TT_FC (0x7 << 20) // (DMA) Transfer Type and Flow Control
  3416 +#define AT91C_DMA_DMS (0x3 << 23) // (DMA) Destination Master Select
  3417 +#define AT91C_DMA_SMS (0x3 << 25) // (DMA) Source Master Select
  3418 +#define AT91C_DMA_LLP_D_EN (0x1 << 27) // (DMA) Destination Block Chaining Enable
  3419 +#define AT91C_DMA_LLP_S_EN (0x1 << 28) // (DMA) Source Block Chaining Enable
  3420 +// -------- DMA_CTLh : (DMA Offset: 0x1c) --------
  3421 +#define AT91C_DMA_BLOCK_TS (0xFFF << 0) // (DMA) Block Transfer Size
  3422 +#define AT91C_DMA_DONE (0x1 << 12) // (DMA) Done bit
  3423 +// -------- DMA_CFGl : (DMA Offset: 0x40) --------
  3424 +#define AT91C_DMA_CH_PRIOR (0x7 << 5) // (DMA) Channel Priority
  3425 +#define AT91C_DMA_CH_SUSP (0x1 << 8) // (DMA) Channel Suspend
  3426 +#define AT91C_DMA_FIFO_EMPT (0x1 << 9) // (DMA) Fifo Empty
  3427 +#define AT91C_DMA_HS_SEL_DS (0x1 << 10) // (DMA) Destination Software or Hardware Handshaking Select
  3428 +#define AT91C_DMA_HS_SEL_SR (0x1 << 11) // (DMA) Source Software or Hardware Handshaking Select
  3429 +#define AT91C_DMA_LOCK_CH_L (0x3 << 12) // (DMA) Channel Lock Level
  3430 +#define AT91C_DMA_LOCK_B_L (0x3 << 14) // (DMA) Bus Lock Level
  3431 +#define AT91C_DMA_LOCK_CH (0x1 << 16) // (DMA) Channel Lock Bit
  3432 +#define AT91C_DMA_LOCK_B (0x1 << 17) // (DMA) Bus Lock Bit
  3433 +#define AT91C_DMA_DS_HS_POL (0x1 << 18) // (DMA) Destination Handshaking Interface Polarity
  3434 +#define AT91C_DMA_SR_HS_POL (0x1 << 19) // (DMA) Source Handshaking Interface Polarity
  3435 +#define AT91C_DMA_MAX_ABRST (0x3FF << 20) // (DMA) Maximum AMBA Burst Length
  3436 +#define AT91C_DMA_RELOAD_SR (0x1 << 30) // (DMA) Automatic Source Reload
  3437 +#define AT91C_DMA_RELOAD_DS (0x1 << 31) // (DMA) Automatic Destination Reload
  3438 +// -------- DMA_CFGh : (DMA Offset: 0x44) --------
  3439 +#define AT91C_DMA_FCMODE (0x1 << 0) // (DMA) Flow Control Mode
  3440 +#define AT91C_DMA_FIFO_MODE (0x1 << 1) // (DMA) Fifo Mode Select
  3441 +#define AT91C_DMA_PROTCTL (0x7 << 2) // (DMA) Protection Control
  3442 +#define AT91C_DMA_DS_UPD_EN (0x1 << 5) // (DMA) Destination Status Update Enable
  3443 +#define AT91C_DMA_SS_UPD_EN (0x1 << 6) // (DMA) Source Status Update Enable
  3444 +#define AT91C_DMA_SRC_PER (0xF << 7) // (DMA) Source Hardware Handshaking Interface
  3445 +#define AT91C_DMA_DEST_PER (0xF << 11) // (DMA) Destination Hardware Handshaking Interface
  3446 +// -------- DMA_SGR : (DMA Offset: 0x48) --------
  3447 +#define AT91C_DMA_SGI (0xFFFFF << 0) // (DMA) Source Gather Interval
  3448 +#define AT91C_DMA_SGC (0xFFF << 20) // (DMA) Source Gather Count
  3449 +// -------- DMA_DSR : (DMA Offset: 0x50) --------
  3450 +#define AT91C_DMA_DSI (0xFFFFF << 0) // (DMA) Destination Scatter Interval
  3451 +#define AT91C_DMA_DSC (0xFFF << 20) // (DMA) Destination Scatter Count
  3452 +// -------- DMA_SAR : (DMA Offset: 0x58) --------
  3453 +// -------- DMA_DAR : (DMA Offset: 0x60) --------
  3454 +// -------- DMA_LLP : (DMA Offset: 0x68) --------
  3455 +// -------- DMA_CTLl : (DMA Offset: 0x70) --------
  3456 +// -------- DMA_CTLh : (DMA Offset: 0x74) --------
  3457 +// -------- DMA_CFGl : (DMA Offset: 0x98) --------
  3458 +// -------- DMA_CFGh : (DMA Offset: 0x9c) --------
  3459 +// -------- DMA_SGR : (DMA Offset: 0xa0) --------
  3460 +// -------- DMA_DSR : (DMA Offset: 0xa8) --------
  3461 +// -------- DMA_RAWTFR : (DMA Offset: 0x2c0) --------
  3462 +#define AT91C_DMA_RAW (0x7 << 0) // (DMA) Raw Interrupt for each Channel
  3463 +// -------- DMA_RAWBLOCK : (DMA Offset: 0x2c8) --------
  3464 +// -------- DMA_RAWSRCTRAN : (DMA Offset: 0x2d0) --------
  3465 +// -------- DMA_RAWDSTTRAN : (DMA Offset: 0x2d8) --------
  3466 +// -------- DMA_RAWERR : (DMA Offset: 0x2e0) --------
  3467 +// -------- DMA_STATUSTFR : (DMA Offset: 0x2e8) --------
  3468 +#define AT91C_DMA_STATUS (0x7 << 0) // (DMA) Interrupt for each Channel
  3469 +// -------- DMA_STATUSBLOCK : (DMA Offset: 0x2f0) --------
  3470 +// -------- DMA_STATUSSRCTRAN : (DMA Offset: 0x2f8) --------
  3471 +// -------- DMA_STATUSDSTTRAN : (DMA Offset: 0x300) --------
  3472 +// -------- DMA_STATUSERR : (DMA Offset: 0x308) --------
  3473 +// -------- DMA_MASKTFR : (DMA Offset: 0x310) --------
  3474 +#define AT91C_DMA_INT_MASK (0x7 << 0) // (DMA) Interrupt Mask for each Channel
  3475 +#define AT91C_DMA_INT_M_WE (0x7 << 8) // (DMA) Interrupt Mask Write Enable for each Channel
  3476 +// -------- DMA_MASKBLOCK : (DMA Offset: 0x318) --------
  3477 +// -------- DMA_MASKSRCTRAN : (DMA Offset: 0x320) --------
  3478 +// -------- DMA_MASKDSTTRAN : (DMA Offset: 0x328) --------
  3479 +// -------- DMA_MASKERR : (DMA Offset: 0x330) --------
  3480 +// -------- DMA_CLEARTFR : (DMA Offset: 0x338) --------
  3481 +#define AT91C_DMA_CLEAR (0x7 << 0) // (DMA) Interrupt Clear for each Channel
  3482 +// -------- DMA_CLEARBLOCK : (DMA Offset: 0x340) --------
  3483 +// -------- DMA_CLEARSRCTRAN : (DMA Offset: 0x348) --------
  3484 +// -------- DMA_CLEARDSTTRAN : (DMA Offset: 0x350) --------
  3485 +// -------- DMA_CLEARERR : (DMA Offset: 0x358) --------
  3486 +// -------- DMA_STATUSINT : (DMA Offset: 0x360) --------
  3487 +#define AT91C_DMA_TFR (0x1 << 0) // (DMA) OR of the content of StatusTfr Register
  3488 +#define AT91C_DMA_BLOCK (0x1 << 1) // (DMA) OR of the content of StatusBlock Register
  3489 +#define AT91C_DMA_SRCT (0x1 << 2) // (DMA) OR of the content of StatusSrcTran Register
  3490 +#define AT91C_DMA_DSTT (0x1 << 3) // (DMA) OR of the content of StatusDstTran Register
  3491 +#define AT91C_DMA_ERR (0x1 << 4) // (DMA) OR of the content of StatusErr Register
  3492 +// -------- DMA_REQSRCREG : (DMA Offset: 0x368) --------
  3493 +#define AT91C_DMA_SRC_REQ (0x7 << 0) // (DMA) Source Request
  3494 +#define AT91C_DMA_REQ_WE (0x7 << 8) // (DMA) Request Write Enable
  3495 +// -------- DMA_REQDSTREG : (DMA Offset: 0x370) --------
  3496 +#define AT91C_DMA_DST_REQ (0x7 << 0) // (DMA) Destination Request
  3497 +// -------- DMA_SGLREQSRCREG : (DMA Offset: 0x378) --------
  3498 +#define AT91C_DMA_S_SG_REQ (0x7 << 0) // (DMA) Source Single Request
  3499 +// -------- DMA_SGLREQDSTREG : (DMA Offset: 0x380) --------
  3500 +#define AT91C_DMA_D_SG_REQ (0x7 << 0) // (DMA) Destination Single Request
  3501 +// -------- DMA_LSTREQSRCREG : (DMA Offset: 0x388) --------
  3502 +#define AT91C_DMA_LSTSRC (0x7 << 0) // (DMA) Source Last Transaction Request
  3503 +#define AT91C_DMA_LSTSR_WE (0x7 << 8) // (DMA) Source Last Transaction Request Write Enable
  3504 +// -------- DMA_LSTREQDSTREG : (DMA Offset: 0x390) --------
  3505 +#define AT91C_DMA_LSTDST (0x7 << 0) // (DMA) Destination Last Transaction Request
  3506 +#define AT91C_DMA_LSTDS_WE (0x7 << 8) // (DMA) Destination Last Transaction Request Write Enable
  3507 +// -------- DMA_DMACFGREG : (DMA Offset: 0x398) --------
  3508 +#define AT91C_DMA_DMA_EN (0x7 << 0) // (DMA) Controller Enable
  3509 +// -------- DMA_CHENREG : (DMA Offset: 0x3a0) --------
  3510 +#define AT91C_DMA_CH_EN (0x7 << 0) // (DMA) Channel Enable
  3511 +#define AT91C_DMA_CH_EN_WE (0x7 << 8) // (DMA) Channel Enable Write Enable
  3512 +// -------- DMA_DMATESTREG : (DMA Offset: 0x3b0) --------
  3513 +#define AT91C_DMA_TEST_SLV_IF (0x1 << 0) // (DMA) Test Mode for Slave Interface
  3514 +
  3515 +// *****************************************************************************
  3516 +// SOFTWARE API DEFINITION FOR USB Device Interface
  3517 +// *****************************************************************************
  3518 +#ifndef __ASSEMBLY__
  3519 +typedef struct _AT91S_UDP {
  3520 + AT91_REG UDP_NUM; // Frame Number Register
  3521 + AT91_REG UDP_GLBSTATE; // Global State Register
  3522 + AT91_REG UDP_FADDR; // Function Address Register
  3523 + AT91_REG Reserved0[1]; //
  3524 + AT91_REG UDP_IER; // Interrupt Enable Register
  3525 + AT91_REG UDP_IDR; // Interrupt Disable Register
  3526 + AT91_REG UDP_IMR; // Interrupt Mask Register
  3527 + AT91_REG UDP_ISR; // Interrupt Status Register
  3528 + AT91_REG UDP_ICR; // Interrupt Clear Register
  3529 + AT91_REG Reserved1[1]; //
  3530 + AT91_REG UDP_RSTEP; // Reset Endpoint Register
  3531 + AT91_REG Reserved2[1]; //
  3532 + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
  3533 + AT91_REG Reserved3[2]; //
  3534 + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
  3535 + AT91_REG Reserved4[3]; //
  3536 + AT91_REG UDP_TXVC; // Transceiver Control Register
  3537 +} AT91S_UDP, *AT91PS_UDP;
  3538 +#else
  3539 +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
  3540 +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
  3541 +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
  3542 +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
  3543 +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
  3544 +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
  3545 +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
  3546 +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
  3547 +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
  3548 +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
  3549 +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
  3550 +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
  3551 +
  3552 +#endif
  3553 +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
  3554 +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
  3555 +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
  3556 +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
  3557 +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
  3558 +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
  3559 +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
  3560 +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
  3561 +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
  3562 +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
  3563 +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
  3564 +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
  3565 +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
  3566 +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
  3567 +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
  3568 +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
  3569 +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
  3570 +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
  3571 +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
  3572 +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
  3573 +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
  3574 +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
  3575 +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
  3576 +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
  3577 +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
  3578 +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
  3579 +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
  3580 +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
  3581 +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
  3582 +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
  3583 +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
  3584 +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
  3585 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
  3586 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
  3587 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
  3588 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
  3589 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
  3590 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
  3591 +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
  3592 +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
  3593 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
  3594 +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
  3595 +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
  3596 +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
  3597 +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
  3598 +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
  3599 +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
  3600 +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
  3601 +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
  3602 +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
  3603 +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
  3604 +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
  3605 +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
  3606 +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
  3607 +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
  3608 +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
  3609 +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
  3610 +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
  3611 +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
  3612 +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
  3613 +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
  3614 +
  3615 +// *****************************************************************************
  3616 +// SOFTWARE API DEFINITION FOR USB Host Interface
  3617 +// *****************************************************************************
  3618 +#ifndef __ASSEMBLY__
  3619 +typedef struct _AT91S_UHP {
  3620 + AT91_REG UHP_HcRevision; // Revision
  3621 + AT91_REG UHP_HcControl; // Operating modes for the Host Controller
  3622 + AT91_REG UHP_HcCommandStatus; // Command & status Register
  3623 + AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register
  3624 + AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register
  3625 + AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register
  3626 + AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area
  3627 + AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor
  3628 + AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list
  3629 + AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register
  3630 + AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list
  3631 + AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list
  3632 + AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor
  3633 + AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs
  3634 + AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame
  3635 + AT91_REG UHP_HcFmNumber; // Frame number
  3636 + AT91_REG UHP_HcPeriodicStart; // Periodic Start
  3637 + AT91_REG UHP_HcLSThreshold; // LS Threshold
  3638 + AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A
  3639 + AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B
  3640 + AT91_REG UHP_HcRhStatus; // Root Hub Status register
  3641 + AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register
  3642 +} AT91S_UHP, *AT91PS_UHP;
  3643 +#else
  3644 +#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision
  3645 +#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller
  3646 +#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register
  3647 +#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register
  3648 +#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register
  3649 +#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register
  3650 +#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area
  3651 +#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor
  3652 +#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list
  3653 +#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register
  3654 +#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list
  3655 +#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list
  3656 +#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor
  3657 +#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs
  3658 +#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame
  3659 +#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number
  3660 +#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start
  3661 +#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold
  3662 +#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A
  3663 +#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B
  3664 +#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register
  3665 +#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register
  3666 +
  3667 +#endif
  3668 +
  3669 +// *****************************************************************************
  3670 +// SOFTWARE API DEFINITION FOR Trickbox (external) / SIMULATION ONLY
  3671 +// *****************************************************************************
  3672 +#ifndef __ASSEMBLY__
  3673 +typedef struct _AT91S_TBOX {
  3674 + AT91_REG TBOX_SHMCTRL; // SHM Probe Control: 0-> shm probe stopped, 1: shm probe started
  3675 + AT91_REG Reserved0[515]; //
  3676 + AT91_REG TBOX_DMAEXTREQ; // DMA External request lines 3 to 0
  3677 + AT91_REG Reserved1[59]; //
  3678 + AT91_REG TBOX_PIOAPUN; // Spy on PIO PUN inputs
  3679 + AT91_REG TBOX_PIOBPUN; // Spy on PIO PUN inputs
  3680 + AT91_REG TBOX_PIOCPUN; // Spy on PIO PUN inputs
  3681 + AT91_REG TBOX_PIODPUN; // Spy on PIO PUN inputs
  3682 + AT91_REG TBOX_PIOEPUN; // Spy on PIO PUN inputs
  3683 + AT91_REG TBOX_PIOAENABLEFORCE; // If each bit is 1, the corresponding bit of PIOA is controlled by TBOX_PIOAFORCEVALUE
  3684 + AT91_REG TBOX_PIOAFORCEVALUE; // Value to force on PIOA when bits TBOX_PIOAENABLEFORCE are 1
  3685 + AT91_REG TBOX_PIOBENABLEFORCE; // If each bit is 1, the corresponding bit of PIOB is controlled by TBOX_PIOBFORCEVALUE
  3686 + AT91_REG TBOX_PIOBFORCEVALUE; // Value to force on PIOA when bits TBOX_PIOBENABLEFORCE are 1
  3687 + AT91_REG TBOX_PIOCENABLEFORCE; // If each bit is 1, the corresponding bit of PIOC is controlled by TBOX_PIOCFORCEVALUE
  3688 + AT91_REG TBOX_PIOCFORCEVALUE; // Value to force on PIOA when bits TBOX_PIOCENABLEFORCE are 1
  3689 + AT91_REG TBOX_PIODENABLEFORCE; // If each bit is 1, the corresponding bit of PIOD is controlled by TBOX_PIODFORCEVALUE
  3690 + AT91_REG TBOX_PIODFORCEVALUE; // Value to force on PIOA when bits TBOX_PIODENABLEFORCE are 1
  3691 + AT91_REG TBOX_PIOEENABLEFORCE; // If each bit is 1, the corresponding bit of PIOE is controlled by TBOX_PIOEFORCEVALUE
  3692 + AT91_REG TBOX_PIOEFORCEVALUE; // Value to force on PIOA when bits TBOX_PIOEENABLEFORCE are 1
  3693 + AT91_REG TBOX_PIOA; // Value Of PIOA
  3694 + AT91_REG TBOX_PIOB; // Value Of PIOB
  3695 + AT91_REG TBOX_PIOC; // Value Of PIOC
  3696 + AT91_REG TBOX_PIOD; // Value Of PIOD
  3697 + AT91_REG TBOX_PIOE; // Value Of PIOE
  3698 + AT91_REG Reserved2[44]; //
  3699 + AT91_REG TBOX_AC97START; // Start of AC97 test: swith PIO mux to connect PIOs to audio codec model.
  3700 + AT91_REG TBOX_PWMSTART; // Start of PWM test: Start to count edges on PWM IOs
  3701 + AT91_REG TBOX_PWM1; // PWM1[4:0]=nb pulses on pb7, PWM1[9:5]=nb pulses on pc28, PWM1[20:16]=nb pulses on pb8, PWM1[25:21]=nb pulses on pc3
  3702 + AT91_REG TBOX_PWM2; // PWM2[3:0]=nb pulses on pb27, PWM2[7:4]=nb pulses on pc29, PWM2[19:16]=nb pulses on pb29, PWM2[23:20]=nb pulses on pe10
  3703 + AT91_REG TBOX_MAC; // MAC testbench : bit 0 = rxtrig, bit 1 = clkofftester, bit 2 = err_sig_loops
  3704 + AT91_REG TBOX_USBDEV; // USB device testbench : bit 0 = flag0, bit 1 = flag1
  3705 + AT91_REG TBOX_KBD; // Keyboard testbench : bit 0 = keypressed; bits[7:6] = key column; bits[5:4] = key row;
  3706 + AT91_REG TBOX_STOPAPBSPY; // When 1, no more APB SPY messages
  3707 + AT91_REG Reserved3[56]; //
  3708 + AT91_REG TBOX_GPSSYNCHRO; // GPS synchronization (Stimulus)
  3709 + AT91_REG TBOX_GPSRAND; // GPS random data for correlator (Stimulus - Internal Node)
  3710 + AT91_REG TBOX_GPSACQSTATUS; // GPS acquisition status (Probe - Internal Node)
  3711 + AT91_REG TBOX_GPSACQDATA; // GPS acquisition data (Probe - Internal Node)
  3712 + AT91_REG Reserved4[36]; //
  3713 + AT91_REG TBOX_GPSSIGFILE; // GPS RFIN/DRFIN driven from files/Samples_GPS.data
  3714 + AT91_REG TBOX_GPSSIGIA; // GPS DRFIN[1:0] aka SIGI_A (Stimulus)
  3715 + AT91_REG TBOX_GPSSIGQA; // GPS DRFIN[3:2] aka SIGQ_A (Stimulus)
  3716 + AT91_REG Reserved5[1]; //
  3717 + AT91_REG TBOX_GPSSIGIB; // GPS DRFIN[5:4] aka SIGI_B (Stimulus)
  3718 + AT91_REG TBOX_GPSSIGQB; // GPS DRFIN[7:6] aka SIGQ_B (Stimulus)
  3719 + AT91_REG Reserved6[2]; //
  3720 + AT91_REG TBOX_GPSDUMPRES; // GPS Dump results and errors
  3721 +} AT91S_TBOX, *AT91PS_TBOX;
  3722 +#else
  3723 +#define TBOX_SHMCTRL (AT91_CAST(AT91_REG *) 0x00000000) // (TBOX_SHMCTRL) SHM Probe Control: 0-> shm probe stopped, 1: shm probe started
  3724 +#define TBOX_DMAEXTREQ (AT91_CAST(AT91_REG *) 0x00000810) // (TBOX_DMAEXTREQ) DMA External request lines 3 to 0
  3725 +#define TBOX_PIOAPUN (AT91_CAST(AT91_REG *) 0x00000900) // (TBOX_PIOAPUN) Spy on PIO PUN inputs
  3726 +#define TBOX_PIOBPUN (AT91_CAST(AT91_REG *) 0x00000904) // (TBOX_PIOBPUN) Spy on PIO PUN inputs
  3727 +#define TBOX_PIOCPUN (AT91_CAST(AT91_REG *) 0x00000908) // (TBOX_PIOCPUN) Spy on PIO PUN inputs
  3728 +#define TBOX_PIODPUN (AT91_CAST(AT91_REG *) 0x0000090C) // (TBOX_PIODPUN) Spy on PIO PUN inputs
  3729 +#define TBOX_PIOEPUN (AT91_CAST(AT91_REG *) 0x00000910) // (TBOX_PIOEPUN) Spy on PIO PUN inputs
  3730 +#define TBOX_PIOAENABLEFORCE (AT91_CAST(AT91_REG *) 0x00000914) // (TBOX_PIOAENABLEFORCE) If each bit is 1, the corresponding bit of PIOA is controlled by TBOX_PIOAFORCEVALUE
  3731 +#define TBOX_PIOAFORCEVALUE (AT91_CAST(AT91_REG *) 0x00000918) // (TBOX_PIOAFORCEVALUE) Value to force on PIOA when bits TBOX_PIOAENABLEFORCE are 1
  3732 +#define TBOX_PIOBENABLEFORCE (AT91_CAST(AT91_REG *) 0x0000091C) // (TBOX_PIOBENABLEFORCE) If each bit is 1, the corresponding bit of PIOB is controlled by TBOX_PIOBFORCEVALUE
  3733 +#define TBOX_PIOBFORCEVALUE (AT91_CAST(AT91_REG *) 0x00000920) // (TBOX_PIOBFORCEVALUE) Value to force on PIOA when bits TBOX_PIOBENABLEFORCE are 1
  3734 +#define TBOX_PIOCENABLEFORCE (AT91_CAST(AT91_REG *) 0x00000924) // (TBOX_PIOCENABLEFORCE) If each bit is 1, the corresponding bit of PIOC is controlled by TBOX_PIOCFORCEVALUE
  3735 +#define TBOX_PIOCFORCEVALUE (AT91_CAST(AT91_REG *) 0x00000928) // (TBOX_PIOCFORCEVALUE) Value to force on PIOA when bits TBOX_PIOCENABLEFORCE are 1
  3736 +#define TBOX_PIODENABLEFORCE (AT91_CAST(AT91_REG *) 0x0000092C) // (TBOX_PIODENABLEFORCE) If each bit is 1, the corresponding bit of PIOD is controlled by TBOX_PIODFORCEVALUE
  3737 +#define TBOX_PIODFORCEVALUE (AT91_CAST(AT91_REG *) 0x00000930) // (TBOX_PIODFORCEVALUE) Value to force on PIOA when bits TBOX_PIODENABLEFORCE are 1
  3738 +#define TBOX_PIOEENABLEFORCE (AT91_CAST(AT91_REG *) 0x00000934) // (TBOX_PIOEENABLEFORCE) If each bit is 1, the corresponding bit of PIOE is controlled by TBOX_PIOEFORCEVALUE
  3739 +#define TBOX_PIOEFORCEVALUE (AT91_CAST(AT91_REG *) 0x00000938) // (TBOX_PIOEFORCEVALUE) Value to force on PIOA when bits TBOX_PIOEENABLEFORCE are 1
  3740 +#define TBOX_PIOA (AT91_CAST(AT91_REG *) 0x0000093C) // (TBOX_PIOA) Value Of PIOA
  3741 +#define TBOX_PIOB (AT91_CAST(AT91_REG *) 0x00000940) // (TBOX_PIOB) Value Of PIOB
  3742 +#define TBOX_PIOC (AT91_CAST(AT91_REG *) 0x00000944) // (TBOX_PIOC) Value Of PIOC
  3743 +#define TBOX_PIOD (AT91_CAST(AT91_REG *) 0x00000948) // (TBOX_PIOD) Value Of PIOD
  3744 +#define TBOX_PIOE (AT91_CAST(AT91_REG *) 0x0000094C) // (TBOX_PIOE) Value Of PIOE
  3745 +#define TBOX_AC97START (AT91_CAST(AT91_REG *) 0x00000A00) // (TBOX_AC97START) Start of AC97 test: swith PIO mux to connect PIOs to audio codec model.
  3746 +#define TBOX_PWMSTART (AT91_CAST(AT91_REG *) 0x00000A04) // (TBOX_PWMSTART) Start of PWM test: Start to count edges on PWM IOs
  3747 +#define TBOX_PWM1 (AT91_CAST(AT91_REG *) 0x00000A08) // (TBOX_PWM1) PWM1[4:0]=nb pulses on pb7, PWM1[9:5]=nb pulses on pc28, PWM1[20:16]=nb pulses on pb8, PWM1[25:21]=nb pulses on pc3
  3748 +#define TBOX_PWM2 (AT91_CAST(AT91_REG *) 0x00000A0C) // (TBOX_PWM2) PWM2[3:0]=nb pulses on pb27, PWM2[7:4]=nb pulses on pc29, PWM2[19:16]=nb pulses on pb29, PWM2[23:20]=nb pulses on pe10
  3749 +#define TBOX_MAC (AT91_CAST(AT91_REG *) 0x00000A10) // (TBOX_MAC) MAC testbench : bit 0 = rxtrig, bit 1 = clkofftester, bit 2 = err_sig_loops
  3750 +#define TBOX_USBDEV (AT91_CAST(AT91_REG *) 0x00000A14) // (TBOX_USBDEV) USB device testbench : bit 0 = flag0, bit 1 = flag1
  3751 +#define TBOX_KBD (AT91_CAST(AT91_REG *) 0x00000A18) // (TBOX_KBD) Keyboard testbench : bit 0 = keypressed; bits[7:6] = key column; bits[5:4] = key row;
  3752 +#define TBOX_STOPAPBSPY (AT91_CAST(AT91_REG *) 0x00000A1C) // (TBOX_STOPAPBSPY) When 1, no more APB SPY messages
  3753 +#define TBOX_GPSSYNCHRO (AT91_CAST(AT91_REG *) 0x00000B00) // (TBOX_GPSSYNCHRO) GPS synchronization (Stimulus)
  3754 +#define TBOX_GPSRAND (AT91_CAST(AT91_REG *) 0x00000B04) // (TBOX_GPSRAND) GPS random data for correlator (Stimulus - Internal Node)
  3755 +#define TBOX_GPSACQSTATUS (AT91_CAST(AT91_REG *) 0x00000B08) // (TBOX_GPSACQSTATUS) GPS acquisition status (Probe - Internal Node)
  3756 +#define TBOX_GPSACQDATA (AT91_CAST(AT91_REG *) 0x00000B0C) // (TBOX_GPSACQDATA) GPS acquisition data (Probe - Internal Node)
  3757 +#define TBOX_GPSSIGFILE (AT91_CAST(AT91_REG *) 0x00000BA0) // (TBOX_GPSSIGFILE) GPS RFIN/DRFIN driven from files/Samples_GPS.data
  3758 +#define TBOX_GPSSIGIA (AT91_CAST(AT91_REG *) 0x00000BA4) // (TBOX_GPSSIGIA) GPS DRFIN[1:0] aka SIGI_A (Stimulus)
  3759 +#define TBOX_GPSSIGQA (AT91_CAST(AT91_REG *) 0x00000BA8) // (TBOX_GPSSIGQA) GPS DRFIN[3:2] aka SIGQ_A (Stimulus)
  3760 +#define TBOX_GPSSIGIB (AT91_CAST(AT91_REG *) 0x00000BB0) // (TBOX_GPSSIGIB) GPS DRFIN[5:4] aka SIGI_B (Stimulus)
  3761 +#define TBOX_GPSSIGQB (AT91_CAST(AT91_REG *) 0x00000BB4) // (TBOX_GPSSIGQB) GPS DRFIN[7:6] aka SIGQ_B (Stimulus)
  3762 +#define TBOX_GPSDUMPRES (AT91_CAST(AT91_REG *) 0x00000BC0) // (TBOX_GPSDUMPRES) GPS Dump results and errors
  3763 +
  3764 +#endif
  3765 +// -------- TBOX_DMAEXTREQ : (TBOX Offset: 0x810) --------
  3766 +#define AT91C_TBOX_DMAEXTREQ0 (0x1 << 0) // (TBOX) DMA external request 0
  3767 +#define AT91C_TBOX_DMAEXTREQ1 (0x1 << 1) // (TBOX) DMA external request 1
  3768 +#define AT91C_TBOX_DMAEXTREQ2 (0x1 << 2) // (TBOX) DMA external request 2
  3769 +#define AT91C_TBOX_DMAEXTREQ3 (0x1 << 3) // (TBOX) DMA external request 3
  3770 +
  3771 +// *****************************************************************************
  3772 +// SOFTWARE API DEFINITION FOR Error Correction Code controller
  3773 +// *****************************************************************************
  3774 +#ifndef __ASSEMBLY__
  3775 +typedef struct _AT91S_ECC {
  3776 + AT91_REG ECC_CR; // ECC reset register
  3777 + AT91_REG ECC_MR; // ECC Page size register
  3778 + AT91_REG ECC_SR; // ECC Status register
  3779 + AT91_REG ECC_PR; // ECC Parity register
  3780 + AT91_REG ECC_NPR; // ECC Parity N register
  3781 + AT91_REG Reserved0[58]; //
  3782 + AT91_REG ECC_VR; // ECC Version register
  3783 +} AT91S_ECC, *AT91PS_ECC;
  3784 +#else
  3785 +#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register
  3786 +#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register
  3787 +#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register
  3788 +#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register
  3789 +#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register
  3790 +#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register
  3791 +
  3792 +#endif
  3793 +// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register --------
  3794 +#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity
  3795 +// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register --------
  3796 +#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size
  3797 +// -------- ECC_SR : (ECC Offset: 0x8) ECC status register --------
  3798 +#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error
  3799 +#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error
  3800 +#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR
  3801 +// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register --------
  3802 +#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error
  3803 +#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit
  3804 +// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register --------
  3805 +#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N
  3806 +// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register --------
  3807 +#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register
  3808 +
  3809 +// *****************************************************************************
  3810 +// SOFTWARE API DEFINITION FOR Image Sensor Interface
  3811 +// *****************************************************************************
  3812 +#ifndef __ASSEMBLY__
  3813 +typedef struct _AT91S_ISI {
  3814 + AT91_REG ISI_CR1; // Control Register 1
  3815 + AT91_REG ISI_CR2; // Control Register 2
  3816 + AT91_REG ISI_SR; // Status Register
  3817 + AT91_REG ISI_IER; // Interrupt Enable Register
  3818 + AT91_REG ISI_IDR; // Interrupt Disable Register
  3819 + AT91_REG ISI_IMR; // Interrupt Mask Register
  3820 + AT91_REG Reserved0[2]; //
  3821 + AT91_REG ISI_PSIZE; // Preview Size Register
  3822 + AT91_REG ISI_PDECF; // Preview Decimation Factor Register
  3823 + AT91_REG ISI_PFBD; // Preview Frame Buffer Address Register
  3824 + AT91_REG ISI_CDBA; // Codec Dma Address Register
  3825 + AT91_REG ISI_Y2RSET0; // Color Space Conversion Register
  3826 + AT91_REG ISI_Y2RSET1; // Color Space Conversion Register
  3827 + AT91_REG ISI_R2YSET0; // Color Space Conversion Register
  3828 + AT91_REG ISI_R2YSET1; // Color Space Conversion Register
  3829 + AT91_REG ISI_R2YSET2; // Color Space Conversion Register
  3830 +} AT91S_ISI, *AT91PS_ISI;
  3831 +#else
  3832 +#define ISI_CR1 (AT91_CAST(AT91_REG *) 0x00000000) // (ISI_CR1) Control Register 1
  3833 +#define ISI_CR2 (AT91_CAST(AT91_REG *) 0x00000004) // (ISI_CR2) Control Register 2
  3834 +#define ISI_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ISI_SR) Status Register
  3835 +#define ISI_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (ISI_IER) Interrupt Enable Register
  3836 +#define ISI_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (ISI_IDR) Interrupt Disable Register
  3837 +#define ISI_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (ISI_IMR) Interrupt Mask Register
  3838 +#define ISI_PSIZE (AT91_CAST(AT91_REG *) 0x00000020) // (ISI_PSIZE) Preview Size Register
  3839 +#define ISI_PDECF (AT91_CAST(AT91_REG *) 0x00000024) // (ISI_PDECF) Preview Decimation Factor Register
  3840 +#define ISI_PFBD (AT91_CAST(AT91_REG *) 0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register
  3841 +#define ISI_CDBA (AT91_CAST(AT91_REG *) 0x0000002C) // (ISI_CDBA) Codec Dma Address Register
  3842 +#define ISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register
  3843 +#define ISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register
  3844 +#define ISI_R2YSET0 (AT91_CAST(AT91_REG *) 0x00000038) // (ISI_R2YSET0) Color Space Conversion Register
  3845 +#define ISI_R2YSET1 (AT91_CAST(AT91_REG *) 0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register
  3846 +#define ISI_R2YSET2 (AT91_CAST(AT91_REG *) 0x00000040) // (ISI_R2YSET2) Color Space Conversion Register
  3847 +
  3848 +#endif
  3849 +// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 --------
  3850 +#define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset
  3851 +#define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable.
  3852 +#define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity
  3853 +#define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity
  3854 +#define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation
  3855 +#define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction
  3856 +#define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed
  3857 +#define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask
  3858 +#define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed
  3859 +#define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed
  3860 +#define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed
  3861 +#define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path
  3862 +#define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay
  3863 +#define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay
  3864 +// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 --------
  3865 +#define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047]
  3866 +#define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode
  3867 +#define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode
  3868 +#define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
  3869 +#define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
  3870 +#define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits
  3871 +#define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode
  3872 +#define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap
  3873 +#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data
  3874 +#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
  3875 +#define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
  3876 +#define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
  3877 +#define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
  3878 +#define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
  3879 +#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration
  3880 +#define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B
  3881 +#define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R
  3882 +#define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB)
  3883 +#define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB)
  3884 +// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register --------
  3885 +#define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame
  3886 +#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable
  3887 +#define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset
  3888 +#define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error
  3889 +#define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow
  3890 +#define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow
  3891 +#define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty
  3892 +#define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty
  3893 +#define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun
  3894 +// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register --------
  3895 +// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register --------
  3896 +// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register --------
  3897 +// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register --------
  3898 +#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path
  3899 +#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path
  3900 +// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register --------
  3901 +#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0
  3902 +#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1
  3903 +#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
  3904 +#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
  3905 +// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register --------
  3906 +#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4
  3907 +#define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset
  3908 +#define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset
  3909 +#define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset
  3910 +// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register --------
  3911 +#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
  3912 +#define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
  3913 +#define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
  3914 +#define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset
  3915 +// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register --------
  3916 +#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
  3917 +#define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
  3918 +#define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
  3919 +#define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset
  3920 +// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register --------
  3921 +#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
  3922 +#define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
  3923 +#define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
  3924 +#define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset
  3925 +
  3926 +// *****************************************************************************
  3927 +// REGISTER ADDRESS DEFINITION FOR AT91SAM9263
  3928 +// *****************************************************************************
  3929 +// ========== Register definition for SYS peripheral ==========
  3930 +#define AT91C_SYS_ECC1 (AT91_CAST(AT91_REG *) 0xFFFFE600) // (SYS) ECC 0
  3931 +#define AT91C_SYS_ECC0 (AT91_CAST(AT91_REG *) 0xFFFFE000) // (SYS) ECC 0
  3932 +#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (SYS) General Purpose Register
  3933 +// ========== Register definition for EBI0 peripheral ==========
  3934 +#define AT91C_EBI0_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFE200) // (EBI0) Dummy register - Do not use
  3935 +// ========== Register definition for SDRAMC0 peripheral ==========
  3936 +#define AT91C_SDRAMC0_MDR (AT91_CAST(AT91_REG *) 0xFFFFE224) // (SDRAMC0) SDRAM Memory Device Register
  3937 +#define AT91C_SDRAMC0_IDR (AT91_CAST(AT91_REG *) 0xFFFFE218) // (SDRAMC0) SDRAM Controller Interrupt Disable Register
  3938 +#define AT91C_SDRAMC0_IMR (AT91_CAST(AT91_REG *) 0xFFFFE21C) // (SDRAMC0) SDRAM Controller Interrupt Mask Register
  3939 +#define AT91C_SDRAMC0_ISR (AT91_CAST(AT91_REG *) 0xFFFFE220) // (SDRAMC0) SDRAM Controller Interrupt Mask Register
  3940 +#define AT91C_SDRAMC0_HSR (AT91_CAST(AT91_REG *) 0xFFFFE20C) // (SDRAMC0) SDRAM Controller High Speed Register
  3941 +#define AT91C_SDRAMC0_TR (AT91_CAST(AT91_REG *) 0xFFFFE204) // (SDRAMC0) SDRAM Controller Refresh Timer Register
  3942 +#define AT91C_SDRAMC0_CR (AT91_CAST(AT91_REG *) 0xFFFFE208) // (SDRAMC0) SDRAM Controller Configuration Register
  3943 +#define AT91C_SDRAMC0_MR (AT91_CAST(AT91_REG *) 0xFFFFE200) // (SDRAMC0) SDRAM Controller Mode Register
  3944 +#define AT91C_SDRAMC0_LPR (AT91_CAST(AT91_REG *) 0xFFFFE210) // (SDRAMC0) SDRAM Controller Low Power Register
  3945 +#define AT91C_SDRAMC0_IER (AT91_CAST(AT91_REG *) 0xFFFFE214) // (SDRAMC0) SDRAM Controller Interrupt Enable Register
  3946 +// ========== Register definition for SMC0 peripheral ==========
  3947 +#define AT91C_SMC0_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFE468) // (SMC0) Cycle Register for CS 6
  3948 +#define AT91C_SMC0_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFE460) // (SMC0) Setup Register for CS 6
  3949 +#define AT91C_SMC0_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFE434) // (SMC0) Pulse Register for CS 3
  3950 +#define AT91C_SMC0_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFE418) // (SMC0) Cycle Register for CS 1
  3951 +#define AT91C_SMC0_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFE450) // (SMC0) Setup Register for CS 5
  3952 +#define AT91C_SMC0_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFE478) // (SMC0) Cycle Register for CS 7
  3953 +#define AT91C_SMC0_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFE404) // (SMC0) Pulse Register for CS 0
  3954 +#define AT91C_SMC0_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFE458) // (SMC0) Cycle Register for CS 5
  3955 +#define AT91C_SMC0_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFE40C) // (SMC0) Control Register for CS 0
  3956 +#define AT91C_SMC0_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFE470) // (SMC0) Setup Register for CS 7
  3957 +#define AT91C_SMC0_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFE44C) // (SMC0) Control Register for CS 4
  3958 +#define AT91C_SMC0_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFE41C) // (SMC0) Control Register for CS 1
  3959 +#define AT91C_SMC0_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFE428) // (SMC0) Cycle Register for CS 2
  3960 +#define AT91C_SMC0_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFE474) // (SMC0) Pulse Register for CS 7
  3961 +#define AT91C_SMC0_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFE464) // (SMC0) Pulse Register for CS 6
  3962 +#define AT91C_SMC0_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFE448) // (SMC0) Cycle Register for CS 4
  3963 +#define AT91C_SMC0_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFE408) // (SMC0) Cycle Register for CS 0
  3964 +#define AT91C_SMC0_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFE46C) // (SMC0) Control Register for CS 6
  3965 +#define AT91C_SMC0_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFE45C) // (SMC0) Control Register for CS 5
  3966 +#define AT91C_SMC0_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFE400) // (SMC0) Setup Register for CS 0
  3967 +#define AT91C_SMC0_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFE440) // (SMC0) Setup Register for CS 4
  3968 +#define AT91C_SMC0_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFE414) // (SMC0) Pulse Register for CS 1
  3969 +#define AT91C_SMC0_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFE42C) // (SMC0) Control Register for CS 2
  3970 +#define AT91C_SMC0_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFE420) // (SMC0) Setup Register for CS 2
  3971 +#define AT91C_SMC0_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFE43C) // (SMC0) Control Register for CS 3
  3972 +#define AT91C_SMC0_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFE430) // (SMC0) Setup Register for CS 3
  3973 +#define AT91C_SMC0_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFE47C) // (SMC0) Control Register for CS 7
  3974 +#define AT91C_SMC0_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFE454) // (SMC0) Pulse Register for CS 5
  3975 +#define AT91C_SMC0_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFE444) // (SMC0) Pulse Register for CS 4
  3976 +#define AT91C_SMC0_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFE424) // (SMC0) Pulse Register for CS 2
  3977 +#define AT91C_SMC0_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFE438) // (SMC0) Cycle Register for CS 3
  3978 +#define AT91C_SMC0_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFE410) // (SMC0) Setup Register for CS 1
  3979 +// ========== Register definition for EBI1 peripheral ==========
  3980 +#define AT91C_EBI1_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFE800) // (EBI1) Dummy register - Do not use
  3981 +// ========== Register definition for SDRAMC1 peripheral ==========
  3982 +#define AT91C_SDRAMC1_IMR (AT91_CAST(AT91_REG *) 0xFFFFE81C) // (SDRAMC1) SDRAM Controller Interrupt Mask Register
  3983 +#define AT91C_SDRAMC1_LPR (AT91_CAST(AT91_REG *) 0xFFFFE810) // (SDRAMC1) SDRAM Controller Low Power Register
  3984 +#define AT91C_SDRAMC1_CR (AT91_CAST(AT91_REG *) 0xFFFFE808) // (SDRAMC1) SDRAM Controller Configuration Register
  3985 +#define AT91C_SDRAMC1_HSR (AT91_CAST(AT91_REG *) 0xFFFFE80C) // (SDRAMC1) SDRAM Controller High Speed Register
  3986 +#define AT91C_SDRAMC1_MDR (AT91_CAST(AT91_REG *) 0xFFFFE824) // (SDRAMC1) SDRAM Memory Device Register
  3987 +#define AT91C_SDRAMC1_MR (AT91_CAST(AT91_REG *) 0xFFFFE800) // (SDRAMC1) SDRAM Controller Mode Register
  3988 +#define AT91C_SDRAMC1_ISR (AT91_CAST(AT91_REG *) 0xFFFFE820) // (SDRAMC1) SDRAM Controller Interrupt Mask Register
  3989 +#define AT91C_SDRAMC1_IDR (AT91_CAST(AT91_REG *) 0xFFFFE818) // (SDRAMC1) SDRAM Controller Interrupt Disable Register
  3990 +#define AT91C_SDRAMC1_IER (AT91_CAST(AT91_REG *) 0xFFFFE814) // (SDRAMC1) SDRAM Controller Interrupt Enable Register
  3991 +#define AT91C_SDRAMC1_TR (AT91_CAST(AT91_REG *) 0xFFFFE804) // (SDRAMC1) SDRAM Controller Refresh Timer Register
  3992 +// ========== Register definition for SMC1 peripheral ==========
  3993 +#define AT91C_SMC1_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEA44) // (SMC1) Pulse Register for CS 4
  3994 +#define AT91C_SMC1_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SMC1) Setup Register for CS 2
  3995 +#define AT91C_SMC1_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SMC1) Cycle Register for CS 0
  3996 +#define AT91C_SMC1_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEA70) // (SMC1) Setup Register for CS 7
  3997 +#define AT91C_SMC1_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEA74) // (SMC1) Pulse Register for CS 7
  3998 +#define AT91C_SMC1_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SMC1) Control Register for CS 0
  3999 +#define AT91C_SMC1_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEA30) // (SMC1) Setup Register for CS 3
  4000 +#define AT91C_SMC1_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEA40) // (SMC1) Setup Register for CS 4
  4001 +#define AT91C_SMC1_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEA68) // (SMC1) Cycle Register for CS 6
  4002 +#define AT91C_SMC1_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SMC1) Control Register for CS 1
  4003 +#define AT91C_SMC1_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEA38) // (SMC1) Cycle Register for CS 3
  4004 +#define AT91C_SMC1_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEA5C) // (SMC1) Control Register for CS 5
  4005 +#define AT91C_SMC1_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEA3C) // (SMC1) Control Register for CS 3
  4006 +#define AT91C_SMC1_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEA48) // (SMC1) Cycle Register for CS 4
  4007 +#define AT91C_SMC1_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEA60) // (SMC1) Setup Register for CS 6
  4008 +#define AT91C_SMC1_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEA34) // (SMC1) Pulse Register for CS 3
  4009 +#define AT91C_SMC1_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEA7C) // (SMC1) Control Register for CS 7
  4010 +#define AT91C_SMC1_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SMC1) Setup Register for CS 1
  4011 +#define AT91C_SMC1_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEA54) // (SMC1) Pulse Register for CS 5
  4012 +#define AT91C_SMC1_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SMC1) Pulse Register for CS 0
  4013 +#define AT91C_SMC1_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEA58) // (SMC1) Cycle Register for CS 5
  4014 +#define AT91C_SMC1_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEA64) // (SMC1) Pulse Register for CS 6
  4015 +#define AT91C_SMC1_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEA50) // (SMC1) Setup Register for CS 5
  4016 +#define AT91C_SMC1_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEA6C) // (SMC1) Control Register for CS 6
  4017 +#define AT91C_SMC1_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEA2C) // (SMC1) Control Register for CS 2
  4018 +#define AT91C_SMC1_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SMC1) Setup Register for CS 0
  4019 +#define AT91C_SMC1_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEA78) // (SMC1) Cycle Register for CS 7
  4020 +#define AT91C_SMC1_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SMC1) Cycle Register for CS 1
  4021 +#define AT91C_SMC1_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SMC1) Pulse Register for CS 2
  4022 +#define AT91C_SMC1_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SMC1) Pulse Register for CS 1
  4023 +#define AT91C_SMC1_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEA28) // (SMC1) Cycle Register for CS 2
  4024 +#define AT91C_SMC1_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEA4C) // (SMC1) Control Register for CS 4
  4025 +// ========== Register definition for MATRIX peripheral ==========
  4026 +#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (MATRIX) Master Configuration Register 7
  4027 +#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFED00) // (MATRIX) Master Remp Control Register
  4028 +#define AT91C_MATRIX_PRBS5 (AT91_CAST(AT91_REG *) 0xFFFFECAC) // (MATRIX) PRBS5
  4029 +#define AT91C_MATRIX_SCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (MATRIX) Slave Configuration Register 6
  4030 +#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (MATRIX) Master Configuration Register 3
  4031 +#define AT91C_MATRIX_SCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (MATRIX) Slave Configuration Register 5
  4032 +#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (MATRIX) Master Configuration Register 1
  4033 +#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (MATRIX) Slave Configuration Register 3
  4034 +#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (MATRIX) Master Configuration Register 4
  4035 +#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (MATRIX) Master Configuration Register 2
  4036 +#define AT91C_MATRIX_PRBS6 (AT91_CAST(AT91_REG *) 0xFFFFECB4) // (MATRIX) PRBS6
  4037 +#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (MATRIX) Slave Configuration Register 4
  4038 +#define AT91C_MATRIX_MCFG8 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (MATRIX) Master Configuration Register 8
  4039 +#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0xFFFFEC98) // (MATRIX) PRAS3
  4040 +#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0xFFFFECA0) // (MATRIX) PRAS4
  4041 +#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0xFFFFEC88) // (MATRIX) PRAS1
  4042 +#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0xFFFFEC80) // (MATRIX) PRAS0
  4043 +#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (MATRIX) Slave Configuration Register 0
  4044 +#define AT91C_MATRIX_PRBS7 (AT91_CAST(AT91_REG *) 0xFFFFECBC) // (MATRIX) PRBS7
  4045 +#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0xFFFFECA4) // (MATRIX) PRBS4
  4046 +#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0xFFFFEC94) // (MATRIX) PRBS2
  4047 +#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (MATRIX) Master Configuration Register 5
  4048 +#define AT91C_MATRIX_SCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (MATRIX) Slave Configuration Register 7
  4049 +#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0xFFFFEC8C) // (MATRIX) PRBS1
  4050 +#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (MATRIX) Master Configuration Register 6
  4051 +#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0xFFFFEC84) // (MATRIX) PRBS0
  4052 +#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (MATRIX) Master Configuration Register 0
  4053 +#define AT91C_MATRIX_PRAS5 (AT91_CAST(AT91_REG *) 0xFFFFECA8) // (MATRIX) PRAS5
  4054 +#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (MATRIX) Slave Configuration Register 1
  4055 +#define AT91C_MATRIX_PRAS7 (AT91_CAST(AT91_REG *) 0xFFFFECB8) // (MATRIX) PRAS7
  4056 +#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0xFFFFEC90) // (MATRIX) PRAS2
  4057 +#define AT91C_MATRIX_PRAS6 (AT91_CAST(AT91_REG *) 0xFFFFECB0) // (MATRIX) PRAS6
  4058 +#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (MATRIX) Slave Configuration Register 2
  4059 +#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0xFFFFEC9C) // (MATRIX) PRBS3
  4060 +// ========== Register definition for CCFG peripheral ==========
  4061 +#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0xFFFFEDFC) // (CCFG) Version Register
  4062 +#define AT91C_CCFG_TCMR (AT91_CAST(AT91_REG *) 0xFFFFED14) // (CCFG) TCM configuration
  4063 +#define AT91C_CCFG_EBI0CSA (AT91_CAST(AT91_REG *) 0xFFFFED20) // (CCFG) EBI0 Chip Select Assignement Register
  4064 +#define AT91C_CCFG_EBI1CSA (AT91_CAST(AT91_REG *) 0xFFFFED24) // (CCFG) EBI1 Chip Select Assignement Register
  4065 +// ========== Register definition for PDC_DBGU peripheral ==========
  4066 +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFEF20) // (PDC_DBGU) PDC Transfer Control Register
  4067 +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFEF04) // (PDC_DBGU) Receive Counter Register
  4068 +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFEF0C) // (PDC_DBGU) Transmit Counter Register
  4069 +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFEF14) // (PDC_DBGU) Receive Next Counter Register
  4070 +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFEF18) // (PDC_DBGU) Transmit Next Pointer Register
  4071 +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFEF10) // (PDC_DBGU) Receive Next Pointer Register
  4072 +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFEF24) // (PDC_DBGU) PDC Transfer Status Register
  4073 +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (PDC_DBGU) Receive Pointer Register
  4074 +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFEF08) // (PDC_DBGU) Transmit Pointer Register
  4075 +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (PDC_DBGU) Transmit Next Counter Register
  4076 +// ========== Register definition for DBGU peripheral ==========
  4077 +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFEE20) // (DBGU) Baud Rate Generator Register
  4078 +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (DBGU) Control Register
  4079 +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFEE1C) // (DBGU) Transmitter Holding Register
  4080 +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (DBGU) Interrupt Disable Register
  4081 +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (DBGU) Chip ID Extension Register
  4082 +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (DBGU) Interrupt Mask Register
  4083 +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFEE48) // (DBGU) Force NTRST Register
  4084 +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (DBGU) Interrupt Enable Register
  4085 +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (DBGU) Channel Status Register
  4086 +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (DBGU) Mode Register
  4087 +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFEE18) // (DBGU) Receiver Holding Register
  4088 +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (DBGU) Chip ID Register
  4089 +// ========== Register definition for AIC peripheral ==========
  4090 +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
  4091 +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
  4092 +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
  4093 +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
  4094 +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
  4095 +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
  4096 +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
  4097 +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
  4098 +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
  4099 +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
  4100 +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
  4101 +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
  4102 +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
  4103 +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
  4104 +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
  4105 +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
  4106 +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
  4107 +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
  4108 +// ========== Register definition for PIOA peripheral ==========
  4109 +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF2A4) // (PIOA) Output Write Disable Register
  4110 +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF254) // (PIOA) Multi-driver Disable Register
  4111 +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF228) // (PIOA) Input Filter Status Register
  4112 +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF24C) // (PIOA) Interrupt Status Register
  4113 +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF234) // (PIOA) Clear Output Data Register
  4114 +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (PIOA) PIO Disable Register
  4115 +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF2A8) // (PIOA) Output Write Status Register
  4116 +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF270) // (PIOA) Select A Register
  4117 +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF268) // (PIOA) Pull-up Status Register
  4118 +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (PIOA) Interrupt Mask Register
  4119 +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (PIOA) Output Status Register
  4120 +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF278) // (PIOA) AB Select Status Register
  4121 +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF250) // (PIOA) Multi-driver Enable Register
  4122 +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF224) // (PIOA) Input Filter Disable Register
  4123 +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF23C) // (PIOA) Pin Data Status Register
  4124 +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF230) // (PIOA) Set Output Data Register
  4125 +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF274) // (PIOA) Select B Register
  4126 +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF2A0) // (PIOA) Output Write Enable Register
  4127 +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF220) // (PIOA) Input Filter Enable Register
  4128 +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF244) // (PIOA) Interrupt Disable Register
  4129 +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (PIOA) Output Disable Registerr
  4130 +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF240) // (PIOA) Interrupt Enable Register
  4131 +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF264) // (PIOA) Pull-up Enable Register
  4132 +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF258) // (PIOA) Multi-driver Status Register
  4133 +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF210) // (PIOA) Output Enable Register
  4134 +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF200) // (PIOA) PIO Enable Register
  4135 +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF260) // (PIOA) Pull-up Disable Register
  4136 +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF238) // (PIOA) Output Data Status Register
  4137 +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF208) // (PIOA) PIO Status Register
  4138 +// ========== Register definition for PIOB peripheral ==========
  4139 +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOB) Output Disable Registerr
  4140 +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOB) Set Output Data Register
  4141 +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOB) Interrupt Status Register
  4142 +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOB) AB Select Status Register
  4143 +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOB) Interrupt Enable Register
  4144 +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOB) Pull-up Disable Register
  4145 +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOB) Interrupt Mask Register
  4146 +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOB) PIO Enable Register
  4147 +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOB) Input Filter Disable Register
  4148 +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOB) Output Write Disable Register
  4149 +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOB) Multi-driver Status Register
  4150 +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOB) Interrupt Disable Register
  4151 +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOB) Output Data Status Register
  4152 +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOB) Pull-up Status Register
  4153 +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOB) Output Write Status Register
  4154 +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOB) Select B Register
  4155 +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOB) Output Write Enable Register
  4156 +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOB) Input Filter Enable Register
  4157 +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOB) Pin Data Status Register
  4158 +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOB) Pull-up Enable Register
  4159 +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOB) Output Status Register
  4160 +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOB) Select A Register
  4161 +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOB) Multi-driver Disable Register
  4162 +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOB) Clear Output Data Register
  4163 +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOB) Multi-driver Enable Register
  4164 +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOB) PIO Disable Register
  4165 +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOB) Input Filter Status Register
  4166 +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOB) Output Enable Register
  4167 +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOB) PIO Status Register
  4168 +// ========== Register definition for PIOC peripheral ==========
  4169 +#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOC) Output Write Disable Register
  4170 +#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOC) Multi-driver Enable Register
  4171 +#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOC) Pull-up Status Register
  4172 +#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOC) Interrupt Mask Register
  4173 +#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOC) Select A Register
  4174 +#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOC) Pull-up Disable Register
  4175 +#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOC) PIO Status Register
  4176 +#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOC) Interrupt Enable Register
  4177 +#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOC) Clear Output Data Register
  4178 +#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOC) Output Write Enable Register
  4179 +#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOC) AB Select Status Register
  4180 +#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOC) Input Filter Disable Register
  4181 +#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOC) Pin Data Status Register
  4182 +#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOC) Interrupt Disable Register
  4183 +#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOC) Output Write Status Register
  4184 +#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOC) PIO Disable Register
  4185 +#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOC) Output Disable Registerr
  4186 +#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOC) Input Filter Status Register
  4187 +#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOC) Pull-up Enable Register
  4188 +#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOC) Set Output Data Register
  4189 +#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOC) Interrupt Status Register
  4190 +#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOC) Output Data Status Register
  4191 +#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOC) Output Status Register
  4192 +#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOC) Multi-driver Status Register
  4193 +#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOC) Input Filter Enable Register
  4194 +#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOC) Select B Register
  4195 +#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOC) Multi-driver Disable Register
  4196 +#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOC) Output Enable Register
  4197 +#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOC) PIO Enable Register
  4198 +// ========== Register definition for PIOD peripheral ==========
  4199 +#define AT91C_PIOD_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOD) Output Write Disable Register
  4200 +#define AT91C_PIOD_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOD) Set Output Data Register
  4201 +#define AT91C_PIOD_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOD) Pull-up Enable Register
  4202 +#define AT91C_PIOD_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOD) Clear Output Data Register
  4203 +#define AT91C_PIOD_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOD) PIO Status Register
  4204 +#define AT91C_PIOD_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOD) PIO Disable Register
  4205 +#define AT91C_PIOD_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOD) Output Disable Registerr
  4206 +#define AT91C_PIOD_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOD) Pull-up Status Register
  4207 +#define AT91C_PIOD_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOD) AB Select Status Register
  4208 +#define AT91C_PIOD_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOD) Input Filter Status Register
  4209 +#define AT91C_PIOD_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOD) Output Enable Register
  4210 +#define AT91C_PIOD_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOD) Interrupt Mask Register
  4211 +#define AT91C_PIOD_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOD) Select A Register
  4212 +#define AT91C_PIOD_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOD) Multi-driver Disable Register
  4213 +#define AT91C_PIOD_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOD) Output Write Status Register
  4214 +#define AT91C_PIOD_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOD) PIO Enable Register
  4215 +#define AT91C_PIOD_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOD) Interrupt Disable Register
  4216 +#define AT91C_PIOD_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOD) Multi-driver Enable Register
  4217 +#define AT91C_PIOD_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOD) Pin Data Status Register
  4218 +#define AT91C_PIOD_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOD) Multi-driver Status Register
  4219 +#define AT91C_PIOD_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOD) Output Write Enable Register
  4220 +#define AT91C_PIOD_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOD) Select B Register
  4221 +#define AT91C_PIOD_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOD) Pull-up Disable Register
  4222 +#define AT91C_PIOD_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOD) Input Filter Disable Register
  4223 +#define AT91C_PIOD_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOD) Interrupt Enable Register
  4224 +#define AT91C_PIOD_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOD) Output Status Register
  4225 +#define AT91C_PIOD_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOD) Output Data Status Register
  4226 +#define AT91C_PIOD_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOD) Interrupt Status Register
  4227 +#define AT91C_PIOD_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOD) Input Filter Enable Register
  4228 +// ========== Register definition for PIOE peripheral ==========
  4229 +#define AT91C_PIOE_ODSR (AT91_CAST(AT91_REG *) 0xFFFFFA38) // (PIOE) Output Data Status Register
  4230 +#define AT91C_PIOE_ABSR (AT91_CAST(AT91_REG *) 0xFFFFFA78) // (PIOE) AB Select Status Register
  4231 +#define AT91C_PIOE_PSR (AT91_CAST(AT91_REG *) 0xFFFFFA08) // (PIOE) PIO Status Register
  4232 +#define AT91C_PIOE_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFFA60) // (PIOE) Pull-up Disable Register
  4233 +#define AT91C_PIOE_OER (AT91_CAST(AT91_REG *) 0xFFFFFA10) // (PIOE) Output Enable Register
  4234 +#define AT91C_PIOE_OWDR (AT91_CAST(AT91_REG *) 0xFFFFFAA4) // (PIOE) Output Write Disable Register
  4235 +#define AT91C_PIOE_PER (AT91_CAST(AT91_REG *) 0xFFFFFA00) // (PIOE) PIO Enable Register
  4236 +#define AT91C_PIOE_IFSR (AT91_CAST(AT91_REG *) 0xFFFFFA28) // (PIOE) Input Filter Status Register
  4237 +#define AT91C_PIOE_IFER (AT91_CAST(AT91_REG *) 0xFFFFFA20) // (PIOE) Input Filter Enable Register
  4238 +#define AT91C_PIOE_ODR (AT91_CAST(AT91_REG *) 0xFFFFFA14) // (PIOE) Output Disable Registerr
  4239 +#define AT91C_PIOE_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFFA68) // (PIOE) Pull-up Status Register
  4240 +#define AT91C_PIOE_IFDR (AT91_CAST(AT91_REG *) 0xFFFFFA24) // (PIOE) Input Filter Disable Register
  4241 +#define AT91C_PIOE_PDSR (AT91_CAST(AT91_REG *) 0xFFFFFA3C) // (PIOE) Pin Data Status Register
  4242 +#define AT91C_PIOE_PPUER (AT91_CAST(AT91_REG *) 0xFFFFFA64) // (PIOE) Pull-up Enable Register
  4243 +#define AT91C_PIOE_IDR (AT91_CAST(AT91_REG *) 0xFFFFFA44) // (PIOE) Interrupt Disable Register
  4244 +#define AT91C_PIOE_MDDR (AT91_CAST(AT91_REG *) 0xFFFFFA54) // (PIOE) Multi-driver Disable Register
  4245 +#define AT91C_PIOE_ISR (AT91_CAST(AT91_REG *) 0xFFFFFA4C) // (PIOE) Interrupt Status Register
  4246 +#define AT91C_PIOE_OSR (AT91_CAST(AT91_REG *) 0xFFFFFA18) // (PIOE) Output Status Register
  4247 +#define AT91C_PIOE_CODR (AT91_CAST(AT91_REG *) 0xFFFFFA34) // (PIOE) Clear Output Data Register
  4248 +#define AT91C_PIOE_MDSR (AT91_CAST(AT91_REG *) 0xFFFFFA58) // (PIOE) Multi-driver Status Register
  4249 +#define AT91C_PIOE_PDR (AT91_CAST(AT91_REG *) 0xFFFFFA04) // (PIOE) PIO Disable Register
  4250 +#define AT91C_PIOE_IER (AT91_CAST(AT91_REG *) 0xFFFFFA40) // (PIOE) Interrupt Enable Register
  4251 +#define AT91C_PIOE_OWSR (AT91_CAST(AT91_REG *) 0xFFFFFAA8) // (PIOE) Output Write Status Register
  4252 +#define AT91C_PIOE_BSR (AT91_CAST(AT91_REG *) 0xFFFFFA74) // (PIOE) Select B Register
  4253 +#define AT91C_PIOE_ASR (AT91_CAST(AT91_REG *) 0xFFFFFA70) // (PIOE) Select A Register
  4254 +#define AT91C_PIOE_SODR (AT91_CAST(AT91_REG *) 0xFFFFFA30) // (PIOE) Set Output Data Register
  4255 +#define AT91C_PIOE_IMR (AT91_CAST(AT91_REG *) 0xFFFFFA48) // (PIOE) Interrupt Mask Register
  4256 +#define AT91C_PIOE_OWER (AT91_CAST(AT91_REG *) 0xFFFFFAA0) // (PIOE) Output Write Enable Register
  4257 +#define AT91C_PIOE_MDER (AT91_CAST(AT91_REG *) 0xFFFFFA50) // (PIOE) Multi-driver Enable Register
  4258 +// ========== Register definition for CKGR peripheral ==========
  4259 +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
  4260 +#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register
  4261 +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
  4262 +#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register
  4263 +// ========== Register definition for PMC peripheral ==========
  4264 +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
  4265 +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
  4266 +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
  4267 +#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
  4268 +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
  4269 +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
  4270 +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
  4271 +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
  4272 +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
  4273 +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
  4274 +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
  4275 +#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
  4276 +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
  4277 +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
  4278 +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
  4279 +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
  4280 +// ========== Register definition for RSTC peripheral ==========
  4281 +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
  4282 +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
  4283 +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
  4284 +// ========== Register definition for SHDWC peripheral ==========
  4285 +#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register
  4286 +#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register
  4287 +#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register
  4288 +// ========== Register definition for RTTC0 peripheral ==========
  4289 +#define AT91C_RTTC0_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC0) Real-time Status Register
  4290 +#define AT91C_RTTC0_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC0) Real-time Mode Register
  4291 +#define AT91C_RTTC0_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC0) Real-time Value Register
  4292 +#define AT91C_RTTC0_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC0) Real-time Alarm Register
  4293 +// ========== Register definition for RTTC1 peripheral ==========
  4294 +#define AT91C_RTTC1_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD54) // (RTTC1) Real-time Alarm Register
  4295 +#define AT91C_RTTC1_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD5C) // (RTTC1) Real-time Status Register
  4296 +#define AT91C_RTTC1_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD58) // (RTTC1) Real-time Value Register
  4297 +#define AT91C_RTTC1_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD50) // (RTTC1) Real-time Mode Register
  4298 +// ========== Register definition for PITC peripheral ==========
  4299 +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
  4300 +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
  4301 +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
  4302 +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
  4303 +// ========== Register definition for WDTC peripheral ==========
  4304 +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
  4305 +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
  4306 +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
  4307 +// ========== Register definition for TC0 peripheral ==========
  4308 +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFF7C024) // (TC0) Interrupt Enable Register
  4309 +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFF7C02C) // (TC0) Interrupt Mask Register
  4310 +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFF7C000) // (TC0) Channel Control Register
  4311 +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFF7C018) // (TC0) Register B
  4312 +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFF7C010) // (TC0) Counter Value
  4313 +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFF7C020) // (TC0) Status Register
  4314 +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFF7C004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
  4315 +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFF7C014) // (TC0) Register A
  4316 +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFF7C01C) // (TC0) Register C
  4317 +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFF7C028) // (TC0) Interrupt Disable Register
  4318 +// ========== Register definition for TC1 peripheral ==========
  4319 +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFF7C064) // (TC1) Interrupt Enable Register
  4320 +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFF7C060) // (TC1) Status Register
  4321 +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFF7C05C) // (TC1) Register C
  4322 +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFF7C050) // (TC1) Counter Value
  4323 +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFF7C054) // (TC1) Register A
  4324 +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFF7C044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
  4325 +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFF7C068) // (TC1) Interrupt Disable Register
  4326 +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFF7C058) // (TC1) Register B
  4327 +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFF7C06C) // (TC1) Interrupt Mask Register
  4328 +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFF7C040) // (TC1) Channel Control Register
  4329 +// ========== Register definition for TC2 peripheral ==========
  4330 +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFF7C0A0) // (TC2) Status Register
  4331 +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFF7C0AC) // (TC2) Interrupt Mask Register
  4332 +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFF7C0A4) // (TC2) Interrupt Enable Register
  4333 +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFF7C090) // (TC2) Counter Value
  4334 +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFF7C098) // (TC2) Register B
  4335 +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFF7C080) // (TC2) Channel Control Register
  4336 +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFF7C084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
  4337 +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFF7C094) // (TC2) Register A
  4338 +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFF7C0A8) // (TC2) Interrupt Disable Register
  4339 +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFF7C09C) // (TC2) Register C
  4340 +// ========== Register definition for TCB0 peripheral ==========
  4341 +#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFF7C0C0) // (TCB0) TC Block Control Register
  4342 +#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFF7C0C4) // (TCB0) TC Block Mode Register
  4343 +// ========== Register definition for TCB1 peripheral ==========
  4344 +#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFF7C104) // (TCB1) TC Block Mode Register
  4345 +#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFF7C100) // (TCB1) TC Block Control Register
  4346 +// ========== Register definition for TCB2 peripheral ==========
  4347 +#define AT91C_TCB2_BCR (AT91_CAST(AT91_REG *) 0xFFF7C140) // (TCB2) TC Block Control Register
  4348 +#define AT91C_TCB2_BMR (AT91_CAST(AT91_REG *) 0xFFF7C144) // (TCB2) TC Block Mode Register
  4349 +// ========== Register definition for PDC_MCI0 peripheral ==========
  4350 +#define AT91C_MCI0_TCR (AT91_CAST(AT91_REG *) 0xFFF8010C) // (PDC_MCI0) Transmit Counter Register
  4351 +#define AT91C_MCI0_TNCR (AT91_CAST(AT91_REG *) 0xFFF8011C) // (PDC_MCI0) Transmit Next Counter Register
  4352 +#define AT91C_MCI0_RNPR (AT91_CAST(AT91_REG *) 0xFFF80110) // (PDC_MCI0) Receive Next Pointer Register
  4353 +#define AT91C_MCI0_TPR (AT91_CAST(AT91_REG *) 0xFFF80108) // (PDC_MCI0) Transmit Pointer Register
  4354 +#define AT91C_MCI0_TNPR (AT91_CAST(AT91_REG *) 0xFFF80118) // (PDC_MCI0) Transmit Next Pointer Register
  4355 +#define AT91C_MCI0_PTSR (AT91_CAST(AT91_REG *) 0xFFF80124) // (PDC_MCI0) PDC Transfer Status Register
  4356 +#define AT91C_MCI0_RCR (AT91_CAST(AT91_REG *) 0xFFF80104) // (PDC_MCI0) Receive Counter Register
  4357 +#define AT91C_MCI0_PTCR (AT91_CAST(AT91_REG *) 0xFFF80120) // (PDC_MCI0) PDC Transfer Control Register
  4358 +#define AT91C_MCI0_RPR (AT91_CAST(AT91_REG *) 0xFFF80100) // (PDC_MCI0) Receive Pointer Register
  4359 +#define AT91C_MCI0_RNCR (AT91_CAST(AT91_REG *) 0xFFF80114) // (PDC_MCI0) Receive Next Counter Register
  4360 +// ========== Register definition for MCI0 peripheral ==========
  4361 +#define AT91C_MCI0_CMDR (AT91_CAST(AT91_REG *) 0xFFF80014) // (MCI0) MCI Command Register
  4362 +#define AT91C_MCI0_IMR (AT91_CAST(AT91_REG *) 0xFFF8004C) // (MCI0) MCI Interrupt Mask Register
  4363 +#define AT91C_MCI0_MR (AT91_CAST(AT91_REG *) 0xFFF80004) // (MCI0) MCI Mode Register
  4364 +#define AT91C_MCI0_CR (AT91_CAST(AT91_REG *) 0xFFF80000) // (MCI0) MCI Control Register
  4365 +#define AT91C_MCI0_IER (AT91_CAST(AT91_REG *) 0xFFF80044) // (MCI0) MCI Interrupt Enable Register
  4366 +#define AT91C_MCI0_RDR (AT91_CAST(AT91_REG *) 0xFFF80030) // (MCI0) MCI Receive Data Register
  4367 +#define AT91C_MCI0_SR (AT91_CAST(AT91_REG *) 0xFFF80040) // (MCI0) MCI Status Register
  4368 +#define AT91C_MCI0_DTOR (AT91_CAST(AT91_REG *) 0xFFF80008) // (MCI0) MCI Data Timeout Register
  4369 +#define AT91C_MCI0_SDCR (AT91_CAST(AT91_REG *) 0xFFF8000C) // (MCI0) MCI SD Card Register
  4370 +#define AT91C_MCI0_BLKR (AT91_CAST(AT91_REG *) 0xFFF80018) // (MCI0) MCI Block Register
  4371 +#define AT91C_MCI0_VR (AT91_CAST(AT91_REG *) 0xFFF800FC) // (MCI0) MCI Version Register
  4372 +#define AT91C_MCI0_TDR (AT91_CAST(AT91_REG *) 0xFFF80034) // (MCI0) MCI Transmit Data Register
  4373 +#define AT91C_MCI0_ARGR (AT91_CAST(AT91_REG *) 0xFFF80010) // (MCI0) MCI Argument Register
  4374 +#define AT91C_MCI0_RSPR (AT91_CAST(AT91_REG *) 0xFFF80020) // (MCI0) MCI Response Register
  4375 +#define AT91C_MCI0_IDR (AT91_CAST(AT91_REG *) 0xFFF80048) // (MCI0) MCI Interrupt Disable Register
  4376 +// ========== Register definition for PDC_MCI1 peripheral ==========
  4377 +#define AT91C_MCI1_PTCR (AT91_CAST(AT91_REG *) 0xFFF84120) // (PDC_MCI1) PDC Transfer Control Register
  4378 +#define AT91C_MCI1_PTSR (AT91_CAST(AT91_REG *) 0xFFF84124) // (PDC_MCI1) PDC Transfer Status Register
  4379 +#define AT91C_MCI1_TPR (AT91_CAST(AT91_REG *) 0xFFF84108) // (PDC_MCI1) Transmit Pointer Register
  4380 +#define AT91C_MCI1_RPR (AT91_CAST(AT91_REG *) 0xFFF84100) // (PDC_MCI1) Receive Pointer Register
  4381 +#define AT91C_MCI1_TNCR (AT91_CAST(AT91_REG *) 0xFFF8411C) // (PDC_MCI1) Transmit Next Counter Register
  4382 +#define AT91C_MCI1_RCR (AT91_CAST(AT91_REG *) 0xFFF84104) // (PDC_MCI1) Receive Counter Register
  4383 +#define AT91C_MCI1_TNPR (AT91_CAST(AT91_REG *) 0xFFF84118) // (PDC_MCI1) Transmit Next Pointer Register
  4384 +#define AT91C_MCI1_TCR (AT91_CAST(AT91_REG *) 0xFFF8410C) // (PDC_MCI1) Transmit Counter Register
  4385 +#define AT91C_MCI1_RNPR (AT91_CAST(AT91_REG *) 0xFFF84110) // (PDC_MCI1) Receive Next Pointer Register
  4386 +#define AT91C_MCI1_RNCR (AT91_CAST(AT91_REG *) 0xFFF84114) // (PDC_MCI1) Receive Next Counter Register
  4387 +// ========== Register definition for MCI1 peripheral ==========
  4388 +#define AT91C_MCI1_SR (AT91_CAST(AT91_REG *) 0xFFF84040) // (MCI1) MCI Status Register
  4389 +#define AT91C_MCI1_RDR (AT91_CAST(AT91_REG *) 0xFFF84030) // (MCI1) MCI Receive Data Register
  4390 +#define AT91C_MCI1_RSPR (AT91_CAST(AT91_REG *) 0xFFF84020) // (MCI1) MCI Response Register
  4391 +#define AT91C_MCI1_CMDR (AT91_CAST(AT91_REG *) 0xFFF84014) // (MCI1) MCI Command Register
  4392 +#define AT91C_MCI1_IMR (AT91_CAST(AT91_REG *) 0xFFF8404C) // (MCI1) MCI Interrupt Mask Register
  4393 +#define AT91C_MCI1_DTOR (AT91_CAST(AT91_REG *) 0xFFF84008) // (MCI1) MCI Data Timeout Register
  4394 +#define AT91C_MCI1_SDCR (AT91_CAST(AT91_REG *) 0xFFF8400C) // (MCI1) MCI SD Card Register
  4395 +#define AT91C_MCI1_IDR (AT91_CAST(AT91_REG *) 0xFFF84048) // (MCI1) MCI Interrupt Disable Register
  4396 +#define AT91C_MCI1_ARGR (AT91_CAST(AT91_REG *) 0xFFF84010) // (MCI1) MCI Argument Register
  4397 +#define AT91C_MCI1_TDR (AT91_CAST(AT91_REG *) 0xFFF84034) // (MCI1) MCI Transmit Data Register
  4398 +#define AT91C_MCI1_BLKR (AT91_CAST(AT91_REG *) 0xFFF84018) // (MCI1) MCI Block Register
  4399 +#define AT91C_MCI1_VR (AT91_CAST(AT91_REG *) 0xFFF840FC) // (MCI1) MCI Version Register
  4400 +#define AT91C_MCI1_CR (AT91_CAST(AT91_REG *) 0xFFF84000) // (MCI1) MCI Control Register
  4401 +#define AT91C_MCI1_MR (AT91_CAST(AT91_REG *) 0xFFF84004) // (MCI1) MCI Mode Register
  4402 +#define AT91C_MCI1_IER (AT91_CAST(AT91_REG *) 0xFFF84044) // (MCI1) MCI Interrupt Enable Register
  4403 +// ========== Register definition for TWI peripheral ==========
  4404 +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFF88028) // (TWI) Interrupt Disable Register
  4405 +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFF88030) // (TWI) Receive Holding Register
  4406 +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFF8802C) // (TWI) Interrupt Mask Register
  4407 +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFF88034) // (TWI) Transmit Holding Register
  4408 +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFF88024) // (TWI) Interrupt Enable Register
  4409 +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFF8800C) // (TWI) Internal Address Register
  4410 +#define AT91C_TWI_SMR (AT91_CAST(AT91_REG *) 0xFFF88008) // (TWI) Slave Mode Register
  4411 +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFF88004) // (TWI) Master Mode Register
  4412 +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFF88000) // (TWI) Control Register
  4413 +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFF88020) // (TWI) Status Register
  4414 +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFF88010) // (TWI) Clock Waveform Generator Register
  4415 +// ========== Register definition for PDC_US0 peripheral ==========
  4416 +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFF8C118) // (PDC_US0) Transmit Next Pointer Register
  4417 +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFF8C124) // (PDC_US0) PDC Transfer Status Register
  4418 +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFF8C120) // (PDC_US0) PDC Transfer Control Register
  4419 +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFF8C114) // (PDC_US0) Receive Next Counter Register
  4420 +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFF8C104) // (PDC_US0) Receive Counter Register
  4421 +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFF8C11C) // (PDC_US0) Transmit Next Counter Register
  4422 +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFF8C10C) // (PDC_US0) Transmit Counter Register
  4423 +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFF8C110) // (PDC_US0) Receive Next Pointer Register
  4424 +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFF8C100) // (PDC_US0) Receive Pointer Register
  4425 +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFF8C108) // (PDC_US0) Transmit Pointer Register
  4426 +// ========== Register definition for US0 peripheral ==========
  4427 +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFF8C024) // (US0) Receiver Time-out Register
  4428 +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFF8C044) // (US0) Nb Errors Register
  4429 +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFF8C01C) // (US0) Transmitter Holding Register
  4430 +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFF8C004) // (US0) Mode Register
  4431 +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFF8C018) // (US0) Receiver Holding Register
  4432 +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFF8C014) // (US0) Channel Status Register
  4433 +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFF8C010) // (US0) Interrupt Mask Register
  4434 +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFF8C00C) // (US0) Interrupt Disable Register
  4435 +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFF8C040) // (US0) FI_DI_Ratio Register
  4436 +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFF8C000) // (US0) Control Register
  4437 +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFF8C008) // (US0) Interrupt Enable Register
  4438 +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFF8C028) // (US0) Transmitter Time-guard Register
  4439 +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFF8C020) // (US0) Baud Rate Generator Register
  4440 +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFF8C04C) // (US0) IRDA_FILTER Register
  4441 +// ========== Register definition for PDC_US1 peripheral ==========
  4442 +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFF90120) // (PDC_US1) PDC Transfer Control Register
  4443 +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFF9011C) // (PDC_US1) Transmit Next Counter Register
  4444 +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFF90104) // (PDC_US1) Receive Counter Register
  4445 +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFF90100) // (PDC_US1) Receive Pointer Register
  4446 +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFF90108) // (PDC_US1) Transmit Pointer Register
  4447 +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFF9010C) // (PDC_US1) Transmit Counter Register
  4448 +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFF90110) // (PDC_US1) Receive Next Pointer Register
  4449 +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFF90118) // (PDC_US1) Transmit Next Pointer Register
  4450 +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFF90114) // (PDC_US1) Receive Next Counter Register
  4451 +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFF90124) // (PDC_US1) PDC Transfer Status Register
  4452 +// ========== Register definition for US1 peripheral ==========
  4453 +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFF90044) // (US1) Nb Errors Register
  4454 +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFF90018) // (US1) Receiver Holding Register
  4455 +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFF90024) // (US1) Receiver Time-out Register
  4456 +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFF90008) // (US1) Interrupt Enable Register
  4457 +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFF9004C) // (US1) IRDA_FILTER Register
  4458 +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFF90000) // (US1) Control Register
  4459 +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFF90010) // (US1) Interrupt Mask Register
  4460 +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFF90028) // (US1) Transmitter Time-guard Register
  4461 +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFF90004) // (US1) Mode Register
  4462 +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFF9000C) // (US1) Interrupt Disable Register
  4463 +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFF90040) // (US1) FI_DI_Ratio Register
  4464 +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFF90014) // (US1) Channel Status Register
  4465 +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFF9001C) // (US1) Transmitter Holding Register
  4466 +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFF90020) // (US1) Baud Rate Generator Register
  4467 +// ========== Register definition for PDC_US2 peripheral ==========
  4468 +#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFF94114) // (PDC_US2) Receive Next Counter Register
  4469 +#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFF94120) // (PDC_US2) PDC Transfer Control Register
  4470 +#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFF94118) // (PDC_US2) Transmit Next Pointer Register
  4471 +#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFF9411C) // (PDC_US2) Transmit Next Counter Register
  4472 +#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFF94108) // (PDC_US2) Transmit Pointer Register
  4473 +#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFF94104) // (PDC_US2) Receive Counter Register
  4474 +#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFF94124) // (PDC_US2) PDC Transfer Status Register
  4475 +#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFF9410C) // (PDC_US2) Transmit Counter Register
  4476 +#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFF94100) // (PDC_US2) Receive Pointer Register
  4477 +#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFF94110) // (PDC_US2) Receive Next Pointer Register
  4478 +// ========== Register definition for US2 peripheral ==========
  4479 +#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFF94028) // (US2) Transmitter Time-guard Register
  4480 +#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFF94018) // (US2) Receiver Holding Register
  4481 +#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFF94010) // (US2) Interrupt Mask Register
  4482 +#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFF94008) // (US2) Interrupt Enable Register
  4483 +#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFF94044) // (US2) Nb Errors Register
  4484 +#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFF94000) // (US2) Control Register
  4485 +#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFF94040) // (US2) FI_DI_Ratio Register
  4486 +#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFF94004) // (US2) Mode Register
  4487 +#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFF9400C) // (US2) Interrupt Disable Register
  4488 +#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFF9401C) // (US2) Transmitter Holding Register
  4489 +#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFF9404C) // (US2) IRDA_FILTER Register
  4490 +#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFF94020) // (US2) Baud Rate Generator Register
  4491 +#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFF94014) // (US2) Channel Status Register
  4492 +#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFF94024) // (US2) Receiver Time-out Register
  4493 +// ========== Register definition for PDC_SSC0 peripheral ==========
  4494 +#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFF98124) // (PDC_SSC0) PDC Transfer Status Register
  4495 +#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFF9810C) // (PDC_SSC0) Transmit Counter Register
  4496 +#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFF98110) // (PDC_SSC0) Receive Next Pointer Register
  4497 +#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFF98114) // (PDC_SSC0) Receive Next Counter Register
  4498 +#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFF98118) // (PDC_SSC0) Transmit Next Pointer Register
  4499 +#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFF98100) // (PDC_SSC0) Receive Pointer Register
  4500 +#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFF98108) // (PDC_SSC0) Transmit Pointer Register
  4501 +#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFF98104) // (PDC_SSC0) Receive Counter Register
  4502 +#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFF9811C) // (PDC_SSC0) Transmit Next Counter Register
  4503 +#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFF98120) // (PDC_SSC0) PDC Transfer Control Register
  4504 +// ========== Register definition for SSC0 peripheral ==========
  4505 +#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFF98014) // (SSC0) Receive Frame Mode Register
  4506 +#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFF98020) // (SSC0) Receive Holding Register
  4507 +#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFF98024) // (SSC0) Transmit Holding Register
  4508 +#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFF98004) // (SSC0) Clock Mode Register
  4509 +#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFF9804C) // (SSC0) Interrupt Mask Register
  4510 +#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFF98048) // (SSC0) Interrupt Disable Register
  4511 +#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFF98044) // (SSC0) Interrupt Enable Register
  4512 +#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFF98034) // (SSC0) Transmit Sync Holding Register
  4513 +#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFF98040) // (SSC0) Status Register
  4514 +#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFF98000) // (SSC0) Control Register
  4515 +#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFF98010) // (SSC0) Receive Clock ModeRegister
  4516 +#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFF9801C) // (SSC0) Transmit Frame Mode Register
  4517 +#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFF98030) // (SSC0) Receive Sync Holding Register
  4518 +#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFF98018) // (SSC0) Transmit Clock Mode Register
  4519 +// ========== Register definition for PDC_SSC1 peripheral ==========
  4520 +#define AT91C_SSC1_TNPR (AT91_CAST(AT91_REG *) 0xFFF9C118) // (PDC_SSC1) Transmit Next Pointer Register
  4521 +#define AT91C_SSC1_PTSR (AT91_CAST(AT91_REG *) 0xFFF9C124) // (PDC_SSC1) PDC Transfer Status Register
  4522 +#define AT91C_SSC1_TNCR (AT91_CAST(AT91_REG *) 0xFFF9C11C) // (PDC_SSC1) Transmit Next Counter Register
  4523 +#define AT91C_SSC1_RNCR (AT91_CAST(AT91_REG *) 0xFFF9C114) // (PDC_SSC1) Receive Next Counter Register
  4524 +#define AT91C_SSC1_TPR (AT91_CAST(AT91_REG *) 0xFFF9C108) // (PDC_SSC1) Transmit Pointer Register
  4525 +#define AT91C_SSC1_RCR (AT91_CAST(AT91_REG *) 0xFFF9C104) // (PDC_SSC1) Receive Counter Register
  4526 +#define AT91C_SSC1_PTCR (AT91_CAST(AT91_REG *) 0xFFF9C120) // (PDC_SSC1) PDC Transfer Control Register
  4527 +#define AT91C_SSC1_RNPR (AT91_CAST(AT91_REG *) 0xFFF9C110) // (PDC_SSC1) Receive Next Pointer Register
  4528 +#define AT91C_SSC1_TCR (AT91_CAST(AT91_REG *) 0xFFF9C10C) // (PDC_SSC1) Transmit Counter Register
  4529 +#define AT91C_SSC1_RPR (AT91_CAST(AT91_REG *) 0xFFF9C100) // (PDC_SSC1) Receive Pointer Register
  4530 +// ========== Register definition for SSC1 peripheral ==========
  4531 +#define AT91C_SSC1_CMR (AT91_CAST(AT91_REG *) 0xFFF9C004) // (SSC1) Clock Mode Register
  4532 +#define AT91C_SSC1_SR (AT91_CAST(AT91_REG *) 0xFFF9C040) // (SSC1) Status Register
  4533 +#define AT91C_SSC1_TSHR (AT91_CAST(AT91_REG *) 0xFFF9C034) // (SSC1) Transmit Sync Holding Register
  4534 +#define AT91C_SSC1_TCMR (AT91_CAST(AT91_REG *) 0xFFF9C018) // (SSC1) Transmit Clock Mode Register
  4535 +#define AT91C_SSC1_IMR (AT91_CAST(AT91_REG *) 0xFFF9C04C) // (SSC1) Interrupt Mask Register
  4536 +#define AT91C_SSC1_IDR (AT91_CAST(AT91_REG *) 0xFFF9C048) // (SSC1) Interrupt Disable Register
  4537 +#define AT91C_SSC1_RCMR (AT91_CAST(AT91_REG *) 0xFFF9C010) // (SSC1) Receive Clock ModeRegister
  4538 +#define AT91C_SSC1_IER (AT91_CAST(AT91_REG *) 0xFFF9C044) // (SSC1) Interrupt Enable Register
  4539 +#define AT91C_SSC1_RSHR (AT91_CAST(AT91_REG *) 0xFFF9C030) // (SSC1) Receive Sync Holding Register
  4540 +#define AT91C_SSC1_CR (AT91_CAST(AT91_REG *) 0xFFF9C000) // (SSC1) Control Register
  4541 +#define AT91C_SSC1_RHR (AT91_CAST(AT91_REG *) 0xFFF9C020) // (SSC1) Receive Holding Register
  4542 +#define AT91C_SSC1_THR (AT91_CAST(AT91_REG *) 0xFFF9C024) // (SSC1) Transmit Holding Register
  4543 +#define AT91C_SSC1_RFMR (AT91_CAST(AT91_REG *) 0xFFF9C014) // (SSC1) Receive Frame Mode Register
  4544 +#define AT91C_SSC1_TFMR (AT91_CAST(AT91_REG *) 0xFFF9C01C) // (SSC1) Transmit Frame Mode Register
  4545 +// ========== Register definition for PDC_AC97C peripheral ==========
  4546 +#define AT91C_AC97C_RNPR (AT91_CAST(AT91_REG *) 0xFFFA0110) // (PDC_AC97C) Receive Next Pointer Register
  4547 +#define AT91C_AC97C_TCR (AT91_CAST(AT91_REG *) 0xFFFA010C) // (PDC_AC97C) Transmit Counter Register
  4548 +#define AT91C_AC97C_TNCR (AT91_CAST(AT91_REG *) 0xFFFA011C) // (PDC_AC97C) Transmit Next Counter Register
  4549 +#define AT91C_AC97C_RCR (AT91_CAST(AT91_REG *) 0xFFFA0104) // (PDC_AC97C) Receive Counter Register
  4550 +#define AT91C_AC97C_RNCR (AT91_CAST(AT91_REG *) 0xFFFA0114) // (PDC_AC97C) Receive Next Counter Register
  4551 +#define AT91C_AC97C_PTCR (AT91_CAST(AT91_REG *) 0xFFFA0120) // (PDC_AC97C) PDC Transfer Control Register
  4552 +#define AT91C_AC97C_TPR (AT91_CAST(AT91_REG *) 0xFFFA0108) // (PDC_AC97C) Transmit Pointer Register
  4553 +#define AT91C_AC97C_RPR (AT91_CAST(AT91_REG *) 0xFFFA0100) // (PDC_AC97C) Receive Pointer Register
  4554 +#define AT91C_AC97C_PTSR (AT91_CAST(AT91_REG *) 0xFFFA0124) // (PDC_AC97C) PDC Transfer Status Register
  4555 +#define AT91C_AC97C_TNPR (AT91_CAST(AT91_REG *) 0xFFFA0118) // (PDC_AC97C) Transmit Next Pointer Register
  4556 +// ========== Register definition for AC97C peripheral ==========
  4557 +#define AT91C_AC97C_CORHR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (AC97C) COdec Transmit Holding Register
  4558 +#define AT91C_AC97C_MR (AT91_CAST(AT91_REG *) 0xFFFA0008) // (AC97C) Mode Register
  4559 +#define AT91C_AC97C_CATHR (AT91_CAST(AT91_REG *) 0xFFFA0024) // (AC97C) Channel A Transmit Holding Register
  4560 +#define AT91C_AC97C_IER (AT91_CAST(AT91_REG *) 0xFFFA0054) // (AC97C) Interrupt Enable Register
  4561 +#define AT91C_AC97C_CASR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (AC97C) Channel A Status Register
  4562 +#define AT91C_AC97C_CBTHR (AT91_CAST(AT91_REG *) 0xFFFA0034) // (AC97C) Channel B Transmit Holding Register (optional)
  4563 +#define AT91C_AC97C_ICA (AT91_CAST(AT91_REG *) 0xFFFA0010) // (AC97C) Input Channel AssignementRegister
  4564 +#define AT91C_AC97C_IMR (AT91_CAST(AT91_REG *) 0xFFFA005C) // (AC97C) Interrupt Mask Register
  4565 +#define AT91C_AC97C_IDR (AT91_CAST(AT91_REG *) 0xFFFA0058) // (AC97C) Interrupt Disable Register
  4566 +#define AT91C_AC97C_CARHR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (AC97C) Channel A Receive Holding Register
  4567 +#define AT91C_AC97C_VERSION (AT91_CAST(AT91_REG *) 0xFFFA00FC) // (AC97C) Version Register
  4568 +#define AT91C_AC97C_CBRHR (AT91_CAST(AT91_REG *) 0xFFFA0030) // (AC97C) Channel B Receive Holding Register (optional)
  4569 +#define AT91C_AC97C_COTHR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (AC97C) COdec Transmit Holding Register
  4570 +#define AT91C_AC97C_OCA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (AC97C) Output Channel Assignement Register
  4571 +#define AT91C_AC97C_CBMR (AT91_CAST(AT91_REG *) 0xFFFA003C) // (AC97C) Channel B Mode Register
  4572 +#define AT91C_AC97C_COMR (AT91_CAST(AT91_REG *) 0xFFFA004C) // (AC97C) CODEC Mask Status Register
  4573 +#define AT91C_AC97C_CBSR (AT91_CAST(AT91_REG *) 0xFFFA0038) // (AC97C) Channel B Status Register
  4574 +#define AT91C_AC97C_COSR (AT91_CAST(AT91_REG *) 0xFFFA0048) // (AC97C) CODEC Status Register
  4575 +#define AT91C_AC97C_CAMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (AC97C) Channel A Mode Register
  4576 +#define AT91C_AC97C_SR (AT91_CAST(AT91_REG *) 0xFFFA0050) // (AC97C) Status Register
  4577 +// ========== Register definition for PDC_SPI0 peripheral ==========
  4578 +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFA4108) // (PDC_SPI0) Transmit Pointer Register
  4579 +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFA4120) // (PDC_SPI0) PDC Transfer Control Register
  4580 +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFA4110) // (PDC_SPI0) Receive Next Pointer Register
  4581 +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFA411C) // (PDC_SPI0) Transmit Next Counter Register
  4582 +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFA410C) // (PDC_SPI0) Transmit Counter Register
  4583 +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFA4104) // (PDC_SPI0) Receive Counter Register
  4584 +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFA4114) // (PDC_SPI0) Receive Next Counter Register
  4585 +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFA4118) // (PDC_SPI0) Transmit Next Pointer Register
  4586 +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFA4100) // (PDC_SPI0) Receive Pointer Register
  4587 +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFA4124) // (PDC_SPI0) PDC Transfer Status Register
  4588 +// ========== Register definition for SPI0 peripheral ==========
  4589 +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFA4004) // (SPI0) Mode Register
  4590 +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (SPI0) Receive Data Register
  4591 +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFA4000) // (SPI0) Control Register
  4592 +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFA4014) // (SPI0) Interrupt Enable Register
  4593 +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFA400C) // (SPI0) Transmit Data Register
  4594 +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (SPI0) Interrupt Disable Register
  4595 +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (SPI0) Chip Select Register
  4596 +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFA4010) // (SPI0) Status Register
  4597 +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (SPI0) Interrupt Mask Register
  4598 +// ========== Register definition for PDC_SPI1 peripheral ==========
  4599 +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_SPI1) Receive Next Counter Register
  4600 +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_SPI1) Transmit Counter Register
  4601 +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_SPI1) Receive Counter Register
  4602 +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_SPI1) Transmit Next Pointer Register
  4603 +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_SPI1) Receive Next Pointer Register
  4604 +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_SPI1) Receive Pointer Register
  4605 +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_SPI1) Transmit Next Counter Register
  4606 +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_SPI1) Transmit Pointer Register
  4607 +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_SPI1) PDC Transfer Status Register
  4608 +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_SPI1) PDC Transfer Control Register
  4609 +// ========== Register definition for SPI1 peripheral ==========
  4610 +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (SPI1) Chip Select Register
  4611 +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFA8014) // (SPI1) Interrupt Enable Register
  4612 +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (SPI1) Receive Data Register
  4613 +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (SPI1) Interrupt Disable Register
  4614 +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (SPI1) Mode Register
  4615 +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (SPI1) Control Register
  4616 +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (SPI1) Status Register
  4617 +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (SPI1) Transmit Data Register
  4618 +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFA801C) // (SPI1) Interrupt Mask Register
  4619 +// ========== Register definition for CAN_MB0 peripheral ==========
  4620 +#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFAC208) // (CAN_MB0) MailBox ID Register
  4621 +#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFAC20C) // (CAN_MB0) MailBox Family ID Register
  4622 +#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFAC204) // (CAN_MB0) MailBox Acceptance Mask Register
  4623 +#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFAC21C) // (CAN_MB0) MailBox Control Register
  4624 +#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFAC200) // (CAN_MB0) MailBox Mode Register
  4625 +#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFAC214) // (CAN_MB0) MailBox Data Low Register
  4626 +#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFAC218) // (CAN_MB0) MailBox Data High Register
  4627 +#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFAC210) // (CAN_MB0) MailBox Status Register
  4628 +// ========== Register definition for CAN_MB1 peripheral ==========
  4629 +#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFAC234) // (CAN_MB1) MailBox Data Low Register
  4630 +#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFAC224) // (CAN_MB1) MailBox Acceptance Mask Register
  4631 +#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFAC228) // (CAN_MB1) MailBox ID Register
  4632 +#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFAC220) // (CAN_MB1) MailBox Mode Register
  4633 +#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFAC23C) // (CAN_MB1) MailBox Control Register
  4634 +#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFAC22C) // (CAN_MB1) MailBox Family ID Register
  4635 +#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFAC230) // (CAN_MB1) MailBox Status Register
  4636 +#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFAC238) // (CAN_MB1) MailBox Data High Register
  4637 +// ========== Register definition for CAN_MB2 peripheral ==========
  4638 +#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFAC248) // (CAN_MB2) MailBox ID Register
  4639 +#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFAC250) // (CAN_MB2) MailBox Status Register
  4640 +#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFAC254) // (CAN_MB2) MailBox Data Low Register
  4641 +#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFAC25C) // (CAN_MB2) MailBox Control Register
  4642 +#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFAC258) // (CAN_MB2) MailBox Data High Register
  4643 +#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFAC244) // (CAN_MB2) MailBox Acceptance Mask Register
  4644 +#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFAC240) // (CAN_MB2) MailBox Mode Register
  4645 +#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFAC24C) // (CAN_MB2) MailBox Family ID Register
  4646 +// ========== Register definition for CAN_MB3 peripheral ==========
  4647 +#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFAC274) // (CAN_MB3) MailBox Data Low Register
  4648 +#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFAC26C) // (CAN_MB3) MailBox Family ID Register
  4649 +#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFAC268) // (CAN_MB3) MailBox ID Register
  4650 +#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFAC278) // (CAN_MB3) MailBox Data High Register
  4651 +#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFAC264) // (CAN_MB3) MailBox Acceptance Mask Register
  4652 +#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFAC260) // (CAN_MB3) MailBox Mode Register
  4653 +#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFAC27C) // (CAN_MB3) MailBox Control Register
  4654 +#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFAC270) // (CAN_MB3) MailBox Status Register
  4655 +// ========== Register definition for CAN_MB4 peripheral ==========
  4656 +#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFAC29C) // (CAN_MB4) MailBox Control Register
  4657 +#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFAC298) // (CAN_MB4) MailBox Data High Register
  4658 +#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFAC288) // (CAN_MB4) MailBox ID Register
  4659 +#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFAC280) // (CAN_MB4) MailBox Mode Register
  4660 +#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFAC290) // (CAN_MB4) MailBox Status Register
  4661 +#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFAC28C) // (CAN_MB4) MailBox Family ID Register
  4662 +#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFAC284) // (CAN_MB4) MailBox Acceptance Mask Register
  4663 +#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFAC294) // (CAN_MB4) MailBox Data Low Register
  4664 +// ========== Register definition for CAN_MB5 peripheral ==========
  4665 +#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFAC2B8) // (CAN_MB5) MailBox Data High Register
  4666 +#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFAC2A8) // (CAN_MB5) MailBox ID Register
  4667 +#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFAC2BC) // (CAN_MB5) MailBox Control Register
  4668 +#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFAC2B0) // (CAN_MB5) MailBox Status Register
  4669 +#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFAC2B4) // (CAN_MB5) MailBox Data Low Register
  4670 +#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFAC2A0) // (CAN_MB5) MailBox Mode Register
  4671 +#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFAC2A4) // (CAN_MB5) MailBox Acceptance Mask Register
  4672 +#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFAC2AC) // (CAN_MB5) MailBox Family ID Register
  4673 +// ========== Register definition for CAN_MB6 peripheral ==========
  4674 +#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFAC2D0) // (CAN_MB6) MailBox Status Register
  4675 +#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFAC2C0) // (CAN_MB6) MailBox Mode Register
  4676 +#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFAC2CC) // (CAN_MB6) MailBox Family ID Register
  4677 +#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFAC2D4) // (CAN_MB6) MailBox Data Low Register
  4678 +#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFAC2C8) // (CAN_MB6) MailBox ID Register
  4679 +#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFAC2DC) // (CAN_MB6) MailBox Control Register
  4680 +#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFAC2C4) // (CAN_MB6) MailBox Acceptance Mask Register
  4681 +#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFAC2D8) // (CAN_MB6) MailBox Data High Register
  4682 +// ========== Register definition for CAN_MB7 peripheral ==========
  4683 +#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFAC2E4) // (CAN_MB7) MailBox Acceptance Mask Register
  4684 +#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFAC2F8) // (CAN_MB7) MailBox Data High Register
  4685 +#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFAC2E8) // (CAN_MB7) MailBox ID Register
  4686 +#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFAC2F0) // (CAN_MB7) MailBox Status Register
  4687 +#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFAC2E0) // (CAN_MB7) MailBox Mode Register
  4688 +#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFAC2FC) // (CAN_MB7) MailBox Control Register
  4689 +#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFAC2EC) // (CAN_MB7) MailBox Family ID Register
  4690 +#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFAC2F4) // (CAN_MB7) MailBox Data Low Register
  4691 +// ========== Register definition for CAN_MB8 peripheral ==========
  4692 +#define AT91C_CAN_MB8_MDH (AT91_CAST(AT91_REG *) 0xFFFAC318) // (CAN_MB8) MailBox Data High Register
  4693 +#define AT91C_CAN_MB8_MMR (AT91_CAST(AT91_REG *) 0xFFFAC300) // (CAN_MB8) MailBox Mode Register
  4694 +#define AT91C_CAN_MB8_MCR (AT91_CAST(AT91_REG *) 0xFFFAC31C) // (CAN_MB8) MailBox Control Register
  4695 +#define AT91C_CAN_MB8_MSR (AT91_CAST(AT91_REG *) 0xFFFAC310) // (CAN_MB8) MailBox Status Register
  4696 +#define AT91C_CAN_MB8_MAM (AT91_CAST(AT91_REG *) 0xFFFAC304) // (CAN_MB8) MailBox Acceptance Mask Register
  4697 +#define AT91C_CAN_MB8_MFID (AT91_CAST(AT91_REG *) 0xFFFAC30C) // (CAN_MB8) MailBox Family ID Register
  4698 +#define AT91C_CAN_MB8_MID (AT91_CAST(AT91_REG *) 0xFFFAC308) // (CAN_MB8) MailBox ID Register
  4699 +#define AT91C_CAN_MB8_MDL (AT91_CAST(AT91_REG *) 0xFFFAC314) // (CAN_MB8) MailBox Data Low Register
  4700 +// ========== Register definition for CAN_MB9 peripheral ==========
  4701 +#define AT91C_CAN_MB9_MID (AT91_CAST(AT91_REG *) 0xFFFAC328) // (CAN_MB9) MailBox ID Register
  4702 +#define AT91C_CAN_MB9_MMR (AT91_CAST(AT91_REG *) 0xFFFAC320) // (CAN_MB9) MailBox Mode Register
  4703 +#define AT91C_CAN_MB9_MDH (AT91_CAST(AT91_REG *) 0xFFFAC338) // (CAN_MB9) MailBox Data High Register
  4704 +#define AT91C_CAN_MB9_MSR (AT91_CAST(AT91_REG *) 0xFFFAC330) // (CAN_MB9) MailBox Status Register
  4705 +#define AT91C_CAN_MB9_MAM (AT91_CAST(AT91_REG *) 0xFFFAC324) // (CAN_MB9) MailBox Acceptance Mask Register
  4706 +#define AT91C_CAN_MB9_MDL (AT91_CAST(AT91_REG *) 0xFFFAC334) // (CAN_MB9) MailBox Data Low Register
  4707 +#define AT91C_CAN_MB9_MFID (AT91_CAST(AT91_REG *) 0xFFFAC32C) // (CAN_MB9) MailBox Family ID Register
  4708 +#define AT91C_CAN_MB9_MCR (AT91_CAST(AT91_REG *) 0xFFFAC33C) // (CAN_MB9) MailBox Control Register
  4709 +// ========== Register definition for CAN_MB10 peripheral ==========
  4710 +#define AT91C_CAN_MB10_MCR (AT91_CAST(AT91_REG *) 0xFFFAC35C) // (CAN_MB10) MailBox Control Register
  4711 +#define AT91C_CAN_MB10_MDH (AT91_CAST(AT91_REG *) 0xFFFAC358) // (CAN_MB10) MailBox Data High Register
  4712 +#define AT91C_CAN_MB10_MAM (AT91_CAST(AT91_REG *) 0xFFFAC344) // (CAN_MB10) MailBox Acceptance Mask Register
  4713 +#define AT91C_CAN_MB10_MID (AT91_CAST(AT91_REG *) 0xFFFAC348) // (CAN_MB10) MailBox ID Register
  4714 +#define AT91C_CAN_MB10_MDL (AT91_CAST(AT91_REG *) 0xFFFAC354) // (CAN_MB10) MailBox Data Low Register
  4715 +#define AT91C_CAN_MB10_MSR (AT91_CAST(AT91_REG *) 0xFFFAC350) // (CAN_MB10) MailBox Status Register
  4716 +#define AT91C_CAN_MB10_MMR (AT91_CAST(AT91_REG *) 0xFFFAC340) // (CAN_MB10) MailBox Mode Register
  4717 +#define AT91C_CAN_MB10_MFID (AT91_CAST(AT91_REG *) 0xFFFAC34C) // (CAN_MB10) MailBox Family ID Register
  4718 +// ========== Register definition for CAN_MB11 peripheral ==========
  4719 +#define AT91C_CAN_MB11_MSR (AT91_CAST(AT91_REG *) 0xFFFAC370) // (CAN_MB11) MailBox Status Register
  4720 +#define AT91C_CAN_MB11_MFID (AT91_CAST(AT91_REG *) 0xFFFAC36C) // (CAN_MB11) MailBox Family ID Register
  4721 +#define AT91C_CAN_MB11_MDL (AT91_CAST(AT91_REG *) 0xFFFAC374) // (CAN_MB11) MailBox Data Low Register
  4722 +#define AT91C_CAN_MB11_MDH (AT91_CAST(AT91_REG *) 0xFFFAC378) // (CAN_MB11) MailBox Data High Register
  4723 +#define AT91C_CAN_MB11_MID (AT91_CAST(AT91_REG *) 0xFFFAC368) // (CAN_MB11) MailBox ID Register
  4724 +#define AT91C_CAN_MB11_MCR (AT91_CAST(AT91_REG *) 0xFFFAC37C) // (CAN_MB11) MailBox Control Register
  4725 +#define AT91C_CAN_MB11_MMR (AT91_CAST(AT91_REG *) 0xFFFAC360) // (CAN_MB11) MailBox Mode Register
  4726 +#define AT91C_CAN_MB11_MAM (AT91_CAST(AT91_REG *) 0xFFFAC364) // (CAN_MB11) MailBox Acceptance Mask Register
  4727 +// ========== Register definition for CAN_MB12 peripheral ==========
  4728 +#define AT91C_CAN_MB12_MAM (AT91_CAST(AT91_REG *) 0xFFFAC384) // (CAN_MB12) MailBox Acceptance Mask Register
  4729 +#define AT91C_CAN_MB12_MDH (AT91_CAST(AT91_REG *) 0xFFFAC398) // (CAN_MB12) MailBox Data High Register
  4730 +#define AT91C_CAN_MB12_MMR (AT91_CAST(AT91_REG *) 0xFFFAC380) // (CAN_MB12) MailBox Mode Register
  4731 +#define AT91C_CAN_MB12_MSR (AT91_CAST(AT91_REG *) 0xFFFAC390) // (CAN_MB12) MailBox Status Register
  4732 +#define AT91C_CAN_MB12_MFID (AT91_CAST(AT91_REG *) 0xFFFAC38C) // (CAN_MB12) MailBox Family ID Register
  4733 +#define AT91C_CAN_MB12_MID (AT91_CAST(AT91_REG *) 0xFFFAC388) // (CAN_MB12) MailBox ID Register
  4734 +#define AT91C_CAN_MB12_MCR (AT91_CAST(AT91_REG *) 0xFFFAC39C) // (CAN_MB12) MailBox Control Register
  4735 +#define AT91C_CAN_MB12_MDL (AT91_CAST(AT91_REG *) 0xFFFAC394) // (CAN_MB12) MailBox Data Low Register
  4736 +// ========== Register definition for CAN_MB13 peripheral ==========
  4737 +#define AT91C_CAN_MB13_MDH (AT91_CAST(AT91_REG *) 0xFFFAC3B8) // (CAN_MB13) MailBox Data High Register
  4738 +#define AT91C_CAN_MB13_MFID (AT91_CAST(AT91_REG *) 0xFFFAC3AC) // (CAN_MB13) MailBox Family ID Register
  4739 +#define AT91C_CAN_MB13_MSR (AT91_CAST(AT91_REG *) 0xFFFAC3B0) // (CAN_MB13) MailBox Status Register
  4740 +#define AT91C_CAN_MB13_MID (AT91_CAST(AT91_REG *) 0xFFFAC3A8) // (CAN_MB13) MailBox ID Register
  4741 +#define AT91C_CAN_MB13_MAM (AT91_CAST(AT91_REG *) 0xFFFAC3A4) // (CAN_MB13) MailBox Acceptance Mask Register
  4742 +#define AT91C_CAN_MB13_MMR (AT91_CAST(AT91_REG *) 0xFFFAC3A0) // (CAN_MB13) MailBox Mode Register
  4743 +#define AT91C_CAN_MB13_MCR (AT91_CAST(AT91_REG *) 0xFFFAC3BC) // (CAN_MB13) MailBox Control Register
  4744 +#define AT91C_CAN_MB13_MDL (AT91_CAST(AT91_REG *) 0xFFFAC3B4) // (CAN_MB13) MailBox Data Low Register
  4745 +// ========== Register definition for CAN_MB14 peripheral ==========
  4746 +#define AT91C_CAN_MB14_MDL (AT91_CAST(AT91_REG *) 0xFFFAC3D4) // (CAN_MB14) MailBox Data Low Register
  4747 +#define AT91C_CAN_MB14_MMR (AT91_CAST(AT91_REG *) 0xFFFAC3C0) // (CAN_MB14) MailBox Mode Register
  4748 +#define AT91C_CAN_MB14_MFID (AT91_CAST(AT91_REG *) 0xFFFAC3CC) // (CAN_MB14) MailBox Family ID Register
  4749 +#define AT91C_CAN_MB14_MCR (AT91_CAST(AT91_REG *) 0xFFFAC3DC) // (CAN_MB14) MailBox Control Register
  4750 +#define AT91C_CAN_MB14_MID (AT91_CAST(AT91_REG *) 0xFFFAC3C8) // (CAN_MB14) MailBox ID Register
  4751 +#define AT91C_CAN_MB14_MDH (AT91_CAST(AT91_REG *) 0xFFFAC3D8) // (CAN_MB14) MailBox Data High Register
  4752 +#define AT91C_CAN_MB14_MSR (AT91_CAST(AT91_REG *) 0xFFFAC3D0) // (CAN_MB14) MailBox Status Register
  4753 +#define AT91C_CAN_MB14_MAM (AT91_CAST(AT91_REG *) 0xFFFAC3C4) // (CAN_MB14) MailBox Acceptance Mask Register
  4754 +// ========== Register definition for CAN_MB15 peripheral ==========
  4755 +#define AT91C_CAN_MB15_MDL (AT91_CAST(AT91_REG *) 0xFFFAC3F4) // (CAN_MB15) MailBox Data Low Register
  4756 +#define AT91C_CAN_MB15_MSR (AT91_CAST(AT91_REG *) 0xFFFAC3F0) // (CAN_MB15) MailBox Status Register
  4757 +#define AT91C_CAN_MB15_MID (AT91_CAST(AT91_REG *) 0xFFFAC3E8) // (CAN_MB15) MailBox ID Register
  4758 +#define AT91C_CAN_MB15_MAM (AT91_CAST(AT91_REG *) 0xFFFAC3E4) // (CAN_MB15) MailBox Acceptance Mask Register
  4759 +#define AT91C_CAN_MB15_MCR (AT91_CAST(AT91_REG *) 0xFFFAC3FC) // (CAN_MB15) MailBox Control Register
  4760 +#define AT91C_CAN_MB15_MFID (AT91_CAST(AT91_REG *) 0xFFFAC3EC) // (CAN_MB15) MailBox Family ID Register
  4761 +#define AT91C_CAN_MB15_MMR (AT91_CAST(AT91_REG *) 0xFFFAC3E0) // (CAN_MB15) MailBox Mode Register
  4762 +#define AT91C_CAN_MB15_MDH (AT91_CAST(AT91_REG *) 0xFFFAC3F8) // (CAN_MB15) MailBox Data High Register
  4763 +// ========== Register definition for CAN peripheral ==========
  4764 +#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (CAN) Abort Command Register
  4765 +#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFAC014) // (CAN) Baudrate Register
  4766 +#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (CAN) Interrupt Disable Register
  4767 +#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFAC01C) // (CAN) Time Stamp Register
  4768 +#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (CAN) Status Register
  4769 +#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (CAN) Interrupt Mask Register
  4770 +#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFAC024) // (CAN) Transfer Command Register
  4771 +#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFAC018) // (CAN) Timer Register
  4772 +#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFAC004) // (CAN) Interrupt Enable Register
  4773 +#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (CAN) Error Counter Register
  4774 +#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFAC0FC) // (CAN) Version Register
  4775 +#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (CAN) Mode Register
  4776 +// ========== Register definition for PWMC_CH0 peripheral ==========
  4777 +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFB820C) // (PWMC_CH0) Channel Counter Register
  4778 +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFB8208) // (PWMC_CH0) Channel Period Register
  4779 +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFB8210) // (PWMC_CH0) Channel Update Register
  4780 +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFB8204) // (PWMC_CH0) Channel Duty Cycle Register
  4781 +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFB8200) // (PWMC_CH0) Channel Mode Register
  4782 +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFB8214) // (PWMC_CH0) Reserved
  4783 +// ========== Register definition for PWMC_CH1 peripheral ==========
  4784 +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFB822C) // (PWMC_CH1) Channel Counter Register
  4785 +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFB8224) // (PWMC_CH1) Channel Duty Cycle Register
  4786 +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFB8220) // (PWMC_CH1) Channel Mode Register
  4787 +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFB8228) // (PWMC_CH1) Channel Period Register
  4788 +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFB8234) // (PWMC_CH1) Reserved
  4789 +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFB8230) // (PWMC_CH1) Channel Update Register
  4790 +// ========== Register definition for PWMC_CH2 peripheral ==========
  4791 +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFB8250) // (PWMC_CH2) Channel Update Register
  4792 +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFB8240) // (PWMC_CH2) Channel Mode Register
  4793 +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFB8254) // (PWMC_CH2) Reserved
  4794 +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFB8248) // (PWMC_CH2) Channel Period Register
  4795 +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFB8244) // (PWMC_CH2) Channel Duty Cycle Register
  4796 +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFB824C) // (PWMC_CH2) Channel Counter Register
  4797 +// ========== Register definition for PWMC_CH3 peripheral ==========
  4798 +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFB8268) // (PWMC_CH3) Channel Period Register
  4799 +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFB8274) // (PWMC_CH3) Reserved
  4800 +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFB8270) // (PWMC_CH3) Channel Update Register
  4801 +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFB8264) // (PWMC_CH3) Channel Duty Cycle Register
  4802 +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFB826C) // (PWMC_CH3) Channel Counter Register
  4803 +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFB8260) // (PWMC_CH3) Channel Mode Register
  4804 +// ========== Register definition for PWMC peripheral ==========
  4805 +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (PWMC) PWMC Interrupt Disable Register
  4806 +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (PWMC) PWMC Mode Register
  4807 +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFB80FC) // (PWMC) PWMC Version Register
  4808 +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (PWMC) PWMC Interrupt Mask Register
  4809 +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (PWMC) PWMC Status Register
  4810 +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (PWMC) PWMC Interrupt Status Register
  4811 +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFB8004) // (PWMC) PWMC Enable Register
  4812 +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFB8010) // (PWMC) PWMC Interrupt Enable Register
  4813 +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFB8008) // (PWMC) PWMC Disable Register
  4814 +// ========== Register definition for MACB peripheral ==========
  4815 +#define AT91C_MACB_ALE (AT91_CAST(AT91_REG *) 0xFFFBC054) // (MACB) Alignment Error Register
  4816 +#define AT91C_MACB_RRE (AT91_CAST(AT91_REG *) 0xFFFBC06C) // (MACB) Receive Ressource Error Register
  4817 +#define AT91C_MACB_SA4H (AT91_CAST(AT91_REG *) 0xFFFBC0B4) // (MACB) Specific Address 4 Top, Last 2 bytes
  4818 +#define AT91C_MACB_TPQ (AT91_CAST(AT91_REG *) 0xFFFBC0BC) // (MACB) Transmit Pause Quantum Register
  4819 +#define AT91C_MACB_RJA (AT91_CAST(AT91_REG *) 0xFFFBC07C) // (MACB) Receive Jabbers Register
  4820 +#define AT91C_MACB_SA2H (AT91_CAST(AT91_REG *) 0xFFFBC0A4) // (MACB) Specific Address 2 Top, Last 2 bytes
  4821 +#define AT91C_MACB_TPF (AT91_CAST(AT91_REG *) 0xFFFBC08C) // (MACB) Transmitted Pause Frames Register
  4822 +#define AT91C_MACB_ROV (AT91_CAST(AT91_REG *) 0xFFFBC070) // (MACB) Receive Overrun Errors Register
  4823 +#define AT91C_MACB_SA4L (AT91_CAST(AT91_REG *) 0xFFFBC0B0) // (MACB) Specific Address 4 Bottom, First 4 bytes
  4824 +#define AT91C_MACB_MAN (AT91_CAST(AT91_REG *) 0xFFFBC034) // (MACB) PHY Maintenance Register
  4825 +#define AT91C_MACB_TID (AT91_CAST(AT91_REG *) 0xFFFBC0B8) // (MACB) Type ID Checking Register
  4826 +#define AT91C_MACB_TBQP (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (MACB) Transmit Buffer Queue Pointer
  4827 +#define AT91C_MACB_SA3L (AT91_CAST(AT91_REG *) 0xFFFBC0A8) // (MACB) Specific Address 3 Bottom, First 4 bytes
  4828 +#define AT91C_MACB_DTF (AT91_CAST(AT91_REG *) 0xFFFBC058) // (MACB) Deferred Transmission Frame Register
  4829 +#define AT91C_MACB_PTR (AT91_CAST(AT91_REG *) 0xFFFBC038) // (MACB) Pause Time Register
  4830 +#define AT91C_MACB_CSE (AT91_CAST(AT91_REG *) 0xFFFBC068) // (MACB) Carrier Sense Error Register
  4831 +#define AT91C_MACB_ECOL (AT91_CAST(AT91_REG *) 0xFFFBC060) // (MACB) Excessive Collision Register
  4832 +#define AT91C_MACB_STE (AT91_CAST(AT91_REG *) 0xFFFBC084) // (MACB) SQE Test Error Register
  4833 +#define AT91C_MACB_MCF (AT91_CAST(AT91_REG *) 0xFFFBC048) // (MACB) Multiple Collision Frame Register
  4834 +#define AT91C_MACB_IER (AT91_CAST(AT91_REG *) 0xFFFBC028) // (MACB) Interrupt Enable Register
  4835 +#define AT91C_MACB_ELE (AT91_CAST(AT91_REG *) 0xFFFBC078) // (MACB) Excessive Length Errors Register
  4836 +#define AT91C_MACB_USRIO (AT91_CAST(AT91_REG *) 0xFFFBC0C0) // (MACB) USER Input/Output Register
  4837 +#define AT91C_MACB_PFR (AT91_CAST(AT91_REG *) 0xFFFBC03C) // (MACB) Pause Frames received Register
  4838 +#define AT91C_MACB_FCSE (AT91_CAST(AT91_REG *) 0xFFFBC050) // (MACB) Frame Check Sequence Error Register
  4839 +#define AT91C_MACB_SA1L (AT91_CAST(AT91_REG *) 0xFFFBC098) // (MACB) Specific Address 1 Bottom, First 4 bytes
  4840 +#define AT91C_MACB_NCR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (MACB) Network Control Register
  4841 +#define AT91C_MACB_HRT (AT91_CAST(AT91_REG *) 0xFFFBC094) // (MACB) Hash Address Top[63:32]
  4842 +#define AT91C_MACB_NCFGR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (MACB) Network Configuration Register
  4843 +#define AT91C_MACB_SCF (AT91_CAST(AT91_REG *) 0xFFFBC044) // (MACB) Single Collision Frame Register
  4844 +#define AT91C_MACB_LCOL (AT91_CAST(AT91_REG *) 0xFFFBC05C) // (MACB) Late Collision Register
  4845 +#define AT91C_MACB_SA3H (AT91_CAST(AT91_REG *) 0xFFFBC0AC) // (MACB) Specific Address 3 Top, Last 2 bytes
  4846 +#define AT91C_MACB_HRB (AT91_CAST(AT91_REG *) 0xFFFBC090) // (MACB) Hash Address Bottom[31:0]
  4847 +#define AT91C_MACB_ISR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (MACB) Interrupt Status Register
  4848 +#define AT91C_MACB_IMR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (MACB) Interrupt Mask Register
  4849 +#define AT91C_MACB_WOL (AT91_CAST(AT91_REG *) 0xFFFBC0C4) // (MACB) Wake On LAN Register
  4850 +#define AT91C_MACB_USF (AT91_CAST(AT91_REG *) 0xFFFBC080) // (MACB) Undersize Frames Register
  4851 +#define AT91C_MACB_TSR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (MACB) Transmit Status Register
  4852 +#define AT91C_MACB_FRO (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (MACB) Frames Received OK Register
  4853 +#define AT91C_MACB_IDR (AT91_CAST(AT91_REG *) 0xFFFBC02C) // (MACB) Interrupt Disable Register
  4854 +#define AT91C_MACB_SA1H (AT91_CAST(AT91_REG *) 0xFFFBC09C) // (MACB) Specific Address 1 Top, Last 2 bytes
  4855 +#define AT91C_MACB_RLE (AT91_CAST(AT91_REG *) 0xFFFBC088) // (MACB) Receive Length Field Mismatch Register
  4856 +#define AT91C_MACB_TUND (AT91_CAST(AT91_REG *) 0xFFFBC064) // (MACB) Transmit Underrun Error Register
  4857 +#define AT91C_MACB_RSR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (MACB) Receive Status Register
  4858 +#define AT91C_MACB_SA2L (AT91_CAST(AT91_REG *) 0xFFFBC0A0) // (MACB) Specific Address 2 Bottom, First 4 bytes
  4859 +#define AT91C_MACB_FTO (AT91_CAST(AT91_REG *) 0xFFFBC040) // (MACB) Frames Transmitted OK Register
  4860 +#define AT91C_MACB_RSE (AT91_CAST(AT91_REG *) 0xFFFBC074) // (MACB) Receive Symbol Errors Register
  4861 +#define AT91C_MACB_NSR (AT91_CAST(AT91_REG *) 0xFFFBC008) // (MACB) Network Status Register
  4862 +#define AT91C_MACB_RBQP (AT91_CAST(AT91_REG *) 0xFFFBC018) // (MACB) Receive Buffer Queue Pointer
  4863 +#define AT91C_MACB_REV (AT91_CAST(AT91_REG *) 0xFFFBC0FC) // (MACB) Revision Register
  4864 +// ========== Register definition for LCDC peripheral ==========
  4865 +#define AT91C_LCDC_BA2 (AT91_CAST(AT91_REG *) 0x00700004) // (LCDC) DMA Base Address Register 2
  4866 +#define AT91C_LCDC_DP3_4 (AT91_CAST(AT91_REG *) 0x00700830) // (LCDC) Dithering Pattern DP3_4 Register
  4867 +#define AT91C_LCDC_FRMA2 (AT91_CAST(AT91_REG *) 0x00700014) // (LCDC) DMA Frame Address Register 2
  4868 +#define AT91C_LCDC_TIM1 (AT91_CAST(AT91_REG *) 0x00700808) // (LCDC) LCD Timing Config 1 Register
  4869 +#define AT91C_LCDC_FIFO (AT91_CAST(AT91_REG *) 0x00700814) // (LCDC) LCD FIFO Register
  4870 +#define AT91C_LCDC_TIM2 (AT91_CAST(AT91_REG *) 0x0070080C) // (LCDC) LCD Timing Config 2 Register
  4871 +#define AT91C_LCDC_DP5_7 (AT91_CAST(AT91_REG *) 0x0070082C) // (LCDC) Dithering Pattern DP5_7 Register
  4872 +#define AT91C_LCDC_IER (AT91_CAST(AT91_REG *) 0x00700848) // (LCDC) Interrupt Enable Register
  4873 +#define AT91C_LCDC_FRMCFG (AT91_CAST(AT91_REG *) 0x00700018) // (LCDC) DMA Frame Configuration Register
  4874 +#define AT91C_LCDC_FRMA1 (AT91_CAST(AT91_REG *) 0x00700010) // (LCDC) DMA Frame Address Register 1
  4875 +#define AT91C_LCDC_DP3_5 (AT91_CAST(AT91_REG *) 0x00700824) // (LCDC) Dithering Pattern DP3_5 Register
  4876 +#define AT91C_LCDC_PWRCON (AT91_CAST(AT91_REG *) 0x0070083C) // (LCDC) Power Control Register
  4877 +#define AT91C_LCDC_IMR (AT91_CAST(AT91_REG *) 0x00700850) // (LCDC) Interrupt Mask Register
  4878 +#define AT91C_LCDC_LUT_ENTRY (AT91_CAST(AT91_REG *) 0x00700C00) // (LCDC) LUT Entries Register
  4879 +#define AT91C_LCDC_IRR (AT91_CAST(AT91_REG *) 0x00700864) // (LCDC) Interrupts Raw Status Register
  4880 +#define AT91C_LCDC_FRMP2 (AT91_CAST(AT91_REG *) 0x0070000C) // (LCDC) DMA Frame Pointer Register 2
  4881 +#define AT91C_LCDC_ICR (AT91_CAST(AT91_REG *) 0x00700858) // (LCDC) Interrupt Clear Register
  4882 +#define AT91C_LCDC_DP1_2 (AT91_CAST(AT91_REG *) 0x0070081C) // (LCDC) Dithering Pattern DP1_2 Register
  4883 +#define AT91C_LCDC_DMACON (AT91_CAST(AT91_REG *) 0x0070001C) // (LCDC) DMA Control Register
  4884 +#define AT91C_LCDC_LCDFRCFG (AT91_CAST(AT91_REG *) 0x00700810) // (LCDC) LCD Frame Config Register
  4885 +#define AT91C_LCDC_DP2_3 (AT91_CAST(AT91_REG *) 0x00700828) // (LCDC) Dithering Pattern DP2_3 Register
  4886 +#define AT91C_LCDC_DP6_7 (AT91_CAST(AT91_REG *) 0x00700838) // (LCDC) Dithering Pattern DP6_7 Register
  4887 +#define AT91C_LCDC_LCDCON1 (AT91_CAST(AT91_REG *) 0x00700800) // (LCDC) LCD Control 1 Register
  4888 +#define AT91C_LCDC_DMA2DCFG (AT91_CAST(AT91_REG *) 0x00700020) // (LCDC) DMA 2D addressing configuration
  4889 +#define AT91C_LCDC_GPR (AT91_CAST(AT91_REG *) 0x0070085C) // (LCDC) General Purpose Register
  4890 +#define AT91C_LCDC_BA1 (AT91_CAST(AT91_REG *) 0x00700000) // (LCDC) DMA Base Address Register 1
  4891 +#define AT91C_LCDC_CTRSTCON (AT91_CAST(AT91_REG *) 0x00700840) // (LCDC) Contrast Control Register
  4892 +#define AT91C_LCDC_CTRSTVAL (AT91_CAST(AT91_REG *) 0x00700844) // (LCDC) Contrast Value Register
  4893 +#define AT91C_LCDC_LCDCON2 (AT91_CAST(AT91_REG *) 0x00700804) // (LCDC) LCD Control 2 Register
  4894 +#define AT91C_LCDC_IDR (AT91_CAST(AT91_REG *) 0x0070084C) // (LCDC) Interrupt Disable Register
  4895 +#define AT91C_LCDC_ISR (AT91_CAST(AT91_REG *) 0x00700854) // (LCDC) Interrupt Enable Register
  4896 +#define AT91C_LCDC_ITR (AT91_CAST(AT91_REG *) 0x00700860) // (LCDC) Interrupts Test Register
  4897 +#define AT91C_LCDC_DP4_7 (AT91_CAST(AT91_REG *) 0x00700820) // (LCDC) Dithering Pattern DP4_7 Register
  4898 +#define AT91C_LCDC_MVAL (AT91_CAST(AT91_REG *) 0x00700818) // (LCDC) LCD Mode Toggle Rate Value Register
  4899 +#define AT91C_LCDC_DP4_5 (AT91_CAST(AT91_REG *) 0x00700834) // (LCDC) Dithering Pattern DP4_5 Register
  4900 +#define AT91C_LCDC_FRMP1 (AT91_CAST(AT91_REG *) 0x00700008) // (LCDC) DMA Frame Pointer Register 1
  4901 +// ========== Register definition for DMA peripheral ==========
  4902 +#define AT91C_DMA_RAWSRCTRAN (AT91_CAST(AT91_REG *) 0x008002D0) // (DMA) Raw Status for IntSrcTran Interrupt
  4903 +#define AT91C_DMA_SGR0 (AT91_CAST(AT91_REG *) 0x00800048) // (DMA) Source Gather Register for channel 0
  4904 +#define AT91C_DMA_REQSRCREG (AT91_CAST(AT91_REG *) 0x00800368) // (DMA) Source Software Transaction Request Register
  4905 +#define AT91C_DMA_STATUSERR (AT91_CAST(AT91_REG *) 0x00800308) // (DMA) Status for IntErr IInterrupt
  4906 +#define AT91C_DMA_SAR1 (AT91_CAST(AT91_REG *) 0x00800058) // (DMA) Source Address Register for channel 1
  4907 +#define AT91C_DMA_CLEARDSTTRAN (AT91_CAST(AT91_REG *) 0x00800350) // (DMA) Clear for IntDstTran IInterrupt
  4908 +#define AT91C_DMA_STATUSSRCTRAN (AT91_CAST(AT91_REG *) 0x008002F8) // (DMA) Status for IntSrcTran Interrupt
  4909 +#define AT91C_DMA_REQDSTREG (AT91_CAST(AT91_REG *) 0x00800370) // (DMA) Destination Software Transaction Request Register
  4910 +#define AT91C_DMA_DSTATAR0 (AT91_CAST(AT91_REG *) 0x00800038) // (DMA) Destination Status Adress Register for channel 0
  4911 +#define AT91C_DMA_LSTREQDSTREG (AT91_CAST(AT91_REG *) 0x00800390) // (DMA) Last Destination Software Transaction Request Register
  4912 +#define AT91C_DMA_SGLREQDSTREG (AT91_CAST(AT91_REG *) 0x00800380) // (DMA) Single Destination Software Transaction Request Register
  4913 +#define AT91C_DMA_CTL1h (AT91_CAST(AT91_REG *) 0x00800074) // (DMA) Control Register for channel 1 - high
  4914 +#define AT91C_DMA_CLEARERR (AT91_CAST(AT91_REG *) 0x00800358) // (DMA) Clear for IntErr Interrupt
  4915 +#define AT91C_DMA_DSR0 (AT91_CAST(AT91_REG *) 0x00800050) // (DMA) Destination Scatter Register for channel 0
  4916 +#define AT91C_DMA_DMATESTREG (AT91_CAST(AT91_REG *) 0x008003B0) // (DMA) DW_ahb_dmac Test Register
  4917 +#define AT91C_DMA_DSR1 (AT91_CAST(AT91_REG *) 0x008000A8) // (DMA) Destination Scatter Register for channel 1
  4918 +#define AT91C_DMA_CTL0l (AT91_CAST(AT91_REG *) 0x00800018) // (DMA) Control Register for channel 0 - low
  4919 +#define AT91C_DMA_STATUSBLOCK (AT91_CAST(AT91_REG *) 0x008002F0) // (DMA) Status for IntBlock Interrupt
  4920 +#define AT91C_DMA_SAR0 (AT91_CAST(AT91_REG *) 0x00800000) // (DMA) Source Address Register for channel 0
  4921 +#define AT91C_DMA_LLP0 (AT91_CAST(AT91_REG *) 0x00800010) // (DMA) Linked List Pointer Register for channel 0
  4922 +#define AT91C_DMA_CTL1l (AT91_CAST(AT91_REG *) 0x00800070) // (DMA) Control Register for channel 1 - low
  4923 +#define AT91C_DMA_SGR1 (AT91_CAST(AT91_REG *) 0x008000A0) // (DMA) Source Gather Register for channel 1
  4924 +#define AT91C_DMA_CFG0l (AT91_CAST(AT91_REG *) 0x00800040) // (DMA) Configuration Register for channel 0 - low
  4925 +#define AT91C_DMA_CFG0h (AT91_CAST(AT91_REG *) 0x00800044) // (DMA) Configuration Register for channel 0 - high
  4926 +#define AT91C_DMA_STATUSTFR (AT91_CAST(AT91_REG *) 0x008002E8) // (DMA) Status for IntTfr Interrupt
  4927 +#define AT91C_DMA_MASKBLOCK (AT91_CAST(AT91_REG *) 0x00800318) // (DMA) Mask for IntBlock Interrupt
  4928 +#define AT91C_DMA_RAWBLOCK (AT91_CAST(AT91_REG *) 0x008002C8) // (DMA) Raw Status for IntBlock Interrupt
  4929 +#define AT91C_DMA_CHENREG (AT91_CAST(AT91_REG *) 0x008003A0) // (DMA) DW_ahb_dmac Channel Enable Register
  4930 +#define AT91C_DMA_DSTAT0 (AT91_CAST(AT91_REG *) 0x00800028) // (DMA) Destination Status Register for channel 0
  4931 +#define AT91C_DMA_CLEARSRCTRAN (AT91_CAST(AT91_REG *) 0x00800348) // (DMA) Clear for IntSrcTran Interrupt
  4932 +#define AT91C_DMA_DAR1 (AT91_CAST(AT91_REG *) 0x00800060) // (DMA) Destination Address Register for channel 1
  4933 +#define AT91C_DMA_CLEARBLOCK (AT91_CAST(AT91_REG *) 0x00800340) // (DMA) Clear for IntBlock Interrupt
  4934 +#define AT91C_DMA_CFG1h (AT91_CAST(AT91_REG *) 0x0080009C) // (DMA) Configuration Register for channel 1 - high
  4935 +#define AT91C_DMA_DSTATAR1 (AT91_CAST(AT91_REG *) 0x00800090) // (DMA) Destination Status Adress Register for channel 1
  4936 +#define AT91C_DMA_RAWERR (AT91_CAST(AT91_REG *) 0x008002E0) // (DMA) Raw Status for IntErr Interrupt
  4937 +#define AT91C_DMA_CTL0h (AT91_CAST(AT91_REG *) 0x0080001C) // (DMA) Control Register for channel 0 - high
  4938 +#define AT91C_DMA_SGLREQSRCREG (AT91_CAST(AT91_REG *) 0x00800378) // (DMA) Single Source Software Transaction Request Register
  4939 +#define AT91C_DMA_LLP1 (AT91_CAST(AT91_REG *) 0x00800068) // (DMA) Linked List Pointer Register for channel 1
  4940 +#define AT91C_DMA_MASKDSTTRAN (AT91_CAST(AT91_REG *) 0x00800328) // (DMA) Mask for IntDstTran Interrupt
  4941 +#define AT91C_DMA_MASKSRCTRAN (AT91_CAST(AT91_REG *) 0x00800320) // (DMA) Mask for IntSrcTran Interrupt
  4942 +#define AT91C_DMA_LSTREQSRCREG (AT91_CAST(AT91_REG *) 0x00800388) // (DMA) Last Source Software Transaction Request Register
  4943 +#define AT91C_DMA_CLEARTFR (AT91_CAST(AT91_REG *) 0x00800338) // (DMA) Clear for IntTfr Interrupt
  4944 +#define AT91C_DMA_SSTATAR1 (AT91_CAST(AT91_REG *) 0x00800088) // (DMA) Source Status Adress Register for channel 1
  4945 +#define AT91C_DMA_DAR0 (AT91_CAST(AT91_REG *) 0x00800008) // (DMA) Destination Address Register for channel 0
  4946 +#define AT91C_DMA_SSTAT0 (AT91_CAST(AT91_REG *) 0x00800020) // (DMA) Source Status Register for channel 0
  4947 +#define AT91C_DMA_DMAIDREG (AT91_CAST(AT91_REG *) 0x008003A8) // (DMA) DW_ahb_dmac ID Register
  4948 +#define AT91C_DMA_DSTAT1 (AT91_CAST(AT91_REG *) 0x00800080) // (DMA) Destination Status Register for channel 1
  4949 +#define AT91C_DMA_RAWTFR (AT91_CAST(AT91_REG *) 0x008002C0) // (DMA) Raw Status for IntTfr Interrupt
  4950 +#define AT91C_DMA_VERSIONID (AT91_CAST(AT91_REG *) 0x008003B8) // (DMA) DW_ahb_dmac Version ID Register
  4951 +#define AT91C_DMA_STATUSDSTTRAN (AT91_CAST(AT91_REG *) 0x00800300) // (DMA) Status for IntDstTran IInterrupt
  4952 +#define AT91C_DMA_MASKERR (AT91_CAST(AT91_REG *) 0x00800330) // (DMA) Mask for IntErr Interrupt
  4953 +#define AT91C_DMA_SSTATAR0 (AT91_CAST(AT91_REG *) 0x00800030) // (DMA) Source Status Adress Register for channel 0
  4954 +#define AT91C_DMA_MASKTFR (AT91_CAST(AT91_REG *) 0x00800310) // (DMA) Mask for IntTfr Interrupt
  4955 +#define AT91C_DMA_SSTAT1 (AT91_CAST(AT91_REG *) 0x00800078) // (DMA) Source Status Register for channel 1
  4956 +#define AT91C_DMA_STATUSINT (AT91_CAST(AT91_REG *) 0x00800360) // (DMA) Status for each Interrupt Type
  4957 +#define AT91C_DMA_DMACFGREG (AT91_CAST(AT91_REG *) 0x00800398) // (DMA) DW_ahb_dmac Configuration Register
  4958 +#define AT91C_DMA_RAWDSTTRAN (AT91_CAST(AT91_REG *) 0x008002D8) // (DMA) Raw Status for IntDstTran Interrupt
  4959 +#define AT91C_DMA_CFG1l (AT91_CAST(AT91_REG *) 0x00800098) // (DMA) Configuration Register for channel 1 - low
  4960 +// ========== Register definition for UDP peripheral ==========
  4961 +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFF78050) // (UDP) Endpoint FIFO Data Register
  4962 +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFF78010) // (UDP) Interrupt Enable Register
  4963 +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFF78030) // (UDP) Endpoint Control and Status Register
  4964 +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFF78028) // (UDP) Reset Endpoint Register
  4965 +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFF78004) // (UDP) Global State Register
  4966 +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFF78074) // (UDP) Transceiver Control Register
  4967 +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFF78014) // (UDP) Interrupt Disable Register
  4968 +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFF7801C) // (UDP) Interrupt Status Register
  4969 +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFF78018) // (UDP) Interrupt Mask Register
  4970 +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFF78008) // (UDP) Function Address Register
  4971 +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFF78000) // (UDP) Frame Number Register
  4972 +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFF78020) // (UDP) Interrupt Clear Register
  4973 +// ========== Register definition for UHP peripheral ==========
  4974 +#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00A00048) // (UHP) Root Hub characteristics A
  4975 +#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x00A0000C) // (UHP) Interrupt Status Register
  4976 +#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00A00044) // (UHP) LS Threshold
  4977 +#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00A00030) // (UHP) Last completed transfer descriptor
  4978 +#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00A00014) // (UHP) Interrupt Disable Register
  4979 +#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00A00054) // (UHP) Root Hub Port Status Register
  4980 +#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00A00004) // (UHP) Operating modes for the Host Controller
  4981 +#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x00A0001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
  4982 +#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00A00020) // (UHP) First Endpoint Descriptor of the Control list
  4983 +#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00A00008) // (UHP) Command & status Register
  4984 +#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x00A0003C) // (UHP) Frame number
  4985 +#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x00A0004C) // (UHP) Root Hub characteristics B
  4986 +#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00A00028) // (UHP) First endpoint register of the Bulk list
  4987 +#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00A00038) // (UHP) Bit time remaining in the current Frame
  4988 +#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00A00000) // (UHP) Revision
  4989 +#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00A00010) // (UHP) Interrupt Enable Register
  4990 +#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00A00024) // (UHP) Endpoint Control and Status Register
  4991 +#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x00A0002C) // (UHP) Current endpoint of the Bulk list
  4992 +#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00A00018) // (UHP) Pointer to the Host Controller Communication Area
  4993 +#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00A00040) // (UHP) Periodic Start
  4994 +#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00A00050) // (UHP) Root Hub Status register
  4995 +#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00A00034) // (UHP) Bit time between 2 consecutive SOFs
  4996 +// ========== Register definition for TBOX peripheral ==========
  4997 +#define AT91C_TBOX_GPSSIGFILE (AT91_CAST(AT91_REG *) 0x70000BA0) // (TBOX) GPS RFIN/DRFIN driven from files/Samples_GPS.data
  4998 +#define AT91C_TBOX_PIOA (AT91_CAST(AT91_REG *) 0x7000093C) // (TBOX) Value Of PIOA
  4999 +#define AT91C_TBOX_PWM1 (AT91_CAST(AT91_REG *) 0x70000A08) // (TBOX) PWM1[4:0]=nb pulses on pb7, PWM1[9:5]=nb pulses on pc28, PWM1[20:16]=nb pulses on pb8, PWM1[25:21]=nb pulses on pc3
  5000 +#define AT91C_TBOX_PIODENABLEFORCE (AT91_CAST(AT91_REG *) 0x7000092C) // (TBOX) If each bit is 1, the corresponding bit of PIOD is controlled by TBOX_PIODFORCEVALUE
  5001 +#define AT91C_TBOX_PIODPUN (AT91_CAST(AT91_REG *) 0x7000090C) // (TBOX) Spy on PIO PUN inputs
  5002 +#define AT91C_TBOX_PIOAENABLEFORCE (AT91_CAST(AT91_REG *) 0x70000914) // (TBOX) If each bit is 1, the corresponding bit of PIOA is controlled by TBOX_PIOAFORCEVALUE
  5003 +#define AT91C_TBOX_PIOD (AT91_CAST(AT91_REG *) 0x70000948) // (TBOX) Value Of PIOD
  5004 +#define AT91C_TBOX_STOPAPBSPY (AT91_CAST(AT91_REG *) 0x70000A1C) // (TBOX) When 1, no more APB SPY messages
  5005 +#define AT91C_TBOX_PIOEENABLEFORCE (AT91_CAST(AT91_REG *) 0x70000934) // (TBOX) If each bit is 1, the corresponding bit of PIOE is controlled by TBOX_PIOEFORCEVALUE
  5006 +#define AT91C_TBOX_PIOBPUN (AT91_CAST(AT91_REG *) 0x70000904) // (TBOX) Spy on PIO PUN inputs
  5007 +#define AT91C_TBOX_USBDEV (AT91_CAST(AT91_REG *) 0x70000A14) // (TBOX) USB device testbench : bit 0 = flag0, bit 1 = flag1
  5008 +#define AT91C_TBOX_GPSRAND (AT91_CAST(AT91_REG *) 0x70000B04) // (TBOX) GPS random data for correlator (Stimulus - Internal Node)
  5009 +#define AT91C_TBOX_KBD (AT91_CAST(AT91_REG *) 0x70000A18) // (TBOX) Keyboard testbench : bit 0 = keypressed; bits[7:6] = key column; bits[5:4] = key row;
  5010 +#define AT91C_TBOX_PIOEFORCEVALUE (AT91_CAST(AT91_REG *) 0x70000938) // (TBOX) Value to force on PIOA when bits TBOX_PIOEENABLEFORCE are 1
  5011 +#define AT91C_TBOX_AC97START (AT91_CAST(AT91_REG *) 0x70000A00) // (TBOX) Start of AC97 test: swith PIO mux to connect PIOs to audio codec model.
  5012 +#define AT91C_TBOX_PIOAPUN (AT91_CAST(AT91_REG *) 0x70000900) // (TBOX) Spy on PIO PUN inputs
  5013 +#define AT91C_TBOX_GPSACQSTATUS (AT91_CAST(AT91_REG *) 0x70000B08) // (TBOX) GPS acquisition status (Probe - Internal Node)
  5014 +#define AT91C_TBOX_PIOEPUN (AT91_CAST(AT91_REG *) 0x70000910) // (TBOX) Spy on PIO PUN inputs
  5015 +#define AT91C_TBOX_PIOE (AT91_CAST(AT91_REG *) 0x7000094C) // (TBOX) Value Of PIOE
  5016 +#define AT91C_TBOX_PIODFORCEVALUE (AT91_CAST(AT91_REG *) 0x70000930) // (TBOX) Value to force on PIOA when bits TBOX_PIODENABLEFORCE are 1
  5017 +#define AT91C_TBOX_PWMSTART (AT91_CAST(AT91_REG *) 0x70000A04) // (TBOX) Start of PWM test: Start to count edges on PWM IOs
  5018 +#define AT91C_TBOX_GPSSIGIB (AT91_CAST(AT91_REG *) 0x70000BB0) // (TBOX) GPS DRFIN[5:4] aka SIGI_B (Stimulus)
  5019 +#define AT91C_TBOX_GPSSYNCHRO (AT91_CAST(AT91_REG *) 0x70000B00) // (TBOX) GPS synchronization (Stimulus)
  5020 +#define AT91C_TBOX_PIOAFORCEVALUE (AT91_CAST(AT91_REG *) 0x70000918) // (TBOX) Value to force on PIOA when bits TBOX_PIOAENABLEFORCE are 1
  5021 +#define AT91C_TBOX_GPSACQDATA (AT91_CAST(AT91_REG *) 0x70000B0C) // (TBOX) GPS acquisition data (Probe - Internal Node)
  5022 +#define AT91C_TBOX_SHMCTRL (AT91_CAST(AT91_REG *) 0x70000000) // (TBOX) SHM Probe Control: 0-> shm probe stopped, 1: shm probe started
  5023 +#define AT91C_TBOX_MAC (AT91_CAST(AT91_REG *) 0x70000A10) // (TBOX) MAC testbench : bit 0 = rxtrig, bit 1 = clkofftester, bit 2 = err_sig_loops
  5024 +#define AT91C_TBOX_GPSSIGIA (AT91_CAST(AT91_REG *) 0x70000BA4) // (TBOX) GPS DRFIN[1:0] aka SIGI_A (Stimulus)
  5025 +#define AT91C_TBOX_PIOBFORCEVALUE (AT91_CAST(AT91_REG *) 0x70000920) // (TBOX) Value to force on PIOA when bits TBOX_PIOBENABLEFORCE are 1
  5026 +#define AT91C_TBOX_PIOCPUN (AT91_CAST(AT91_REG *) 0x70000908) // (TBOX) Spy on PIO PUN inputs
  5027 +#define AT91C_TBOX_PIOCFORCEVALUE (AT91_CAST(AT91_REG *) 0x70000928) // (TBOX) Value to force on PIOA when bits TBOX_PIOCENABLEFORCE are 1
  5028 +#define AT91C_TBOX_PIOC (AT91_CAST(AT91_REG *) 0x70000944) // (TBOX) Value Of PIOC
  5029 +#define AT91C_TBOX_DMAEXTREQ (AT91_CAST(AT91_REG *) 0x70000810) // (TBOX) DMA External request lines 3 to 0
  5030 +#define AT91C_TBOX_GPSDUMPRES (AT91_CAST(AT91_REG *) 0x70000BC0) // (TBOX) GPS Dump results and errors
  5031 +#define AT91C_TBOX_PIOCENABLEFORCE (AT91_CAST(AT91_REG *) 0x70000924) // (TBOX) If each bit is 1, the corresponding bit of PIOC is controlled by TBOX_PIOCFORCEVALUE
  5032 +#define AT91C_TBOX_PWM2 (AT91_CAST(AT91_REG *) 0x70000A0C) // (TBOX) PWM2[3:0]=nb pulses on pb27, PWM2[7:4]=nb pulses on pc29, PWM2[19:16]=nb pulses on pb29, PWM2[23:20]=nb pulses on pe10
  5033 +#define AT91C_TBOX_GPSSIGQA (AT91_CAST(AT91_REG *) 0x70000BA8) // (TBOX) GPS DRFIN[3:2] aka SIGQ_A (Stimulus)
  5034 +#define AT91C_TBOX_PIOB (AT91_CAST(AT91_REG *) 0x70000940) // (TBOX) Value Of PIOB
  5035 +#define AT91C_TBOX_PIOBENABLEFORCE (AT91_CAST(AT91_REG *) 0x7000091C) // (TBOX) If each bit is 1, the corresponding bit of PIOB is controlled by TBOX_PIOBFORCEVALUE
  5036 +#define AT91C_TBOX_GPSSIGQB (AT91_CAST(AT91_REG *) 0x70000BB4) // (TBOX) GPS DRFIN[7:6] aka SIGQ_B (Stimulus)
  5037 +// ========== Register definition for HECC0 peripheral ==========
  5038 +#define AT91C_HECC0_SR (AT91_CAST(AT91_REG *) 0xFFFFE008) // (HECC0) ECC Status register
  5039 +#define AT91C_HECC0_VR (AT91_CAST(AT91_REG *) 0xFFFFE0FC) // (HECC0) ECC Version register
  5040 +#define AT91C_HECC0_CR (AT91_CAST(AT91_REG *) 0xFFFFE000) // (HECC0) ECC reset register
  5041 +#define AT91C_HECC0_PR (AT91_CAST(AT91_REG *) 0xFFFFE00C) // (HECC0) ECC Parity register
  5042 +#define AT91C_HECC0_MR (AT91_CAST(AT91_REG *) 0xFFFFE004) // (HECC0) ECC Page size register
  5043 +#define AT91C_HECC0_NPR (AT91_CAST(AT91_REG *) 0xFFFFE010) // (HECC0) ECC Parity N register
  5044 +// ========== Register definition for HECC1 peripheral ==========
  5045 +#define AT91C_HECC1_MR (AT91_CAST(AT91_REG *) 0xFFFFE604) // (HECC1) ECC Page size register
  5046 +#define AT91C_HECC1_VR (AT91_CAST(AT91_REG *) 0xFFFFE6FC) // (HECC1) ECC Version register
  5047 +#define AT91C_HECC1_PR (AT91_CAST(AT91_REG *) 0xFFFFE60C) // (HECC1) ECC Parity register
  5048 +#define AT91C_HECC1_CR (AT91_CAST(AT91_REG *) 0xFFFFE600) // (HECC1) ECC reset register
  5049 +#define AT91C_HECC1_NPR (AT91_CAST(AT91_REG *) 0xFFFFE610) // (HECC1) ECC Parity N register
  5050 +#define AT91C_HECC1_SR (AT91_CAST(AT91_REG *) 0xFFFFE608) // (HECC1) ECC Status register
  5051 +// ========== Register definition for HISI peripheral ==========
  5052 +#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 0xFFFC402C) // (HISI) Codec Dma Address Register
  5053 +#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 0xFFFC4024) // (HISI) Preview Decimation Factor Register
  5054 +#define AT91C_HISI_IMR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (HISI) Interrupt Mask Register
  5055 +#define AT91C_HISI_IER (AT91_CAST(AT91_REG *) 0xFFFC400C) // (HISI) Interrupt Enable Register
  5056 +#define AT91C_HISI_SR (AT91_CAST(AT91_REG *) 0xFFFC4008) // (HISI) Status Register
  5057 +#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0xFFFC4030) // (HISI) Color Space Conversion Register
  5058 +#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 0xFFFC4028) // (HISI) Preview Frame Buffer Address Register
  5059 +#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 0xFFFC4020) // (HISI) Preview Size Register
  5060 +#define AT91C_HISI_IDR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (HISI) Interrupt Disable Register
  5061 +#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 0xFFFC4040) // (HISI) Color Space Conversion Register
  5062 +#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 0xFFFC4038) // (HISI) Color Space Conversion Register
  5063 +#define AT91C_HISI_CR1 (AT91_CAST(AT91_REG *) 0xFFFC4000) // (HISI) Control Register 1
  5064 +#define AT91C_HISI_CR2 (AT91_CAST(AT91_REG *) 0xFFFC4004) // (HISI) Control Register 2
  5065 +#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0xFFFC4034) // (HISI) Color Space Conversion Register
  5066 +#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 0xFFFC403C) // (HISI) Color Space Conversion Register
  5067 +
  5068 +// *****************************************************************************
  5069 +// PIO DEFINITIONS FOR AT91SAM9263
  5070 +// *****************************************************************************
  5071 +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
  5072 +#define AT91C_PA0_MCI0_DA0 (AT91C_PIO_PA0) //
  5073 +#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) //
  5074 +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
  5075 +#define AT91C_PA1_MCI0_CDA (AT91C_PIO_PA1) //
  5076 +#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) //
  5077 +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
  5078 +#define AT91C_PA10_MCI1_DA2 (AT91C_PIO_PA10) //
  5079 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
  5080 +#define AT91C_PA11_MCI1_DA3 (AT91C_PIO_PA11) //
  5081 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
  5082 +#define AT91C_PA12_MCI0_CK (AT91C_PIO_PA12) //
  5083 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
  5084 +#define AT91C_PA13_CANTX (AT91C_PIO_PA13) //
  5085 +#define AT91C_PA13_PCK0 (AT91C_PIO_PA13) //
  5086 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
  5087 +#define AT91C_PA14_CANRX (AT91C_PIO_PA14) //
  5088 +#define AT91C_PA14_IRQ0 (AT91C_PIO_PA14) //
  5089 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
  5090 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) //
  5091 +#define AT91C_PA15_IRQ1 (AT91C_PIO_PA15) //
  5092 +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
  5093 +#define AT91C_PA16_MCI0_CDB (AT91C_PIO_PA16) //
  5094 +#define AT91C_PA16_EBI1_D16 (AT91C_PIO_PA16) //
  5095 +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
  5096 +#define AT91C_PA17_MCI0_DB0 (AT91C_PIO_PA17) //
  5097 +#define AT91C_PA17_EBI1_D17 (AT91C_PIO_PA17) //
  5098 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
  5099 +#define AT91C_PA18_MCI0_DB1 (AT91C_PIO_PA18) //
  5100 +#define AT91C_PA18_EBI1_D18 (AT91C_PIO_PA18) //
  5101 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
  5102 +#define AT91C_PA19_MCI0_DB2 (AT91C_PIO_PA19) //
  5103 +#define AT91C_PA19_EBI1_D19 (AT91C_PIO_PA19) //
  5104 +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
  5105 +#define AT91C_PA2_UNCONNECTED_PA2_A (AT91C_PIO_PA2) //
  5106 +#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) //
  5107 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
  5108 +#define AT91C_PA20_MCI0_DB3 (AT91C_PIO_PA20) //
  5109 +#define AT91C_PA20_EBI1_D20 (AT91C_PIO_PA20) //
  5110 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
  5111 +#define AT91C_PA21_MCI1_CDB (AT91C_PIO_PA21) //
  5112 +#define AT91C_PA21_EBI1_D21 (AT91C_PIO_PA21) //
  5113 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
  5114 +#define AT91C_PA22_MCI1_DB0 (AT91C_PIO_PA22) //
  5115 +#define AT91C_PA22_EBI1_D22 (AT91C_PIO_PA22) //
  5116 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
  5117 +#define AT91C_PA23_MCI1_DB1 (AT91C_PIO_PA23) //
  5118 +#define AT91C_PA23_EBI1_D23 (AT91C_PIO_PA23) //
  5119 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
  5120 +#define AT91C_PA24_MCI1_DB2 (AT91C_PIO_PA24) //
  5121 +#define AT91C_PA24_EBI1_D24 (AT91C_PIO_PA24) //
  5122 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
  5123 +#define AT91C_PA25_MCI1_DB3 (AT91C_PIO_PA25) //
  5124 +#define AT91C_PA25_EBI1_D25 (AT91C_PIO_PA25) //
  5125 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
  5126 +#define AT91C_PA26_TXD0 (AT91C_PIO_PA26) //
  5127 +#define AT91C_PA26_EBI1_D26 (AT91C_PIO_PA26) //
  5128 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
  5129 +#define AT91C_PA27_RXD0 (AT91C_PIO_PA27) //
  5130 +#define AT91C_PA27_EBI1_D27 (AT91C_PIO_PA27) //
  5131 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
  5132 +#define AT91C_PA28_RTS0 (AT91C_PIO_PA28) //
  5133 +#define AT91C_PA28_EBI1_D28 (AT91C_PIO_PA28) //
  5134 +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
  5135 +#define AT91C_PA29_CTS0 (AT91C_PIO_PA29) //
  5136 +#define AT91C_PA29_EBI1_D29 (AT91C_PIO_PA29) //
  5137 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
  5138 +#define AT91C_PA3_MCI0_DA1 (AT91C_PIO_PA3) //
  5139 +#define AT91C_PA3_SPI0_NPCS1 (AT91C_PIO_PA3) //
  5140 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
  5141 +#define AT91C_PA30_SCK0 (AT91C_PIO_PA30) //
  5142 +#define AT91C_PA30_EBI1_D30 (AT91C_PIO_PA30) //
  5143 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
  5144 +#define AT91C_PA31_DMARQ0 (AT91C_PIO_PA31) //
  5145 +#define AT91C_PA31_EBI1_D31 (AT91C_PIO_PA31) //
  5146 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
  5147 +#define AT91C_PA4_MCI0_DA2 (AT91C_PIO_PA4) //
  5148 +#define AT91C_PA4_SPI0_NPCS2A (AT91C_PIO_PA4) //
  5149 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
  5150 +#define AT91C_PA5_MCI0_DA3 (AT91C_PIO_PA5) //
  5151 +#define AT91C_PA5_SPI0_NPCS0 (AT91C_PIO_PA5) //
  5152 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
  5153 +#define AT91C_PA6_MCI1_CK (AT91C_PIO_PA6) //
  5154 +#define AT91C_PA6_PCK2 (AT91C_PIO_PA6) //
  5155 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
  5156 +#define AT91C_PA7_MCI1_CDA (AT91C_PIO_PA7) //
  5157 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
  5158 +#define AT91C_PA8_MCI1_DA0 (AT91C_PIO_PA8) //
  5159 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
  5160 +#define AT91C_PA9_MCI1_DA1 (AT91C_PIO_PA9) //
  5161 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
  5162 +#define AT91C_PB0_AC97FS (AT91C_PIO_PB0) //
  5163 +#define AT91C_PB0_TF0 (AT91C_PIO_PB0) //
  5164 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
  5165 +#define AT91C_PB1_AC97CK (AT91C_PIO_PB1) //
  5166 +#define AT91C_PB1_TK0 (AT91C_PIO_PB1) //
  5167 +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
  5168 +#define AT91C_PB10_RK1 (AT91C_PIO_PB10) //
  5169 +#define AT91C_PB10_PCK1 (AT91C_PIO_PB10) //
  5170 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
  5171 +#define AT91C_PB11_RF1 (AT91C_PIO_PB11) //
  5172 +#define AT91C_PB11_SPI0_NPCS3B (AT91C_PIO_PB11) //
  5173 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
  5174 +#define AT91C_PB12_SPI1_MISO (AT91C_PIO_PB12) //
  5175 +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
  5176 +#define AT91C_PB13_SPI1_MOSI (AT91C_PIO_PB13) //
  5177 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
  5178 +#define AT91C_PB14_SPI1_SPCK (AT91C_PIO_PB14) //
  5179 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
  5180 +#define AT91C_PB15_SPI1_NPCS0 (AT91C_PIO_PB15) //
  5181 +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
  5182 +#define AT91C_PB16_SPI1_NPCS1 (AT91C_PIO_PB16) //
  5183 +#define AT91C_PB16_PCK1 (AT91C_PIO_PB16) //
  5184 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
  5185 +#define AT91C_PB17_SPI1_NPCS2B (AT91C_PIO_PB17) //
  5186 +#define AT91C_PB17_TIOA2 (AT91C_PIO_PB17) //
  5187 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
  5188 +#define AT91C_PB18_SPI1_NPCS3B (AT91C_PIO_PB18) //
  5189 +#define AT91C_PB18_TIOB2 (AT91C_PIO_PB18) //
  5190 +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
  5191 +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
  5192 +#define AT91C_PB2_AC97TX (AT91C_PIO_PB2) //
  5193 +#define AT91C_PB2_TD0 (AT91C_PIO_PB2) //
  5194 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
  5195 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
  5196 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
  5197 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
  5198 +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
  5199 +#define AT91C_PB24_UNCONNECTED_PB24_A (AT91C_PIO_PB24) //
  5200 +#define AT91C_PB24_DMARQ3 (AT91C_PIO_PB24) //
  5201 +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
  5202 +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
  5203 +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
  5204 +#define AT91C_PB27_UNCONNECTED_PB27_A (AT91C_PIO_PB27) //
  5205 +#define AT91C_PB27_PWM2 (AT91C_PIO_PB27) //
  5206 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
  5207 +#define AT91C_PB28_UNCONNECTED_PB28_A (AT91C_PIO_PB28) //
  5208 +#define AT91C_PB28_TCLK0 (AT91C_PIO_PB28) //
  5209 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
  5210 +#define AT91C_PB29_UNCONNECTED_PB29_A (AT91C_PIO_PB29) //
  5211 +#define AT91C_PB29_PWM3 (AT91C_PIO_PB29) //
  5212 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
  5213 +#define AT91C_PB3_AC97RX (AT91C_PIO_PB3) //
  5214 +#define AT91C_PB3_RD0 (AT91C_PIO_PB3) //
  5215 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
  5216 +#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31
  5217 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
  5218 +#define AT91C_PB4_TWD (AT91C_PIO_PB4) //
  5219 +#define AT91C_PB4_RK0 (AT91C_PIO_PB4) //
  5220 +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
  5221 +#define AT91C_PB5_TWCK (AT91C_PIO_PB5) //
  5222 +#define AT91C_PB5_RF0 (AT91C_PIO_PB5) //
  5223 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
  5224 +#define AT91C_PB6_TF1 (AT91C_PIO_PB6) //
  5225 +#define AT91C_PB6_DMARQ1 (AT91C_PIO_PB6) //
  5226 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
  5227 +#define AT91C_PB7_TK1 (AT91C_PIO_PB7) //
  5228 +#define AT91C_PB7_PWM0 (AT91C_PIO_PB7) //
  5229 +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
  5230 +#define AT91C_PB8_TD1 (AT91C_PIO_PB8) //
  5231 +#define AT91C_PB8_PWM1 (AT91C_PIO_PB8) //
  5232 +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
  5233 +#define AT91C_PB9_RD1 (AT91C_PIO_PB9) //
  5234 +#define AT91C_PB9_LCDCC (AT91C_PIO_PB9) //
  5235 +#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0
  5236 +#define AT91C_PC0_LCDVSYNC (AT91C_PIO_PC0) //
  5237 +#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1
  5238 +#define AT91C_PC1_LCDHSYNC (AT91C_PIO_PC1) //
  5239 +#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10
  5240 +#define AT91C_PC10_LCDD6 (AT91C_PIO_PC10) //
  5241 +#define AT91C_PC10_LCDD11B (AT91C_PIO_PC10) //
  5242 +#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11
  5243 +#define AT91C_PC11_LCDD7 (AT91C_PIO_PC11) //
  5244 +#define AT91C_PC11_LCDD12B (AT91C_PIO_PC11) //
  5245 +#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12
  5246 +#define AT91C_PC12_LCDD8 (AT91C_PIO_PC12) //
  5247 +#define AT91C_PC12_LCDD13B (AT91C_PIO_PC12) //
  5248 +#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13
  5249 +#define AT91C_PC13_LCDD9 (AT91C_PIO_PC13) //
  5250 +#define AT91C_PC13_LCDD14B (AT91C_PIO_PC13) //
  5251 +#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14
  5252 +#define AT91C_PC14_LCDD10 (AT91C_PIO_PC14) //
  5253 +#define AT91C_PC14_LCDD15B (AT91C_PIO_PC14) //
  5254 +#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15
  5255 +#define AT91C_PC15_LCDD11 (AT91C_PIO_PC15) //
  5256 +#define AT91C_PC15_LCDD19B (AT91C_PIO_PC15) //
  5257 +#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16
  5258 +#define AT91C_PC16_LCDD12 (AT91C_PIO_PC16) //
  5259 +#define AT91C_PC16_LCDD20B (AT91C_PIO_PC16) //
  5260 +#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17
  5261 +#define AT91C_PC17_LCDD13 (AT91C_PIO_PC17) //
  5262 +#define AT91C_PC17_LCDD21B (AT91C_PIO_PC17) //
  5263 +#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18
  5264 +#define AT91C_PC18_LCDD14 (AT91C_PIO_PC18) //
  5265 +#define AT91C_PC18_LCDD22B (AT91C_PIO_PC18) //
  5266 +#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19
  5267 +#define AT91C_PC19_LCDD15 (AT91C_PIO_PC19) //
  5268 +#define AT91C_PC19_LCDD23B (AT91C_PIO_PC19) //
  5269 +#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2
  5270 +#define AT91C_PC2_LCDDOTCK (AT91C_PIO_PC2) //
  5271 +#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20
  5272 +#define AT91C_PC20_LCDD16 (AT91C_PIO_PC20) //
  5273 +#define AT91C_PC20_ETX2 (AT91C_PIO_PC20) //
  5274 +#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21
  5275 +#define AT91C_PC21_LCDD17 (AT91C_PIO_PC21) //
  5276 +#define AT91C_PC21_ETX3 (AT91C_PIO_PC21) //
  5277 +#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22
  5278 +#define AT91C_PC22_LCDD18 (AT91C_PIO_PC22) //
  5279 +#define AT91C_PC22_ERX2 (AT91C_PIO_PC22) //
  5280 +#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23
  5281 +#define AT91C_PC23_LCDD19 (AT91C_PIO_PC23) //
  5282 +#define AT91C_PC23_ERX3 (AT91C_PIO_PC23) //
  5283 +#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24
  5284 +#define AT91C_PC24_LCDD20 (AT91C_PIO_PC24) //
  5285 +#define AT91C_PC24_ETXER (AT91C_PIO_PC24) //
  5286 +#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25
  5287 +#define AT91C_PC25_LCDD21 (AT91C_PIO_PC25) //
  5288 +#define AT91C_PC25_ERXDV (AT91C_PIO_PC25) //
  5289 +#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26
  5290 +#define AT91C_PC26_LCDD22 (AT91C_PIO_PC26) //
  5291 +#define AT91C_PC26_ECOL (AT91C_PIO_PC26) //
  5292 +#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27
  5293 +#define AT91C_PC27_LCDD23 (AT91C_PIO_PC27) //
  5294 +#define AT91C_PC27_ERXCK (AT91C_PIO_PC27) //
  5295 +#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28
  5296 +#define AT91C_PC28_PWM0 (AT91C_PIO_PC28) //
  5297 +#define AT91C_PC28_TCLK1 (AT91C_PIO_PC28) //
  5298 +#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29
  5299 +#define AT91C_PC29_PCK0 (AT91C_PIO_PC29) //
  5300 +#define AT91C_PC29_PWM2 (AT91C_PIO_PC29) //
  5301 +#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3
  5302 +#define AT91C_PC3_LCDEN (AT91C_PIO_PC3) //
  5303 +#define AT91C_PC3_PWM1 (AT91C_PIO_PC3) //
  5304 +#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30
  5305 +#define AT91C_PC30_DRXD (AT91C_PIO_PC30) //
  5306 +#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31
  5307 +#define AT91C_PC31_DTXD (AT91C_PIO_PC31) //
  5308 +#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4
  5309 +#define AT91C_PC4_LCDD0 (AT91C_PIO_PC4) //
  5310 +#define AT91C_PC4_LCDD3B (AT91C_PIO_PC4) //
  5311 +#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5
  5312 +#define AT91C_PC5_LCDD1 (AT91C_PIO_PC5) //
  5313 +#define AT91C_PC5_LCDD4B (AT91C_PIO_PC5) //
  5314 +#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6
  5315 +#define AT91C_PC6_LCDD2 (AT91C_PIO_PC6) //
  5316 +#define AT91C_PC6_LCDD5B (AT91C_PIO_PC6) //
  5317 +#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7
  5318 +#define AT91C_PC7_LCDD3 (AT91C_PIO_PC7) //
  5319 +#define AT91C_PC7_LCDD6B (AT91C_PIO_PC7) //
  5320 +#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8
  5321 +#define AT91C_PC8_LCDD4 (AT91C_PIO_PC8) //
  5322 +#define AT91C_PC8_LCDD7B (AT91C_PIO_PC8) //
  5323 +#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9
  5324 +#define AT91C_PC9_LCDD5 (AT91C_PIO_PC9) //
  5325 +#define AT91C_PC9_LCDD10B (AT91C_PIO_PC9) //
  5326 +#define AT91C_PIO_PD0 (1 << 0) // Pin Controlled by PD0
  5327 +#define AT91C_PD0_TXD1 (AT91C_PIO_PD0) //
  5328 +#define AT91C_PD0_SPI0_NPCS2D (AT91C_PIO_PD0) //
  5329 +#define AT91C_PIO_PD1 (1 << 1) // Pin Controlled by PD1
  5330 +#define AT91C_PD1_RXD1 (AT91C_PIO_PD1) //
  5331 +#define AT91C_PD1_SPI0_NPCS3D (AT91C_PIO_PD1) //
  5332 +#define AT91C_PIO_PD10 (1 << 10) // Pin Controlled by PD10
  5333 +#define AT91C_PD10_UNCONNECTED_PD10_A (AT91C_PIO_PD10) //
  5334 +#define AT91C_PD10_SCK1 (AT91C_PIO_PD10) //
  5335 +#define AT91C_PIO_PD11 (1 << 11) // Pin Controlled by PD11
  5336 +#define AT91C_PD11_EBI0_NCS2 (AT91C_PIO_PD11) //
  5337 +#define AT91C_PD11_TSYNC (AT91C_PIO_PD11) //
  5338 +#define AT91C_PIO_PD12 (1 << 12) // Pin Controlled by PD12
  5339 +#define AT91C_PD12_EBI0_A23 (AT91C_PIO_PD12) //
  5340 +#define AT91C_PD12_TCLK (AT91C_PIO_PD12) //
  5341 +#define AT91C_PIO_PD13 (1 << 13) // Pin Controlled by PD13
  5342 +#define AT91C_PD13_EBI0_A24 (AT91C_PIO_PD13) //
  5343 +#define AT91C_PD13_TPS0 (AT91C_PIO_PD13) //
  5344 +#define AT91C_PIO_PD14 (1 << 14) // Pin Controlled by PD14
  5345 +#define AT91C_PD14_EBI0_A25_CFNRW (AT91C_PIO_PD14) //
  5346 +#define AT91C_PD14_TPS1 (AT91C_PIO_PD14) //
  5347 +#define AT91C_PIO_PD15 (1 << 15) // Pin Controlled by PD15
  5348 +#define AT91C_PD15_EBI0_NCS3_NANDCS (AT91C_PIO_PD15) //
  5349 +#define AT91C_PD15_TPS2 (AT91C_PIO_PD15) //
  5350 +#define AT91C_PIO_PD16 (1 << 16) // Pin Controlled by PD16
  5351 +#define AT91C_PD16_EBI0_D16 (AT91C_PIO_PD16) //
  5352 +#define AT91C_PD16_TPK0 (AT91C_PIO_PD16) //
  5353 +#define AT91C_PIO_PD17 (1 << 17) // Pin Controlled by PD17
  5354 +#define AT91C_PD17_EBI0_D17 (AT91C_PIO_PD17) //
  5355 +#define AT91C_PD17_TPK1 (AT91C_PIO_PD17) //
  5356 +#define AT91C_PIO_PD18 (1 << 18) // Pin Controlled by PD18
  5357 +#define AT91C_PD18_EBI0_D18 (AT91C_PIO_PD18) //
  5358 +#define AT91C_PD18_TPK2 (AT91C_PIO_PD18) //
  5359 +#define AT91C_PIO_PD19 (1 << 19) // Pin Controlled by PD19
  5360 +#define AT91C_PD19_EBI0_D19 (AT91C_PIO_PD19) //
  5361 +#define AT91C_PD19_TPK3 (AT91C_PIO_PD19) //
  5362 +#define AT91C_PIO_PD2 (1 << 2) // Pin Controlled by PD2
  5363 +#define AT91C_PD2_TXD2 (AT91C_PIO_PD2) //
  5364 +#define AT91C_PD2_SPI1_NPCS2D (AT91C_PIO_PD2) //
  5365 +#define AT91C_PIO_PD20 (1 << 20) // Pin Controlled by PD20
  5366 +#define AT91C_PD20_EBI0_D20 (AT91C_PIO_PD20) //
  5367 +#define AT91C_PD20_TPK4 (AT91C_PIO_PD20) //
  5368 +#define AT91C_PIO_PD21 (1 << 21) // Pin Controlled by PD21
  5369 +#define AT91C_PD21_EBI0_D21 (AT91C_PIO_PD21) //
  5370 +#define AT91C_PD21_TPK5 (AT91C_PIO_PD21) //
  5371 +#define AT91C_PIO_PD22 (1 << 22) // Pin Controlled by PD22
  5372 +#define AT91C_PD22_EBI0_D22 (AT91C_PIO_PD22) //
  5373 +#define AT91C_PD22_TPK6 (AT91C_PIO_PD22) //
  5374 +#define AT91C_PIO_PD23 (1 << 23) // Pin Controlled by PD23
  5375 +#define AT91C_PD23_EBI0_D23 (AT91C_PIO_PD23) //
  5376 +#define AT91C_PD23_TPK7 (AT91C_PIO_PD23) //
  5377 +#define AT91C_PIO_PD24 (1 << 24) // Pin Controlled by PD24
  5378 +#define AT91C_PD24_EBI0_D24 (AT91C_PIO_PD24) //
  5379 +#define AT91C_PD24_TPK8 (AT91C_PIO_PD24) //
  5380 +#define AT91C_PIO_PD25 (1 << 25) // Pin Controlled by PD25
  5381 +#define AT91C_PD25_EBI0_D25 (AT91C_PIO_PD25) //
  5382 +#define AT91C_PD25_TPK9 (AT91C_PIO_PD25) //
  5383 +#define AT91C_PIO_PD26 (1 << 26) // Pin Controlled by PD26
  5384 +#define AT91C_PD26_EBI0_D26 (AT91C_PIO_PD26) //
  5385 +#define AT91C_PD26_TPK10 (AT91C_PIO_PD26) //
  5386 +#define AT91C_PIO_PD27 (1 << 27) // Pin Controlled by PD27
  5387 +#define AT91C_PD27_EBI0_D27 (AT91C_PIO_PD27) //
  5388 +#define AT91C_PD27_TPK11 (AT91C_PIO_PD27) //
  5389 +#define AT91C_PIO_PD28 (1 << 28) // Pin Controlled by PD28
  5390 +#define AT91C_PD28_EBI0_D28 (AT91C_PIO_PD28) //
  5391 +#define AT91C_PD28_TPK12 (AT91C_PIO_PD28) //
  5392 +#define AT91C_PIO_PD29 (1 << 29) // Pin Controlled by PD29
  5393 +#define AT91C_PD29_EBI0_D29 (AT91C_PIO_PD29) //
  5394 +#define AT91C_PD29_TPK13 (AT91C_PIO_PD29) //
  5395 +#define AT91C_PIO_PD3 (1 << 3) // Pin Controlled by PD3
  5396 +#define AT91C_PD3_RXD2 (AT91C_PIO_PD3) //
  5397 +#define AT91C_PD3_SPI1_NPCS3D (AT91C_PIO_PD3) //
  5398 +#define AT91C_PIO_PD30 (1 << 30) // Pin Controlled by PD30
  5399 +#define AT91C_PD30_EBI0_D30 (AT91C_PIO_PD30) //
  5400 +#define AT91C_PD30_TPK14 (AT91C_PIO_PD30) //
  5401 +#define AT91C_PIO_PD31 (1 << 31) // Pin Controlled by PD31
  5402 +#define AT91C_PD31_EBI0_D31 (AT91C_PIO_PD31) //
  5403 +#define AT91C_PD31_TPK15 (AT91C_PIO_PD31) //
  5404 +#define AT91C_PIO_PD4 (1 << 4) // Pin Controlled by PD4
  5405 +#define AT91C_PD4_FIQ (AT91C_PIO_PD4) //
  5406 +#define AT91C_PD4_DMARQ2 (AT91C_PIO_PD4) //
  5407 +#define AT91C_PIO_PD5 (1 << 5) // Pin Controlled by PD5
  5408 +#define AT91C_PD5_EBI0_NWAIT (AT91C_PIO_PD5) //
  5409 +#define AT91C_PD5_RTS2 (AT91C_PIO_PD5) //
  5410 +#define AT91C_PIO_PD6 (1 << 6) // Pin Controlled by PD6
  5411 +#define AT91C_PD6_EBI0_NCS4_CFCS0 (AT91C_PIO_PD6) //
  5412 +#define AT91C_PD6_CTS2 (AT91C_PIO_PD6) //
  5413 +#define AT91C_PIO_PD7 (1 << 7) // Pin Controlled by PD7
  5414 +#define AT91C_PD7_EBI0_NCS5_CFCS1 (AT91C_PIO_PD7) //
  5415 +#define AT91C_PD7_RTS1 (AT91C_PIO_PD7) //
  5416 +#define AT91C_PIO_PD8 (1 << 8) // Pin Controlled by PD8
  5417 +#define AT91C_PD8_EBI0_CFCE1 (AT91C_PIO_PD8) //
  5418 +#define AT91C_PD8_CTS1 (AT91C_PIO_PD8) //
  5419 +#define AT91C_PIO_PD9 (1 << 9) // Pin Controlled by PD9
  5420 +#define AT91C_PD9_EBI0_CFCE2 (AT91C_PIO_PD9) //
  5421 +#define AT91C_PD9_SCK2 (AT91C_PIO_PD9) //
  5422 +#define AT91C_PIO_PE0 (1 << 0) // Pin Controlled by PE0
  5423 +#define AT91C_PE0_ISI_D0 (AT91C_PIO_PE0) //
  5424 +#define AT91C_PIO_PE1 (1 << 1) // Pin Controlled by PE1
  5425 +#define AT91C_PE1_ISI_D1 (AT91C_PIO_PE1) //
  5426 +#define AT91C_PIO_PE10 (1 << 10) // Pin Controlled by PE10
  5427 +#define AT91C_PE10_ISI_VSYNC (AT91C_PIO_PE10) //
  5428 +#define AT91C_PE10_PWM3 (AT91C_PIO_PE10) //
  5429 +#define AT91C_PIO_PE11 (1 << 11) // Pin Controlled by PE11
  5430 +#define AT91C_PE11_ISI_MCK (AT91C_PIO_PE11) //
  5431 +#define AT91C_PE11_PCK3 (AT91C_PIO_PE11) //
  5432 +#define AT91C_PIO_PE12 (1 << 12) // Pin Controlled by PE12
  5433 +#define AT91C_PE12_KBDR0 (AT91C_PIO_PE12) //
  5434 +#define AT91C_PE12_ISI_D8 (AT91C_PIO_PE12) //
  5435 +#define AT91C_PIO_PE13 (1 << 13) // Pin Controlled by PE13
  5436 +#define AT91C_PE13_KBDR1 (AT91C_PIO_PE13) //
  5437 +#define AT91C_PE13_ISI_D9 (AT91C_PIO_PE13) //
  5438 +#define AT91C_PIO_PE14 (1 << 14) // Pin Controlled by PE14
  5439 +#define AT91C_PE14_KBDR2 (AT91C_PIO_PE14) //
  5440 +#define AT91C_PE14_ISI_D10 (AT91C_PIO_PE14) //
  5441 +#define AT91C_PIO_PE15 (1 << 15) // Pin Controlled by PE15
  5442 +#define AT91C_PE15_KBDR3 (AT91C_PIO_PE15) //
  5443 +#define AT91C_PE15_ISI_D11 (AT91C_PIO_PE15) //
  5444 +#define AT91C_PIO_PE16 (1 << 16) // Pin Controlled by PE16
  5445 +#define AT91C_PE16_KBDR4 (AT91C_PIO_PE16) //
  5446 +#define AT91C_PIO_PE17 (1 << 17) // Pin Controlled by PE17
  5447 +#define AT91C_PE17_KBDC0 (AT91C_PIO_PE17) //
  5448 +#define AT91C_PIO_PE18 (1 << 18) // Pin Controlled by PE18
  5449 +#define AT91C_PE18_KBDC1 (AT91C_PIO_PE18) //
  5450 +#define AT91C_PE18_TIOA0 (AT91C_PIO_PE18) //
  5451 +#define AT91C_PIO_PE19 (1 << 19) // Pin Controlled by PE19
  5452 +#define AT91C_PE19_KBDC2 (AT91C_PIO_PE19) //
  5453 +#define AT91C_PE19_TIOB0 (AT91C_PIO_PE19) //
  5454 +#define AT91C_PIO_PE2 (1 << 2) // Pin Controlled by PE2
  5455 +#define AT91C_PE2_ISI_D2 (AT91C_PIO_PE2) //
  5456 +#define AT91C_PIO_PE20 (1 << 20) // Pin Controlled by PE20
  5457 +#define AT91C_PE20_KBDC3 (AT91C_PIO_PE20) //
  5458 +#define AT91C_PE20_EBI1_NWAIT (AT91C_PIO_PE20) //
  5459 +#define AT91C_PIO_PE21 (1 << 21) // Pin Controlled by PE21
  5460 +#define AT91C_PE21_ETXCK (AT91C_PIO_PE21) //
  5461 +#define AT91C_PE21_EBI1_NANDWE (AT91C_PIO_PE21) //
  5462 +#define AT91C_PIO_PE22 (1 << 22) // Pin Controlled by PE22
  5463 +#define AT91C_PE22_ECRS (AT91C_PIO_PE22) //
  5464 +#define AT91C_PE22_EBI1_NCS2_NANDCS (AT91C_PIO_PE22) //
  5465 +#define AT91C_PIO_PE23 (1 << 23) // Pin Controlled by PE23
  5466 +#define AT91C_PE23_ETX0 (AT91C_PIO_PE23) //
  5467 +#define AT91C_PE23_EBI1_NANDOE (AT91C_PIO_PE23) //
  5468 +#define AT91C_PIO_PE24 (1 << 24) // Pin Controlled by PE24
  5469 +#define AT91C_PE24_ETX1 (AT91C_PIO_PE24) //
  5470 +#define AT91C_PE24_EBI1_NWR3_NBS3 (AT91C_PIO_PE24) //
  5471 +#define AT91C_PIO_PE25 (1 << 25) // Pin Controlled by PE25
  5472 +#define AT91C_PE25_ERX0 (AT91C_PIO_PE25) //
  5473 +#define AT91C_PE25_EBI1_NCS1_SDCS (AT91C_PIO_PE25) //
  5474 +#define AT91C_PIO_PE26 (1 << 26) // Pin Controlled by PE26
  5475 +#define AT91C_PE26_ERX1 (AT91C_PIO_PE26) //
  5476 +#define AT91C_PIO_PE27 (1 << 27) // Pin Controlled by PE27
  5477 +#define AT91C_PE27_ERXER (AT91C_PIO_PE27) //
  5478 +#define AT91C_PE27_EBI1_SDCKE (AT91C_PIO_PE27) //
  5479 +#define AT91C_PIO_PE28 (1 << 28) // Pin Controlled by PE28
  5480 +#define AT91C_PE28_ETXEN (AT91C_PIO_PE28) //
  5481 +#define AT91C_PE28_EBI1_RAS (AT91C_PIO_PE28) //
  5482 +#define AT91C_PIO_PE29 (1 << 29) // Pin Controlled by PE29
  5483 +#define AT91C_PE29_EMDC (AT91C_PIO_PE29) //
  5484 +#define AT91C_PE29_EBI1_CAS (AT91C_PIO_PE29) //
  5485 +#define AT91C_PIO_PE3 (1 << 3) // Pin Controlled by PE3
  5486 +#define AT91C_PE3_ISI_D3 (AT91C_PIO_PE3) //
  5487 +#define AT91C_PIO_PE30 (1 << 30) // Pin Controlled by PE30
  5488 +#define AT91C_PE30_EMDIO (AT91C_PIO_PE30) //
  5489 +#define AT91C_PE30_EBI1_SDWE (AT91C_PIO_PE30) //
  5490 +#define AT91C_PIO_PE31 (1 << 31) // Pin Controlled by PE31
  5491 +#define AT91C_PE31_EF100 (AT91C_PIO_PE31) //
  5492 +#define AT91C_PE31_EBI1_SDA10 (AT91C_PIO_PE31) //
  5493 +#define AT91C_PIO_PE4 (1 << 4) // Pin Controlled by PE4
  5494 +#define AT91C_PE4_ISI_D4 (AT91C_PIO_PE4) //
  5495 +#define AT91C_PIO_PE5 (1 << 5) // Pin Controlled by PE5
  5496 +#define AT91C_PE5_ISI_D5 (AT91C_PIO_PE5) //
  5497 +#define AT91C_PIO_PE6 (1 << 6) // Pin Controlled by PE6
  5498 +#define AT91C_PE6_ISI_D6 (AT91C_PIO_PE6) //
  5499 +#define AT91C_PIO_PE7 (1 << 7) // Pin Controlled by PE7
  5500 +#define AT91C_PE7_ISI_D7 (AT91C_PIO_PE7) //
  5501 +#define AT91C_PIO_PE8 (1 << 8) // Pin Controlled by PE8
  5502 +#define AT91C_PE8_ISI_PCK (AT91C_PIO_PE8) //
  5503 +#define AT91C_PE8_TIOA1 (AT91C_PIO_PE8) //
  5504 +#define AT91C_PIO_PE9 (1 << 9) // Pin Controlled by PE9
  5505 +#define AT91C_PE9_ISI_HSYNC (AT91C_PIO_PE9) //
  5506 +#define AT91C_PE9_TIOB1 (AT91C_PIO_PE9) //
  5507 +
  5508 +// *****************************************************************************
  5509 +// PERIPHERAL ID DEFINITIONS FOR AT91SAM9263
  5510 +// *****************************************************************************
  5511 +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
  5512 +#define AT91C_ID_SYS ( 1) // System Controller
  5513 +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
  5514 +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
  5515 +#define AT91C_ID_PIOCDE ( 4) // Parallel IO Controller C, Parallel IO Controller D, Parallel IO Controller E
  5516 +#define AT91C_ID_US0 ( 7) // USART 0
  5517 +#define AT91C_ID_US1 ( 8) // USART 1
  5518 +#define AT91C_ID_US2 ( 9) // USART 2
  5519 +#define AT91C_ID_MCI0 (10) // Multimedia Card Interface 0
  5520 +#define AT91C_ID_MCI1 (11) // Multimedia Card Interface 1
  5521 +#define AT91C_ID_CAN (12) // CAN Controller
  5522 +#define AT91C_ID_TWI (13) // Two-Wire Interface
  5523 +#define AT91C_ID_SPI0 (14) // Serial Peripheral Interface 0
  5524 +#define AT91C_ID_SPI1 (15) // Serial Peripheral Interface 1
  5525 +#define AT91C_ID_SSC0 (16) // Serial Synchronous Controller 0
  5526 +#define AT91C_ID_SSC1 (17) // Serial Synchronous Controller 1
  5527 +#define AT91C_ID_AC97C (18) // AC97 Controller
  5528 +#define AT91C_ID_TC012 (19) // Timer Counter 0, Timer Counter 1, Timer Counter 2
  5529 +#define AT91C_ID_PWMC (20) // PWM Controller
  5530 +#define AT91C_ID_EMAC (21) // Ethernet Mac
  5531 +#define AT91C_ID_UDP (24) // USB Device Port
  5532 +#define AT91C_ID_HISI (25) // Image Sensor Interface
  5533 +#define AT91C_ID_LCDC (26) // LCD Controller
  5534 +#define AT91C_ID_DMA (27) // DMA Controller
  5535 +#define AT91C_ID_UHP (29) // USB Host Port
  5536 +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
  5537 +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
  5538 +#define AT91C_ALL_INT (0xEF3FFF9F) // ALL VALID INTERRUPTS
  5539 +
  5540 +// *****************************************************************************
  5541 +// BASE ADDRESS DEFINITIONS FOR AT91SAM9263
  5542 +// *****************************************************************************
  5543 +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFE000) // (SYS) Base Address
  5544 +#define AT91C_BASE_EBI0 (AT91_CAST(AT91PS_EBI0) 0xFFFFE200) // (EBI0) Base Address
  5545 +#define AT91C_BASE_SDRAMC0 (AT91_CAST(AT91PS_SDRAMC) 0xFFFFE200) // (SDRAMC0) Base Address
  5546 +#define AT91C_BASE_SMC0 (AT91_CAST(AT91PS_SMC) 0xFFFFE400) // (SMC0) Base Address
  5547 +#define AT91C_BASE_EBI1 (AT91_CAST(AT91PS_EBI1) 0xFFFFE800) // (EBI1) Base Address
  5548 +#define AT91C_BASE_SDRAMC1 (AT91_CAST(AT91PS_SDRAMC) 0xFFFFE800) // (SDRAMC1) Base Address
  5549 +#define AT91C_BASE_SMC1 (AT91_CAST(AT91PS_SMC) 0xFFFFEA00) // (SMC1) Base Address
  5550 +#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEC00) // (MATRIX) Base Address
  5551 +#define AT91C_BASE_CCFG (AT91_CAST(AT91PS_CCFG) 0xFFFFED10) // (CCFG) Base Address
  5552 +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFEF00) // (PDC_DBGU) Base Address
  5553 +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFEE00) // (DBGU) Base Address
  5554 +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
  5555 +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF200) // (PIOA) Base Address
  5556 +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOB) Base Address
  5557 +#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOC) Base Address
  5558 +#define AT91C_BASE_PIOD (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOD) Base Address
  5559 +#define AT91C_BASE_PIOE (AT91_CAST(AT91PS_PIO) 0xFFFFFA00) // (PIOE) Base Address
  5560 +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
  5561 +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
  5562 +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
  5563 +#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address
  5564 +#define AT91C_BASE_RTTC0 (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC0) Base Address
  5565 +#define AT91C_BASE_RTTC1 (AT91_CAST(AT91PS_RTTC) 0xFFFFFD50) // (RTTC1) Base Address
  5566 +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
  5567 +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
  5568 +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFF7C000) // (TC0) Base Address
  5569 +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFF7C040) // (TC1) Base Address
  5570 +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFF7C080) // (TC2) Base Address
  5571 +#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFF7C000) // (TCB0) Base Address
  5572 +#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFF7C040) // (TCB1) Base Address
  5573 +#define AT91C_BASE_TCB2 (AT91_CAST(AT91PS_TCB) 0xFFF7C080) // (TCB2) Base Address
  5574 +#define AT91C_BASE_PDC_MCI0 (AT91_CAST(AT91PS_PDC) 0xFFF80100) // (PDC_MCI0) Base Address
  5575 +#define AT91C_BASE_MCI0 (AT91_CAST(AT91PS_MCI) 0xFFF80000) // (MCI0) Base Address
  5576 +#define AT91C_BASE_PDC_MCI1 (AT91_CAST(AT91PS_PDC) 0xFFF84100) // (PDC_MCI1) Base Address
  5577 +#define AT91C_BASE_MCI1 (AT91_CAST(AT91PS_MCI) 0xFFF84000) // (MCI1) Base Address
  5578 +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFF88000) // (TWI) Base Address
  5579 +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFF8C100) // (PDC_US0) Base Address
  5580 +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFF8C000) // (US0) Base Address
  5581 +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFF90100) // (PDC_US1) Base Address
  5582 +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFF90000) // (US1) Base Address
  5583 +#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFF94100) // (PDC_US2) Base Address
  5584 +#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFF94000) // (US2) Base Address
  5585 +#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFF98100) // (PDC_SSC0) Base Address
  5586 +#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFF98000) // (SSC0) Base Address
  5587 +#define AT91C_BASE_PDC_SSC1 (AT91_CAST(AT91PS_PDC) 0xFFF9C100) // (PDC_SSC1) Base Address
  5588 +#define AT91C_BASE_SSC1 (AT91_CAST(AT91PS_SSC) 0xFFF9C000) // (SSC1) Base Address
  5589 +#define AT91C_BASE_PDC_AC97C (AT91_CAST(AT91PS_PDC) 0xFFFA0100) // (PDC_AC97C) Base Address
  5590 +#define AT91C_BASE_AC97C (AT91_CAST(AT91PS_AC97C) 0xFFFA0000) // (AC97C) Base Address
  5591 +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFA4100) // (PDC_SPI0) Base Address
  5592 +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFA4000) // (SPI0) Base Address
  5593 +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_SPI1) Base Address
  5594 +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFA8000) // (SPI1) Base Address
  5595 +#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC200) // (CAN_MB0) Base Address
  5596 +#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC220) // (CAN_MB1) Base Address
  5597 +#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC240) // (CAN_MB2) Base Address
  5598 +#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC260) // (CAN_MB3) Base Address
  5599 +#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC280) // (CAN_MB4) Base Address
  5600 +#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC2A0) // (CAN_MB5) Base Address
  5601 +#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC2C0) // (CAN_MB6) Base Address
  5602 +#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC2E0) // (CAN_MB7) Base Address
  5603 +#define AT91C_BASE_CAN_MB8 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC300) // (CAN_MB8) Base Address
  5604 +#define AT91C_BASE_CAN_MB9 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC320) // (CAN_MB9) Base Address
  5605 +#define AT91C_BASE_CAN_MB10 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC340) // (CAN_MB10) Base Address
  5606 +#define AT91C_BASE_CAN_MB11 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC360) // (CAN_MB11) Base Address
  5607 +#define AT91C_BASE_CAN_MB12 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC380) // (CAN_MB12) Base Address
  5608 +#define AT91C_BASE_CAN_MB13 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC3A0) // (CAN_MB13) Base Address
  5609 +#define AT91C_BASE_CAN_MB14 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC3C0) // (CAN_MB14) Base Address
  5610 +#define AT91C_BASE_CAN_MB15 (AT91_CAST(AT91PS_CAN_MB) 0xFFFAC3E0) // (CAN_MB15) Base Address
  5611 +#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFAC000) // (CAN) Base Address
  5612 +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFB8200) // (PWMC_CH0) Base Address
  5613 +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFB8220) // (PWMC_CH1) Base Address
  5614 +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFB8240) // (PWMC_CH2) Base Address
  5615 +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFB8260) // (PWMC_CH3) Base Address
  5616 +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFB8000) // (PWMC) Base Address
  5617 +#define AT91C_BASE_MACB (AT91_CAST(AT91PS_EMAC) 0xFFFBC000) // (MACB) Base Address
  5618 +#define AT91C_BASE_LCDC (AT91_CAST(AT91PS_LCDC) 0x00700000) // (LCDC) Base Address
  5619 +#define AT91C_BASE_DMA (AT91_CAST(AT91PS_DMA) 0x00800000) // (DMA) Base Address
  5620 +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFF78000) // (UDP) Base Address
  5621 +#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00A00000) // (UHP) Base Address
  5622 +#define AT91C_BASE_TBOX (AT91_CAST(AT91PS_TBOX) 0x70000000) // (TBOX) Base Address
  5623 +#define AT91C_BASE_HECC0 (AT91_CAST(AT91PS_ECC) 0xFFFFE000) // (HECC0) Base Address
  5624 +#define AT91C_BASE_HECC1 (AT91_CAST(AT91PS_ECC) 0xFFFFE600) // (HECC1) Base Address
  5625 +#define AT91C_BASE_HISI (AT91_CAST(AT91PS_ISI) 0xFFFC4000) // (HISI) Base Address
  5626 +
  5627 +// *****************************************************************************
  5628 +// MEMORY MAPPING DEFINITIONS FOR AT91SAM9263
  5629 +// *****************************************************************************
  5630 +// ITCM
  5631 +#define AT91C_ITCM (0x00100000) // Maximum ITCM Area base address
  5632 +#define AT91C_ITCM_SIZE (0x00010000) // Maximum ITCM Area size in byte (64 Kbytes)
  5633 +// DTCM
  5634 +#define AT91C_DTCM (0x00200000) // Maximum DTCM Area base address
  5635 +#define AT91C_DTCM_SIZE (0x00010000) // Maximum DTCM Area size in byte (64 Kbytes)
  5636 +// IRAM
  5637 +#define AT91C_IRAM (0x00300000) // Maximum Internal SRAM base address
  5638 +#define AT91C_IRAM_SIZE (0x00014000) // Maximum Internal SRAM size in byte (80 Kbytes)
  5639 +// IRAM_MIN
  5640 +#define AT91C_IRAM_MIN (0x00300000) // Minimum Internal RAM base address
  5641 +#define AT91C_IRAM_MIN_SIZE (0x00004000) // Minimum Internal RAM size in byte (16 Kbytes)
  5642 +// IROM
  5643 +#define AT91C_IROM (0x00400000) // Internal ROM base address
  5644 +#define AT91C_IROM_SIZE (0x00020000) // Internal ROM size in byte (128 Kbytes)
  5645 +// IRAM2
  5646 +#define AT91C_IRAM2 (0x00500000) // IRAM2 base address
  5647 +#define AT91C_IRAM2_SIZE (0x00004000) // IRAM2 size in byte (16 Kbytes)
  5648 +// EBI0_CS0
  5649 +#define AT91C_EBI0_CS0 (0x10000000) // EBI0 Chip Select 0 base address
  5650 +#define AT91C_EBI0_CS0_SIZE (0x10000000) // EBI0 Chip Select 0 size in byte (262144 Kbytes)
  5651 +// EBI0_CS1
  5652 +#define AT91C_EBI0_CS1 (0x20000000) // EBI0 Chip Select 1 base address
  5653 +#define AT91C_EBI0_CS1_SIZE (0x10000000) // EBI0 Chip Select 1 size in byte (262144 Kbytes)
  5654 +// EBI0_SDRAM
  5655 +#define AT91C_EBI0_SDRAM (0x20000000) // SDRAM on EBI0 Chip Select 1 base address
  5656 +#define AT91C_EBI0_SDRAM_SIZE (0x10000000) // SDRAM on EBI0 Chip Select 1 size in byte (262144 Kbytes)
  5657 +// EBI0_SDRAM_16BIT
  5658 +#define AT91C_EBI0_SDRAM_16BIT (0x20000000) // SDRAM on EBI0 Chip Select 1 base address
  5659 +#define AT91C_EBI0_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI0 Chip Select 1 size in byte (32768 Kbytes)
  5660 +// EBI0_SDRAM_32BIT
  5661 +#define AT91C_EBI0_SDRAM_32BIT (0x20000000) // SDRAM on EBI0 Chip Select 1 base address
  5662 +#define AT91C_EBI0_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI0 Chip Select 1 size in byte (65536 Kbytes)
  5663 +// EBI0_CS2
  5664 +#define AT91C_EBI0_CS2 (0x30000000) // EBI0 Chip Select 2 base address
  5665 +#define AT91C_EBI0_CS2_SIZE (0x10000000) // EBI0 Chip Select 2 size in byte (262144 Kbytes)
  5666 +// EBI0_CS3
  5667 +#define AT91C_EBI0_CS3 (0x40000000) // EBI0 Chip Select 3 base address
  5668 +#define AT91C_EBI0_CS3_SIZE (0x10000000) // EBI0 Chip Select 3 size in byte (262144 Kbytes)
  5669 +// EBI0_SM
  5670 +#define AT91C_EBI0_SM (0x40000000) // SmartMedia on EBI0 Chip Select 3 base address
  5671 +#define AT91C_EBI0_SM_SIZE (0x10000000) // SmartMedia on EBI0 Chip Select 3 size in byte (262144 Kbytes)
  5672 +// EBI0_CS4
  5673 +#define AT91C_EBI0_CS4 (0x50000000) // EBI0 Chip Select 4 base address
  5674 +#define AT91C_EBI0_CS4_SIZE (0x10000000) // EBI0 Chip Select 4 size in byte (262144 Kbytes)
  5675 +// EBI0_CF0
  5676 +#define AT91C_EBI0_CF0 (0x50000000) // CompactFlash 0 on EBI0 Chip Select 4 base address
  5677 +#define AT91C_EBI0_CF0_SIZE (0x10000000) // CompactFlash 0 on EBI0 Chip Select 4 size in byte (262144 Kbytes)
  5678 +// EBI0_CS5
  5679 +#define AT91C_EBI0_CS5 (0x60000000) // EBI0 Chip Select 5 base address
  5680 +#define AT91C_EBI0_CS5_SIZE (0x10000000) // EBI0 Chip Select 5 size in byte (262144 Kbytes)
  5681 +// EBI0_CF1
  5682 +#define AT91C_EBI0_CF1 (0x60000000) // CompactFlash 1 on EBI0Chip Select 5 base address
  5683 +#define AT91C_EBI0_CF1_SIZE (0x10000000) // CompactFlash 1 on EBI0Chip Select 5 size in byte (262144 Kbytes)
  5684 +// EBI1_CS0
  5685 +#define AT91C_EBI1_CS0 (0x70000000) // EBI1 Chip Select 0 base address
  5686 +#define AT91C_EBI1_CS0_SIZE (0x10000000) // EBI1 Chip Select 0 size in byte (262144 Kbytes)
  5687 +// EBI1_CS1
  5688 +#define AT91C_EBI1_CS1 (0x80000000) // EBI1 Chip Select 1 base address
  5689 +#define AT91C_EBI1_CS1_SIZE (0x10000000) // EBI1 Chip Select 1 size in byte (262144 Kbytes)
  5690 +// EBI1_SDRAM_16BIT
  5691 +#define AT91C_EBI1_SDRAM_16BIT (0x80000000) // SDRAM on EBI1 Chip Select 1 base address
  5692 +#define AT91C_EBI1_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI1 Chip Select 1 size in byte (32768 Kbytes)
  5693 +// EBI1_SDRAM_32BIT
  5694 +#define AT91C_EBI1_SDRAM_32BIT (0x80000000) // SDRAM on EBI1 Chip Select 1 base address
  5695 +#define AT91C_EBI1_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI1 Chip Select 1 size in byte (65536 Kbytes)
  5696 +// EBI1_CS2
  5697 +#define AT91C_EBI1_CS2 (0x90000000) // EBI1 Chip Select 2 base address
  5698 +#define AT91C_EBI1_CS2_SIZE (0x10000000) // EBI1 Chip Select 2 size in byte (262144 Kbytes)
  5699 +// EBI1_SM
  5700 +#define AT91C_EBI1_SM (0x90000000) // SmartMedia on EBI1 Chip Select 2 base address
  5701 +#define AT91C_EBI1_SM_SIZE (0x10000000) // SmartMedia on EBI1 Chip Select 2 size in byte (262144 Kbytes)
  5702 +
  5703 +#endif
... ...
virtual_lab/include/project.h 0 → 100644
  View file @0637b04
  1 +/* ----------------------------------------------------------------------------
  2 + * ATMEL Microcontroller Software Support - ROUSSET -
  3 + * ----------------------------------------------------------------------------
  4 + * Copyright (c) 2006, Atmel Corporation
  5 + *
  6 + * All rights reserved.
  7 + *
  8 + * Redistribution and use in source and binary forms, with or without
  9 + * modification, are permitted provided that the following conditions are met:
  10 + *
  11 + * - Redistributions of source code must retain the above copyright notice,
  12 + * this list of conditions and the disclaiimer below.
  13 + *
  14 + * - Redistributions in binary form must reproduce the above copyright notice,
  15 + * this list of conditions and the disclaimer below in the documentation and/or
  16 + * other materials provided with the distribution.
  17 + *
  18 + * Atmel's name may not be used to endorse or promote products derived from
  19 + * this software without specific prior written permission.
  20 + *
  21 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  22 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  24 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  25 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  27 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  28 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  29 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31 + * ----------------------------------------------------------------------------
  32 + */
  33 +/*-----------------------------------------------------------------------------
  34 + * File Name : project.h
  35 + * Object : project specific include file
  36 + * Creation : FDy 10-Nov-2006
  37 + *-----------------------------------------------------------------------------
  38 + */
  39 +#ifndef _PROJECT_H
  40 +#define _PROJECT_H
  41 +
  42 +/// Include your AT91 Library files and specific compiler definitions
  43 +
  44 +#include "AT91SAM9263-EK.h"
  45 +#include "AT91SAM9263.h"
  46 +
  47 +#ifndef __ASSEMBLY__
  48 +extern void dbgu_print_ascii(const char *buffer);
  49 +extern void dbgu_print_hex8(unsigned long);
  50 +#endif
  51 +
  52 +#endif // _PROJECT_H
... ...
virtual_lab/lowlevel.c 0 → 100644
  View file @0637b04
  1 +/* ----------------------------------------------------------------------------
  2 + * ATMEL Microcontroller Software Support - ROUSSET -
  3 + * ----------------------------------------------------------------------------
  4 + * Copyright (c) 2006, Atmel Corporation
  5 + *
  6 + * All rights reserved.
  7 + *
  8 + * Redistribution and use in source and binary forms, with or without
  9 + * modification, are permitted provided that the following conditions are met:
  10 + *
  11 + * - Redistributions of source code must retain the above copyright notice,
  12 + * this list of conditions and the disclaiimer below.
  13 + *
  14 + * - Redistributions in binary form must reproduce the above copyright notice,
  15 + * this list of conditions and the disclaimer below in the documentation and/or
  16 + * other materials provided with the distribution.
  17 + *
  18 + * Atmel's name may not be used to endorse or promote products derived from
  19 + * this software without specific prior written permission.
  20 + *
  21 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  22 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  24 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  25 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  27 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  28 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  29 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31 + * ----------------------------------------------------------------------------
  32 + */
  33 +/*-----------------------------------------------------------------------------
  34 + * File Name : lowlevel.c
  35 + * Object : low level initialization file
  36 + * Creation : FDy 20-Nov-2006
  37 + *-----------------------------------------------------------------------------
  38 + */
  39 +
  40 +/* Include Standard files */
  41 +#include "project.h"
  42 +
  43 +
  44 +/*-----------------------------------------------------------------------------
  45 + * Function Name : default_spurious_handler
  46 + * Object : default handler for spurious interrupt
  47 + *-----------------------------------------------------------------------------*/
  48 +void default_spurious_handler(void)
  49 +{
  50 + dbgu_print_ascii("-F- Spurious Interrupt\n\r ");
  51 + while (1);
  52 +}
  53 +
  54 +/*-----------------------------------------------------------------------------
  55 + * Function Name : default_fiq_handler
  56 + * Object : default handler for fast interrupt
  57 + *-----------------------------------------------------------------------------*/
  58 +void default_fiq_handler(void)
  59 +{
  60 + dbgu_print_ascii("-F- Unexpected FIQ Interrupt\n\r ");
  61 + while (1);
  62 +}
  63 +
  64 +/*-----------------------------------------------------------------------------
  65 + * Function Name : default_irq_handler
  66 + * Object : default handler for irq
  67 + *-----------------------------------------------------------------------------*/
  68 +void default_irq_handler(void)
  69 +{
  70 + dbgu_print_ascii("-F- Unexpected IRQ Interrupt\n\r ");
  71 + while (1);
  72 +}
  73 +
  74 +/*-----------------------------------------------------------------------------
  75 + * Function Name : lowlevel_init
  76 + * Object : This function performs very low level HW initialization
  77 + * this function can use a Stack, depending the compilation
  78 + * optimization mode
  79 + *-----------------------------------------------------------------------------*/
  80 +void lowlevel_init(void)
  81 +{
  82 + unsigned char i = 0;
  83 +
  84 + ///////////////////////////////////////////////////////////////////////////
  85 + // Init PMC Step 1. Enable Main Oscillator
  86 + // Main Oscillator startup time is board specific:
  87 + // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms
  88 + // (0x40 for AT91C_CKGR_OSCOUNT field)
  89 + ///////////////////////////////////////////////////////////////////////////
  90 + AT91C_BASE_PMC->PMC_MOR = (((AT91C_CKGR_OSCOUNT & (0x40 << 8)) | AT91C_CKGR_MOSCEN));
  91 + // Wait Main Oscillator stabilization
  92 + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
  93 +
  94 + ///////////////////////////////////////////////////////////////////////////
  95 + // Init PMC Step 2.
  96 + // Set PLLA to 200MHz (198,656MHz)
  97 + // PLL Startup time depends on PLL RC filter: worst case is choosen
  98 + ///////////////////////////////////////////////////////////////////////////
  99 + AT91C_BASE_PMC->PMC_PLLAR = AT91C_CKGR_SRCA |
  100 + AT91C_CKGR_OUTA_2 |
  101 + (0x3F << 8) |
  102 + (AT91C_CKGR_MULA & (0x6D << 16)) |
  103 + (AT91C_CKGR_DIVA & 9);
  104 + // Wait for PLLA stabilization
  105 + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
  106 + // Wait until the master clock is established for the case we already
  107 + // turn on the PLLA
  108 + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
  109 +
  110 + ///////////////////////////////////////////////////////////////////////////
  111 + // Init PMC Step 3.
  112 + // Selection of Master Clock MCK equal to (Processor Clock PCK) PLLA/2=100MHz
  113 + // The PMC_MCKR register must not be programmed in a single write operation
  114 + // (see. Product Errata Sheet)
  115 + ///////////////////////////////////////////////////////////////////////////
  116 + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;
  117 + // Wait until the master clock is established
  118 + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
  119 +
  120 + AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;
  121 + // Wait until the master clock is established
  122 + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
  123 +
  124 + ///////////////////////////////////////////////////////////////////////////
  125 + // Reset AIC: assign default handler for each interrupt source
  126 + ///////////////////////////////////////////////////////////////////////////
  127 + AT91C_BASE_AIC->AIC_SVR[0] = (int) default_fiq_handler ;
  128 + for (i = 1; i < 31; i++) {
  129 + AT91C_BASE_AIC->AIC_SVR[i] = (int) default_irq_handler ;
  130 + }
  131 + AT91C_BASE_AIC->AIC_SPU = (unsigned int) default_spurious_handler;
  132 +
  133 + // Perform 8 IT acknoledge (write any value in EOICR)
  134 + for (i = 0; i < 8 ; i++) {
  135 + AT91C_BASE_AIC->AIC_EOICR = 0;
  136 + }
  137 +
  138 + ///////////////////////////////////////////////////////////////////////////
  139 + // Disable Watchdog
  140 + ///////////////////////////////////////////////////////////////////////////
  141 + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
  142 +
  143 + ///////////////////////////////////////////////////////////////////////////
  144 + // Remap
  145 + ///////////////////////////////////////////////////////////////////////////
  146 + AT91C_BASE_MATRIX->MATRIX_MRCR = AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D;
  147 +}
... ...
virtual_lab/main.c
  View file @0637b04
1   -int main()
  1 +#include <stdint.h>
  2 +#include <stdbool.h>
  3 +
  4 +#define PB_PER (*((volatile uint32_t*)0xFFFFF400))
  5 +#define PB_OER (*((volatile uint32_t*)0xFFFFF410))
  6 +#define PB_SODR (*((volatile uint32_t*)0xFFFFF430))
  7 +#define PB_CODR (*((volatile uint32_t*)0xFFFFF434))
  8 +#define PB_PDSR (*((volatile uint32_t*)0xFFFFF43C))
  9 +
  10 +#define PC_PER (*((volatile uint32_t*)0xFFFFF600))
  11 +#define PC_ODR (*((volatile uint32_t*)0xFFFFF614))
  12 +#define PC_OER (*((volatile uint32_t*)0xFFFFF610))
  13 +#define PC_SODR (*((volatile uint32_t*)0xFFFFF630))
  14 +#define PC_CODR (*((volatile uint32_t*)0xFFFFF634))
  15 +#define PC_PDSR (*((volatile uint32_t*)0xFFFFF63C))
  16 +#define PC_PUER (*((volatile uint32_t*)0xFFFFF664))
  17 +
  18 +#define PMC_PCER (*((volatile uint32_t*)0xFFFFFC10))
  19 +
  20 +#define PER_ID_PBIOC_TO_PIOE 4
  21 +
  22 +#define DS1 (1 << 8) //PB8
  23 +#define DS2 (1 << 29) //PC29
  24 +
  25 +#define BT2 (1 << 4) //PC4
  26 +#define BT1 (1 << 5) //PC5
  27 +
  28 +void _exit(int c){while(1);};
  29 +
  30 +void dabt_handler(){};
  31 +void pabt_handler(){};
  32 +void dbgu_print_ascii(){};;
  33 +
  34 +void delay(void)
2 35 {
3   - while(1);
4   -}
5 36 \ No newline at end of file
  37 + volatile uint32_t i;
  38 + for(i = 0; i < 1000000; i++);
  39 +}
  40 +
  41 +int main(void)
  42 +{
  43 + PMC_PCER = 1 << PER_ID_PBIOC_TO_PIOE;
  44 + PB_PER = DS1; //PIO enable register
  45 + PB_OER = DS1; //PIO controller output enable register
  46 + PC_PER = DS2 | BT1 | BT2; //PIO enable register
  47 + PC_OER = DS2; //PIO controller output enable register
  48 + PC_ODR = BT1 | BT2;
  49 + PC_PUER = BT1 | BT2;
  50 + while(true)
  51 + {
  52 + /*
  53 + PB_SODR = DS1;
  54 + PC_CODR = DS2;
  55 + delay();
  56 + PB_CODR = DS1;
  57 + PC_SODR = DS2;
  58 + delay();
  59 + */
  60 + if(PC_PDSR & BT1)
  61 + PB_SODR = DS1;
  62 + else
  63 + PB_CODR = DS1;
  64 + if(PC_PDSR & BT2)
  65 + PC_SODR = DS2;
  66 + else
  67 + PC_CODR = DS2;
  68 + }
  69 +}
... ...
virtual_lab/script.lds 0 → 100644
  View file @0637b04
  1 +/* Script for -z combreloc */
  2 +/* Copyright (C) 2014-2020 Free Software Foundation, Inc.
  3 + Copying and distribution of this script, with or without modification,
  4 + are permitted in any medium without royalty provided the copyright
  5 + notice and this notice are preserved. */
  6 +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
  7 + "elf32-littlearm")
  8 +OUTPUT_ARCH(arm)
  9 +ENTRY(_start)
  10 +SEARCH_DIR("/usr/lib/arm-none-eabi/lib");
  11 +SECTIONS
  12 +{
  13 + /* Read-only sections, merged into text segment: */
  14 + PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x8000)); . = SEGMENT_START("text-segment", 0x8000);
  15 + .interp : { *(.interp) }
  16 + .note.gnu.build-id : { *(.note.gnu.build-id) }
  17 + .hash : { *(.hash) }
  18 + .gnu.hash : { *(.gnu.hash) }
  19 + .dynsym : { *(.dynsym) }
  20 + .dynstr : { *(.dynstr) }
  21 + .gnu.version : { *(.gnu.version) }
  22 + .gnu.version_d : { *(.gnu.version_d) }
  23 + .gnu.version_r : { *(.gnu.version_r) }
  24 + .rel.dyn :
  25 + {
  26 + *(.rel.init)
  27 + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
  28 + *(.rel.fini)
  29 + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
  30 + *(.rel.data.rel.ro .rel.data.rel.ro.* .rel.gnu.linkonce.d.rel.ro.*)
  31 + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
  32 + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
  33 + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
  34 + *(.rel.ctors)
  35 + *(.rel.dtors)
  36 + *(.rel.got)
  37 + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
  38 + PROVIDE_HIDDEN (__rel_iplt_start = .);
  39 + *(.rel.iplt)
  40 + PROVIDE_HIDDEN (__rel_iplt_end = .);
  41 + }
  42 + .rela.dyn :
  43 + {
  44 + *(.rela.init)
  45 + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
  46 + *(.rela.fini)
  47 + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
  48 + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
  49 + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
  50 + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
  51 + *(.rela.ctors)
  52 + *(.rela.dtors)
  53 + *(.rela.got)
  54 + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
  55 + PROVIDE_HIDDEN (__rela_iplt_start = .);
  56 + *(.rela.iplt)
  57 + PROVIDE_HIDDEN (__rela_iplt_end = .);
  58 + }
  59 + .rel.plt :
  60 + {
  61 + *(.rel.plt)
  62 + }
  63 + .rela.plt :
  64 + {
  65 + *(.rela.plt)
  66 + }
  67 + .init :
  68 + {
  69 + KEEP (*(SORT_NONE(.init)))
  70 + }
  71 + .plt : { *(.plt) }
  72 + .iplt : { *(.iplt) }
  73 + .text :
  74 + {
  75 + *(.text.unlikely .text.*_unlikely .text.unlikely.*)
  76 + *(.text.exit .text.exit.*)
  77 + *(.text.startup .text.startup.*)
  78 + *(.text.hot .text.hot.*)
  79 + *(SORT(.text.sorted.*))
  80 + *(.text .stub .text.* .gnu.linkonce.t.*)
  81 + /* .gnu.warning sections are handled specially by elf.em. */
  82 + *(.gnu.warning)
  83 + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
  84 + }
  85 + .fini :
  86 + {
  87 + KEEP (*(SORT_NONE(.fini)))
  88 + }
  89 + PROVIDE (__etext = .);
  90 + PROVIDE (_etext = .);
  91 + PROVIDE (etext = .);
  92 + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
  93 + .rodata1 : { *(.rodata1) }
  94 + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
  95 + .ARM.exidx :
  96 + {
  97 + PROVIDE_HIDDEN (__exidx_start = .);
  98 + *(.ARM.exidx* .gnu.linkonce.armexidx.*)
  99 + PROVIDE_HIDDEN (__exidx_end = .);
  100 + }
  101 + .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
  102 + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) }
  103 + .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }
  104 + .gnu_extab : ONLY_IF_RO { *(.gnu_extab*) }
  105 + /* These sections are generated by the Sun/Oracle C++ compiler. */
  106 + .exception_ranges : ONLY_IF_RO { *(.exception_ranges*) }
  107 + /* Adjust the address for the data segment. We want to adjust up to
  108 + the same address within the page on the next page up. */
  109 + . = ALIGN(CONSTANT (MAXPAGESIZE)) + (. & (CONSTANT (MAXPAGESIZE) - 1));
  110 + /* Exception handling */
  111 + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) }
  112 + .gnu_extab : ONLY_IF_RW { *(.gnu_extab) }
  113 + .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
  114 + .exception_ranges : ONLY_IF_RW { *(.exception_ranges*) }
  115 + /* Thread Local Storage sections */
  116 + .tdata :
  117 + {
  118 + PROVIDE_HIDDEN (__tdata_start = .);
  119 + *(.tdata .tdata.* .gnu.linkonce.td.*)
  120 + }
  121 + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
  122 + .preinit_array :
  123 + {
  124 + PROVIDE_HIDDEN (__preinit_array_start = .);
  125 + KEEP (*(.preinit_array))
  126 + PROVIDE_HIDDEN (__preinit_array_end = .);
  127 + }
  128 + .init_array :
  129 + {
  130 + PROVIDE_HIDDEN (__init_array_start = .);
  131 + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
  132 + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
  133 + PROVIDE_HIDDEN (__init_array_end = .);
  134 + }
  135 + .fini_array :
  136 + {
  137 + PROVIDE_HIDDEN (__fini_array_start = .);
  138 + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
  139 + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
  140 + PROVIDE_HIDDEN (__fini_array_end = .);
  141 + }
  142 + .ctors :
  143 + {
  144 + /* gcc uses crtbegin.o to find the start of
  145 + the constructors, so we make sure it is
  146 + first. Because this is a wildcard, it
  147 + doesn't matter if the user does not
  148 + actually link against crtbegin.o; the
  149 + linker won't look for a file to match a
  150 + wildcard. The wildcard also means that it
  151 + doesn't matter which directory crtbegin.o
  152 + is in. */
  153 + KEEP (*crtbegin.o(.ctors))
  154 + KEEP (*crtbegin?.o(.ctors))
  155 + /* We don't want to include the .ctor section from
  156 + the crtend.o file until after the sorted ctors.
  157 + The .ctor section from the crtend file contains the
  158 + end of ctors marker and it must be last */
  159 + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
  160 + KEEP (*(SORT(.ctors.*)))
  161 + KEEP (*(.ctors))
  162 + }
  163 + .dtors :
  164 + {
  165 + KEEP (*crtbegin.o(.dtors))
  166 + KEEP (*crtbegin?.o(.dtors))
  167 + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
  168 + KEEP (*(SORT(.dtors.*)))
  169 + KEEP (*(.dtors))
  170 + }
  171 + .jcr : { KEEP (*(.jcr)) }
  172 + .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }
  173 + .dynamic : { *(.dynamic) }
  174 + .got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }
  175 + _sdata = .;
  176 + .data :
  177 + {
  178 + __data_start = .;
  179 + *(.data .data.* .gnu.linkonce.d.*)
  180 + SORT(CONSTRUCTORS)
  181 + }
  182 + .data1 : { *(.data1) }
  183 + _edata = .; PROVIDE (edata = .);
  184 + . = .;
  185 + __bss_start = .;
  186 + __bss_start__ = .;
  187 + _sbss = .;
  188 + .bss :
  189 + {
  190 + *(.dynbss)
  191 + *(.bss .bss.* .gnu.linkonce.b.*)
  192 + *(COMMON)
  193 + /* Align here to ensure that the .bss section occupies space up to
  194 + _end. Align after .bss to ensure correct alignment even if the
  195 + .bss section disappears because there are no input sections.
  196 + FIXME: Why do we need it? When there is no .bss section, we do not
  197 + pad the .data section. */
  198 + . = ALIGN(. != 0 ? 32 / 8 : 1);
  199 + }
  200 + _bss_end__ = .; __bss_end__ = .;
  201 + _ebss = .;
  202 + . = ALIGN(32 / 8);
  203 + . = SEGMENT_START("ldata-segment", .);
  204 + . = ALIGN(32 / 8);
  205 + __end__ = .;
  206 + _end = .; PROVIDE (end = .);
  207 + .stack 0x80000 :
  208 + {
  209 + _stack = .;
  210 + *(.stack)
  211 + }
  212 + /* Stabs debugging sections. */
  213 + .stab 0 : { *(.stab) }
  214 + .stabstr 0 : { *(.stabstr) }
  215 + .stab.excl 0 : { *(.stab.excl) }
  216 + .stab.exclstr 0 : { *(.stab.exclstr) }
  217 + .stab.index 0 : { *(.stab.index) }
  218 + .stab.indexstr 0 : { *(.stab.indexstr) }
  219 + .comment 0 : { *(.comment) }
  220 + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
  221 + /* DWARF debug sections.
  222 + Symbols in the DWARF debugging sections are relative to the beginning
  223 + of the section so we begin them at 0. */
  224 + /* DWARF 1 */
  225 + .debug 0 : { *(.debug) }
  226 + .line 0 : { *(.line) }
  227 + /* GNU DWARF 1 extensions */
  228 + .debug_srcinfo 0 : { *(.debug_srcinfo) }
  229 + .debug_sfnames 0 : { *(.debug_sfnames) }
  230 + /* DWARF 1.1 and DWARF 2 */
  231 + .debug_aranges 0 : { *(.debug_aranges) }
  232 + .debug_pubnames 0 : { *(.debug_pubnames) }
  233 + /* DWARF 2 */
  234 + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
  235 + .debug_abbrev 0 : { *(.debug_abbrev) }
  236 + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
  237 + .debug_frame 0 : { *(.debug_frame) }
  238 + .debug_str 0 : { *(.debug_str) }
  239 + .debug_loc 0 : { *(.debug_loc) }
  240 + .debug_macinfo 0 : { *(.debug_macinfo) }
  241 + /* SGI/MIPS DWARF 2 extensions */
  242 + .debug_weaknames 0 : { *(.debug_weaknames) }
  243 + .debug_funcnames 0 : { *(.debug_funcnames) }
  244 + .debug_typenames 0 : { *(.debug_typenames) }
  245 + .debug_varnames 0 : { *(.debug_varnames) }
  246 + /* DWARF 3 */
  247 + .debug_pubtypes 0 : { *(.debug_pubtypes) }
  248 + .debug_ranges 0 : { *(.debug_ranges) }
  249 + /* DWARF Extension. */
  250 + .debug_macro 0 : { *(.debug_macro) }
  251 + .debug_addr 0 : { *(.debug_addr) }
  252 + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }
  253 +.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
  254 +/* This section contains data that is not initialised during load
  255 + *or* application reset. */
  256 + .noinit (NOLOAD) :
  257 + {
  258 + . = ALIGN(2);
  259 + PROVIDE (__noinit_start = .);
  260 + *(.noinit)
  261 + . = ALIGN(2);
  262 + PROVIDE (__noinit_end = .);
  263 + }
  264 + /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
  265 +}
... ...