gwj / at91sam9263 · Commits

Commit 00f219bf50f05f75706baa7e6660c9fd1095b666

Authored by blueswir1
1 parent 38bc628b

Convert movr and (partially) movcc to TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4010 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 42 additions and 24 deletions
target-sparc/op.c
  View file @00f219b
@@ -1589,12 +1589,6 @@ void OPPROTO op_fmovq_cc(void) @@ -1589,12 +1589,6 @@ void OPPROTO op_fmovq_cc(void)
1589 } 1589 }
1590 #endif 1590 #endif
1591 1591
1592 -void OPPROTO op_mov_cc(void)  
1593 -{  
1594 - if (T2)  
1595 - T0 = T1;  
1596 -}  
1597 -  
1598 void OPPROTO op_flushw(void) 1592 void OPPROTO op_flushw(void)
1599 { 1593 {
1600 if (env->cansave != NWINDOWS - 2) { 1594 if (env->cansave != NWINDOWS - 2) {
target-sparc/translate.c
  View file @00f219b
@@ -577,6 +577,18 @@ static void gen_cond_reg(int cond) @@ -577,6 +577,18 @@ static void gen_cond_reg(int cond)
577 break; 577 break;
578 } 578 }
579 } 579 }
  580 +
  581 +// Inverted logic
  582 +static const int gen_tcg_cond_reg[8] = {
  583 + -1,
  584 + TCG_COND_NE,
  585 + TCG_COND_GT,
  586 + TCG_COND_GE,
  587 + -1,
  588 + TCG_COND_EQ,
  589 + TCG_COND_LE,
  590 + TCG_COND_LT,
  591 +};
580 #endif 592 #endif
581 593
582 /* XXX: potentially incorrect if dynamic npc */ 594 /* XXX: potentially incorrect if dynamic npc */
@@ -2452,15 +2464,9 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2452,15 +2464,9 @@ static void disas_sparc_insn(DisasContext * dc)
2452 { 2464 {
2453 int cc = GET_FIELD_SP(insn, 11, 12); 2465 int cc = GET_FIELD_SP(insn, 11, 12);
2454 int cond = GET_FIELD_SP(insn, 14, 17); 2466 int cond = GET_FIELD_SP(insn, 14, 17);
2455 - if (IS_IMM) { /* immediate */  
2456 - rs2 = GET_FIELD_SPs(insn, 0, 10);  
2457 - gen_movl_simm_T1(rs2);  
2458 - }  
2459 - else {  
2460 - rs2 = GET_FIELD_SP(insn, 0, 4);  
2461 - gen_movl_reg_T1(rs2);  
2462 - }  
2463 - gen_movl_reg_T0(rd); 2467 + TCGv r_zero;
  2468 + int l1;
  2469 +
2464 flush_T2(dc); 2470 flush_T2(dc);
2465 if (insn & (1 << 18)) { 2471 if (insn & (1 << 18)) {
2466 if (cc == 0) 2472 if (cc == 0)
@@ -2472,8 +2478,21 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2472,8 +2478,21 @@ static void disas_sparc_insn(DisasContext * dc)
2472 } else { 2478 } else {
2473 gen_fcond[cc][cond](); 2479 gen_fcond[cc][cond]();
2474 } 2480 }
2475 - gen_op_mov_cc();  
2476 - gen_movl_T0_reg(rd); 2481 +
  2482 + l1 = gen_new_label();
  2483 +
  2484 + r_zero = tcg_temp_new(TCG_TYPE_TL);
  2485 + tcg_gen_movi_tl(r_zero, 0);
  2486 + tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[2], r_zero, l1);
  2487 + if (IS_IMM) { /* immediate */
  2488 + rs2 = GET_FIELD_SPs(insn, 0, 10);
  2489 + gen_movl_simm_T1(rs2);
  2490 + } else {
  2491 + rs2 = GET_FIELD_SP(insn, 0, 4);
  2492 + gen_movl_reg_T1(rs2);
  2493 + }
  2494 + gen_movl_T1_reg(rd);
  2495 + gen_set_label(l1);
2477 break; 2496 break;
2478 } 2497 }
2479 case 0x2d: /* V9 sdivx */ 2498 case 0x2d: /* V9 sdivx */
@@ -2498,21 +2517,26 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2498,21 +2517,26 @@ static void disas_sparc_insn(DisasContext * dc)
2498 case 0x2f: /* V9 movr */ 2517 case 0x2f: /* V9 movr */
2499 { 2518 {
2500 int cond = GET_FIELD_SP(insn, 10, 12); 2519 int cond = GET_FIELD_SP(insn, 10, 12);
  2520 + TCGv r_zero;
  2521 + int l1;
  2522 +
2501 rs1 = GET_FIELD(insn, 13, 17); 2523 rs1 = GET_FIELD(insn, 13, 17);
2502 - flush_T2(dc);  
2503 gen_movl_reg_T0(rs1); 2524 gen_movl_reg_T0(rs1);
2504 - gen_cond_reg(cond); 2525 +
  2526 + l1 = gen_new_label();
  2527 +
  2528 + r_zero = tcg_temp_new(TCG_TYPE_TL);
  2529 + tcg_gen_movi_tl(r_zero, 0);
  2530 + tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
2505 if (IS_IMM) { /* immediate */ 2531 if (IS_IMM) { /* immediate */
2506 rs2 = GET_FIELD_SPs(insn, 0, 9); 2532 rs2 = GET_FIELD_SPs(insn, 0, 9);
2507 gen_movl_simm_T1(rs2); 2533 gen_movl_simm_T1(rs2);
2508 - }  
2509 - else { 2534 + } else {
2510 rs2 = GET_FIELD_SP(insn, 0, 4); 2535 rs2 = GET_FIELD_SP(insn, 0, 4);
2511 gen_movl_reg_T1(rs2); 2536 gen_movl_reg_T1(rs2);
2512 } 2537 }
2513 - gen_movl_reg_T0(rd);  
2514 - gen_op_mov_cc();  
2515 - gen_movl_T0_reg(rd); 2538 + gen_movl_T1_reg(rd);
  2539 + gen_set_label(l1);
2516 break; 2540 break;
2517 } 2541 }
2518 #endif 2542 #endif