gwj / at91sam9263 · Commits

Commit 38bc628b08e5d43024cb407cd0605a068fcc5536

Authored by blueswir1
1 parent 0cf767d6

Convert addx, subx, next_insn and mov_pc_npc to TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4009 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 29 additions and 27 deletions
target-sparc/op.c
  View file @38bc628
... ... @@ -215,11 +215,6 @@ void OPPROTO op_add_T1_T0_cc(void)
215 215 FORCE_RET();
216 216 }
217 217  
218   -void OPPROTO op_addx_T1_T0(void)
219   -{
220   - T0 += T1 + FLAG_SET(PSR_CARRY);
221   -}
222   -
223 218 void OPPROTO op_addx_T1_T0_cc(void)
224 219 {
225 220 target_ulong src1;
... ... @@ -413,11 +408,6 @@ void OPPROTO op_sub_T1_T0_cc(void)
413 408 FORCE_RET();
414 409 }
415 410  
416   -void OPPROTO op_subx_T1_T0(void)
417   -{
418   - T0 -= T1 + FLAG_SET(PSR_CARRY);
419   -}
420   -
421 411 void OPPROTO op_subx_T1_T0_cc(void)
422 412 {
423 413 target_ulong src1;
... ... @@ -1184,17 +1174,6 @@ void OPPROTO op_eval_brgez(void)
1184 1174 }
1185 1175 #endif
1186 1176  
1187   -void OPPROTO op_mov_pc_npc(void)
1188   -{
1189   - env->pc = env->npc;
1190   -}
1191   -
1192   -void OPPROTO op_next_insn(void)
1193   -{
1194   - env->pc = env->npc;
1195   - env->npc = env->npc + 4;
1196   -}
1197   -
1198 1177 void OPPROTO op_jmp_label(void)
1199 1178 {
1200 1179 GOTO_LABEL_PARAM(1);
... ...
target-sparc/translate.c
  View file @38bc628
... ... @@ -412,16 +412,26 @@ static inline void gen_mov_pc_npc(DisasContext * dc)
412 412 {
413 413 if (dc->npc == JUMP_PC) {
414 414 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
415   - gen_op_mov_pc_npc();
  415 + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
  416 + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
416 417 dc->pc = DYNAMIC_PC;
417 418 } else if (dc->npc == DYNAMIC_PC) {
418   - gen_op_mov_pc_npc();
  419 + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
  420 + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
419 421 dc->pc = DYNAMIC_PC;
420 422 } else {
421 423 dc->pc = dc->npc;
422 424 }
423 425 }
424 426  
  427 +static inline void gen_op_next_insn(void)
  428 +{
  429 + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
  430 + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
  431 + tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4);
  432 + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
  433 +}
  434 +
425 435 static GenOpFunc * const gen_cond[2][16] = {
426 436 {
427 437 gen_op_eval_bn,
... ... @@ -991,6 +1001,13 @@ static inline void gen_ldstub_asi(int insn)
991 1001 }
992 1002 #endif
993 1003  
  1004 +static inline void gen_mov_reg_C(TCGv reg)
  1005 +{
  1006 + tcg_gen_ld_i32(reg, cpu_env, offsetof(CPUSPARCState, psr));
  1007 + tcg_gen_shri_i32(reg, reg, 20);
  1008 + tcg_gen_andi_i32(reg, reg, 0x1);
  1009 +}
  1010 +
994 1011 /* before an instruction, dc->pc must be static */
995 1012 static void disas_sparc_insn(DisasContext * dc)
996 1013 {
... ... @@ -2111,8 +2128,11 @@ static void disas_sparc_insn(DisasContext * dc)
2111 2128 case 0x8:
2112 2129 if (xop & 0x10)
2113 2130 gen_op_addx_T1_T0_cc();
2114   - else
2115   - gen_op_addx_T1_T0();
  2131 + else {
  2132 + gen_mov_reg_C(cpu_tmp0);
  2133 + tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
  2134 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  2135 + }
2116 2136 break;
2117 2137 #ifdef TARGET_SPARC64
2118 2138 case 0x9: /* V9 mulx */
... ... @@ -2132,8 +2152,11 @@ static void disas_sparc_insn(DisasContext * dc)
2132 2152 case 0xc:
2133 2153 if (xop & 0x10)
2134 2154 gen_op_subx_T1_T0_cc();
2135   - else
2136   - gen_op_subx_T1_T0();
  2155 + else {
  2156 + gen_mov_reg_C(cpu_tmp0);
  2157 + tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
  2158 + tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  2159 + }
2137 2160 break;
2138 2161 #ifdef TARGET_SPARC64
2139 2162 case 0xd: /* V9 udivx */
... ...