gwj / at91sam9263 · Commits

Commit 007ac6faed12abdd4113e2460ba4464aacb7f4dd

Authored by aurel32
1 parent 585c88d5

target-mips: fix call to check_*() functions 

check_*() functions may in fine call generate_exception(), which ends
by a call to tcg_gen_exit_tb(). As a consequence, we have to make sure
that no TCG temp variables are crossing a check_*() function.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7127 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 24 additions and 12 deletions
target-mips/translate.c
  View file @007ac6f
@@ -6382,10 +6382,13 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, @@ -6382,10 +6382,13 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6382 TCGv_i32 fp0 = tcg_temp_new_i32(); 6382 TCGv_i32 fp0 = tcg_temp_new_i32();
6383 TCGv_i32 fp1 = tcg_temp_new_i32(); 6383 TCGv_i32 fp1 = tcg_temp_new_i32();
6384 6384
  6385 + if (ctx->opcode & (1 << 6)) {
  6386 + check_cop1x(ctx);
  6387 + }
  6388 +
6385 gen_load_fpr32(fp0, fs); 6389 gen_load_fpr32(fp0, fs);
6386 gen_load_fpr32(fp1, ft); 6390 gen_load_fpr32(fp1, ft);
6387 if (ctx->opcode & (1 << 6)) { 6391 if (ctx->opcode & (1 << 6)) {
6388 - check_cop1x(ctx);  
6389 gen_cmpabs_s(func-48, fp0, fp1, cc); 6392 gen_cmpabs_s(func-48, fp0, fp1, cc);
6390 opn = condnames_abs[func-48]; 6393 opn = condnames_abs[func-48];
6391 } else { 6394 } else {
@@ -6744,16 +6747,17 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, @@ -6744,16 +6747,17 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6744 { 6747 {
6745 TCGv_i64 fp0 = tcg_temp_new_i64(); 6748 TCGv_i64 fp0 = tcg_temp_new_i64();
6746 TCGv_i64 fp1 = tcg_temp_new_i64(); 6749 TCGv_i64 fp1 = tcg_temp_new_i64();
  6750 + if (ctx->opcode & (1 << 6)) {
  6751 + check_cop1x(ctx);
  6752 + }
  6753 + check_cp1_registers(ctx, fs | ft);
6747 6754
6748 gen_load_fpr64(ctx, fp0, fs); 6755 gen_load_fpr64(ctx, fp0, fs);
6749 gen_load_fpr64(ctx, fp1, ft); 6756 gen_load_fpr64(ctx, fp1, ft);
6750 if (ctx->opcode & (1 << 6)) { 6757 if (ctx->opcode & (1 << 6)) {
6751 - check_cop1x(ctx);  
6752 - check_cp1_registers(ctx, fs | ft);  
6753 gen_cmpabs_d(func-48, fp0, fp1, cc); 6758 gen_cmpabs_d(func-48, fp0, fp1, cc);
6754 opn = condnames_abs[func-48]; 6759 opn = condnames_abs[func-48];
6755 } else { 6760 } else {
6756 - check_cp1_registers(ctx, fs | ft);  
6757 gen_cmp_d(func-48, fp0, fp1, cc); 6761 gen_cmp_d(func-48, fp0, fp1, cc);
6758 opn = condnames[func-48]; 6762 opn = condnames[func-48];
6759 } 6763 }
@@ -7222,6 +7226,22 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, @@ -7222,6 +7226,22 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7222 int store = 0; 7226 int store = 0;
7223 TCGv t0 = tcg_temp_new(); 7227 TCGv t0 = tcg_temp_new();
7224 7228
  7229 + switch (opc) {
  7230 + case OPC_LWXC1:
  7231 + case OPC_SWXC1:
  7232 + check_cop1x(ctx);
  7233 + break;
  7234 + case OPC_LDXC1:
  7235 + case OPC_SDXC1:
  7236 + check_cop1x(ctx);
  7237 + check_cp1_registers(ctx, fd);
  7238 + break;
  7239 + case OPC_LUXC1:
  7240 + case OPC_SUXC1:
  7241 + check_cp1_64bitmode(ctx);
  7242 + break;
  7243 + }
  7244 +
7225 if (base == 0) { 7245 if (base == 0) {
7226 gen_load_gpr(t0, index); 7246 gen_load_gpr(t0, index);
7227 } else if (index == 0) { 7247 } else if (index == 0) {
@@ -7235,7 +7255,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, @@ -7235,7 +7255,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7235 save_cpu_state(ctx, 0); 7255 save_cpu_state(ctx, 0);
7236 switch (opc) { 7256 switch (opc) {
7237 case OPC_LWXC1: 7257 case OPC_LWXC1:
7238 - check_cop1x(ctx);  
7239 { 7258 {
7240 TCGv_i32 fp0 = tcg_temp_new_i32(); 7259 TCGv_i32 fp0 = tcg_temp_new_i32();
7241 7260
@@ -7247,8 +7266,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, @@ -7247,8 +7266,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7247 opn = "lwxc1"; 7266 opn = "lwxc1";
7248 break; 7267 break;
7249 case OPC_LDXC1: 7268 case OPC_LDXC1:
7250 - check_cop1x(ctx);  
7251 - check_cp1_registers(ctx, fd);  
7252 { 7269 {
7253 TCGv_i64 fp0 = tcg_temp_new_i64(); 7270 TCGv_i64 fp0 = tcg_temp_new_i64();
7254 7271
@@ -7259,7 +7276,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, @@ -7259,7 +7276,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7259 opn = "ldxc1"; 7276 opn = "ldxc1";
7260 break; 7277 break;
7261 case OPC_LUXC1: 7278 case OPC_LUXC1:
7262 - check_cp1_64bitmode(ctx);  
7263 tcg_gen_andi_tl(t0, t0, ~0x7); 7279 tcg_gen_andi_tl(t0, t0, ~0x7);
7264 { 7280 {
7265 TCGv_i64 fp0 = tcg_temp_new_i64(); 7281 TCGv_i64 fp0 = tcg_temp_new_i64();
@@ -7271,7 +7287,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, @@ -7271,7 +7287,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7271 opn = "luxc1"; 7287 opn = "luxc1";
7272 break; 7288 break;
7273 case OPC_SWXC1: 7289 case OPC_SWXC1:
7274 - check_cop1x(ctx);  
7275 { 7290 {
7276 TCGv_i32 fp0 = tcg_temp_new_i32(); 7291 TCGv_i32 fp0 = tcg_temp_new_i32();
7277 TCGv t1 = tcg_temp_new(); 7292 TCGv t1 = tcg_temp_new();
@@ -7286,8 +7301,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, @@ -7286,8 +7301,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7286 store = 1; 7301 store = 1;
7287 break; 7302 break;
7288 case OPC_SDXC1: 7303 case OPC_SDXC1:
7289 - check_cop1x(ctx);  
7290 - check_cp1_registers(ctx, fs);  
7291 { 7304 {
7292 TCGv_i64 fp0 = tcg_temp_new_i64(); 7305 TCGv_i64 fp0 = tcg_temp_new_i64();
7293 7306
@@ -7299,7 +7312,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, @@ -7299,7 +7312,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7299 store = 1; 7312 store = 1;
7300 break; 7313 break;
7301 case OPC_SUXC1: 7314 case OPC_SUXC1:
7302 - check_cp1_64bitmode(ctx);  
7303 tcg_gen_andi_tl(t0, t0, ~0x7); 7315 tcg_gen_andi_tl(t0, t0, ~0x7);
7304 { 7316 {
7305 TCGv_i64 fp0 = tcg_temp_new_i64(); 7317 TCGv_i64 fp0 = tcg_temp_new_i64();