/**Status:2008/11/02*-MinimumimplementationforLinuxconsole:mmioregsandCRTlayer.*-Alwaysupdatesfullscreen.**TODO:*-Panelsupport*-Hardwarecursorsupport*-Touchpanelsupport*-USBsupport*-UARTsupport*-Performancetuning*///#defineDEBUG_SM501//#defineDEBUG_BITBLT#ifdefDEBUG_SM501#defineSM501_DPRINTF(fmt...)printf(fmt)#else#defineSM501_DPRINTF(fmt...)do{}while(0)#endif#defineMMIO_BASE_OFFSET0x3e00000/* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" *//* System Configuration area *//* System config base */#defineSM501_SYS_CONFIG(0x000000)/* config 1 */#defineSM501_SYSTEM_CONTROL(0x000000)#defineSM501_SYSCTRL_PANEL_TRISTATE(1<<0)#defineSM501_SYSCTRL_MEM_TRISTATE(1<<1)#defineSM501_SYSCTRL_CRT_TRISTATE(1<<2)#defineSM501_SYSCTRL_PCI_SLAVE_BURST_MASK(3<<4)#defineSM501_SYSCTRL_PCI_SLAVE_BURST_1(0<<4)#defineSM501_SYSCTRL_PCI_SLAVE_BURST_2(1<<4)#defineSM501_SYSCTRL_PCI_SLAVE_BURST_4(2<<4)#defineSM501_SYSCTRL_PCI_SLAVE_BURST_8(3<<4)#defineSM501_SYSCTRL_PCI_CLOCK_RUN_EN(1<<6)#defineSM501_SYSCTRL_PCI_RETRY_DISABLE(1<<7)#defineSM501_SYSCTRL_PCI_SUBSYS_LOCK(1<<11)#defineSM501_SYSCTRL_PCI_BURST_READ_EN(1<<15)/* miscellaneous control */#defineSM501_MISC_CONTROL(0x000004)#defineSM501_MISC_BUS_SH(0x0)#defineSM501_MISC_BUS_PCI(0x1)#defineSM501_MISC_BUS_XSCALE(0x2)#defineSM501_MISC_BUS_NEC(0x6)#defineSM501_MISC_BUS_MASK(0x7)#defineSM501_MISC_VR_62MB(1<<3)#defineSM501_MISC_CDR_RESET(1<<7)#defineSM501_MISC_USB_LB(1<<8)#defineSM501_MISC_USB_SLAVE(1<<9)#defineSM501_MISC_BL_1(1<<10)#defineSM501_MISC_MC(1<<11)#defineSM501_MISC_DAC_POWER(1<<12)#defineSM501_MISC_IRQ_INVERT(1<<16)#defineSM501_MISC_SH(1<<17)#defineSM501_MISC_HOLD_EMPTY(0<<18)#defineSM501_MISC_HOLD_8(1<<18)#defineSM501_MISC_HOLD_16(2<<18)#defineSM501_MISC_HOLD_24(3<<18)#defineSM501_MISC_HOLD_32(4<<18)#defineSM501_MISC_HOLD_MASK(7<<18)#defineSM501_MISC_FREQ_12(1<<24)#defineSM501_MISC_PNL_24BIT(1<<25)#defineSM501_MISC_8051_LE(1<<26)#defineSM501_GPIO31_0_CONTROL(0x000008)#defineSM501_GPIO63_32_CONTROL(0x00000C)#defineSM501_DRAM_CONTROL(0x000010)/* command list */#defineSM501_ARBTRTN_CONTROL(0x000014)/* command list */#defineSM501_COMMAND_LIST_STATUS(0x000024)/* interrupt debug */#defineSM501_RAW_IRQ_STATUS(0x000028)#defineSM501_RAW_IRQ_CLEAR(0x000028)#defineSM501_IRQ_STATUS(0x00002C)#defineSM501_IRQ_MASK(0x000030)#defineSM501_DEBUG_CONTROL(0x000034)/* power management */#defineSM501_POWERMODE_P2X_SRC(1<<29)#defineSM501_POWERMODE_V2X_SRC(1<<20)#defineSM501_POWERMODE_M_SRC(1<<12)#defineSM501_POWERMODE_M1_SRC(1<<4)#defineSM501_CURRENT_GATE(0x000038)#defineSM501_CURRENT_CLOCK(0x00003C)#defineSM501_POWER_MODE_0_GATE(0x000040)#defineSM501_POWER_MODE_0_CLOCK(0x000044)#defineSM501_POWER_MODE_1_GATE(0x000048)#defineSM501_POWER_MODE_1_CLOCK(0x00004C)#defineSM501_SLEEP_MODE_GATE(0x000050)#defineSM501_POWER_MODE_CONTROL(0x000054)/* power gates for units within the 501 */#defineSM501_GATE_HOST(0)#defineSM501_GATE_MEMORY(1)#defineSM501_GATE_DISPLAY(2)#defineSM501_GATE_2D_ENGINE(3)#defineSM501_GATE_CSC(4)#defineSM501_GATE_ZVPORT(5)#defineSM501_GATE_GPIO(6)#defineSM501_GATE_UART0(7)#defineSM501_GATE_UART1(8)#defineSM501_GATE_SSP(10)#defineSM501_GATE_USB_HOST(11)#defineSM501_GATE_USB_GADGET(12)#defineSM501_GATE_UCONTROLLER(17)#defineSM501_GATE_AC97(18)/* panel clock */#defineSM501_CLOCK_P2XCLK(24)/* crt clock */#defineSM501_CLOCK_V2XCLK(16)/* main clock */#defineSM501_CLOCK_MCLK(8)/* SDRAM controller clock */#defineSM501_CLOCK_M1XCLK(0)/* config 2 */#defineSM501_PCI_MASTER_BASE(0x000058)#defineSM501_ENDIAN_CONTROL(0x00005C)#defineSM501_DEVICEID(0x000060)/* 0x050100A0 */#defineSM501_DEVICEID_SM501(0x05010000)#defineSM501_DEVICEID_IDMASK(0xffff0000)#defineSM501_DEVICEID_REVMASK(0x000000ff)#defineSM501_PLLCLOCK_COUNT(0x000064)#defineSM501_MISC_TIMING(0x000068)#defineSM501_CURRENT_SDRAM_CLOCK(0x00006C)#defineSM501_PROGRAMMABLE_PLL_CONTROL(0x000074)/* GPIO base */#defineSM501_GPIO(0x010000)#defineSM501_GPIO_DATA_LOW(0x00)#defineSM501_GPIO_DATA_HIGH(0x04)#defineSM501_GPIO_DDR_LOW(0x08)#defineSM501_GPIO_DDR_HIGH(0x0C)#defineSM501_GPIO_IRQ_SETUP(0x10)#defineSM501_GPIO_IRQ_STATUS(0x14)#defineSM501_GPIO_IRQ_RESET(0x14)/* I2C controller base */#defineSM501_I2C(0x010040)#defineSM501_I2C_BYTE_COUNT(0x00)#defineSM501_I2C_CONTROL(0x01)#defineSM501_I2C_STATUS(0x02)#defineSM501_I2C_RESET(0x02)#defineSM501_I2C_SLAVE_ADDRESS(0x03)#defineSM501_I2C_DATA(0x04)/* SSP base */#defineSM501_SSP(0x020000)/* Uart 0 base */#defineSM501_UART0(0x030000)/* Uart 1 base */#defineSM501_UART1(0x030020)/* USB host port base */#defineSM501_USB_HOST(0x040000)/* USB slave/gadget base */#defineSM501_USB_GADGET(0x060000)/* USB slave/gadget data port base */#defineSM501_USB_GADGET_DATA(0x070000)/* Display controller/video engine base */#defineSM501_DC(0x080000)/* common defines for the SM501 address registers */#defineSM501_ADDR_FLIP(1<<31)#defineSM501_ADDR_EXT(1<<27)#defineSM501_ADDR_CS1(1<<26)#defineSM501_ADDR_MASK(0x3f<<26)#defineSM501_FIFO_MASK(0x3<<16)#defineSM501_FIFO_1(0x0<<16)#defineSM501_FIFO_3(0x1<<16)#defineSM501_FIFO_7(0x2<<16)#defineSM501_FIFO_11(0x3<<16)/* common registers for panel and the crt */#defineSM501_OFF_DC_H_TOT(0x000)#defineSM501_OFF_DC_V_TOT(0x008)#defineSM501_OFF_DC_H_SYNC(0x004)#defineSM501_OFF_DC_V_SYNC(0x00C)#defineSM501_DC_PANEL_CONTROL(0x000)#defineSM501_DC_PANEL_CONTROL_FPEN(1<<27)#defineSM501_DC_PANEL_CONTROL_BIAS(1<<26)#defineSM501_DC_PANEL_CONTROL_DATA(1<<25)#defineSM501_DC_PANEL_CONTROL_VDD(1<<24)#defineSM501_DC_PANEL_CONTROL_DP(1<<23)#defineSM501_DC_PANEL_CONTROL_TFT_888(0<<21)#defineSM501_DC_PANEL_CONTROL_TFT_333(1<<21)#defineSM501_DC_PANEL_CONTROL_TFT_444(2<<21)#defineSM501_DC_PANEL_CONTROL_DE(1<<20)#defineSM501_DC_PANEL_CONTROL_LCD_TFT(0<<18)#defineSM501_DC_PANEL_CONTROL_LCD_STN8(1<<18)#defineSM501_DC_PANEL_CONTROL_LCD_STN12(2<<18)#defineSM501_DC_PANEL_CONTROL_CP(1<<14)#defineSM501_DC_PANEL_CONTROL_VSP(1<<13)#defineSM501_DC_PANEL_CONTROL_HSP(1<<12)#defineSM501_DC_PANEL_CONTROL_CK(1<<9)#defineSM501_DC_PANEL_CONTROL_TE(1<<8)#defineSM501_DC_PANEL_CONTROL_VPD(1<<7)#defineSM501_DC_PANEL_CONTROL_VP(1<<6)#defineSM501_DC_PANEL_CONTROL_HPD(1<<5)#defineSM501_DC_PANEL_CONTROL_HP(1<<4)#defineSM501_DC_PANEL_CONTROL_GAMMA(1<<3)#defineSM501_DC_PANEL_CONTROL_EN(1<<2)#defineSM501_DC_PANEL_CONTROL_8BPP(0<<0)#defineSM501_DC_PANEL_CONTROL_16BPP(1<<0)#defineSM501_DC_PANEL_CONTROL_32BPP(2<<0)#defineSM501_DC_PANEL_PANNING_CONTROL(0x004)#defineSM501_DC_PANEL_COLOR_KEY(0x008)#defineSM501_DC_PANEL_FB_ADDR(0x00C)#defineSM501_DC_PANEL_FB_OFFSET(0x010)#defineSM501_DC_PANEL_FB_WIDTH(0x014)#defineSM501_DC_PANEL_FB_HEIGHT(0x018)#defineSM501_DC_PANEL_TL_LOC(0x01C)#defineSM501_DC_PANEL_BR_LOC(0x020)#defineSM501_DC_PANEL_H_TOT(0x024)#defineSM501_DC_PANEL_H_SYNC(0x028)#defineSM501_DC_PANEL_V_TOT(0x02C)#defineSM501_DC_PANEL_V_SYNC(0x030)#defineSM501_DC_PANEL_CUR_LINE(0x034)#defineSM501_DC_VIDEO_CONTROL(0x040)#defineSM501_DC_VIDEO_FB0_ADDR(0x044)#defineSM501_DC_VIDEO_FB_WIDTH(0x048)#defineSM501_DC_VIDEO_FB0_LAST_ADDR(0x04C)#defineSM501_DC_VIDEO_TL_LOC(0x050)#defineSM501_DC_VIDEO_BR_LOC(0x054)#defineSM501_DC_VIDEO_SCALE(0x058)#defineSM501_DC_VIDEO_INIT_SCALE(0x05C)#defineSM501_DC_VIDEO_YUV_CONSTANTS(0x060)#defineSM501_DC_VIDEO_FB1_ADDR(0x064)#defineSM501_DC_VIDEO_FB1_LAST_ADDR(0x068)#defineSM501_DC_VIDEO_ALPHA_CONTROL(0x080)#defineSM501_DC_VIDEO_ALPHA_FB_ADDR(0x084)#defineSM501_DC_VIDEO_ALPHA_FB_OFFSET(0x088)#defineSM501_DC_VIDEO_ALPHA_FB_LAST_ADDR(0x08C)#defineSM501_DC_VIDEO_ALPHA_TL_LOC(0x090)#defineSM501_DC_VIDEO_ALPHA_BR_LOC(0x094)#defineSM501_DC_VIDEO_ALPHA_SCALE(0x098)#defineSM501_DC_VIDEO_ALPHA_INIT_SCALE(0x09C)#defineSM501_DC_VIDEO_ALPHA_CHROMA_KEY(0x0A0)#defineSM501_DC_VIDEO_ALPHA_COLOR_LOOKUP(0x0A4)#defineSM501_DC_PANEL_HWC_BASE(0x0F0)#defineSM501_DC_PANEL_HWC_ADDR(0x0F0)#defineSM501_DC_PANEL_HWC_LOC(0x0F4)#defineSM501_DC_PANEL_HWC_COLOR_1_2(0x0F8)#defineSM501_DC_PANEL_HWC_COLOR_3(0x0FC)#defineSM501_HWC_EN(1<<31)#defineSM501_OFF_HWC_ADDR(0x00)#defineSM501_OFF_HWC_LOC(0x04)#defineSM501_OFF_HWC_COLOR_1_2(0x08)#defineSM501_OFF_HWC_COLOR_3(0x0C)#defineSM501_DC_ALPHA_CONTROL(0x100)#defineSM501_DC_ALPHA_FB_ADDR(0x104)#defineSM501_DC_ALPHA_FB_OFFSET(0x108)#defineSM501_DC_ALPHA_TL_LOC(0x10C)#defineSM501_DC_ALPHA_BR_LOC(0x110)#defineSM501_DC_ALPHA_CHROMA_KEY(0x114)#defineSM501_DC_ALPHA_COLOR_LOOKUP(0x118)#defineSM501_DC_CRT_CONTROL(0x200)#defineSM501_DC_CRT_CONTROL_TVP(1<<15)#defineSM501_DC_CRT_CONTROL_CP(1<<14)#defineSM501_DC_CRT_CONTROL_VSP(1<<13)#defineSM501_DC_CRT_CONTROL_HSP(1<<12)#defineSM501_DC_CRT_CONTROL_VS(1<<11)#defineSM501_DC_CRT_CONTROL_BLANK(1<<10)#defineSM501_DC_CRT_CONTROL_SEL(1<<9)#defineSM501_DC_CRT_CONTROL_TE(1<<8)#defineSM501_DC_CRT_CONTROL_PIXEL_MASK(0xF<<4)#defineSM501_DC_CRT_CONTROL_GAMMA(1<<3)#defineSM501_DC_CRT_CONTROL_ENABLE(1<<2)#defineSM501_DC_CRT_CONTROL_8BPP(0<<0)#defineSM501_DC_CRT_CONTROL_16BPP(1<<0)#defineSM501_DC_CRT_CONTROL_32BPP(2<<0)#defineSM501_DC_CRT_FB_ADDR(0x204)#defineSM501_DC_CRT_FB_OFFSET(0x208)#defineSM501_DC_CRT_H_TOT(0x20C)#defineSM501_DC_CRT_H_SYNC(0x210)#defineSM501_DC_CRT_V_TOT(0x214)#defineSM501_DC_CRT_V_SYNC(0x218)#defineSM501_DC_CRT_SIGNATURE_ANALYZER(0x21C)#defineSM501_DC_CRT_CUR_LINE(0x220)#defineSM501_DC_CRT_MONITOR_DETECT(0x224)#defineSM501_DC_CRT_HWC_BASE(0x230)#defineSM501_DC_CRT_HWC_ADDR(0x230)#defineSM501_DC_CRT_HWC_LOC(0x234)#defineSM501_DC_CRT_HWC_COLOR_1_2(0x238)#defineSM501_DC_CRT_HWC_COLOR_3(0x23C)#defineSM501_DC_PANEL_PALETTE(0x400)#defineSM501_DC_VIDEO_PALETTE(0x800)#defineSM501_DC_CRT_PALETTE(0xC00)/* Zoom Video port base */#defineSM501_ZVPORT(0x090000)/* AC97/I2S base */#defineSM501_AC97(0x0A0000)/* 8051 micro controller base */#defineSM501_UCONTROLLER(0x0B0000)/* 8051 micro controller SRAM base */#defineSM501_UCONTROLLER_SRAM(0x0C0000)/* DMA base */#defineSM501_DMA(0x0D0000)/* 2d engine base */#defineSM501_2D_ENGINE(0x100000)#defineSM501_2D_SOURCE(0x00)#defineSM501_2D_DESTINATION(0x04)#defineSM501_2D_DIMENSION(0x08)#defineSM501_2D_CONTROL(0x0C)#defineSM501_2D_PITCH(0x10)#defineSM501_2D_FOREGROUND(0x14)#defineSM501_2D_BACKGROUND(0x18)#defineSM501_2D_STRETCH(0x1C)#defineSM501_2D_COLOR_COMPARE(0x20)#defineSM501_2D_COLOR_COMPARE_MASK(0x24)#defineSM501_2D_MASK(0x28)#defineSM501_2D_CLIP_TL(0x2C)#defineSM501_2D_CLIP_BR(0x30)#defineSM501_2D_MONO_PATTERN_LOW(0x34)#defineSM501_2D_MONO_PATTERN_HIGH(0x38)#defineSM501_2D_WINDOW_WIDTH(0x3C)#defineSM501_2D_SOURCE_BASE(0x40)#defineSM501_2D_DESTINATION_BASE(0x44)#defineSM501_2D_ALPHA(0x48)#defineSM501_2D_WRAP(0x4C)#defineSM501_2D_STATUS(0x50)#defineSM501_CSC_Y_SOURCE_BASE(0xC8)#defineSM501_CSC_CONSTANTS(0xCC)#defineSM501_CSC_Y_SOURCE_X(0xD0)#defineSM501_CSC_Y_SOURCE_Y(0xD4)#defineSM501_CSC_U_SOURCE_BASE(0xD8)#defineSM501_CSC_V_SOURCE_BASE(0xDC)#defineSM501_CSC_SOURCE_DIMENSION(0xE0)#defineSM501_CSC_SOURCE_PITCH(0xE4)#defineSM501_CSC_DESTINATION(0xE8)#defineSM501_CSC_DESTINATION_DIMENSION(0xEC)#defineSM501_CSC_DESTINATION_PITCH(0xF0)#defineSM501_CSC_SCALE_FACTOR(0xF4)#defineSM501_CSC_DESTINATION_BASE(0xF8)#defineSM501_CSC_CONTROL(0xFC)/* 2d engine data port base */#defineSM501_2D_ENGINE_DATA(0x110000)/* end of register definitions *//* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */staticconstuint32_tsm501_mem_local_size[]={[0]=4*1024*1024,[1]=8*1024*1024,[2]=16*1024*1024,[3]=32*1024*1024,[4]=64*1024*1024,[5]=2*1024*1024,};#defineget_local_mem_size(s)sm501_mem_local_size[(s)->local_mem_size_index]typedefstructSM501State{/* graphic console status */DisplayState*ds;/* status & internal resources */target_phys_addr_tbase;uint32_tlocal_mem_size_index;uint8_t*local_mem;uint32_tlast_width;uint32_tlast_height;/* mmio registers */uint32_tsystem_control;uint32_tmisc_control;uint32_tgpio_31_0_control;uint32_tgpio_63_32_control;uint32_tdram_control;uint32_tirq_mask;uint32_tmisc_timing;uint32_tpower_mode_control;uint32_tuart0_ier;uint32_tuart0_lcr;uint32_tuart0_mcr;uint32_tuart0_scr;uint8_tdc_palette[0x400*3];uint32_tdc_panel_control;uint32_tdc_panel_panning_control;uint32_tdc_panel_fb_addr;uint32_tdc_panel_fb_offset;uint32_tdc_panel_fb_width;uint32_tdc_panel_fb_height;uint32_tdc_panel_tl_location;uint32_tdc_panel_br_location;uint32_tdc_panel_h_total;uint32_tdc_panel_h_sync;uint32_tdc_panel_v_total;uint32_tdc_panel_v_sync;uint32_tdc_panel_hwc_addr;uint32_tdc_panel_hwc_location;uint32_tdc_panel_hwc_color_1_2;uint32_tdc_panel_hwc_color_3;uint32_tdc_crt_control;uint32_tdc_crt_fb_addr;uint32_tdc_crt_fb_offset;uint32_tdc_crt_h_total;uint32_tdc_crt_h_sync;uint32_tdc_crt_v_total;uint32_tdc_crt_v_sync;uint32_tdc_crt_hwc_addr;uint32_tdc_crt_hwc_location;uint32_tdc_crt_hwc_color_1_2;uint32_tdc_crt_hwc_color_3;}SM501State;staticuint32_tget_local_mem_size_index(uint32_tsize){uint32_tnorm_size=0;inti,index=0;
caseSM501_SYSTEM_CONTROL:ret=s->system_control;break;caseSM501_MISC_CONTROL:ret=s->misc_control;break;caseSM501_GPIO31_0_CONTROL:ret=s->gpio_31_0_control;break;caseSM501_GPIO63_32_CONTROL:ret=s->gpio_63_32_control;break;caseSM501_DEVICEID:ret=0x050100A0;break;caseSM501_DRAM_CONTROL:ret=(s->dram_control&0x07F107C0)|s->local_mem_size_index<<13;break;caseSM501_IRQ_MASK:ret=s->irq_mask;break;caseSM501_MISC_TIMING:/* TODO : simulate gate control */ret=s->misc_timing;break;caseSM501_CURRENT_GATE:/* TODO : simulate gate control */ret=0x00021807;break;caseSM501_CURRENT_CLOCK:ret=0x2A1A0A09;break;caseSM501_POWER_MODE_CONTROL:ret=s->power_mode_control;break;default:printf("sm501 system config : not implemented register read."
caseSM501_SYSTEM_CONTROL:s->system_control=value&0xE300B8F7;break;caseSM501_MISC_CONTROL:s->misc_control=value&0xFF7FFF20;break;caseSM501_GPIO31_0_CONTROL:s->gpio_31_0_control=value;break;caseSM501_GPIO63_32_CONTROL:s->gpio_63_32_control=value;break;caseSM501_DRAM_CONTROL:s->local_mem_size_index=(value>>13)&0x7;/* rODO : check validity of size change */s->dram_control|=value&0x7FFFFFC3;break;caseSM501_IRQ_MASK:s->irq_mask=value;break;caseSM501_MISC_TIMING:s->misc_timing=value&0xF31F1FFF;break;caseSM501_POWER_MODE_0_GATE:caseSM501_POWER_MODE_1_GATE:caseSM501_POWER_MODE_0_CLOCK:caseSM501_POWER_MODE_1_CLOCK:/* TODO : simulate gate & clock control */break;caseSM501_POWER_MODE_CONTROL:s->power_mode_control=value&0x00000003;break;default:printf("sm501 system config : not implemented register write."
assert(0);}}staticCPUReadMemoryFunc*sm501_disp_ctrl_readfn[]={NULL,NULL,&sm501_disp_ctrl_read,};staticCPUWriteMemoryFunc*sm501_disp_ctrl_writefn[]={NULL,NULL,&sm501_disp_ctrl_write,};/* draw line functions for all console modes */#include"pixel_ops.h"typedefvoiddraw_line_func(uint8_t*d,constuint8_t*s,intwidth,constuint32_t*pal);#defineDEPTH8#include"sm501_template.h"#defineDEPTH15#include"sm501_template.h"#defineBGR_FORMAT#defineDEPTH15#include"sm501_template.h"#defineDEPTH16#include"sm501_template.h"#defineBGR_FORMAT#defineDEPTH16#include"sm501_template.h"#defineDEPTH32#include"sm501_template.h"#defineBGR_FORMAT#defineDEPTH32#include"sm501_template.h"staticdraw_line_func*draw_line8_funcs[]={draw_line8_8,draw_line8_15,draw_line8_16,draw_line8_32,draw_line8_32bgr,draw_line8_15bgr,draw_line8_16bgr,};staticdraw_line_func*draw_line16_funcs[]={draw_line16_8,draw_line16_15,draw_line16_16,draw_line16_32,draw_line16_32bgr,draw_line16_15bgr,draw_line16_16bgr,};staticdraw_line_func*draw_line32_funcs[]={draw_line32_8,draw_line32_15,draw_line32_16,draw_line32_32,draw_line32_32bgr,draw_line32_15bgr,draw_line32_16bgr,};staticinlineintget_depth_index(DisplayState*s){
s->last_width=width;s->last_height=height;full_update=1;}/* draw each line according to conditions */for(y=0;y<height;y++){intupdate=full_update;uint8_t*line_end=&src[width*src_bpp-1];intpage0=(src-phys_ram_base)&TARGET_PAGE_MASK;intpage1=(line_end-phys_ram_base)&TARGET_PAGE_MASK;intpage;/* check dirty flags for each line */for(page=page0;page<=page1;page+=TARGET_PAGE_SIZE)if(cpu_physical_memory_get_dirty(page,VGA_DIRTY_FLAG))update=1;/* draw line and change status */if(update){
uint32_tlocal_mem_bytes,CharDriverState*chr){SM501State*s;intsm501_system_config_index;intsm501_disp_ctrl_index;/* allocate management data region */s=(SM501State*)qemu_mallocz(sizeof(SM501State));s->base=base;s->local_mem_size_index=get_local_mem_size_index(local_mem_bytes);SM501_DPRINTF("local mem size=%x. index=%d\n",get_local_mem_size(s),s->local_mem_size_index);s->system_control=0x00100000;s->misc_control=0x00001000;/* assumes SH, active=low */s->dc_panel_control=0x00010000;s->dc_crt_control=0x00010000;/* allocate local memory */s->local_mem=(uint8*)phys_ram_base+local_mem_base;cpu_register_physical_memory(base,local_mem_bytes,local_mem_base);/* map mmio */sm501_system_config_index=cpu_register_io_memory(0,sm501_system_config_readfn,sm501_system_config_writefn,s);cpu_register_physical_memory(base+MMIO_BASE_OFFSET,0x6c,sm501_system_config_index);sm501_disp_ctrl_index=cpu_register_io_memory(0,sm501_disp_ctrl_readfn,sm501_disp_ctrl_writefn,s);cpu_register_physical_memory(base+MMIO_BASE_OFFSET+SM501_DC,
/* bridge to serial emulation module */if(chr)serial_mm_init(base+MMIO_BASE_OFFSET+SM501_UART0,2,0,/* TODO : chain irq to IRL */115200,chr,1);/* create qemu graphic console */