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/*
* QEMU IDE disk and CD-ROM Emulator
*
* Copyright (c) 2003 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "vl.h"
/* debug IDE devices */
//#define DEBUG_IDE
//#define DEBUG_IDE_ATAPI
/* Bits of HD_STATUS */
#define ERR_STAT 0x01
#define INDEX_STAT 0x02
#define ECC_STAT 0x04 /* Corrected error */
#define DRQ_STAT 0x08
#define SEEK_STAT 0x10
#define SRV_STAT 0x10
#define WRERR_STAT 0x20
#define READY_STAT 0x40
#define BUSY_STAT 0x80
/* Bits for HD_ERROR */
#define MARK_ERR 0x01 /* Bad address mark */
#define TRK0_ERR 0x02 /* couldn't find track 0 */
#define ABRT_ERR 0x04 /* Command aborted */
#define MCR_ERR 0x08 /* media change request */
#define ID_ERR 0x10 /* ID field not found */
#define MC_ERR 0x20 /* media changed */
#define ECC_ERR 0x40 /* Uncorrectable ECC error */
#define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
#define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
/* Bits of HD_NSECTOR */
#define CD 0x01
#define IO 0x02
#define REL 0x04
#define TAG_MASK 0xf8
#define IDE_CMD_RESET 0x04
#define IDE_CMD_DISABLE_IRQ 0x02
/* ATA/ATAPI Commands pre T13 Spec */
#define WIN_NOP 0x00
/*
* 0x01->0x02 Reserved
*/
#define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
/*
* 0x04->0x07 Reserved
*/
#define WIN_SRST 0x08 /* ATAPI soft reset command */
#define WIN_DEVICE_RESET 0x08
/*
* 0x09->0x0F Reserved
*/
#define WIN_RECAL 0x10
#define WIN_RESTORE WIN_RECAL
/*
* 0x10->0x1F Reserved
*/
#define WIN_READ 0x20 /* 28-Bit */
#define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
#define WIN_READ_LONG 0x22 /* 28-Bit */
#define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
#define WIN_READ_EXT 0x24 /* 48-Bit */
#define WIN_READDMA_EXT 0x25 /* 48-Bit */
#define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
#define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
/*
* 0x28
*/
#define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
/*
* 0x2A->0x2F Reserved
*/
#define WIN_WRITE 0x30 /* 28-Bit */
#define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
#define WIN_WRITE_LONG 0x32 /* 28-Bit */
#define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
#define WIN_WRITE_EXT 0x34 /* 48-Bit */
#define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
#define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
#define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
#define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
#define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
/*
* 0x3A->0x3B Reserved
*/
#define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
/*
* 0x3D->0x3F Reserved
*/
#define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
#define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
#define WIN_VERIFY_EXT 0x42 /* 48-Bit */
/*
* 0x43->0x4F Reserved
*/
#define WIN_FORMAT 0x50
/*
* 0x51->0x5F Reserved
*/
#define WIN_INIT 0x60
/*
* 0x61->0x5F Reserved
*/
#define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
#define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
#define WIN_DIAGNOSE 0x90
#define WIN_SPECIFY 0x91 /* set drive geometry translation */
#define WIN_DOWNLOAD_MICROCODE 0x92
#define WIN_STANDBYNOW2 0x94
#define WIN_STANDBY2 0x96
#define WIN_SETIDLE2 0x97
#define WIN_CHECKPOWERMODE2 0x98
#define WIN_SLEEPNOW2 0x99
/*
* 0x9A VENDOR
*/
#define WIN_PACKETCMD 0xA0 /* Send a packet command. */
#define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
#define WIN_QUEUED_SERVICE 0xA2
#define WIN_SMART 0xB0 /* self-monitoring and reporting */
#define CFA_ERASE_SECTORS 0xC0
#define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
#define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
#define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
#define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
#define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
#define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
#define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
#define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
#define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
#define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
#define WIN_GETMEDIASTATUS 0xDA
#define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
#define WIN_POSTBOOT 0xDC
#define WIN_PREBOOT 0xDD
#define WIN_DOORLOCK 0xDE /* lock door on removable drives */
#define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
#define WIN_STANDBYNOW1 0xE0
#define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
#define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
#define WIN_SETIDLE1 0xE3
#define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
#define WIN_CHECKPOWERMODE1 0xE5
#define WIN_SLEEPNOW1 0xE6
#define WIN_FLUSH_CACHE 0xE7
#define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
#define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
/* SET_FEATURES 0x22 or 0xDD */
#define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
#define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
#define WIN_MEDIAEJECT 0xED
#define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
#define WIN_SETFEATURES 0xEF /* set special drive features */
#define EXABYTE_ENABLE_NEST 0xF0
#define WIN_SECURITY_SET_PASS 0xF1
#define WIN_SECURITY_UNLOCK 0xF2
#define WIN_SECURITY_ERASE_PREPARE 0xF3
#define WIN_SECURITY_ERASE_UNIT 0xF4
#define WIN_SECURITY_FREEZE_LOCK 0xF5
#define WIN_SECURITY_DISABLE 0xF6
#define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
#define WIN_SET_MAX 0xF9
#define DISABLE_SEAGATE 0xFB
/* set to 1 set disable mult support */
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#define MAX_MULT_SECTORS 16
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/* ATAPI defines */
#define ATAPI_PACKET_SIZE 12
/* The generic packet command opcodes for CD/DVD Logical Units,
* From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
#define GPCMD_BLANK 0xa1
#define GPCMD_CLOSE_TRACK 0x5b
#define GPCMD_FLUSH_CACHE 0x35
#define GPCMD_FORMAT_UNIT 0x04
#define GPCMD_GET_CONFIGURATION 0x46
#define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
#define GPCMD_GET_PERFORMANCE 0xac
#define GPCMD_INQUIRY 0x12
#define GPCMD_LOAD_UNLOAD 0xa6
#define GPCMD_MECHANISM_STATUS 0xbd
#define GPCMD_MODE_SELECT_10 0x55
#define GPCMD_MODE_SENSE_10 0x5a
#define GPCMD_PAUSE_RESUME 0x4b
#define GPCMD_PLAY_AUDIO_10 0x45
#define GPCMD_PLAY_AUDIO_MSF 0x47
#define GPCMD_PLAY_AUDIO_TI 0x48
#define GPCMD_PLAY_CD 0xbc
#define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e
#define GPCMD_READ_10 0x28
#define GPCMD_READ_12 0xa8
#define GPCMD_READ_CDVD_CAPACITY 0x25
#define GPCMD_READ_CD 0xbe
#define GPCMD_READ_CD_MSF 0xb9
#define GPCMD_READ_DISC_INFO 0x51
#define GPCMD_READ_DVD_STRUCTURE 0xad
#define GPCMD_READ_FORMAT_CAPACITIES 0x23
#define GPCMD_READ_HEADER 0x44
#define GPCMD_READ_TRACK_RZONE_INFO 0x52
#define GPCMD_READ_SUBCHANNEL 0x42
#define GPCMD_READ_TOC_PMA_ATIP 0x43
#define GPCMD_REPAIR_RZONE_TRACK 0x58
#define GPCMD_REPORT_KEY 0xa4
#define GPCMD_REQUEST_SENSE 0x03
#define GPCMD_RESERVE_RZONE_TRACK 0x53
#define GPCMD_SCAN 0xba
#define GPCMD_SEEK 0x2b
#define GPCMD_SEND_DVD_STRUCTURE 0xad
#define GPCMD_SEND_EVENT 0xa2
#define GPCMD_SEND_KEY 0xa3
#define GPCMD_SEND_OPC 0x54
#define GPCMD_SET_READ_AHEAD 0xa7
#define GPCMD_SET_STREAMING 0xb6
#define GPCMD_START_STOP_UNIT 0x1b
#define GPCMD_STOP_PLAY_SCAN 0x4e
#define GPCMD_TEST_UNIT_READY 0x00
#define GPCMD_VERIFY_10 0x2f
#define GPCMD_WRITE_10 0x2a
#define GPCMD_WRITE_AND_VERIFY_10 0x2e
/* This is listed as optional in ATAPI 2.6, but is (curiously)
* missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
* Table 377 as an MMC command for SCSi devices though... Most ATAPI
* drives support it. */
#define GPCMD_SET_SPEED 0xbb
/* This seems to be a SCSI specific CD-ROM opcode
* to play data at track/index */
#define GPCMD_PLAYAUDIO_TI 0x48
/*
* From MS Media Status Notification Support Specification. For
* older drives only.
*/
#define GPCMD_GET_MEDIA_STATUS 0xda
/* Mode page codes for mode sense/set */
#define GPMODE_R_W_ERROR_PAGE 0x01
#define GPMODE_WRITE_PARMS_PAGE 0x05
#define GPMODE_AUDIO_CTL_PAGE 0x0e
#define GPMODE_POWER_PAGE 0x1a
#define GPMODE_FAULT_FAIL_PAGE 0x1c
#define GPMODE_TO_PROTECT_PAGE 0x1d
#define GPMODE_CAPABILITIES_PAGE 0x2a
#define GPMODE_ALL_PAGES 0x3f
/* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
* of MODE_SENSE_POWER_PAGE */
#define GPMODE_CDROM_PAGE 0x0d
#define ATAPI_INT_REASON_CD 0x01 /* 0 = data transfer */
#define ATAPI_INT_REASON_IO 0x02 /* 1 = transfer to the host */
#define ATAPI_INT_REASON_REL 0x04
#define ATAPI_INT_REASON_TAG 0xf8
/* same constants as bochs */
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#define ASC_ILLEGAL_OPCODE 0x20
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#define ASC_LOGICAL_BLOCK_OOR 0x21
#define ASC_INV_FIELD_IN_CMD_PACKET 0x24
#define ASC_MEDIUM_NOT_PRESENT 0x3a
#define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39
#define SENSE_NONE 0
#define SENSE_NOT_READY 2
#define SENSE_ILLEGAL_REQUEST 5
#define SENSE_UNIT_ATTENTION 6
struct IDEState;
typedef void EndTransferFunc(struct IDEState *);
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/* NOTE: IDEState represents in fact one drive */
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typedef struct IDEState {
/* ide config */
int is_cdrom;
int cylinders, heads, sectors;
int64_t nb_sectors;
int mult_sectors;
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SetIRQFunc *set_irq;
void *irq_opaque;
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int irq;
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PCIDevice *pci_dev;
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struct BMDMAState *bmdma;
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int drive_serial;
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/* ide regs */
uint8_t feature;
uint8_t error;
uint16_t nsector; /* 0 is 256 to ease computations */
uint8_t sector;
uint8_t lcyl;
uint8_t hcyl;
uint8_t select;
uint8_t status;
/* 0x3f6 command, only meaningful for drive 0 */
uint8_t cmd;
/* depends on bit 4 in select, only meaningful for drive 0 */
struct IDEState *cur_drive;
BlockDriverState *bs;
/* ATAPI specific */
uint8_t sense_key;
uint8_t asc;
int packet_transfer_size;
int elementary_transfer_size;
int io_buffer_index;
int lba;
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int cd_sector_size;
int atapi_dma; /* true if dma is requested for the packet cmd */
/* ATA DMA state */
int io_buffer_size;
/* PIO transfer handling */
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int req_nb_sectors; /* number of sectors per interrupt */
EndTransferFunc *end_transfer_func;
uint8_t *data_ptr;
uint8_t *data_end;
uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
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QEMUTimer *sector_write_timer; /* only used for win2k instal hack */
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} IDEState;
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#define BM_STATUS_DMAING 0x01
#define BM_STATUS_ERROR 0x02
#define BM_STATUS_INT 0x04
#define BM_CMD_START 0x01
#define BM_CMD_READ 0x08
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#define IDE_TYPE_PIIX3 0
#define IDE_TYPE_CMD646 1
/* CMD646 specific */
#define MRDMODE 0x71
#define MRDMODE_INTR_CH0 0x04
#define MRDMODE_INTR_CH1 0x08
#define MRDMODE_BLK_CH0 0x10
#define MRDMODE_BLK_CH1 0x20
#define UDIDETCR0 0x73
#define UDIDETCR1 0x7B
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typedef int IDEDMAFunc(IDEState *s,
target_phys_addr_t phys_addr,
int transfer_size1);
typedef struct BMDMAState {
uint8_t cmd;
uint8_t status;
uint32_t addr;
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struct PCIIDEState *pci_dev;
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/* current transfer state */
IDEState *ide_if;
IDEDMAFunc *dma_cb;
} BMDMAState;
typedef struct PCIIDEState {
PCIDevice dev;
IDEState ide_if[4];
BMDMAState bmdma[2];
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int type; /* see IDE_TYPE_xxx */
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} PCIIDEState;
static void ide_dma_start(IDEState *s, IDEDMAFunc *dma_cb);
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static void padstr(char *str, const char *src, int len)
{
int i, v;
for(i = 0; i < len; i++) {
if (*src)
v = *src++;
else
v = ' ';
*(char *)((long)str ^ 1) = v;
str++;
}
}
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static void padstr8(uint8_t *buf, int buf_size, const char *src)
{
int i;
for(i = 0; i < buf_size; i++) {
if (*src)
buf[i] = *src++;
else
buf[i] = ' ';
}
}
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static void put_le16(uint16_t *p, unsigned int v)
{
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*p = cpu_to_le16(v);
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}
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static void ide_identify(IDEState *s)
{
uint16_t *p;
unsigned int oldsize;
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char buf[20];
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memset(s->io_buffer, 0, 512);
p = (uint16_t *)s->io_buffer;
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put_le16(p + 0, 0x0040);
put_le16(p + 1, s->cylinders);
put_le16(p + 3, s->heads);
put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
put_le16(p + 5, 512); /* XXX: retired, remove ? */
put_le16(p + 6, s->sectors);
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snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
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put_le16(p + 20, 3); /* XXX: retired, remove ? */
put_le16(p + 21, 512); /* cache size in sectors */
put_le16(p + 22, 4); /* ecc bytes */
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padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); /* model */
#if MAX_MULT_SECTORS > 1
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put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
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#endif
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put_le16(p + 48, 1); /* dword I/O */
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put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
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put_le16(p + 51, 0x200); /* PIO transfer cycle */
put_le16(p + 52, 0x200); /* DMA transfer cycle */
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put_le16(p + 53, 1 | 1 << 2); /* words 54-58,88 are valid */
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put_le16(p + 54, s->cylinders);
put_le16(p + 55, s->heads);
put_le16(p + 56, s->sectors);
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oldsize = s->cylinders * s->heads * s->sectors;
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put_le16(p + 57, oldsize);
put_le16(p + 58, oldsize >> 16);
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if (s->mult_sectors)
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put_le16(p + 59, 0x100 | s->mult_sectors);
put_le16(p + 60, s->nb_sectors);
put_le16(p + 61, s->nb_sectors >> 16);
put_le16(p + 80, (1 << 1) | (1 << 2));
put_le16(p + 82, (1 << 14));
put_le16(p + 83, (1 << 14));
put_le16(p + 84, (1 << 14));
put_le16(p + 85, (1 << 14));
put_le16(p + 86, 0);
put_le16(p + 87, (1 << 14));
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put_le16(p + 88, 0x1f | (1 << 13));
put_le16(p + 93, 1 | (1 << 14) | 0x2000 | 0x4000);
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}
static void ide_atapi_identify(IDEState *s)
{
uint16_t *p;
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char buf[20];
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memset(s->io_buffer, 0, 512);
p = (uint16_t *)s->io_buffer;
/* Removable CDROM, 50us response, 12 byte packets */
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put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
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snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
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put_le16(p + 20, 3); /* buffer type */
put_le16(p + 21, 512); /* cache size in sectors */
put_le16(p + 22, 4); /* ecc bytes */
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padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
padstr((uint8_t *)(p + 27), "QEMU CD-ROM", 40); /* model */
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put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
put_le16(p + 64, 1); /* PIO modes */
put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
|
|
486
|
|
|
487
488
|
put_le16(p + 71, 30); /* in ns */
put_le16(p + 72, 30); /* in ns */
|
|
489
|
|
|
490
|
put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
|
|
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
|
}
static void ide_set_signature(IDEState *s)
{
s->select &= 0xf0; /* clear head */
/* put signature */
s->nsector = 1;
s->sector = 1;
if (s->is_cdrom) {
s->lcyl = 0x14;
s->hcyl = 0xeb;
} else if (s->bs) {
s->lcyl = 0;
s->hcyl = 0;
} else {
s->lcyl = 0xff;
s->hcyl = 0xff;
}
}
static inline void ide_abort_command(IDEState *s)
{
s->status = READY_STAT | ERR_STAT;
s->error = ABRT_ERR;
}
static inline void ide_set_irq(IDEState *s)
{
|
|
519
|
BMDMAState *bm = s->bmdma;
|
|
520
|
if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
|
|
521
|
if (bm) {
|
|
522
|
bm->status |= BM_STATUS_INT;
|
|
523
524
|
}
s->set_irq(s->irq_opaque, s->irq, 1);
|
|
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
|
}
}
/* prepare data transfer and tell what to do after */
static void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
EndTransferFunc *end_transfer_func)
{
s->end_transfer_func = end_transfer_func;
s->data_ptr = buf;
s->data_end = buf + size;
s->status |= DRQ_STAT;
}
static void ide_transfer_stop(IDEState *s)
{
s->end_transfer_func = ide_transfer_stop;
s->data_ptr = s->io_buffer;
s->data_end = s->io_buffer;
s->status &= ~DRQ_STAT;
}
static int64_t ide_get_sector(IDEState *s)
{
int64_t sector_num;
if (s->select & 0x40) {
/* lba */
sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
(s->lcyl << 8) | s->sector;
} else {
sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
(s->select & 0x0f) * s->sectors +
(s->sector - 1);
}
return sector_num;
}
static void ide_set_sector(IDEState *s, int64_t sector_num)
{
unsigned int cyl, r;
if (s->select & 0x40) {
s->select = (s->select & 0xf0) | (sector_num >> 24);
s->hcyl = (sector_num >> 16);
s->lcyl = (sector_num >> 8);
s->sector = (sector_num);
} else {
cyl = sector_num / (s->heads * s->sectors);
r = sector_num % (s->heads * s->sectors);
s->hcyl = cyl >> 8;
s->lcyl = cyl;
|
|
574
|
s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
|
|
575
576
577
578
579
580
581
582
583
584
|
s->sector = (r % s->sectors) + 1;
}
}
static void ide_sector_read(IDEState *s)
{
int64_t sector_num;
int ret, n;
s->status = READY_STAT | SEEK_STAT;
|
|
585
|
s->error = 0; /* not needed by IDE spec, but needed by Windows */
|
|
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
|
sector_num = ide_get_sector(s);
n = s->nsector;
if (n == 0) {
/* no more sector to read from disk */
ide_transfer_stop(s);
} else {
#if defined(DEBUG_IDE)
printf("read sector=%Ld\n", sector_num);
#endif
if (n > s->req_nb_sectors)
n = s->req_nb_sectors;
ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
ide_set_irq(s);
ide_set_sector(s, sector_num + n);
s->nsector -= n;
}
}
|
|
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
|
static int ide_read_dma_cb(IDEState *s,
target_phys_addr_t phys_addr,
int transfer_size1)
{
int len, transfer_size, n;
int64_t sector_num;
transfer_size = transfer_size1;
while (transfer_size > 0) {
len = s->io_buffer_size - s->io_buffer_index;
if (len <= 0) {
/* transfert next data */
n = s->nsector;
if (n == 0)
break;
if (n > MAX_MULT_SECTORS)
n = MAX_MULT_SECTORS;
sector_num = ide_get_sector(s);
bdrv_read(s->bs, sector_num, s->io_buffer, n);
s->io_buffer_index = 0;
s->io_buffer_size = n * 512;
len = s->io_buffer_size;
sector_num += n;
ide_set_sector(s, sector_num);
s->nsector -= n;
}
if (len > transfer_size)
len = transfer_size;
cpu_physical_memory_write(phys_addr,
s->io_buffer + s->io_buffer_index, len);
s->io_buffer_index += len;
transfer_size -= len;
phys_addr += len;
}
if (s->io_buffer_index >= s->io_buffer_size && s->nsector == 0) {
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
#ifdef DEBUG_IDE_ATAPI
printf("dma status=0x%x\n", s->status);
#endif
return 0;
}
return transfer_size1 - transfer_size;
}
static void ide_sector_read_dma(IDEState *s)
{
s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
s->io_buffer_index = 0;
s->io_buffer_size = 0;
ide_dma_start(s, ide_read_dma_cb);
}
|
|
658
659
660
661
662
663
|
static void ide_sector_write_timer_cb(void *opaque)
{
IDEState *s = opaque;
ide_set_irq(s);
}
|
|
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
|
static void ide_sector_write(IDEState *s)
{
int64_t sector_num;
int ret, n, n1;
s->status = READY_STAT | SEEK_STAT;
sector_num = ide_get_sector(s);
#if defined(DEBUG_IDE)
printf("write sector=%Ld\n", sector_num);
#endif
n = s->nsector;
if (n > s->req_nb_sectors)
n = s->req_nb_sectors;
ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
s->nsector -= n;
if (s->nsector == 0) {
/* no more sector to write */
ide_transfer_stop(s);
} else {
n1 = s->nsector;
if (n1 > s->req_nb_sectors)
n1 = s->req_nb_sectors;
ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
}
ide_set_sector(s, sector_num + n);
|
|
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
|
#ifdef TARGET_I386
if (win2k_install_hack) {
/* It seems there is a bug in the Windows 2000 installer HDD
IDE driver which fills the disk with empty logs when the
IDE write IRQ comes too early. This hack tries to correct
that at the expense of slower write performances. Use this
option _only_ to install Windows 2000. You must disable it
for normal use. */
qemu_mod_timer(s->sector_write_timer,
qemu_get_clock(vm_clock) + (ticks_per_sec / 1000));
} else
#endif
{
ide_set_irq(s);
}
|
|
705
706
|
}
|
|
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
|
static int ide_write_dma_cb(IDEState *s,
target_phys_addr_t phys_addr,
int transfer_size1)
{
int len, transfer_size, n;
int64_t sector_num;
transfer_size = transfer_size1;
for(;;) {
len = s->io_buffer_size - s->io_buffer_index;
if (len == 0) {
n = s->io_buffer_size >> 9;
sector_num = ide_get_sector(s);
bdrv_write(s->bs, sector_num, s->io_buffer,
s->io_buffer_size >> 9);
sector_num += n;
ide_set_sector(s, sector_num);
s->nsector -= n;
n = s->nsector;
if (n == 0) {
/* end of transfer */
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
return 0;
}
if (n > MAX_MULT_SECTORS)
n = MAX_MULT_SECTORS;
s->io_buffer_index = 0;
s->io_buffer_size = n * 512;
len = s->io_buffer_size;
}
if (transfer_size <= 0)
break;
if (len > transfer_size)
len = transfer_size;
cpu_physical_memory_read(phys_addr,
s->io_buffer + s->io_buffer_index, len);
s->io_buffer_index += len;
transfer_size -= len;
phys_addr += len;
}
return transfer_size1 - transfer_size;
}
static void ide_sector_write_dma(IDEState *s)
{
int n;
s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
n = s->nsector;
if (n > MAX_MULT_SECTORS)
n = MAX_MULT_SECTORS;
s->io_buffer_index = 0;
s->io_buffer_size = n * 512;
ide_dma_start(s, ide_write_dma_cb);
}
|
|
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
|
static void ide_atapi_cmd_ok(IDEState *s)
{
s->error = 0;
s->status = READY_STAT;
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
ide_set_irq(s);
}
static void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
{
#ifdef DEBUG_IDE_ATAPI
printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
#endif
s->error = sense_key << 4;
s->status = READY_STAT | ERR_STAT;
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
s->sense_key = sense_key;
s->asc = asc;
ide_set_irq(s);
}
static inline void cpu_to_ube16(uint8_t *buf, int val)
{
buf[0] = val >> 8;
buf[1] = val;
}
static inline void cpu_to_ube32(uint8_t *buf, unsigned int val)
{
buf[0] = val >> 24;
buf[1] = val >> 16;
buf[2] = val >> 8;
buf[3] = val;
}
static inline int ube16_to_cpu(const uint8_t *buf)
{
return (buf[0] << 8) | buf[1];
}
static inline int ube32_to_cpu(const uint8_t *buf)
{
return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
}
|
|
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
|
static void lba_to_msf(uint8_t *buf, int lba)
{
lba += 150;
buf[0] = (lba / 75) / 60;
buf[1] = (lba / 75) % 60;
buf[2] = lba % 75;
}
static void cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf,
int sector_size)
{
switch(sector_size) {
case 2048:
bdrv_read(bs, (int64_t)lba << 2, buf, 4);
break;
case 2352:
/* sync bytes */
buf[0] = 0x00;
|
|
826
827
|
memset(buf + 1, 0xff, 10);
buf[11] = 0x00;
|
|
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
|
buf += 12;
/* MSF */
lba_to_msf(buf, lba);
buf[3] = 0x01; /* mode 1 data */
buf += 4;
/* data */
bdrv_read(bs, (int64_t)lba << 2, buf, 4);
buf += 2048;
/* ECC */
memset(buf, 0, 288);
break;
default:
break;
}
}
|
|
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
|
/* The whole ATAPI transfer logic is handled in this function */
static void ide_atapi_cmd_reply_end(IDEState *s)
{
int byte_count_limit, size;
#ifdef DEBUG_IDE_ATAPI
printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
s->packet_transfer_size,
s->elementary_transfer_size,
s->io_buffer_index);
#endif
if (s->packet_transfer_size <= 0) {
/* end of transfer */
ide_transfer_stop(s);
s->status = READY_STAT;
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
ide_set_irq(s);
#ifdef DEBUG_IDE_ATAPI
printf("status=0x%x\n", s->status);
#endif
} else {
/* see if a new sector must be read */
|
|
865
866
|
if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) {
cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
|
|
867
868
869
870
871
872
|
s->lba++;
s->io_buffer_index = 0;
}
if (s->elementary_transfer_size > 0) {
/* there are some data left to transmit in this elementary
transfer */
|
|
873
|
size = s->cd_sector_size - s->io_buffer_index;
|
|
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
|
if (size > s->elementary_transfer_size)
size = s->elementary_transfer_size;
ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
size, ide_atapi_cmd_reply_end);
s->packet_transfer_size -= size;
s->elementary_transfer_size -= size;
s->io_buffer_index += size;
} else {
/* a new transfer is needed */
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
byte_count_limit = s->lcyl | (s->hcyl << 8);
#ifdef DEBUG_IDE_ATAPI
printf("byte_count_limit=%d\n", byte_count_limit);
#endif
if (byte_count_limit == 0xffff)
byte_count_limit--;
size = s->packet_transfer_size;
if (size > byte_count_limit) {
/* byte count limit must be even if this case */
if (byte_count_limit & 1)
byte_count_limit--;
size = byte_count_limit;
}
|
|
897
898
|
s->lcyl = size;
s->hcyl = size >> 8;
|
|
899
900
901
|
s->elementary_transfer_size = size;
/* we cannot transmit more than one sector at a time */
if (s->lba != -1) {
|
|
902
903
|
if (size > (s->cd_sector_size - s->io_buffer_index))
size = (s->cd_sector_size - s->io_buffer_index);
|
|
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
|
}
ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
size, ide_atapi_cmd_reply_end);
s->packet_transfer_size -= size;
s->elementary_transfer_size -= size;
s->io_buffer_index += size;
ide_set_irq(s);
#ifdef DEBUG_IDE_ATAPI
printf("status=0x%x\n", s->status);
#endif
}
}
}
/* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size)
{
if (size > max_size)
size = max_size;
s->lba = -1; /* no sector read */
s->packet_transfer_size = size;
s->elementary_transfer_size = 0;
s->io_buffer_index = 0;
s->status = READY_STAT;
ide_atapi_cmd_reply_end(s);
}
/* start a CD-CDROM read command */
|
|
933
934
|
static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors,
int sector_size)
|
|
935
936
|
{
s->lba = lba;
|
|
937
|
s->packet_transfer_size = nb_sectors * sector_size;
|
|
938
|
s->elementary_transfer_size = 0;
|
|
939
940
|
s->io_buffer_index = sector_size;
s->cd_sector_size = sector_size;
|
|
941
942
943
944
945
|
s->status = READY_STAT;
ide_atapi_cmd_reply_end(s);
}
|
|
946
947
948
949
950
951
952
953
954
|
/* ATAPI DMA support */
static int ide_atapi_cmd_read_dma_cb(IDEState *s,
target_phys_addr_t phys_addr,
int transfer_size1)
{
int len, transfer_size;
transfer_size = transfer_size1;
while (transfer_size > 0) {
|
|
955
956
957
|
#ifdef DEBUG_IDE_ATAPI
printf("transfer_size: %d phys_addr=%08x\n", transfer_size, phys_addr);
#endif
|
|
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
|
if (s->packet_transfer_size <= 0)
break;
len = s->cd_sector_size - s->io_buffer_index;
if (len <= 0) {
/* transfert next data */
cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
s->lba++;
s->io_buffer_index = 0;
len = s->cd_sector_size;
}
if (len > transfer_size)
len = transfer_size;
cpu_physical_memory_write(phys_addr,
s->io_buffer + s->io_buffer_index, len);
s->packet_transfer_size -= len;
s->io_buffer_index += len;
transfer_size -= len;
phys_addr += len;
}
if (s->packet_transfer_size <= 0) {
s->status = READY_STAT;
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
ide_set_irq(s);
#ifdef DEBUG_IDE_ATAPI
printf("dma status=0x%x\n", s->status);
#endif
return 0;
}
return transfer_size1 - transfer_size;
}
/* start a CD-CDROM read command with DMA */
/* XXX: test if DMA is available */
static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors,
int sector_size)
{
s->lba = lba;
s->packet_transfer_size = nb_sectors * sector_size;
s->io_buffer_index = sector_size;
s->cd_sector_size = sector_size;
s->status = READY_STAT | DRQ_STAT;
ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
}
static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors,
int sector_size)
{
#ifdef DEBUG_IDE_ATAPI
printf("read: LBA=%d nb_sectors=%d\n", lba, nb_sectors);
#endif
if (s->atapi_dma) {
ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size);
} else {
ide_atapi_cmd_read_pio(s, lba, nb_sectors, sector_size);
}
}
|
|
1016
|
/* same toc as bochs. Return -1 if error or the toc length */
|
|
1017
|
/* XXX: check this */
|
|
1018
1019
1020
1021
1022
1023
1024
1025
|
static int cdrom_read_toc(IDEState *s, uint8_t *buf, int msf, int start_track)
{
uint8_t *q;
int nb_sectors, len;
if (start_track > 1 && start_track != 0xaa)
return -1;
q = buf + 2;
|
|
1026
1027
|
*q++ = 1; /* first session */
*q++ = 1; /* last session */
|
|
1028
1029
1030
1031
1032
1033
1034
|
if (start_track <= 1) {
*q++ = 0; /* reserved */
*q++ = 0x14; /* ADR, control */
*q++ = 1; /* track number */
*q++ = 0; /* reserved */
if (msf) {
*q++ = 0; /* reserved */
|
|
1035
1036
|
lba_to_msf(q, 0);
q += 3;
|
|
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
|
} else {
/* sector 0 */
cpu_to_ube32(q, 0);
q += 4;
}
}
/* lead out track */
*q++ = 0; /* reserved */
*q++ = 0x16; /* ADR, control */
*q++ = 0xaa; /* track number */
*q++ = 0; /* reserved */
nb_sectors = s->nb_sectors >> 2;
if (msf) {
*q++ = 0; /* reserved */
|
|
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
|
lba_to_msf(q, nb_sectors);
q += 3;
} else {
cpu_to_ube32(q, nb_sectors);
q += 4;
}
len = q - buf;
cpu_to_ube16(buf, len - 2);
return len;
}
/* mostly same info as PearPc */
static int cdrom_read_toc_raw(IDEState *s, uint8_t *buf, int msf,
int session_num)
{
uint8_t *q;
int nb_sectors, len;
q = buf + 2;
*q++ = 1; /* first session */
*q++ = 1; /* last session */
*q++ = 1; /* session number */
*q++ = 0x14; /* data track */
*q++ = 0; /* track number */
*q++ = 0xa0; /* lead-in */
*q++ = 0; /* min */
*q++ = 0; /* sec */
*q++ = 0; /* frame */
*q++ = 0;
*q++ = 1; /* first track */
*q++ = 0x00; /* disk type */
*q++ = 0x00;
*q++ = 1; /* session number */
*q++ = 0x14; /* data track */
*q++ = 0; /* track number */
*q++ = 0xa1;
*q++ = 0; /* min */
*q++ = 0; /* sec */
*q++ = 0; /* frame */
*q++ = 0;
*q++ = 1; /* last track */
*q++ = 0x00;
*q++ = 0x00;
*q++ = 1; /* session number */
*q++ = 0x14; /* data track */
*q++ = 0; /* track number */
*q++ = 0xa2; /* lead-out */
*q++ = 0; /* min */
*q++ = 0; /* sec */
*q++ = 0; /* frame */
nb_sectors = s->nb_sectors >> 2;
if (msf) {
*q++ = 0; /* reserved */
lba_to_msf(q, nb_sectors);
q += 3;
|
|
1109
1110
1111
1112
|
} else {
cpu_to_ube32(q, nb_sectors);
q += 4;
}
|
|
1113
1114
1115
1116
1117
1118
1119
1120
|
*q++ = 1; /* session number */
*q++ = 0x14; /* ADR, control */
*q++ = 0; /* track number */
*q++ = 1; /* point */
*q++ = 0; /* min */
*q++ = 0; /* sec */
*q++ = 0; /* frame */
|
|
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
|
if (msf) {
*q++ = 0;
lba_to_msf(q, 0);
q += 3;
} else {
*q++ = 0;
*q++ = 0;
*q++ = 0;
*q++ = 0;
}
|
|
1131
|
|
|
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
|
len = q - buf;
cpu_to_ube16(buf, len - 2);
return len;
}
static void ide_atapi_cmd(IDEState *s)
{
const uint8_t *packet;
uint8_t *buf;
int max_len;
packet = s->io_buffer;
buf = s->io_buffer;
#ifdef DEBUG_IDE_ATAPI
{
int i;
printf("ATAPI limit=0x%x packet:", s->lcyl | (s->hcyl << 8));
for(i = 0; i < ATAPI_PACKET_SIZE; i++) {
printf(" %02x", packet[i]);
}
printf("\n");
}
#endif
switch(s->io_buffer[0]) {
case GPCMD_TEST_UNIT_READY:
|
|
1157
|
if (bdrv_is_inserted(s->bs)) {
|
|
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
|
ide_atapi_cmd_ok(s);
} else {
ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
}
break;
case GPCMD_MODE_SENSE_10:
{
int action, code;
max_len = ube16_to_cpu(packet + 7);
action = packet[2] >> 6;
code = packet[2] & 0x3f;
switch(action) {
case 0: /* current values */
switch(code) {
case 0x01: /* error recovery */
cpu_to_ube16(&buf[0], 16 + 6);
buf[2] = 0x70;
buf[3] = 0;
buf[4] = 0;
buf[5] = 0;
buf[6] = 0;
buf[7] = 0;
buf[8] = 0x01;
buf[9] = 0x06;
buf[10] = 0x00;
buf[11] = 0x05;
buf[12] = 0x00;
buf[13] = 0x00;
buf[14] = 0x00;
buf[15] = 0x00;
ide_atapi_cmd_reply(s, 16, max_len);
break;
case 0x2a:
cpu_to_ube16(&buf[0], 28 + 6);
buf[2] = 0x70;
buf[3] = 0;
buf[4] = 0;
buf[5] = 0;
buf[6] = 0;
buf[7] = 0;
buf[8] = 0x2a;
buf[9] = 0x12;
buf[10] = 0x00;
buf[11] = 0x00;
buf[12] = 0x70;
buf[13] = 3 << 5;
buf[14] = (1 << 0) | (1 << 3) | (1 << 5);
|
|
1209
|
if (bdrv_is_locked(s->bs))
|
|
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
|
buf[6] |= 1 << 1;
buf[15] = 0x00;
cpu_to_ube16(&buf[16], 706);
buf[18] = 0;
buf[19] = 2;
cpu_to_ube16(&buf[20], 512);
cpu_to_ube16(&buf[22], 706);
buf[24] = 0;
buf[25] = 0;
buf[26] = 0;
buf[27] = 0;
ide_atapi_cmd_reply(s, 28, max_len);
break;
default:
goto error_cmd;
}
break;
case 1: /* changeable values */
goto error_cmd;
case 2: /* default values */
goto error_cmd;
default:
case 3: /* saved values */
ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
break;
}
}
break;
case GPCMD_REQUEST_SENSE:
max_len = packet[4];
memset(buf, 0, 18);
buf[0] = 0x70 | (1 << 7);
buf[2] = s->sense_key;
buf[7] = 10;
buf[12] = s->asc;
ide_atapi_cmd_reply(s, 18, max_len);
break;
case GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
|
|
1249
1250
|
if (bdrv_is_inserted(s->bs)) {
bdrv_set_locked(s->bs, packet[4] & 1);
|
|
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
|
ide_atapi_cmd_ok(s);
} else {
ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
}
break;
case GPCMD_READ_10:
case GPCMD_READ_12:
{
int nb_sectors, lba;
|
|
1262
|
if (!bdrv_is_inserted(s->bs)) {
|
|
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
|
ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
break;
}
if (packet[0] == GPCMD_READ_10)
nb_sectors = ube16_to_cpu(packet + 7);
else
nb_sectors = ube32_to_cpu(packet + 6);
lba = ube32_to_cpu(packet + 2);
if (nb_sectors == 0) {
ide_atapi_cmd_ok(s);
break;
}
if (((int64_t)(lba + nb_sectors) << 2) > s->nb_sectors) {
ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_LOGICAL_BLOCK_OOR);
break;
}
|
|
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
|
ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
}
break;
case GPCMD_READ_CD:
{
int nb_sectors, lba, transfer_request;
if (!bdrv_is_inserted(s->bs)) {
ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
break;
}
nb_sectors = (packet[6] << 16) | (packet[7] << 8) | packet[8];
lba = ube32_to_cpu(packet + 2);
if (nb_sectors == 0) {
ide_atapi_cmd_ok(s);
break;
}
if (((int64_t)(lba + nb_sectors) << 2) > s->nb_sectors) {
ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_LOGICAL_BLOCK_OOR);
break;
}
transfer_request = packet[9];
switch(transfer_request & 0xf8) {
case 0x00:
/* nothing */
ide_atapi_cmd_ok(s);
break;
case 0x10:
/* normal read */
ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
break;
case 0xf8:
/* read all data */
ide_atapi_cmd_read(s, lba, nb_sectors, 2352);
break;
default:
ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_INV_FIELD_IN_CMD_PACKET);
break;
}
|
|
1323
1324
1325
1326
1327
|
}
break;
case GPCMD_SEEK:
{
int lba;
|
|
1328
|
if (!bdrv_is_inserted(s->bs)) {
|
|
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
|
ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
break;
}
lba = ube32_to_cpu(packet + 2);
if (((int64_t)lba << 2) > s->nb_sectors) {
ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_LOGICAL_BLOCK_OOR);
break;
}
ide_atapi_cmd_ok(s);
}
break;
case GPCMD_START_STOP_UNIT:
{
int start, eject;
start = packet[4] & 1;
eject = (packet[4] >> 1) & 1;
|
|
1348
1349
1350
1351
|
if (eject && !start) {
/* eject the disk */
bdrv_close(s->bs);
}
|
|
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
|
ide_atapi_cmd_ok(s);
}
break;
case GPCMD_MECHANISM_STATUS:
{
max_len = ube16_to_cpu(packet + 8);
cpu_to_ube16(buf, 0);
/* no current LBA */
buf[2] = 0;
buf[3] = 0;
buf[4] = 0;
buf[5] = 1;
cpu_to_ube16(buf + 6, 0);
ide_atapi_cmd_reply(s, 8, max_len);
}
break;
case GPCMD_READ_TOC_PMA_ATIP:
{
int format, msf, start_track, len;
|
|
1372
|
if (!bdrv_is_inserted(s->bs)) {
|
|
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
|
ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
break;
}
max_len = ube16_to_cpu(packet + 7);
format = packet[9] >> 6;
msf = (packet[1] >> 1) & 1;
start_track = packet[6];
switch(format) {
case 0:
len = cdrom_read_toc(s, buf, msf, start_track);
if (len < 0)
goto error_cmd;
ide_atapi_cmd_reply(s, len, max_len);
break;
case 1:
/* multi session : only a single session defined */
memset(buf, 0, 12);
buf[1] = 0x0a;
buf[2] = 0x01;
buf[3] = 0x01;
ide_atapi_cmd_reply(s, 12, max_len);
break;
|
|
1396
1397
1398
1399
1400
1401
|
case 2:
len = cdrom_read_toc_raw(s, buf, msf, start_track);
if (len < 0)
goto error_cmd;
ide_atapi_cmd_reply(s, len, max_len);
break;
|
|
1402
|
default:
|
|
1403
1404
1405
1406
|
error_cmd:
ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_INV_FIELD_IN_CMD_PACKET);
break;
|
|
1407
1408
1409
1410
|
}
}
break;
case GPCMD_READ_CDVD_CAPACITY:
|
|
1411
|
if (!bdrv_is_inserted(s->bs)) {
|
|
1412
1413
1414
1415
1416
1417
1418
1419
1420
|
ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
break;
}
/* NOTE: it is really the number of sectors minus 1 */
cpu_to_ube32(buf, (s->nb_sectors >> 2) - 1);
cpu_to_ube32(buf + 4, 2048);
ide_atapi_cmd_reply(s, 8, 8);
break;
|
|
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
|
case GPCMD_INQUIRY:
max_len = packet[4];
buf[0] = 0x05; /* CD-ROM */
buf[1] = 0x80; /* removable */
buf[2] = 0x00; /* ISO */
buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
buf[4] = 31; /* additionnal length */
buf[5] = 0; /* reserved */
buf[6] = 0; /* reserved */
buf[7] = 0; /* reserved */
padstr8(buf + 8, 8, "QEMU");
padstr8(buf + 16, 16, "QEMU CD-ROM");
padstr8(buf + 32, 4, QEMU_VERSION);
ide_atapi_cmd_reply(s, 36, max_len);
break;
|
|
1436
1437
|
default:
ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
|
|
1438
|
ASC_ILLEGAL_OPCODE);
|
|
1439
1440
1441
1442
|
break;
}
}
|
|
1443
1444
|
/* called when the inserted state of the media has changed */
static void cdrom_change_cb(void *opaque)
|
|
1445
|
{
|
|
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
|
IDEState *s = opaque;
int64_t nb_sectors;
/* XXX: send interrupt too */
bdrv_get_geometry(s->bs, &nb_sectors);
s->nb_sectors = nb_sectors;
}
static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEState *ide_if = opaque;
|
|
1457
|
IDEState *s;
|
|
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
|
int unit, n;
#ifdef DEBUG_IDE
printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
#endif
addr &= 7;
switch(addr) {
case 0:
break;
case 1:
|
|
1468
1469
1470
|
/* NOTE: data is written to the two drives */
ide_if[0].feature = val;
ide_if[1].feature = val;
|
|
1471
1472
1473
1474
|
break;
case 2:
if (val == 0)
val = 256;
|
|
1475
1476
|
ide_if[0].nsector = val;
ide_if[1].nsector = val;
|
|
1477
1478
|
break;
case 3:
|
|
1479
1480
|
ide_if[0].sector = val;
ide_if[1].sector = val;
|
|
1481
1482
|
break;
case 4:
|
|
1483
1484
|
ide_if[0].lcyl = val;
ide_if[1].lcyl = val;
|
|
1485
1486
|
break;
case 5:
|
|
1487
1488
|
ide_if[0].hcyl = val;
ide_if[1].hcyl = val;
|
|
1489
1490
|
break;
case 6:
|
|
1491
1492
|
ide_if[0].select = (val & ~0x10) | 0xa0;
ide_if[1].select = (val | 0x10) | 0xa0;
|
|
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
|
/* select drive */
unit = (val >> 4) & 1;
s = ide_if + unit;
ide_if->cur_drive = s;
break;
default:
case 7:
/* command */
#if defined(DEBUG_IDE)
printf("ide: CMD=%02x\n", val);
#endif
|
|
1504
|
s = ide_if->cur_drive;
|
|
1505
1506
1507
|
/* ignore commands to non existant slave */
if (s != ide_if && !s->bs)
break;
|
|
1508
1509
1510
1511
|
switch(val) {
case WIN_IDENTIFY:
if (s->bs && !s->is_cdrom) {
ide_identify(s);
|
|
1512
|
s->status = READY_STAT | SEEK_STAT;
|
|
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
|
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
} else {
if (s->is_cdrom) {
ide_set_signature(s);
}
ide_abort_command(s);
}
ide_set_irq(s);
break;
case WIN_SPECIFY:
case WIN_RECAL:
|
|
1524
|
s->error = 0;
|
|
1525
|
s->status = READY_STAT | SEEK_STAT;
|
|
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
|
ide_set_irq(s);
break;
case WIN_SETMULT:
if (s->nsector > MAX_MULT_SECTORS ||
s->nsector == 0 ||
(s->nsector & (s->nsector - 1)) != 0) {
ide_abort_command(s);
} else {
s->mult_sectors = s->nsector;
s->status = READY_STAT;
}
ide_set_irq(s);
break;
|
|
1539
1540
1541
1542
1543
1544
|
case WIN_VERIFY:
case WIN_VERIFY_ONCE:
/* do sector number check ? */
s->status = READY_STAT;
ide_set_irq(s);
break;
|
|
1545
1546
|
case WIN_READ:
case WIN_READ_ONCE:
|
|
1547
1548
|
if (!s->bs)
goto abort_cmd;
|
|
1549
1550
1551
1552
1553
|
s->req_nb_sectors = 1;
ide_sector_read(s);
break;
case WIN_WRITE:
case WIN_WRITE_ONCE:
|
|
1554
|
s->error = 0;
|
|
1555
|
s->status = SEEK_STAT | READY_STAT;
|
|
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
|
s->req_nb_sectors = 1;
ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
break;
case WIN_MULTREAD:
if (!s->mult_sectors)
goto abort_cmd;
s->req_nb_sectors = s->mult_sectors;
ide_sector_read(s);
break;
case WIN_MULTWRITE:
if (!s->mult_sectors)
goto abort_cmd;
|
|
1568
|
s->error = 0;
|
|
1569
|
s->status = SEEK_STAT | READY_STAT;
|
|
1570
1571
1572
1573
1574
1575
|
s->req_nb_sectors = s->mult_sectors;
n = s->nsector;
if (n > s->req_nb_sectors)
n = s->req_nb_sectors;
ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
break;
|
|
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
|
case WIN_READDMA:
case WIN_READDMA_ONCE:
if (!s->bs)
goto abort_cmd;
ide_sector_read_dma(s);
break;
case WIN_WRITEDMA:
case WIN_WRITEDMA_ONCE:
if (!s->bs)
goto abort_cmd;
ide_sector_write_dma(s);
break;
|
|
1588
1589
1590
1591
1592
|
case WIN_READ_NATIVE_MAX:
ide_set_sector(s, s->nb_sectors - 1);
s->status = READY_STAT;
ide_set_irq(s);
break;
|
|
1593
1594
1595
1596
1597
|
case WIN_CHECKPOWERMODE1:
s->nsector = 0xff; /* device active or idle */
s->status = READY_STAT;
ide_set_irq(s);
break;
|
|
1598
1599
1600
1601
1602
1603
|
case WIN_SETFEATURES:
if (!s->bs)
goto abort_cmd;
/* XXX: valid for CDROM ? */
switch(s->feature) {
case 0x02: /* write cache enable */
|
|
1604
|
case 0x03: /* set transfer mode */
|
|
1605
1606
1607
|
case 0x82: /* write cache disable */
case 0xaa: /* read look-ahead enable */
case 0x55: /* read look-ahead disable */
|
|
1608
|
s->status = READY_STAT | SEEK_STAT;
|
|
1609
1610
1611
1612
1613
1614
|
ide_set_irq(s);
break;
default:
goto abort_cmd;
}
break;
|
|
1615
|
case WIN_STANDBYNOW1:
|
|
1616
|
case WIN_IDLEIMMEDIATE:
|
|
1617
|
case WIN_FLUSH_CACHE:
|
|
1618
1619
1620
|
s->status = READY_STAT;
ide_set_irq(s);
break;
|
|
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
|
/* ATAPI commands */
case WIN_PIDENTIFY:
if (s->is_cdrom) {
ide_atapi_identify(s);
s->status = READY_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
} else {
ide_abort_command(s);
}
ide_set_irq(s);
break;
|
|
1632
1633
1634
1635
1636
|
case WIN_DIAGNOSE:
ide_set_signature(s);
s->status = 0x00; /* NOTE: READY is _not_ set */
s->error = 0x01;
break;
|
|
1637
1638
1639
1640
|
case WIN_SRST:
if (!s->is_cdrom)
goto abort_cmd;
ide_set_signature(s);
|
|
1641
|
s->status = 0x00; /* NOTE: READY is _not_ set */
|
|
1642
1643
1644
1645
1646
|
s->error = 0x01;
break;
case WIN_PACKETCMD:
if (!s->is_cdrom)
goto abort_cmd;
|
|
1647
1648
|
/* overlapping commands not supported */
if (s->feature & 0x02)
|
|
1649
|
goto abort_cmd;
|
|
1650
|
s->atapi_dma = s->feature & 1;
|
|
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
|
s->nsector = 1;
ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
ide_atapi_cmd);
break;
default:
abort_cmd:
ide_abort_command(s);
ide_set_irq(s);
break;
}
}
}
|
|
1664
|
static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
|
|
1665
|
{
|
|
1666
1667
|
IDEState *ide_if = opaque;
IDEState *s = ide_if->cur_drive;
|
|
1668
1669
1670
1671
1672
1673
1674
1675
1676
|
uint32_t addr;
int ret;
addr = addr1 & 7;
switch(addr) {
case 0:
ret = 0xff;
break;
case 1:
|
|
1677
|
if (!ide_if[0].bs && !ide_if[1].bs)
|
|
1678
1679
1680
|
ret = 0;
else
ret = s->error;
|
|
1681
1682
|
break;
case 2:
|
|
1683
|
if (!ide_if[0].bs && !ide_if[1].bs)
|
|
1684
1685
1686
|
ret = 0;
else
ret = s->nsector & 0xff;
|
|
1687
1688
|
break;
case 3:
|
|
1689
|
if (!ide_if[0].bs && !ide_if[1].bs)
|
|
1690
1691
1692
|
ret = 0;
else
ret = s->sector;
|
|
1693
1694
|
break;
case 4:
|
|
1695
|
if (!ide_if[0].bs && !ide_if[1].bs)
|
|
1696
1697
1698
|
ret = 0;
else
ret = s->lcyl;
|
|
1699
1700
|
break;
case 5:
|
|
1701
|
if (!ide_if[0].bs && !ide_if[1].bs)
|
|
1702
1703
1704
|
ret = 0;
else
ret = s->hcyl;
|
|
1705
1706
|
break;
case 6:
|
|
1707
|
if (!ide_if[0].bs && !ide_if[1].bs)
|
|
1708
1709
|
ret = 0;
else
|
|
1710
|
ret = s->select;
|
|
1711
1712
1713
|
break;
default:
case 7:
|
|
1714
1715
|
if ((!ide_if[0].bs && !ide_if[1].bs) ||
(s != ide_if && !s->bs))
|
|
1716
1717
1718
|
ret = 0;
else
ret = s->status;
|
|
1719
|
s->set_irq(s->irq_opaque, s->irq, 0);
|
|
1720
1721
1722
1723
1724
1725
1726
1727
|
break;
}
#ifdef DEBUG_IDE
printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
#endif
return ret;
}
|
|
1728
|
static uint32_t ide_status_read(void *opaque, uint32_t addr)
|
|
1729
|
{
|
|
1730
1731
|
IDEState *ide_if = opaque;
IDEState *s = ide_if->cur_drive;
|
|
1732
|
int ret;
|
|
1733
|
|
|
1734
1735
|
if ((!ide_if[0].bs && !ide_if[1].bs) ||
(s != ide_if && !s->bs))
|
|
1736
1737
1738
|
ret = 0;
else
ret = s->status;
|
|
1739
1740
1741
1742
1743
1744
|
#ifdef DEBUG_IDE
printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
#endif
return ret;
}
|
|
1745
|
static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
|
|
1746
|
{
|
|
1747
|
IDEState *ide_if = opaque;
|
|
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
|
IDEState *s;
int i;
#ifdef DEBUG_IDE
printf("ide: write control addr=0x%x val=%02x\n", addr, val);
#endif
/* common for both drives */
if (!(ide_if[0].cmd & IDE_CMD_RESET) &&
(val & IDE_CMD_RESET)) {
/* reset low to high */
for(i = 0;i < 2; i++) {
s = &ide_if[i];
s->status = BUSY_STAT | SEEK_STAT;
s->error = 0x01;
}
} else if ((ide_if[0].cmd & IDE_CMD_RESET) &&
!(val & IDE_CMD_RESET)) {
/* high to low */
for(i = 0;i < 2; i++) {
s = &ide_if[i];
|
|
1768
1769
1770
|
if (s->is_cdrom)
s->status = 0x00; /* NOTE: READY is _not_ set */
else
|
|
1771
|
s->status = READY_STAT | SEEK_STAT;
|
|
1772
1773
1774
1775
1776
1777
1778
1779
|
ide_set_signature(s);
}
}
ide_if[0].cmd = val;
ide_if[1].cmd = val;
}
|
|
1780
|
static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
|
|
1781
|
{
|
|
1782
|
IDEState *s = ((IDEState *)opaque)->cur_drive;
|
|
1783
1784
1785
|
uint8_t *p;
p = s->data_ptr;
|
|
1786
|
*(uint16_t *)p = le16_to_cpu(val);
|
|
1787
1788
1789
1790
1791
1792
|
p += 2;
s->data_ptr = p;
if (p >= s->data_end)
s->end_transfer_func(s);
}
|
|
1793
|
static uint32_t ide_data_readw(void *opaque, uint32_t addr)
|
|
1794
|
{
|
|
1795
|
IDEState *s = ((IDEState *)opaque)->cur_drive;
|
|
1796
1797
1798
|
uint8_t *p;
int ret;
p = s->data_ptr;
|
|
1799
|
ret = cpu_to_le16(*(uint16_t *)p);
|
|
1800
1801
1802
1803
1804
1805
1806
|
p += 2;
s->data_ptr = p;
if (p >= s->data_end)
s->end_transfer_func(s);
return ret;
}
|
|
1807
|
static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
|
|
1808
|
{
|
|
1809
|
IDEState *s = ((IDEState *)opaque)->cur_drive;
|
|
1810
1811
1812
|
uint8_t *p;
p = s->data_ptr;
|
|
1813
|
*(uint32_t *)p = le32_to_cpu(val);
|
|
1814
1815
1816
1817
1818
1819
|
p += 4;
s->data_ptr = p;
if (p >= s->data_end)
s->end_transfer_func(s);
}
|
|
1820
|
static uint32_t ide_data_readl(void *opaque, uint32_t addr)
|
|
1821
|
{
|
|
1822
|
IDEState *s = ((IDEState *)opaque)->cur_drive;
|
|
1823
1824
1825
1826
|
uint8_t *p;
int ret;
p = s->data_ptr;
|
|
1827
|
ret = cpu_to_le32(*(uint32_t *)p);
|
|
1828
1829
1830
1831
1832
1833
1834
|
p += 4;
s->data_ptr = p;
if (p >= s->data_end)
s->end_transfer_func(s);
return ret;
}
|
|
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
|
static void ide_dummy_transfer_stop(IDEState *s)
{
s->data_ptr = s->io_buffer;
s->data_end = s->io_buffer;
s->io_buffer[0] = 0xff;
s->io_buffer[1] = 0xff;
s->io_buffer[2] = 0xff;
s->io_buffer[3] = 0xff;
}
|
|
1845
1846
1847
1848
1849
1850
1851
|
static void ide_reset(IDEState *s)
{
s->mult_sectors = MAX_MULT_SECTORS;
s->cur_drive = s;
s->select = 0xa0;
s->status = READY_STAT;
ide_set_signature(s);
|
|
1852
1853
1854
1855
|
/* init the transfer handler so that 0xffff is returned on data
accesses */
s->end_transfer_func = ide_dummy_transfer_stop;
ide_dummy_transfer_stop(s);
|
|
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
|
}
struct partition {
uint8_t boot_ind; /* 0x80 - active */
uint8_t head; /* starting head */
uint8_t sector; /* starting sector */
uint8_t cyl; /* starting cylinder */
uint8_t sys_ind; /* What partition type */
uint8_t end_head; /* end head */
uint8_t end_sector; /* end sector */
uint8_t end_cyl; /* end cylinder */
uint32_t start_sect; /* starting sector counting from 0 */
uint32_t nr_sects; /* nr of sectors in partition */
} __attribute__((packed));
|
|
1871
1872
1873
|
/* try to guess the disk logical geometry from the MSDOS partition table. Return 0 if OK, -1 if could not guess */
static int guess_disk_lchs(IDEState *s,
int *pcylinders, int *pheads, int *psectors)
|
|
1874
1875
|
{
uint8_t buf[512];
|
|
1876
|
int ret, i, heads, sectors, cylinders;
|
|
1877
1878
1879
1880
1881
|
struct partition *p;
uint32_t nr_sects;
ret = bdrv_read(s->bs, 0, buf, 1);
if (ret < 0)
|
|
1882
|
return -1;
|
|
1883
1884
|
/* test msdos magic */
if (buf[510] != 0x55 || buf[511] != 0xaa)
|
|
1885
|
return -1;
|
|
1886
1887
|
for(i = 0; i < 4; i++) {
p = ((struct partition *)(buf + 0x1be)) + i;
|
|
1888
|
nr_sects = le32_to_cpu(p->nr_sects);
|
|
1889
1890
1891
|
if (nr_sects && p->end_head) {
/* We make the assumption that the partition terminates on
a cylinder boundary */
|
|
1892
1893
1894
1895
1896
1897
1898
|
heads = p->end_head + 1;
sectors = p->end_sector & 63;
if (sectors == 0)
continue;
cylinders = s->nb_sectors / (heads * sectors);
if (cylinders < 1 || cylinders > 16383)
continue;
|
|
1899
1900
1901
|
*pheads = heads;
*psectors = sectors;
*pcylinders = cylinders;
|
|
1902
|
#if 0
|
|
1903
1904
|
printf("guessed geometry: LCHS=%d %d %d\n",
cylinders, heads, sectors);
|
|
1905
|
#endif
|
|
1906
|
return 0;
|
|
1907
1908
|
}
}
|
|
1909
|
return -1;
|
|
1910
1911
|
}
|
|
1912
1913
1914
|
static void ide_init2(IDEState *ide_state,
BlockDriverState *hd0, BlockDriverState *hd1,
SetIRQFunc *set_irq, void *irq_opaque, int irq)
|
|
1915
|
{
|
|
1916
|
IDEState *s;
|
|
1917
|
static int drive_serial = 1;
|
|
1918
|
int i, cylinders, heads, secs, translation;
|
|
1919
1920
|
int64_t nb_sectors;
|
|
1921
1922
1923
1924
1925
1926
|
for(i = 0; i < 2; i++) {
s = ide_state + i;
if (i == 0)
s->bs = hd0;
else
s->bs = hd1;
|
|
1927
1928
1929
|
if (s->bs) {
bdrv_get_geometry(s->bs, &nb_sectors);
s->nb_sectors = nb_sectors;
|
|
1930
1931
1932
|
/* if a geometry hint is available, use it */
bdrv_get_geometry_hint(s->bs, &cylinders, &heads, &secs);
if (cylinders != 0) {
|
|
1933
|
s->cylinders = cylinders;
|
|
1934
1935
1936
|
s->heads = heads;
s->sectors = secs;
} else {
|
|
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
|
if (guess_disk_lchs(s, &cylinders, &heads, &secs) == 0) {
if (heads > 16) {
/* if heads > 16, it means that a BIOS LBA
translation was active, so the default
hardware geometry is OK */
goto default_geometry;
} else {
s->cylinders = cylinders;
s->heads = heads;
s->sectors = secs;
/* disable any translation to be in sync with
the logical geometry */
translation = bdrv_get_translation_hint(s->bs);
if (translation == BIOS_ATA_TRANSLATION_AUTO) {
bdrv_set_translation_hint(s->bs,
BIOS_ATA_TRANSLATION_NONE);
}
}
} else {
default_geometry:
|
|
1957
|
/* if no geometry, use a standard physical disk geometry */
|
|
1958
1959
1960
1961
1962
1963
1964
1965
1966
|
cylinders = nb_sectors / (16 * 63);
if (cylinders > 16383)
cylinders = 16383;
else if (cylinders < 2)
cylinders = 2;
s->cylinders = cylinders;
s->heads = 16;
s->sectors = 63;
}
|
|
1967
|
bdrv_set_geometry_hint(s->bs, s->cylinders, s->heads, s->sectors);
|
|
1968
1969
1970
1971
|
}
if (bdrv_get_type_hint(s->bs) == BDRV_TYPE_CDROM) {
s->is_cdrom = 1;
bdrv_set_change_cb(s->bs, cdrom_change_cb, s);
|
|
1972
1973
|
}
}
|
|
1974
|
s->drive_serial = drive_serial++;
|
|
1975
1976
|
s->set_irq = set_irq;
s->irq_opaque = irq_opaque;
|
|
1977
|
s->irq = irq;
|
|
1978
1979
|
s->sector_write_timer = qemu_new_timer(vm_clock,
ide_sector_write_timer_cb, s);
|
|
1980
1981
|
ide_reset(s);
}
|
|
1982
1983
|
}
|
|
1984
|
static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2)
|
|
1985
|
{
|
|
1986
1987
1988
1989
1990
|
register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state);
register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state);
if (iobase2) {
register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
|
|
1991
|
}
|
|
1992
1993
1994
1995
1996
1997
|
/* data ports */
register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state);
register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
|
|
1998
|
}
|
|
1999
2000
|
/***********************************************************/
|
|
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
|
/* ISA IDE definitions */
void isa_ide_init(int iobase, int iobase2, int irq,
BlockDriverState *hd0, BlockDriverState *hd1)
{
IDEState *ide_state;
ide_state = qemu_mallocz(sizeof(IDEState) * 2);
if (!ide_state)
return;
|
|
2012
|
ide_init2(ide_state, hd0, hd1, pic_set_irq_new, isa_pic, irq);
|
|
2013
2014
2015
2016
|
ide_init_ioport(ide_state, iobase, iobase2);
}
/***********************************************************/
|
|
2017
2018
|
/* PCI IDE definitions */
|
|
2019
2020
|
static void cmd646_update_irq(PCIIDEState *d);
|
|
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
|
static void ide_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCIIDEState *d = (PCIIDEState *)pci_dev;
IDEState *ide_state;
if (region_num <= 3) {
ide_state = &d->ide_if[(region_num >> 1) * 2];
if (region_num & 1) {
register_ioport_read(addr + 2, 1, 1, ide_status_read, ide_state);
register_ioport_write(addr + 2, 1, 1, ide_cmd_write, ide_state);
} else {
register_ioport_write(addr, 8, 1, ide_ioport_write, ide_state);
register_ioport_read(addr, 8, 1, ide_ioport_read, ide_state);
/* data ports */
register_ioport_write(addr, 2, 2, ide_data_writew, ide_state);
register_ioport_read(addr, 2, 2, ide_data_readw, ide_state);
register_ioport_write(addr, 4, 4, ide_data_writel, ide_state);
register_ioport_read(addr, 4, 4, ide_data_readl, ide_state);
}
}
}
|
|
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
|
/* XXX: full callback usage to prepare non blocking I/Os support -
error handling */
static void ide_dma_loop(BMDMAState *bm)
{
struct {
uint32_t addr;
uint32_t size;
} prd;
target_phys_addr_t cur_addr;
int len, i, len1;
cur_addr = bm->addr;
/* at most one page to avoid hanging if erroneous parameters */
for(i = 0; i < 512; i++) {
cpu_physical_memory_read(cur_addr, (uint8_t *)&prd, 8);
prd.addr = le32_to_cpu(prd.addr);
prd.size = le32_to_cpu(prd.size);
#ifdef DEBUG_IDE
printf("ide: dma: prd: %08x: addr=0x%08x size=0x%08x\n",
(int)cur_addr, prd.addr, prd.size);
#endif
len = prd.size & 0xfffe;
if (len == 0)
len = 0x10000;
while (len > 0) {
len1 = bm->dma_cb(bm->ide_if, prd.addr, len);
if (len1 == 0)
goto the_end;
prd.addr += len1;
len -= len1;
}
/* end of transfer */
if (prd.size & 0x80000000)
break;
cur_addr += 8;
}
/* end of transfer */
the_end:
bm->status &= ~BM_STATUS_DMAING;
bm->status |= BM_STATUS_INT;
bm->dma_cb = NULL;
bm->ide_if = NULL;
}
static void ide_dma_start(IDEState *s, IDEDMAFunc *dma_cb)
{
BMDMAState *bm = s->bmdma;
if(!bm)
return;
bm->ide_if = s;
bm->dma_cb = dma_cb;
if (bm->status & BM_STATUS_DMAING) {
ide_dma_loop(bm);
}
}
static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
{
BMDMAState *bm = opaque;
#ifdef DEBUG_IDE
printf("%s: 0x%08x\n", __func__, val);
#endif
if (!(val & BM_CMD_START)) {
/* XXX: do it better */
bm->status &= ~BM_STATUS_DMAING;
bm->cmd = val & 0x09;
} else {
bm->status |= BM_STATUS_DMAING;
bm->cmd = val & 0x09;
/* start dma transfer if possible */
if (bm->dma_cb)
ide_dma_loop(bm);
}
}
|
|
2120
|
static uint32_t bmdma_readb(void *opaque, uint32_t addr)
|
|
2121
2122
|
{
BMDMAState *bm = opaque;
|
|
2123
|
PCIIDEState *pci_dev;
|
|
2124
|
uint32_t val;
|
|
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
|
switch(addr & 3) {
case 0:
val = bm->cmd;
break;
case 1:
pci_dev = bm->pci_dev;
if (pci_dev->type == IDE_TYPE_CMD646) {
val = pci_dev->dev.config[MRDMODE];
} else {
val = 0xff;
}
break;
case 2:
val = bm->status;
break;
case 3:
pci_dev = bm->pci_dev;
if (pci_dev->type == IDE_TYPE_CMD646) {
if (bm == &pci_dev->bmdma[0])
val = pci_dev->dev.config[UDIDETCR0];
else
val = pci_dev->dev.config[UDIDETCR1];
} else {
val = 0xff;
}
break;
default:
val = 0xff;
break;
}
|
|
2156
|
#ifdef DEBUG_IDE
|
|
2157
|
printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
|
|
2158
2159
2160
2161
|
#endif
return val;
}
|
|
2162
|
static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
|
|
2163
2164
|
{
BMDMAState *bm = opaque;
|
|
2165
|
PCIIDEState *pci_dev;
|
|
2166
|
#ifdef DEBUG_IDE
|
|
2167
|
printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
|
|
2168
|
#endif
|
|
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
|
switch(addr & 3) {
case 1:
pci_dev = bm->pci_dev;
if (pci_dev->type == IDE_TYPE_CMD646) {
pci_dev->dev.config[MRDMODE] =
(pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
cmd646_update_irq(pci_dev);
}
break;
case 2:
bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
break;
case 3:
pci_dev = bm->pci_dev;
if (pci_dev->type == IDE_TYPE_CMD646) {
if (bm == &pci_dev->bmdma[0])
pci_dev->dev.config[UDIDETCR0] = val;
else
pci_dev->dev.config[UDIDETCR1] = val;
}
break;
}
|
|
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
|
}
static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
{
BMDMAState *bm = opaque;
uint32_t val;
val = bm->addr;
#ifdef DEBUG_IDE
printf("%s: 0x%08x\n", __func__, val);
#endif
return val;
}
static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
{
BMDMAState *bm = opaque;
#ifdef DEBUG_IDE
printf("%s: 0x%08x\n", __func__, val);
#endif
bm->addr = val & ~3;
}
static void bmdma_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCIIDEState *d = (PCIIDEState *)pci_dev;
int i;
for(i = 0;i < 2; i++) {
BMDMAState *bm = &d->bmdma[i];
d->ide_if[2 * i].bmdma = bm;
d->ide_if[2 * i + 1].bmdma = bm;
|
|
2223
2224
|
bm->pci_dev = (PCIIDEState *)pci_dev;
|
|
2225
2226
|
register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
|
|
2227
2228
|
register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
register_ioport_read(addr, 4, 1, bmdma_readb, bm);
|
|
2229
2230
2231
2232
2233
2234
2235
|
register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
addr += 8;
}
}
|
|
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
|
/* XXX: call it also when the MRDMODE is changed from the PCI config
registers */
static void cmd646_update_irq(PCIIDEState *d)
{
int pci_level;
pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
pci_set_irq((PCIDevice *)d, 0, pci_level);
}
/* the PCI irq level is the logical OR of the two channels */
static void cmd646_set_irq(void *opaque, int channel, int level)
{
PCIIDEState *d = opaque;
int irq_mask;
irq_mask = MRDMODE_INTR_CH0 << channel;
if (level)
d->dev.config[MRDMODE] |= irq_mask;
else
d->dev.config[MRDMODE] &= ~irq_mask;
cmd646_update_irq(d);
}
/* CMD646 PCI IDE controller */
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
int secondary_ide_enabled)
|
|
2265
2266
2267
|
{
PCIIDEState *d;
uint8_t *pci_conf;
|
|
2268
2269
|
int i;
|
|
2270
2271
|
d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
sizeof(PCIIDEState),
|
|
2272
|
-1,
|
|
2273
|
NULL, NULL);
|
|
2274
|
d->type = IDE_TYPE_CMD646;
|
|
2275
|
pci_conf = d->dev.config;
|
|
2276
2277
2278
2279
2280
2281
2282
2283
|
pci_conf[0x00] = 0x95; // CMD646
pci_conf[0x01] = 0x10;
pci_conf[0x02] = 0x46;
pci_conf[0x03] = 0x06;
pci_conf[0x08] = 0x07; // IDE controller revision
pci_conf[0x09] = 0x8f;
|
|
2284
2285
|
pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
|
|
2286
2287
2288
2289
2290
2291
|
pci_conf[0x0e] = 0x00; // header_type
if (secondary_ide_enabled) {
/* XXX: if not enabled, really disable the seconday IDE controller */
pci_conf[0x51] = 0x80; /* enable IDE1 */
}
|
|
2292
2293
2294
2295
2296
2297
2298
2299
2300
|
pci_register_io_region((PCIDevice *)d, 0, 0x8,
PCI_ADDRESS_SPACE_IO, ide_map);
pci_register_io_region((PCIDevice *)d, 1, 0x4,
PCI_ADDRESS_SPACE_IO, ide_map);
pci_register_io_region((PCIDevice *)d, 2, 0x8,
PCI_ADDRESS_SPACE_IO, ide_map);
pci_register_io_region((PCIDevice *)d, 3, 0x4,
PCI_ADDRESS_SPACE_IO, ide_map);
|
|
2301
2302
|
pci_register_io_region((PCIDevice *)d, 4, 0x10,
PCI_ADDRESS_SPACE_IO, bmdma_map);
|
|
2303
|
|
|
2304
|
pci_conf[0x3d] = 0x01; // interrupt on pin 1
|
|
2305
|
|
|
2306
2307
|
for(i = 0; i < 4; i++)
d->ide_if[i].pci_dev = (PCIDevice *)d;
|
|
2308
2309
2310
2311
|
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
cmd646_set_irq, d, 0);
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
cmd646_set_irq, d, 1);
|
|
2312
2313
2314
2315
|
}
/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
|
|
2316
|
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table)
|
|
2317
2318
2319
2320
2321
|
{
PCIIDEState *d;
uint8_t *pci_conf;
/* register a function 1 of PIIX3 */
|
|
2322
2323
2324
|
d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
sizeof(PCIIDEState),
((PCIDevice *)piix3_state)->devfn + 1,
|
|
2325
|
NULL, NULL);
|
|
2326
2327
|
d->type = IDE_TYPE_PIIX3;
|
|
2328
2329
2330
2331
2332
|
pci_conf = d->dev.config;
pci_conf[0x00] = 0x86; // Intel
pci_conf[0x01] = 0x80;
pci_conf[0x02] = 0x10;
pci_conf[0x03] = 0x70;
|
|
2333
|
pci_conf[0x09] = 0x80; // legacy ATA mode
|
|
2334
2335
2336
2337
|
pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
pci_conf[0x0e] = 0x00; // header_type
|
|
2338
2339
|
pci_register_io_region((PCIDevice *)d, 4, 0x10,
PCI_ADDRESS_SPACE_IO, bmdma_map);
|
|
2340
|
|
|
2341
|
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
|
|
2342
|
pic_set_irq_new, isa_pic, 14);
|
|
2343
|
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
|
|
2344
|
pic_set_irq_new, isa_pic, 15);
|
|
2345
2346
|
ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
|
|
2347
|
}
|
|
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
|
/***********************************************************/
/* MacIO based PowerPC IDE */
/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
target_phys_addr_t addr, uint32_t val)
{
addr = (addr & 0xFFF) >> 4;
switch (addr) {
case 1 ... 7:
ide_ioport_write(opaque, addr, val);
break;
case 8:
case 22:
ide_cmd_write(opaque, 0, val);
break;
default:
break;
}
}
static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
{
uint8_t retval;
addr = (addr & 0xFFF) >> 4;
switch (addr) {
case 1 ... 7:
retval = ide_ioport_read(opaque, addr);
break;
case 8:
case 22:
retval = ide_status_read(opaque, 0);
break;
default:
retval = 0xFF;
break;
}
return retval;
}
static void pmac_ide_writew (void *opaque,
target_phys_addr_t addr, uint32_t val)
{
addr = (addr & 0xFFF) >> 4;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
#endif
if (addr == 0) {
ide_data_writew(opaque, 0, val);
}
}
static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
{
uint16_t retval;
addr = (addr & 0xFFF) >> 4;
if (addr == 0) {
retval = ide_data_readw(opaque, 0);
} else {
retval = 0xFFFF;
}
#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap16(retval);
#endif
return retval;
}
static void pmac_ide_writel (void *opaque,
target_phys_addr_t addr, uint32_t val)
{
addr = (addr & 0xFFF) >> 4;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
if (addr == 0) {
ide_data_writel(opaque, 0, val);
}
}
static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
{
uint32_t retval;
addr = (addr & 0xFFF) >> 4;
if (addr == 0) {
retval = ide_data_readl(opaque, 0);
} else {
retval = 0xFFFFFFFF;
}
#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap32(retval);
#endif
return retval;
}
static CPUWriteMemoryFunc *pmac_ide_write[] = {
pmac_ide_writeb,
pmac_ide_writew,
pmac_ide_writel,
};
static CPUReadMemoryFunc *pmac_ide_read[] = {
pmac_ide_readb,
pmac_ide_readw,
pmac_ide_readl,
};
/* hd_table must contain 4 block drivers */
/* PowerMac uses memory mapped registers, not I/O. Return the memory
I/O index to access the ide. */
int pmac_ide_init (BlockDriverState **hd_table,
|
|
2462
|
SetIRQFunc *set_irq, void *irq_opaque, int irq)
|
|
2463
2464
2465
2466
2467
|
{
IDEState *ide_if;
int pmac_ide_memory;
ide_if = qemu_mallocz(sizeof(IDEState) * 2);
|
|
2468
2469
|
ide_init2(&ide_if[0], hd_table[0], hd_table[1],
set_irq, irq_opaque, irq);
|
|
2470
2471
2472
2473
2474
|
pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
pmac_ide_write, &ide_if[0]);
return pmac_ide_memory;
}
|