|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
/*
* defines common to all virtual CPUs
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef CPU_ALL_H
#define CPU_ALL_H
|
|
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
|
#if defined(__arm__) || defined(__sparc__)
#define WORDS_ALIGNED
#endif
/* some important defines:
*
* WORDS_ALIGNED : if defined, the host cpu can only make word aligned
* memory accesses.
*
* WORDS_BIGENDIAN : if defined, the host cpu is big endian and
* otherwise little endian.
*
* (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
*
* TARGET_WORDS_BIGENDIAN : same for target cpu
*/
|
|
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
|
#include "bswap.h"
#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
#define BSWAP_NEEDED
#endif
#ifdef BSWAP_NEEDED
static inline uint16_t tswap16(uint16_t s)
{
return bswap16(s);
}
static inline uint32_t tswap32(uint32_t s)
{
return bswap32(s);
}
static inline uint64_t tswap64(uint64_t s)
{
return bswap64(s);
}
static inline void tswap16s(uint16_t *s)
{
*s = bswap16(*s);
}
static inline void tswap32s(uint32_t *s)
{
*s = bswap32(*s);
}
static inline void tswap64s(uint64_t *s)
{
*s = bswap64(*s);
}
#else
static inline uint16_t tswap16(uint16_t s)
{
return s;
}
static inline uint32_t tswap32(uint32_t s)
{
return s;
}
static inline uint64_t tswap64(uint64_t s)
{
return s;
}
static inline void tswap16s(uint16_t *s)
{
}
static inline void tswap32s(uint32_t *s)
{
}
static inline void tswap64s(uint64_t *s)
{
}
#endif
#if TARGET_LONG_SIZE == 4
#define tswapl(s) tswap32(s)
#define tswapls(s) tswap32s((uint32_t *)(s))
|
|
112
|
#define bswaptls(s) bswap32s(s)
|
|
113
114
115
|
#else
#define tswapl(s) tswap64(s)
#define tswapls(s) tswap64s((uint64_t *)(s))
|
|
116
|
#define bswaptls(s) bswap64s(s)
|
|
117
118
|
#endif
|
|
119
120
|
/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
endian ! */
|
|
121
|
typedef union {
|
|
122
|
float64 d;
|
|
123
124
|
#if defined(WORDS_BIGENDIAN) \
|| (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
|
|
125
126
|
struct {
uint32_t upper;
|
|
127
|
uint32_t lower;
|
|
128
129
130
131
|
} l;
#else
struct {
uint32_t lower;
|
|
132
|
uint32_t upper;
|
|
133
134
135
136
137
|
} l;
#endif
uint64_t ll;
} CPU_DoubleU;
|
|
138
139
|
/* CPU memory access without any memory or io remapping */
|
|
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
|
/*
* the generic syntax for the memory accesses is:
*
* load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
*
* store: st{type}{size}{endian}_{access_type}(ptr, val)
*
* type is:
* (empty): integer access
* f : float access
*
* sign is:
* (empty): for floats or 32 bit size
* u : unsigned
* s : signed
*
* size is:
* b: 8 bits
* w: 16 bits
* l: 32 bits
* q: 64 bits
*
* endian is:
* (empty): target cpu endianness or 8 bit access
* r : reversed target cpu endianness (not implemented yet)
* be : big endian (not implemented yet)
* le : little endian (not implemented yet)
*
* access_type is:
* raw : host memory access
* user : user mode access using soft MMU
* kernel : kernel mode access using soft MMU
*/
|
|
173
|
static inline int ldub_p(void *ptr)
|
|
174
175
176
177
|
{
return *(uint8_t *)ptr;
}
|
|
178
|
static inline int ldsb_p(void *ptr)
|
|
179
180
181
182
|
{
return *(int8_t *)ptr;
}
|
|
183
|
static inline void stb_p(void *ptr, int v)
|
|
184
185
186
187
188
189
190
|
{
*(uint8_t *)ptr = v;
}
/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
kernel handles unaligned load/stores may give better results, but
it is a system wide setting : bad */
|
|
191
|
#if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
|
|
192
193
|
/* conservative code for little endian unaligned accesses */
|
|
194
|
static inline int lduw_le_p(void *ptr)
|
|
195
196
197
198
199
200
201
202
203
204
205
|
{
#ifdef __powerpc__
int val;
__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
return val;
#else
uint8_t *p = ptr;
return p[0] | (p[1] << 8);
#endif
}
|
|
206
|
static inline int ldsw_le_p(void *ptr)
|
|
207
208
209
210
211
212
213
214
215
216
217
|
{
#ifdef __powerpc__
int val;
__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
return (int16_t)val;
#else
uint8_t *p = ptr;
return (int16_t)(p[0] | (p[1] << 8));
#endif
}
|
|
218
|
static inline int ldl_le_p(void *ptr)
|
|
219
220
221
222
223
224
225
226
227
228
229
|
{
#ifdef __powerpc__
int val;
__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
return val;
#else
uint8_t *p = ptr;
return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
#endif
}
|
|
230
|
static inline uint64_t ldq_le_p(void *ptr)
|
|
231
232
233
|
{
uint8_t *p = ptr;
uint32_t v1, v2;
|
|
234
235
|
v1 = ldl_le_p(p);
v2 = ldl_le_p(p + 4);
|
|
236
237
238
|
return v1 | ((uint64_t)v2 << 32);
}
|
|
239
|
static inline void stw_le_p(void *ptr, int v)
|
|
240
241
242
243
244
245
246
247
248
249
|
{
#ifdef __powerpc__
__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
#else
uint8_t *p = ptr;
p[0] = v;
p[1] = v >> 8;
#endif
}
|
|
250
|
static inline void stl_le_p(void *ptr, int v)
|
|
251
252
253
254
255
256
257
258
259
260
261
262
|
{
#ifdef __powerpc__
__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
#else
uint8_t *p = ptr;
p[0] = v;
p[1] = v >> 8;
p[2] = v >> 16;
p[3] = v >> 24;
#endif
}
|
|
263
|
static inline void stq_le_p(void *ptr, uint64_t v)
|
|
264
265
|
{
uint8_t *p = ptr;
|
|
266
267
|
stl_le_p(p, (uint32_t)v);
stl_le_p(p + 4, v >> 32);
|
|
268
269
270
271
|
}
/* float access */
|
|
272
|
static inline float32 ldfl_le_p(void *ptr)
|
|
273
274
|
{
union {
|
|
275
|
float32 f;
|
|
276
277
|
uint32_t i;
} u;
|
|
278
|
u.i = ldl_le_p(ptr);
|
|
279
280
281
|
return u.f;
}
|
|
282
|
static inline void stfl_le_p(void *ptr, float32 v)
|
|
283
284
|
{
union {
|
|
285
|
float32 f;
|
|
286
287
288
|
uint32_t i;
} u;
u.f = v;
|
|
289
|
stl_le_p(ptr, u.i);
|
|
290
291
|
}
|
|
292
|
static inline float64 ldfq_le_p(void *ptr)
|
|
293
|
{
|
|
294
|
CPU_DoubleU u;
|
|
295
296
|
u.l.lower = ldl_le_p(ptr);
u.l.upper = ldl_le_p(ptr + 4);
|
|
297
298
299
|
return u.d;
}
|
|
300
|
static inline void stfq_le_p(void *ptr, float64 v)
|
|
301
|
{
|
|
302
|
CPU_DoubleU u;
|
|
303
|
u.d = v;
|
|
304
305
|
stl_le_p(ptr, u.l.lower);
stl_le_p(ptr + 4, u.l.upper);
|
|
306
307
|
}
|
|
308
309
310
311
312
313
314
315
316
317
318
|
#else
static inline int lduw_le_p(void *ptr)
{
return *(uint16_t *)ptr;
}
static inline int ldsw_le_p(void *ptr)
{
return *(int16_t *)ptr;
}
|
|
319
|
|
|
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
|
static inline int ldl_le_p(void *ptr)
{
return *(uint32_t *)ptr;
}
static inline uint64_t ldq_le_p(void *ptr)
{
return *(uint64_t *)ptr;
}
static inline void stw_le_p(void *ptr, int v)
{
*(uint16_t *)ptr = v;
}
static inline void stl_le_p(void *ptr, int v)
{
*(uint32_t *)ptr = v;
}
static inline void stq_le_p(void *ptr, uint64_t v)
{
*(uint64_t *)ptr = v;
}
/* float access */
static inline float32 ldfl_le_p(void *ptr)
{
return *(float32 *)ptr;
}
static inline float64 ldfq_le_p(void *ptr)
{
return *(float64 *)ptr;
}
static inline void stfl_le_p(void *ptr, float32 v)
{
*(float32 *)ptr = v;
}
static inline void stfq_le_p(void *ptr, float64 v)
{
*(float64 *)ptr = v;
}
#endif
#if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
static inline int lduw_be_p(void *ptr)
|
|
371
|
{
|
|
372
373
374
375
376
377
378
379
|
#if defined(__i386__)
int val;
asm volatile ("movzwl %1, %0\n"
"xchgb %b0, %h0\n"
: "=q" (val)
: "m" (*(uint16_t *)ptr));
return val;
#else
|
|
380
|
uint8_t *b = (uint8_t *) ptr;
|
|
381
382
|
return ((b[0] << 8) | b[1]);
#endif
|
|
383
384
|
}
|
|
385
|
static inline int ldsw_be_p(void *ptr)
|
|
386
|
{
|
|
387
388
389
390
391
392
393
394
395
396
397
|
#if defined(__i386__)
int val;
asm volatile ("movzwl %1, %0\n"
"xchgb %b0, %h0\n"
: "=q" (val)
: "m" (*(uint16_t *)ptr));
return (int16_t)val;
#else
uint8_t *b = (uint8_t *) ptr;
return (int16_t)((b[0] << 8) | b[1]);
#endif
|
|
398
399
|
}
|
|
400
|
static inline int ldl_be_p(void *ptr)
|
|
401
|
{
|
|
402
|
#if defined(__i386__) || defined(__x86_64__)
|
|
403
404
405
406
407
408
409
|
int val;
asm volatile ("movl %1, %0\n"
"bswap %0\n"
: "=r" (val)
: "m" (*(uint32_t *)ptr));
return val;
#else
|
|
410
|
uint8_t *b = (uint8_t *) ptr;
|
|
411
412
|
return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
#endif
|
|
413
414
|
}
|
|
415
|
static inline uint64_t ldq_be_p(void *ptr)
|
|
416
417
|
{
uint32_t a,b;
|
|
418
419
|
a = ldl_be_p(ptr);
b = ldl_be_p(ptr+4);
|
|
420
421
422
|
return (((uint64_t)a<<32)|b);
}
|
|
423
|
static inline void stw_be_p(void *ptr, int v)
|
|
424
|
{
|
|
425
426
427
428
429
430
|
#if defined(__i386__)
asm volatile ("xchgb %b0, %h0\n"
"movw %w0, %1\n"
: "=q" (v)
: "m" (*(uint16_t *)ptr), "0" (v));
#else
|
|
431
432
433
|
uint8_t *d = (uint8_t *) ptr;
d[0] = v >> 8;
d[1] = v;
|
|
434
|
#endif
|
|
435
436
|
}
|
|
437
|
static inline void stl_be_p(void *ptr, int v)
|
|
438
|
{
|
|
439
|
#if defined(__i386__) || defined(__x86_64__)
|
|
440
441
442
443
444
|
asm volatile ("bswap %0\n"
"movl %0, %1\n"
: "=r" (v)
: "m" (*(uint32_t *)ptr), "0" (v));
#else
|
|
445
446
447
448
449
|
uint8_t *d = (uint8_t *) ptr;
d[0] = v >> 24;
d[1] = v >> 16;
d[2] = v >> 8;
d[3] = v;
|
|
450
|
#endif
|
|
451
452
|
}
|
|
453
|
static inline void stq_be_p(void *ptr, uint64_t v)
|
|
454
|
{
|
|
455
456
|
stl_be_p(ptr, v >> 32);
stl_be_p(ptr + 4, v);
|
|
457
458
459
460
|
}
/* float access */
|
|
461
|
static inline float32 ldfl_be_p(void *ptr)
|
|
462
463
|
{
union {
|
|
464
|
float32 f;
|
|
465
466
|
uint32_t i;
} u;
|
|
467
|
u.i = ldl_be_p(ptr);
|
|
468
469
470
|
return u.f;
}
|
|
471
|
static inline void stfl_be_p(void *ptr, float32 v)
|
|
472
473
|
{
union {
|
|
474
|
float32 f;
|
|
475
476
477
|
uint32_t i;
} u;
u.f = v;
|
|
478
|
stl_be_p(ptr, u.i);
|
|
479
480
|
}
|
|
481
|
static inline float64 ldfq_be_p(void *ptr)
|
|
482
483
|
{
CPU_DoubleU u;
|
|
484
485
|
u.l.upper = ldl_be_p(ptr);
u.l.lower = ldl_be_p(ptr + 4);
|
|
486
487
488
|
return u.d;
}
|
|
489
|
static inline void stfq_be_p(void *ptr, float64 v)
|
|
490
491
492
|
{
CPU_DoubleU u;
u.d = v;
|
|
493
494
|
stl_be_p(ptr, u.l.upper);
stl_be_p(ptr + 4, u.l.lower);
|
|
495
496
|
}
|
|
497
498
|
#else
|
|
499
|
static inline int lduw_be_p(void *ptr)
|
|
500
501
502
503
|
{
return *(uint16_t *)ptr;
}
|
|
504
|
static inline int ldsw_be_p(void *ptr)
|
|
505
506
507
508
|
{
return *(int16_t *)ptr;
}
|
|
509
|
static inline int ldl_be_p(void *ptr)
|
|
510
511
512
513
|
{
return *(uint32_t *)ptr;
}
|
|
514
|
static inline uint64_t ldq_be_p(void *ptr)
|
|
515
516
517
518
|
{
return *(uint64_t *)ptr;
}
|
|
519
|
static inline void stw_be_p(void *ptr, int v)
|
|
520
521
522
523
|
{
*(uint16_t *)ptr = v;
}
|
|
524
|
static inline void stl_be_p(void *ptr, int v)
|
|
525
526
527
528
|
{
*(uint32_t *)ptr = v;
}
|
|
529
|
static inline void stq_be_p(void *ptr, uint64_t v)
|
|
530
531
532
533
534
535
|
{
*(uint64_t *)ptr = v;
}
/* float access */
|
|
536
|
static inline float32 ldfl_be_p(void *ptr)
|
|
537
|
{
|
|
538
|
return *(float32 *)ptr;
|
|
539
540
|
}
|
|
541
|
static inline float64 ldfq_be_p(void *ptr)
|
|
542
|
{
|
|
543
|
return *(float64 *)ptr;
|
|
544
545
|
}
|
|
546
|
static inline void stfl_be_p(void *ptr, float32 v)
|
|
547
|
{
|
|
548
|
*(float32 *)ptr = v;
|
|
549
550
|
}
|
|
551
|
static inline void stfq_be_p(void *ptr, float64 v)
|
|
552
|
{
|
|
553
|
*(float64 *)ptr = v;
|
|
554
|
}
|
|
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
|
#endif
/* target CPU memory access functions */
#if defined(TARGET_WORDS_BIGENDIAN)
#define lduw_p(p) lduw_be_p(p)
#define ldsw_p(p) ldsw_be_p(p)
#define ldl_p(p) ldl_be_p(p)
#define ldq_p(p) ldq_be_p(p)
#define ldfl_p(p) ldfl_be_p(p)
#define ldfq_p(p) ldfq_be_p(p)
#define stw_p(p, v) stw_be_p(p, v)
#define stl_p(p, v) stl_be_p(p, v)
#define stq_p(p, v) stq_be_p(p, v)
#define stfl_p(p, v) stfl_be_p(p, v)
#define stfq_p(p, v) stfq_be_p(p, v)
#else
#define lduw_p(p) lduw_le_p(p)
#define ldsw_p(p) ldsw_le_p(p)
#define ldl_p(p) ldl_le_p(p)
#define ldq_p(p) ldq_le_p(p)
#define ldfl_p(p) ldfl_le_p(p)
#define ldfq_p(p) ldfq_le_p(p)
#define stw_p(p, v) stw_le_p(p, v)
#define stl_p(p, v) stl_le_p(p, v)
#define stq_p(p, v) stq_le_p(p, v)
#define stfl_p(p, v) stfl_le_p(p, v)
#define stfq_p(p, v) stfq_le_p(p, v)
|
|
583
584
|
#endif
|
|
585
586
|
/* MMU memory access macros */
|
|
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
|
/* NOTE: we use double casts if pointers and target_ulong have
different sizes */
#define ldub_raw(p) ldub_p((uint8_t *)(long)(p))
#define ldsb_raw(p) ldsb_p((uint8_t *)(long)(p))
#define lduw_raw(p) lduw_p((uint8_t *)(long)(p))
#define ldsw_raw(p) ldsw_p((uint8_t *)(long)(p))
#define ldl_raw(p) ldl_p((uint8_t *)(long)(p))
#define ldq_raw(p) ldq_p((uint8_t *)(long)(p))
#define ldfl_raw(p) ldfl_p((uint8_t *)(long)(p))
#define ldfq_raw(p) ldfq_p((uint8_t *)(long)(p))
#define stb_raw(p, v) stb_p((uint8_t *)(long)(p), v)
#define stw_raw(p, v) stw_p((uint8_t *)(long)(p), v)
#define stl_raw(p, v) stl_p((uint8_t *)(long)(p), v)
#define stq_raw(p, v) stq_p((uint8_t *)(long)(p), v)
#define stfl_raw(p, v) stfl_p((uint8_t *)(long)(p), v)
#define stfq_raw(p, v) stfq_p((uint8_t *)(long)(p), v)
|
|
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
|
#if defined(CONFIG_USER_ONLY)
/* if user mode, no other memory access functions */
#define ldub(p) ldub_raw(p)
#define ldsb(p) ldsb_raw(p)
#define lduw(p) lduw_raw(p)
#define ldsw(p) ldsw_raw(p)
#define ldl(p) ldl_raw(p)
#define ldq(p) ldq_raw(p)
#define ldfl(p) ldfl_raw(p)
#define ldfq(p) ldfq_raw(p)
#define stb(p, v) stb_raw(p, v)
#define stw(p, v) stw_raw(p, v)
#define stl(p, v) stl_raw(p, v)
#define stq(p, v) stq_raw(p, v)
#define stfl(p, v) stfl_raw(p, v)
#define stfq(p, v) stfq_raw(p, v)
#define ldub_code(p) ldub_raw(p)
#define ldsb_code(p) ldsb_raw(p)
#define lduw_code(p) lduw_raw(p)
#define ldsw_code(p) ldsw_raw(p)
#define ldl_code(p) ldl_raw(p)
#define ldub_kernel(p) ldub_raw(p)
#define ldsb_kernel(p) ldsb_raw(p)
#define lduw_kernel(p) lduw_raw(p)
#define ldsw_kernel(p) ldsw_raw(p)
#define ldl_kernel(p) ldl_raw(p)
|
|
634
635
|
#define ldfl_kernel(p) ldfl_raw(p)
#define ldfq_kernel(p) ldfq_raw(p)
|
|
636
637
638
639
|
#define stb_kernel(p, v) stb_raw(p, v)
#define stw_kernel(p, v) stw_raw(p, v)
#define stl_kernel(p, v) stl_raw(p, v)
#define stq_kernel(p, v) stq_raw(p, v)
|
|
640
641
|
#define stfl_kernel(p, v) stfl_raw(p, v)
#define stfq_kernel(p, vt) stfq_raw(p, v)
|
|
642
643
644
|
#endif /* defined(CONFIG_USER_ONLY) */
|
|
645
646
647
648
649
650
|
/* page related stuff */
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
|
|
651
652
653
654
|
extern unsigned long qemu_real_host_page_size;
extern unsigned long qemu_host_page_bits;
extern unsigned long qemu_host_page_size;
extern unsigned long qemu_host_page_mask;
|
|
655
|
|
|
656
|
#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
|
|
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
|
/* same as PROT_xxx */
#define PAGE_READ 0x0001
#define PAGE_WRITE 0x0002
#define PAGE_EXEC 0x0004
#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
#define PAGE_VALID 0x0008
/* original state of the write flag (used when tracking self-modifying
code */
#define PAGE_WRITE_ORG 0x0010
void page_dump(FILE *f);
int page_get_flags(unsigned long address);
void page_set_flags(unsigned long start, unsigned long end, int flags);
void page_unprotect_range(uint8_t *data, unsigned long data_size);
#define SINGLE_CPU_DEFINES
#ifdef SINGLE_CPU_DEFINES
#if defined(TARGET_I386)
#define CPUState CPUX86State
#define cpu_init cpu_x86_init
#define cpu_exec cpu_x86_exec
#define cpu_gen_code cpu_x86_gen_code
#define cpu_signal_handler cpu_x86_signal_handler
#elif defined(TARGET_ARM)
#define CPUState CPUARMState
#define cpu_init cpu_arm_init
#define cpu_exec cpu_arm_exec
#define cpu_gen_code cpu_arm_gen_code
#define cpu_signal_handler cpu_arm_signal_handler
|
|
692
693
694
695
696
697
698
699
|
#elif defined(TARGET_SPARC)
#define CPUState CPUSPARCState
#define cpu_init cpu_sparc_init
#define cpu_exec cpu_sparc_exec
#define cpu_gen_code cpu_sparc_gen_code
#define cpu_signal_handler cpu_sparc_signal_handler
|
|
700
701
702
703
704
705
706
707
|
#elif defined(TARGET_PPC)
#define CPUState CPUPPCState
#define cpu_init cpu_ppc_init
#define cpu_exec cpu_ppc_exec
#define cpu_gen_code cpu_ppc_gen_code
#define cpu_signal_handler cpu_ppc_signal_handler
|
|
708
709
710
711
712
713
714
|
#elif defined(TARGET_MIPS)
#define CPUState CPUMIPSState
#define cpu_init cpu_mips_init
#define cpu_exec cpu_mips_exec
#define cpu_gen_code cpu_mips_gen_code
#define cpu_signal_handler cpu_mips_signal_handler
|
|
715
716
717
718
719
720
|
#else
#error unsupported target CPU
#endif
|
|
721
722
|
#endif /* SINGLE_CPU_DEFINES */
|
|
723
724
725
726
|
void cpu_dump_state(CPUState *env, FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
int flags);
|
|
727
|
void cpu_abort(CPUState *env, const char *fmt, ...);
|
|
728
|
extern CPUState *first_cpu;
|
|
729
|
extern CPUState *cpu_single_env;
|
|
730
|
extern int code_copy_enabled;
|
|
731
|
|
|
732
733
734
|
#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
|
|
735
|
#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
|
|
736
737
|
#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
|
|
738
|
void cpu_interrupt(CPUState *s, int mask);
|
|
739
|
void cpu_reset_interrupt(CPUState *env, int mask);
|
|
740
|
|
|
741
742
|
int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
|
|
743
|
void cpu_single_step(CPUState *env, int enabled);
|
|
744
|
void cpu_reset(CPUState *s);
|
|
745
|
|
|
746
747
748
749
750
|
/* Return the physical page corresponding to a virtual one. Use it
only for debugging because no protection checks are done. Return -1
if no page found. */
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
|
|
751
752
|
#define CPU_LOG_TB_OUT_ASM (1 << 0)
#define CPU_LOG_TB_IN_ASM (1 << 1)
|
|
753
754
755
756
757
|
#define CPU_LOG_TB_OP (1 << 2)
#define CPU_LOG_TB_OP_OPT (1 << 3)
#define CPU_LOG_INT (1 << 4)
#define CPU_LOG_EXEC (1 << 5)
#define CPU_LOG_PCALL (1 << 6)
|
|
758
|
#define CPU_LOG_IOPORT (1 << 7)
|
|
759
|
#define CPU_LOG_TB_CPU (1 << 8)
|
|
760
761
762
763
764
765
766
767
768
769
|
/* define log items */
typedef struct CPULogItem {
int mask;
const char *name;
const char *help;
} CPULogItem;
extern CPULogItem cpu_log_items[];
|
|
770
771
|
void cpu_set_log(int log_flags);
void cpu_set_log_filename(const char *filename);
|
|
772
|
int cpu_str_to_log_mask(const char *str);
|
|
773
|
|
|
774
775
776
777
778
779
780
781
782
783
784
785
786
|
/* IO ports API */
/* NOTE: as these functions may be even used when there is an isa
brige on non x86 targets, we always defined them */
#ifndef NO_CPU_IO_DEFS
void cpu_outb(CPUState *env, int addr, int val);
void cpu_outw(CPUState *env, int addr, int val);
void cpu_outl(CPUState *env, int addr, int val);
int cpu_inb(CPUState *env, int addr);
int cpu_inw(CPUState *env, int addr);
int cpu_inl(CPUState *env, int addr);
#endif
|
|
787
788
|
/* memory API */
|
|
789
790
791
|
extern int phys_ram_size;
extern int phys_ram_fd;
extern uint8_t *phys_ram_base;
|
|
792
|
extern uint8_t *phys_ram_dirty;
|
|
793
794
795
796
|
/* physical memory access */
#define TLB_INVALID_MASK (1 << 3)
#define IO_MEM_SHIFT 4
|
|
797
|
#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
|
|
798
799
800
801
|
#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
|
|
802
|
#define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
|
|
803
|
|
|
804
805
|
typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
|
|
806
|
|
|
807
808
809
|
void cpu_register_physical_memory(target_phys_addr_t start_addr,
unsigned long size,
unsigned long phys_offset);
|
|
810
811
|
int cpu_register_io_memory(int io_index,
CPUReadMemoryFunc **mem_read,
|
|
812
813
|
CPUWriteMemoryFunc **mem_write,
void *opaque);
|
|
814
815
|
CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
|
|
816
|
|
|
817
|
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
|
|
818
|
int len, int is_write);
|
|
819
820
|
static inline void cpu_physical_memory_read(target_phys_addr_t addr,
uint8_t *buf, int len)
|
|
821
822
823
|
{
cpu_physical_memory_rw(addr, buf, len, 0);
}
|
|
824
825
|
static inline void cpu_physical_memory_write(target_phys_addr_t addr,
const uint8_t *buf, int len)
|
|
826
827
828
|
{
cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
}
|
|
829
830
|
uint32_t ldub_phys(target_phys_addr_t addr);
uint32_t lduw_phys(target_phys_addr_t addr);
|
|
831
|
uint32_t ldl_phys(target_phys_addr_t addr);
|
|
832
|
uint64_t ldq_phys(target_phys_addr_t addr);
|
|
833
|
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
|
|
834
835
|
void stb_phys(target_phys_addr_t addr, uint32_t val);
void stw_phys(target_phys_addr_t addr, uint32_t val);
|
|
836
|
void stl_phys(target_phys_addr_t addr, uint32_t val);
|
|
837
|
void stq_phys(target_phys_addr_t addr, uint64_t val);
|
|
838
839
840
|
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
uint8_t *buf, int len, int is_write);
|
|
841
|
|
|
842
843
|
#define VGA_DIRTY_FLAG 0x01
#define CODE_DIRTY_FLAG 0x02
|
|
844
|
|
|
845
|
/* read dirty bit (return 0 or 1) */
|
|
846
|
static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
|
|
847
|
{
|
|
848
849
850
|
return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
}
|
|
851
|
static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
|
|
852
853
854
|
int dirty_flags)
{
return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
|
|
855
856
|
}
|
|
857
|
static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
|
|
858
|
{
|
|
859
|
phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
|
|
860
861
|
}
|
|
862
|
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
|
|
863
|
int dirty_flags);
|
|
864
|
void cpu_tlb_update_dirty(CPUState *env);
|
|
865
|
|
|
866
867
868
|
void dump_exec_info(FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
|
|
869
|
#endif /* CPU_ALL_H */
|