gwj / at91sam9263 · Commits

  • sh4: fix tas.b @Rn instruction ...
    825c69ce 
    (Shin-ichiro KAWASAKI, based on a patch from Andrzej Zaborowski)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5074 c046a42c-6fe2-441c-8c8c-71466251a162
    aurel32 authored
     
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  • [sh4] code translation bug fix ...
    7da76bce 
    When a TLB miss occurs while pre-decrement store instruction such as
"mov.l Rm, @-Rn" is executed, re-execution of such instruction cause
status confusion. Because pre Rn decrement is executed before TLB miss,
re-execution decrements Rn again.
In other words, in a translated instruction array, register status
should not modified before memory access instruction.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5069 c046a42c-6fe2-441c-8c8c-71466251a162
    aurel32 authored
     
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  • [sh4] MMU bug fix ...
    06afe2c8 
    Some bugs on SH4 MMU are fixed.

- When a TLB entry is overwritten or invalidated, tlb_flush_page() should be
  invoked to invalidate old entry.
- When a ASID is changed, tlb_flush() should be invoke to invalidate entries
  which have old ASID.
- The check for shared bit in TLB entry causes multiple TLB hit exception.
  As SH3's MMU, shared bit is ignored.
- ASID is used when MMUCR's SV bit or SR's MD bit is zero.
  No need to check both bits are zero.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5068 c046a42c-6fe2-441c-8c8c-71466251a162
    aurel32 authored
     
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  • [sh4] memory mapped TLB entries ...
    29e179bc 
    SH4 MMU's memory mapped TLB feature is implemented.
SH-Linux seems to write to memory mapped TLB to invalidate a TLB entry,
but does not to read it. So only memory write feature is implemented.
Work on memory read feature is left.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5067 c046a42c-6fe2-441c-8c8c-71466251a162
    aurel32 authored
     
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  • [sh4] delay slot bug fix ...
    274a9e70 
    Two bugs about delay slot handlings are fixed.

- After an exception occurred in delay slot, the branch instruction
  before delay slot should be executed again. To judge such re-execution
  is necessery or not, delay slot status is kept in SH4 CPU data structure.
- When a branch instruction is placed at the end of memory segment,
  the delay slot is placed at the start of next memory segment.
  It means delay slot comes to the start of a translation block.
  In such occasion, DELAY_SLOT_CLAREME flag is used to transmit status
  between translation blocks. When an exception occurs on this kind of
  delay slot, DELAY_SLOT_CLEARME flag cause a status confusion in exception
  handling. DELAY_SLOT_CLEARME flag should be cleared on exceptions.

And some items are added to CPU status dump.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5066 c046a42c-6fe2-441c-8c8c-71466251a162
    aurel32 authored
     
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  • [sh4] sleep instruction ...
    833ed386 
    This patch adds sleep instruction.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5065 c046a42c-6fe2-441c-8c8c-71466251a162
    aurel32 authored
     
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  • SH4, fix several instructions ...
    24988dc2 
    fix instruction code for frchg, fschg, ocbp.
fix addressing mode handling for @Rn+, @-Rn, @(disp,gbr).
fix operation for div0s.
fix comments for mov imm, add imm, @(r0+,gbr), mac.l @Rm+,@Rn+.
fix ldb to ldub for or/tst/xor.b #imm,@(r0,gbr).
add fmov extended operations.
add fcmp/eq, fcmp/gt, fneg, fabs, fsqrt, fcnvsd, fcnvds.

(Takashi Yoshii)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4040 c046a42c-6fe2-441c-8c8c-71466251a162
    aurel32 authored
     
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  • Replace is_user variable with mmu_idx in softmmu core, ...
    6ebbf390 
    allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
  and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
  hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
  and using the same definition in code translation code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
    j_mayer authored
     
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