• The dump output was not nicely formatted for bytes
    larger than 0x7f, because signed values expanded to
    sizeof(int) bytes. So for example 0xab did not print
    as "ab", but as "ffffffab".
    
    I also cleaned the function prototype, which avoids
    new type casts and allows to remove an existing
    type cast.
    
    Signed-off-by: Stefan Weil <weil@mail.berlios.de>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Stefan Weil authored
     
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  • Add an option to specify the number of MSI-X vectors for PCI NIC cards. This
    can also be used to disable MSI-X, for compatibility with old qemu. This
    option currently only affects virtio cards.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • Request up to 3 vectors in virtio-net. Actual bindings might supply
    less.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • Add pci_get/set_byte to keep *_word and *_long access functions company.
    They are unused for now.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • Implement bindings for virtio save/load. Use them in virtio pci.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • This enables actual support for MSI-X in virtio PCI.
    First user will be virtio-net.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • Extend virtio to support many interrupt vectors, and rearrange code in
    preparation for multi-vector support (mostly move reset out to bindings,
    because we will have to reset the vectors in transport-specific code).
    Actual bindings in pci, and use in net, to follow.
    Load and save are not connected to bindings yet, so they are left
    stubbed out for now.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • Implement MSI support in APIC. Note that MSI and MMIO APIC registers
    are at the same memory location, but actually not on the global bus: MSI
    is on PCI bus, APIC is connected directly to the CPU. We map them on the
    global bus at the same address which happens to work because MSI
    registers are reserved in APIC MMIO and vice versa.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • Add functions implementing MSI-X support. First user will be virtio-pci.
    Note that platform must set a flag to declare MSI supported: this
    is a safety measure to avoid breaking platforms which should support
    MSI-X but currently lack this in the interrupt controller emulation.
    For PC this will be set by APIC.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • Add "cmask" table of constant register masks: if a bit is not writeable
    and is set in cmask table, this bit is checked on load.  An attempt to
    load an image that would change such a register causes load to fail.
    Use this table to make sure that load does not modify registers that
    guest can not change (directly or indirectly).
    
    Note: we can't just assume that read-only registers never change,
    because the guest could change a register indirectly.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • Add routines to manage PCI capability list. First user will be MSI-X.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • Add inline routines for convenient access to pci devices
    with correct (little) endianness. Will be used by MSI-X support.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • Change much of hw/pci to use symbolic constants and a table-driven
    design: add a mask table with writable bits set and readonly bits unset.
    Detect change by comparing original and new registers.
    
    This makes it easy to support capabilities where read-only/writeable
    bit layout differs between devices, depending on capabilities present.
    
    As a result, writing a single byte in BAR registers now works as
    it should. Writing to upper limit registers in the bridge
    also works as it should. Code is also shorter.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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