Commit ff8ef2a8613fad811e75d16a3570a8e8ea4b0655
1 parent
98daeaf6
Get rid of gen_set_psr_T0 and replace it by gen_set_psr/gen_set_psr_im.
Signed-off-by: Filip Navara <filip.navara@gmail.com>
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1 changed file
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24 additions
and
20 deletions
target-arm/translate.c
@@ -3418,8 +3418,8 @@ static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) { | @@ -3418,8 +3418,8 @@ static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) { | ||
3418 | return mask; | 3418 | return mask; |
3419 | } | 3419 | } |
3420 | 3420 | ||
3421 | -/* Returns nonzero if access to the PSR is not permitted. */ | ||
3422 | -static int gen_set_psr_T0(DisasContext *s, uint32_t mask, int spsr) | 3421 | +/* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */ |
3422 | +static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0) | ||
3423 | { | 3423 | { |
3424 | TCGv tmp; | 3424 | TCGv tmp; |
3425 | if (spsr) { | 3425 | if (spsr) { |
@@ -3429,16 +3429,26 @@ static int gen_set_psr_T0(DisasContext *s, uint32_t mask, int spsr) | @@ -3429,16 +3429,26 @@ static int gen_set_psr_T0(DisasContext *s, uint32_t mask, int spsr) | ||
3429 | 3429 | ||
3430 | tmp = load_cpu_field(spsr); | 3430 | tmp = load_cpu_field(spsr); |
3431 | tcg_gen_andi_i32(tmp, tmp, ~mask); | 3431 | tcg_gen_andi_i32(tmp, tmp, ~mask); |
3432 | - tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask); | ||
3433 | - tcg_gen_or_i32(tmp, tmp, cpu_T[0]); | 3432 | + tcg_gen_andi_i32(t0, t0, mask); |
3433 | + tcg_gen_or_i32(tmp, tmp, t0); | ||
3434 | store_cpu_field(tmp, spsr); | 3434 | store_cpu_field(tmp, spsr); |
3435 | } else { | 3435 | } else { |
3436 | - gen_set_cpsr(cpu_T[0], mask); | 3436 | + gen_set_cpsr(t0, mask); |
3437 | } | 3437 | } |
3438 | + dead_tmp(t0); | ||
3438 | gen_lookup_tb(s); | 3439 | gen_lookup_tb(s); |
3439 | return 0; | 3440 | return 0; |
3440 | } | 3441 | } |
3441 | 3442 | ||
3443 | +/* Returns nonzero if access to the PSR is not permitted. */ | ||
3444 | +static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val) | ||
3445 | +{ | ||
3446 | + TCGv tmp; | ||
3447 | + tmp = new_tmp(); | ||
3448 | + tcg_gen_movi_i32(tmp, val); | ||
3449 | + return gen_set_psr(s, mask, spsr, tmp); | ||
3450 | +} | ||
3451 | + | ||
3442 | /* Generate an old-style exception return. Marks pc as dead. */ | 3452 | /* Generate an old-style exception return. Marks pc as dead. */ |
3443 | static void gen_exception_return(DisasContext *s, TCGv pc) | 3453 | static void gen_exception_return(DisasContext *s, TCGv pc) |
3444 | { | 3454 | { |
@@ -5889,8 +5899,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) | @@ -5889,8 +5899,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) | ||
5889 | val |= (insn & 0x1f); | 5899 | val |= (insn & 0x1f); |
5890 | } | 5900 | } |
5891 | if (mask) { | 5901 | if (mask) { |
5892 | - gen_op_movl_T0_im(val); | ||
5893 | - gen_set_psr_T0(s, mask, 0); | 5902 | + gen_set_psr_im(s, mask, 0, val); |
5894 | } | 5903 | } |
5895 | return; | 5904 | return; |
5896 | } | 5905 | } |
@@ -5930,9 +5939,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) | @@ -5930,9 +5939,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) | ||
5930 | shift = ((insn >> 8) & 0xf) * 2; | 5939 | shift = ((insn >> 8) & 0xf) * 2; |
5931 | if (shift) | 5940 | if (shift) |
5932 | val = (val >> shift) | (val << (32 - shift)); | 5941 | val = (val >> shift) | (val << (32 - shift)); |
5933 | - gen_op_movl_T0_im(val); | ||
5934 | i = ((insn & (1 << 22)) != 0); | 5942 | i = ((insn & (1 << 22)) != 0); |
5935 | - if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i)) | 5943 | + if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val)) |
5936 | goto illegal_op; | 5944 | goto illegal_op; |
5937 | } | 5945 | } |
5938 | } | 5946 | } |
@@ -5946,9 +5954,9 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) | @@ -5946,9 +5954,9 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) | ||
5946 | case 0x0: /* move program status register */ | 5954 | case 0x0: /* move program status register */ |
5947 | if (op1 & 1) { | 5955 | if (op1 & 1) { |
5948 | /* PSR = reg */ | 5956 | /* PSR = reg */ |
5949 | - gen_movl_T0_reg(s, rm); | 5957 | + tmp = load_reg(s, rm); |
5950 | i = ((op1 & 2) != 0); | 5958 | i = ((op1 & 2) != 0); |
5951 | - if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i)) | 5959 | + if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp)) |
5952 | goto illegal_op; | 5960 | goto illegal_op; |
5953 | } else { | 5961 | } else { |
5954 | /* reg = PSR */ | 5962 | /* reg = PSR */ |
@@ -7677,10 +7685,10 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) | @@ -7677,10 +7685,10 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) | ||
7677 | case 1: /* msr spsr. */ | 7685 | case 1: /* msr spsr. */ |
7678 | if (IS_M(env)) | 7686 | if (IS_M(env)) |
7679 | goto illegal_op; | 7687 | goto illegal_op; |
7680 | - gen_movl_T0_reg(s, rn); | ||
7681 | - if (gen_set_psr_T0(s, | 7688 | + tmp = load_reg(s, rn); |
7689 | + if (gen_set_psr(s, | ||
7682 | msr_mask(env, s, (insn >> 8) & 0xf, op == 1), | 7690 | msr_mask(env, s, (insn >> 8) & 0xf, op == 1), |
7683 | - op == 1)) | 7691 | + op == 1, tmp)) |
7684 | goto illegal_op; | 7692 | goto illegal_op; |
7685 | break; | 7693 | break; |
7686 | case 2: /* cps, nop-hint. */ | 7694 | case 2: /* cps, nop-hint. */ |
@@ -7707,8 +7715,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) | @@ -7707,8 +7715,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) | ||
7707 | imm |= (insn & 0x1f); | 7715 | imm |= (insn & 0x1f); |
7708 | } | 7716 | } |
7709 | if (offset) { | 7717 | if (offset) { |
7710 | - gen_op_movl_T0_im(imm); | ||
7711 | - gen_set_psr_T0(s, offset, 0); | 7718 | + gen_set_psr_im(s, offset, 0, imm); |
7712 | } | 7719 | } |
7713 | break; | 7720 | break; |
7714 | case 3: /* Special control operations. */ | 7721 | case 3: /* Special control operations. */ |
@@ -8603,10 +8610,7 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s) | @@ -8603,10 +8610,7 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s) | ||
8603 | shift = CPSR_A | CPSR_I | CPSR_F; | 8610 | shift = CPSR_A | CPSR_I | CPSR_F; |
8604 | else | 8611 | else |
8605 | shift = 0; | 8612 | shift = 0; |
8606 | - | ||
8607 | - val = ((insn & 7) << 6) & shift; | ||
8608 | - gen_op_movl_T0_im(val); | ||
8609 | - gen_set_psr_T0(s, shift, 0); | 8613 | + gen_set_psr_im(s, shift, 0, ((insn & 7) << 6) & shift); |
8610 | } | 8614 | } |
8611 | break; | 8615 | break; |
8612 | 8616 |