gwj / at91sam9263 · Commits

Commit fea0c503a0f055d82daa9e86637274aa49e98412

Authored by aurel32
1 parent 4da0033e

target-ppc: be more consistent with temp variables naming 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5596 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 74 additions and 74 deletions
target-ppc/translate.c
  View file @fea0c50
@@ -832,15 +832,15 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) @@ -832,15 +832,15 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
832 int l1, l2; 832 int l1, l2;
833 uint32_t bi = rC(ctx->opcode); 833 uint32_t bi = rC(ctx->opcode);
834 uint32_t mask; 834 uint32_t mask;
835 - TCGv temp; 835 + TCGv t0;
836 836
837 l1 = gen_new_label(); 837 l1 = gen_new_label();
838 l2 = gen_new_label(); 838 l2 = gen_new_label();
839 839
840 mask = 1 << (3 - (bi & 0x03)); 840 mask = 1 << (3 - (bi & 0x03));
841 - temp = tcg_temp_new(TCG_TYPE_I32);  
842 - tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);  
843 - tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 841 + t0 = tcg_temp_new(TCG_TYPE_I32);
  842 + tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
  843 + tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
844 if (rA(ctx->opcode) == 0) 844 if (rA(ctx->opcode) == 0)
845 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 845 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
846 else 846 else
@@ -1953,22 +1953,22 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06); @@ -1953,22 +1953,22 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1953 /* slw & slw. */ 1953 /* slw & slw. */
1954 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER) 1954 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1955 { 1955 {
1956 - TCGv temp; 1956 + TCGv t0;
1957 int l1, l2; 1957 int l1, l2;
1958 l1 = gen_new_label(); 1958 l1 = gen_new_label();
1959 l2 = gen_new_label(); 1959 l2 = gen_new_label();
1960 1960
1961 - temp = tcg_temp_local_new(TCG_TYPE_TL);  
1962 - tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);  
1963 - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 1961 + t0 = tcg_temp_local_new(TCG_TYPE_TL);
  1962 + tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
  1963 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1964 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1964 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1965 tcg_gen_br(l2); 1965 tcg_gen_br(l2);
1966 gen_set_label(l1); 1966 gen_set_label(l1);
1967 - tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);  
1968 - tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp); 1967 + tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
  1968 + tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1969 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 1969 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1970 gen_set_label(l2); 1970 gen_set_label(l2);
1971 - tcg_temp_free(temp); 1971 + tcg_temp_free(t0);
1972 if (unlikely(Rc(ctx->opcode) != 0)) 1972 if (unlikely(Rc(ctx->opcode) != 0))
1973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1974 } 1974 }
@@ -1986,22 +1986,22 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) @@ -1986,22 +1986,22 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1986 int sh = SH(ctx->opcode); 1986 int sh = SH(ctx->opcode);
1987 if (sh != 0) { 1987 if (sh != 0) {
1988 int l1, l2; 1988 int l1, l2;
1989 - TCGv temp; 1989 + TCGv t0;
1990 l1 = gen_new_label(); 1990 l1 = gen_new_label();
1991 l2 = gen_new_label(); 1991 l2 = gen_new_label();
1992 - temp = tcg_temp_local_new(TCG_TYPE_TL);  
1993 - tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);  
1994 - tcg_gen_brcondi_tl(TCG_COND_GE, temp, 0, l1);  
1995 - tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);  
1996 - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 1992 + t0 = tcg_temp_local_new(TCG_TYPE_TL);
  1993 + tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
  1994 + tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
  1995 + tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
  1996 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1997 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); 1997 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1998 tcg_gen_br(l2); 1998 tcg_gen_br(l2);
1999 gen_set_label(l1); 1999 gen_set_label(l1);
2000 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); 2000 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2001 gen_set_label(l2); 2001 gen_set_label(l2);
2002 - tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);  
2003 - tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], temp, sh);  
2004 - tcg_temp_free(temp); 2002 + tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
  2003 + tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
  2004 + tcg_temp_free(t0);
2005 } else { 2005 } else {
2006 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2006 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2007 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); 2007 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
@@ -2012,24 +2012,24 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) @@ -2012,24 +2012,24 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
2012 /* srw & srw. */ 2012 /* srw & srw. */
2013 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER) 2013 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
2014 { 2014 {
2015 - TCGv temp, temp2; 2015 + TCGv t0, t1;
2016 int l1, l2; 2016 int l1, l2;
2017 l1 = gen_new_label(); 2017 l1 = gen_new_label();
2018 l2 = gen_new_label(); 2018 l2 = gen_new_label();
2019 2019
2020 - temp = tcg_temp_local_new(TCG_TYPE_TL);  
2021 - tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);  
2022 - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 2020 + t0 = tcg_temp_local_new(TCG_TYPE_TL);
  2021 + tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
  2022 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2023 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2023 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2024 tcg_gen_br(l2); 2024 tcg_gen_br(l2);
2025 gen_set_label(l1); 2025 gen_set_label(l1);
2026 - tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);  
2027 - temp2 = tcg_temp_new(TCG_TYPE_TL);  
2028 - tcg_gen_ext32u_tl(temp2, cpu_gpr[rS(ctx->opcode)]);  
2029 - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], temp2, temp);  
2030 - tcg_temp_free(temp2); 2026 + tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
  2027 + t1 = tcg_temp_new(TCG_TYPE_TL);
  2028 + tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
  2029 + tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
  2030 + tcg_temp_free(t1);
2031 gen_set_label(l2); 2031 gen_set_label(l2);
2032 - tcg_temp_free(temp); 2032 + tcg_temp_free(t0);
2033 if (unlikely(Rc(ctx->opcode) != 0)) 2033 if (unlikely(Rc(ctx->opcode) != 0))
2034 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2034 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2035 } 2035 }
@@ -2037,21 +2037,21 @@ GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER) @@ -2037,21 +2037,21 @@ GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
2037 /* sld & sld. */ 2037 /* sld & sld. */
2038 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B) 2038 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2039 { 2039 {
2040 - TCGv temp; 2040 + TCGv t0;
2041 int l1, l2; 2041 int l1, l2;
2042 l1 = gen_new_label(); 2042 l1 = gen_new_label();
2043 l2 = gen_new_label(); 2043 l2 = gen_new_label();
2044 2044
2045 - temp = tcg_temp_local_new(TCG_TYPE_TL);  
2046 - tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);  
2047 - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 2045 + t0 = tcg_temp_local_new(TCG_TYPE_TL);
  2046 + tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x40);
  2047 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2048 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2048 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2049 tcg_gen_br(l2); 2049 tcg_gen_br(l2);
2050 gen_set_label(l1); 2050 gen_set_label(l1);
2051 - tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);  
2052 - tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp); 2051 + tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
  2052 + tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2053 gen_set_label(l2); 2053 gen_set_label(l2);
2054 - tcg_temp_free(temp); 2054 + tcg_temp_free(t0);
2055 if (unlikely(Rc(ctx->opcode) != 0)) 2055 if (unlikely(Rc(ctx->opcode) != 0))
2056 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2056 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2057 } 2057 }
@@ -2069,13 +2069,13 @@ static always_inline void gen_sradi (DisasContext *ctx, int n) @@ -2069,13 +2069,13 @@ static always_inline void gen_sradi (DisasContext *ctx, int n)
2069 int sh = SH(ctx->opcode) + (n << 5); 2069 int sh = SH(ctx->opcode) + (n << 5);
2070 if (sh != 0) { 2070 if (sh != 0) {
2071 int l1, l2; 2071 int l1, l2;
2072 - TCGv temp; 2072 + TCGv t0;
2073 l1 = gen_new_label(); 2073 l1 = gen_new_label();
2074 l2 = gen_new_label(); 2074 l2 = gen_new_label();
2075 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 2075 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2076 - temp = tcg_temp_new(TCG_TYPE_TL);  
2077 - tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);  
2078 - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 2076 + t0 = tcg_temp_new(TCG_TYPE_TL);
  2077 + tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
  2078 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2079 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); 2079 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2080 tcg_gen_br(l2); 2080 tcg_gen_br(l2);
2081 gen_set_label(l1); 2081 gen_set_label(l1);
@@ -2100,21 +2100,21 @@ GEN_HANDLER2(sradi1, &quot;sradi&quot;, 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B) @@ -2100,21 +2100,21 @@ GEN_HANDLER2(sradi1, &quot;sradi&quot;, 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2100 /* srd & srd. */ 2100 /* srd & srd. */
2101 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B) 2101 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2102 { 2102 {
2103 - TCGv temp; 2103 + TCGv t0;
2104 int l1, l2; 2104 int l1, l2;
2105 l1 = gen_new_label(); 2105 l1 = gen_new_label();
2106 l2 = gen_new_label(); 2106 l2 = gen_new_label();
2107 2107
2108 - temp = tcg_temp_local_new(TCG_TYPE_TL);  
2109 - tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);  
2110 - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 2108 + t0 = tcg_temp_local_new(TCG_TYPE_TL);
  2109 + tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x40);
  2110 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2111 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2111 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2112 tcg_gen_br(l2); 2112 tcg_gen_br(l2);
2113 gen_set_label(l1); 2113 gen_set_label(l1);
2114 - tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);  
2115 - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp); 2114 + tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
  2115 + tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2116 gen_set_label(l2); 2116 gen_set_label(l2);
2117 - tcg_temp_free(temp); 2117 + tcg_temp_free(t0);
2118 if (unlikely(Rc(ctx->opcode) != 0)) 2118 if (unlikely(Rc(ctx->opcode) != 0))
2119 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2119 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2120 } 2120 }
@@ -3652,30 +3652,30 @@ GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \ @@ -3652,30 +3652,30 @@ GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3652 { \ 3652 { \
3653 uint8_t bitmask; \ 3653 uint8_t bitmask; \
3654 int sh; \ 3654 int sh; \
3655 - TCGv temp1, temp2; \ 3655 + TCGv t0, t1; \
3656 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3656 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3657 - temp1 = tcg_temp_new(TCG_TYPE_I32); \ 3657 + t0 = tcg_temp_new(TCG_TYPE_I32); \
3658 if (sh > 0) \ 3658 if (sh > 0) \
3659 - tcg_gen_shri_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3659 + tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3660 else if (sh < 0) \ 3660 else if (sh < 0) \
3661 - tcg_gen_shli_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3661 + tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3662 else \ 3662 else \
3663 - tcg_gen_mov_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2]); \  
3664 - temp2 = tcg_temp_new(TCG_TYPE_I32); \ 3663 + tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
  3664 + t1 = tcg_temp_new(TCG_TYPE_I32); \
3665 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3665 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3666 if (sh > 0) \ 3666 if (sh > 0) \
3667 - tcg_gen_shri_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3667 + tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3668 else if (sh < 0) \ 3668 else if (sh < 0) \
3669 - tcg_gen_shli_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3669 + tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3670 else \ 3670 else \
3671 - tcg_gen_mov_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2]); \  
3672 - tcg_op(temp1, temp1, temp2); \ 3671 + tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
  3672 + tcg_op(t0, t0, t1); \
3673 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ 3673 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3674 - tcg_gen_andi_i32(temp1, temp1, bitmask); \  
3675 - tcg_gen_andi_i32(temp2, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \  
3676 - tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], temp1, temp2); \  
3677 - tcg_temp_free(temp1); \  
3678 - tcg_temp_free(temp2); \ 3674 + tcg_gen_andi_i32(t0, t0, bitmask); \
  3675 + tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
  3676 + tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
  3677 + tcg_temp_free(t0); \
  3678 + tcg_temp_free(t1); \
3679 } 3679 }
3680 3680
3681 /* crand */ 3681 /* crand */
@@ -3926,9 +3926,9 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) @@ -3926,9 +3926,9 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3926 tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4); 3926 tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
3927 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 3927 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3928 } else { 3928 } else {
3929 - TCGv temp = tcg_const_tl(crm);  
3930 - tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], temp);  
3931 - tcg_temp_free(temp); 3929 + TCGv t0 = tcg_const_tl(crm);
  3930 + tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], t0);
  3931 + tcg_temp_free(t0);
3932 } 3932 }
3933 } 3933 }
3934 3934
@@ -4040,10 +4040,10 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) @@ -4040,10 +4040,10 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4040 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE) 4040 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4041 { 4041 {
4042 /* XXX: specification says this is treated as a load by the MMU */ 4042 /* XXX: specification says this is treated as a load by the MMU */
4043 - TCGv temp = tcg_temp_new(TCG_TYPE_TL);  
4044 - gen_addr_reg_index(temp, ctx);  
4045 - gen_qemu_ld8u(temp, temp, ctx->mem_idx);  
4046 - tcg_temp_free(temp); 4043 + TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
  4044 + gen_addr_reg_index(t0, ctx);
  4045 + gen_qemu_ld8u(t0, t0, ctx->mem_idx);
  4046 + tcg_temp_free(t0);
4047 } 4047 }
4048 4048
4049 /* dcbi (Supervisor only) */ 4049 /* dcbi (Supervisor only) */
@@ -4072,10 +4072,10 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) @@ -4072,10 +4072,10 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4072 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE) 4072 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4073 { 4073 {
4074 /* XXX: specification say this is treated as a load by the MMU */ 4074 /* XXX: specification say this is treated as a load by the MMU */
4075 - TCGv temp = tcg_temp_new(TCG_TYPE_TL);  
4076 - gen_addr_reg_index(temp, ctx);  
4077 - gen_qemu_ld8u(temp, temp, ctx->mem_idx);  
4078 - tcg_temp_free(temp); 4075 + TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
  4076 + gen_addr_reg_index(t0, ctx);
  4077 + gen_qemu_ld8u(t0, t0, ctx->mem_idx);
  4078 + tcg_temp_free(t0);
4079 } 4079 }
4080 4080
4081 /* dcbt */ 4081 /* dcbt */