gwj / at91sam9263 · Commits

Commit fdf9b3e831e8e6b5ceb2a44c742da7d1ab558242

Authored by bellard
1 parent 66a93e0f

sh4 target (Samuel Tardieu) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1861 c046a42c-6fe2-441c-8c8c-71466251a162
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Makefile.target
  View file @fdf9b3e
... ... @@ -225,6 +225,10 @@ ifeq ($(TARGET_BASE_ARCH), arm)
225 225 LIBOBJS+= op_helper.o helper.o
226 226 endif
227 227  
  228 +ifeq ($(TARGET_BASE_ARCH), sh4)
  229 +LIBOBJS+= op_helper.o helper.o
  230 +endif
  231 +
228 232 # NOTE: the disassembler code is only needed for debugging
229 233 LIBOBJS+=disas.o
230 234 ifeq ($(findstring i386, $(TARGET_ARCH) $(ARCH)),i386)
... ... @@ -254,6 +258,9 @@ endif
254 258 ifeq ($(findstring m68k, $(TARGET_ARCH) $(ARCH)),m68k)
255 259 LIBOBJS+=m68k-dis.o
256 260 endif
  261 +ifeq ($(findstring sh4, $(TARGET_ARCH) $(ARCH)),sh4)
  262 +LIBOBJS+=sh4-dis.o
  263 +endif
257 264  
258 265 ifdef CONFIG_GDBSTUB
259 266 OBJS+=gdbstub.o
... ... @@ -341,6 +348,9 @@ ifeq ($(TARGET_BASE_ARCH), arm)
341 348 VL_OBJS+= integratorcp.o versatilepb.o ps2.o smc91c111.o arm_pic.o arm_timer.o
342 349 VL_OBJS+= pl011.o pl050.o pl080.o pl110.o pl190.o
343 350 endif
  351 +ifeq ($(TARGET_BASE_ARCH), sh4)
  352 +VL_OBJS+= shix.o sh7750.o sh7750_regnames.o tc58128.o
  353 +endif
344 354 ifdef CONFIG_GDBSTUB
345 355 VL_OBJS+=gdbstub.o
346 356 endif
... ... @@ -462,6 +472,16 @@ endif
462 472  
463 473 loader.o: loader.c elf_ops.h
464 474  
  475 +ifeq ($(TARGET_ARCH), sh4)
  476 +op.o: op.c op_mem.c cpu.h
  477 +op_helper.o: op_helper.c exec.h cpu.h
  478 +helper.o: helper.c exec.h cpu.h
  479 +sh7750.o: sh7750.c sh7750.h sh7750_regs.h sh7750_regnames.h cpu.h
  480 +shix.o: shix.c sh7750.h sh7750_regs.h sh7750_regnames.h tc58128.h
  481 +sh7750_regnames.o: sh7750_regnames.c sh7750_regnames.h sh7750_regs.h
  482 +tc58128.o: tc58128.c tc58128.h sh7750.h
  483 +endif
  484 +
465 485 %.o: %.c
466 486 $(CC) $(CFLAGS) $(DEFINES) -c -o $@ $<
467 487  
... ...
configure
  View file @fdf9b3e
... ... @@ -359,7 +359,7 @@ if test -z &quot;$target_list&quot; ; then
359 359 fi
360 360 # the following are Linux specific
361 361 if [ "$user" = "yes" ] ; then
362   - target_list="i386-user arm-user armeb-user sparc-user ppc-user mips-user mipsel-user $target_list"
  362 + target_list="i386-user arm-user armeb-user sparc-user ppc-user mips-user mipsel-user sh4-user $target_list"
363 363 fi
364 364 else
365 365 target_list=`echo "$target_list" | sed -e 's/,/ /g'`
... ... @@ -807,6 +807,10 @@ elif test &quot;$target_cpu&quot; = &quot;mips&quot; -o &quot;$target_cpu&quot; = &quot;mipsel&quot; ; then
807 807 echo "TARGET_ARCH=mips" >> $config_mak
808 808 echo "#define TARGET_ARCH \"mips\"" >> $config_h
809 809 echo "#define TARGET_MIPS 1" >> $config_h
  810 +elif test "$target_cpu" = "sh4" ; then
  811 + echo "TARGET_ARCH=sh4" >> $config_mak
  812 + echo "#define TARGET_ARCH \"sh4\"" >> $config_h
  813 + echo "#define TARGET_SH4 1" >> $config_h
810 814 else
811 815 echo "Unsupported target CPU"
812 816 exit 1
... ...
cpu-all.h
  View file @fdf9b3e
... ... @@ -732,6 +732,13 @@ void page_unprotect_range(target_ulong data, target_ulong data_size);
732 732 #define cpu_gen_code cpu_mips_gen_code
733 733 #define cpu_signal_handler cpu_mips_signal_handler
734 734  
  735 +#elif defined(TARGET_SH4)
  736 +#define CPUState CPUSH4State
  737 +#define cpu_init cpu_sh4_init
  738 +#define cpu_exec cpu_sh4_exec
  739 +#define cpu_gen_code cpu_sh4_gen_code
  740 +#define cpu_signal_handler cpu_sh4_signal_handler
  741 +
735 742 #else
736 743  
737 744 #error unsupported target CPU
... ...
cpu-exec.c
  View file @fdf9b3e
... ... @@ -190,6 +190,10 @@ static inline TranslationBlock *tb_find_fast(void)
190 190 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
191 191 cs_base = 0;
192 192 pc = env->PC;
  193 +#elif defined(TARGET_SH4)
  194 + flags = env->sr & (SR_MD | SR_RB);
  195 + cs_base = 0; /* XXXXX */
  196 + pc = env->pc;
193 197 #else
194 198 #error unsupported CPU
195 199 #endif
... ... @@ -363,6 +367,8 @@ int cpu_exec(CPUState *env1)
363 367 #endif
364 368 #elif defined(TARGET_PPC)
365 369 #elif defined(TARGET_MIPS)
  370 +#elif defined(TARGET_SH4)
  371 + /* XXXXX */
366 372 #else
367 373 #error unsupported target CPU
368 374 #endif
... ... @@ -407,6 +413,8 @@ int cpu_exec(CPUState *env1)
407 413 do_interrupt(env->exception_index);
408 414 #elif defined(TARGET_ARM)
409 415 do_interrupt(env);
  416 +#elif defined(TARGET_SH4)
  417 + do_interrupt(env);
410 418 #endif
411 419 }
412 420 env->exception_index = -1;
... ... @@ -550,6 +558,8 @@ int cpu_exec(CPUState *env1)
550 558 env->exception_index = EXCP_IRQ;
551 559 do_interrupt(env);
552 560 }
  561 +#elif defined(TARGET_SH4)
  562 + /* XXXXX */
553 563 #endif
554 564 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
555 565 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
... ... @@ -608,6 +618,8 @@ int cpu_exec(CPUState *env1)
608 618 cpu_dump_state(env, logfile, fprintf, 0);
609 619 #elif defined(TARGET_MIPS)
610 620 cpu_dump_state(env, logfile, fprintf, 0);
  621 +#elif defined(TARGET_SH4)
  622 + cpu_dump_state(env, logfile, fprintf, 0);
611 623 #else
612 624 #error unsupported target CPU
613 625 #endif
... ... @@ -817,6 +829,8 @@ int cpu_exec(CPUState *env1)
817 829 #endif
818 830 #elif defined(TARGET_PPC)
819 831 #elif defined(TARGET_MIPS)
  832 +#elif defined(TARGET_SH4)
  833 + /* XXXXX */
820 834 #else
821 835 #error unsupported target CPU
822 836 #endif
... ... @@ -1121,6 +1135,55 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1121 1135 return 1;
1122 1136 }
1123 1137  
  1138 +#elif defined (TARGET_SH4)
  1139 +static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
  1140 + int is_write, sigset_t *old_set,
  1141 + void *puc)
  1142 +{
  1143 + TranslationBlock *tb;
  1144 + int ret;
  1145 +
  1146 + if (cpu_single_env)
  1147 + env = cpu_single_env; /* XXX: find a correct solution for multithread */
  1148 +#if defined(DEBUG_SIGNAL)
  1149 + printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
  1150 + pc, address, is_write, *(unsigned long *)old_set);
  1151 +#endif
  1152 + /* XXX: locking issue */
  1153 + if (is_write && page_unprotect(h2g(address), pc, puc)) {
  1154 + return 1;
  1155 + }
  1156 +
  1157 + /* see if it is an MMU fault */
  1158 + ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
  1159 + if (ret < 0)
  1160 + return 0; /* not an MMU fault */
  1161 + if (ret == 0)
  1162 + return 1; /* the MMU fault was handled without causing real CPU fault */
  1163 +
  1164 + /* now we have a real cpu fault */
  1165 + tb = tb_find_pc(pc);
  1166 + if (tb) {
  1167 + /* the PC is inside the translated code. It means that we have
  1168 + a virtual CPU fault */
  1169 + cpu_restore_state(tb, env, pc, puc);
  1170 + }
  1171 + if (ret == 1) {
  1172 +#if 0
  1173 + printf("PF exception: NIP=0x%08x error=0x%x %p\n",
  1174 + env->nip, env->error_code, tb);
  1175 +#endif
  1176 + /* we restore the process signal mask as the sigreturn should
  1177 + do it (XXX: use sigsetjmp) */
  1178 + sigprocmask(SIG_SETMASK, old_set, NULL);
  1179 + // do_raise_exception_err(env->exception_index, env->error_code);
  1180 + } else {
  1181 + /* activate soft MMU for this block */
  1182 + cpu_resume_from_signal(env, puc);
  1183 + }
  1184 + /* never comes here */
  1185 + return 1;
  1186 +}
1124 1187 #else
1125 1188 #error unsupported target CPU
1126 1189 #endif
... ...
dis-asm.h
  View file @fdf9b3e
... ... @@ -163,10 +163,23 @@ enum bfd_architecture
163 163 #define bfd_mach_z8002 2
164 164 bfd_arch_h8500, /* Hitachi H8/500 */
165 165 bfd_arch_sh, /* Hitachi SH */
166   -#define bfd_mach_sh 0
  166 +#define bfd_mach_sh 1
  167 +#define bfd_mach_sh2 0x20
  168 +#define bfd_mach_sh_dsp 0x2d
  169 +#define bfd_mach_sh2a 0x2a
  170 +#define bfd_mach_sh2a_nofpu 0x2b
  171 +#define bfd_mach_sh2e 0x2e
167 172 #define bfd_mach_sh3 0x30
  173 +#define bfd_mach_sh3_nommu 0x31
  174 +#define bfd_mach_sh3_dsp 0x3d
168 175 #define bfd_mach_sh3e 0x3e
169 176 #define bfd_mach_sh4 0x40
  177 +#define bfd_mach_sh4_nofpu 0x41
  178 +#define bfd_mach_sh4_nommu_nofpu 0x42
  179 +#define bfd_mach_sh4a 0x4a
  180 +#define bfd_mach_sh4a_nofpu 0x4b
  181 +#define bfd_mach_sh4al_dsp 0x4d
  182 +#define bfd_mach_sh5 0x50
170 183 bfd_arch_alpha, /* Dec Alpha */
171 184 bfd_arch_arm, /* Advanced Risc Machines ARM */
172 185 #define bfd_mach_arm_2 1
... ...
... ... @@ -73,7 +73,7 @@ generic_print_address (addr, info)
73 73 bfd_vma addr;
74 74 struct disassemble_info *info;
75 75 {
76   - (*info->fprintf_func) (info->stream, "0x%llx", addr);
  76 + (*info->fprintf_func) (info->stream, "0x%llx", addr);
77 77 }
78 78  
79 79 /* Just return the given address. */
... ... @@ -194,6 +194,9 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags)
194 194 #endif
195 195 #elif defined(TARGET_M68K)
196 196 print_insn = print_insn_m68k;
  197 +#elif defined(TARGET_SH4)
  198 + disasm_info.mach = bfd_mach_sh4;
  199 + print_insn = print_insn_sh;
197 200 #else
198 201 fprintf(out, "0x" TARGET_FMT_lx
199 202 ": Asm output not supported on this arch\n", code);
... ...
exec-all.h
  View file @fdf9b3e
... ... @@ -560,6 +560,8 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
560 560 is_user = (env->psrs == 0);
561 561 #elif defined (TARGET_ARM)
562 562 is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
  563 +#elif defined (TARGET_SH4)
  564 + is_user = ((env->sr & SR_MD) == 0);
563 565 #else
564 566 #error unimplemented CPU
565 567 #endif
... ...
gdbstub.c
  View file @fdf9b3e
... ... @@ -487,6 +487,45 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
487 487 env->PC = tswapl(*(uint32_t *)ptr);
488 488 ptr += 4;
489 489 }
  490 +#elif defined (TARGET_SH4)
  491 +static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
  492 +{
  493 + uint32_t *ptr = (uint32_t *)mem_buf;
  494 + int i;
  495 +
  496 +#define SAVE(x) *ptr++=tswapl(x)
  497 + for (i = 0; i < 16; i++) SAVE(env->gregs[i]);
  498 + SAVE (env->pc);
  499 + SAVE (env->pr);
  500 + SAVE (env->gbr);
  501 + SAVE (env->vbr);
  502 + SAVE (env->mach);
  503 + SAVE (env->macl);
  504 + SAVE (env->sr);
  505 + SAVE (0); /* TICKS */
  506 + SAVE (0); /* STALLS */
  507 + SAVE (0); /* CYCLES */
  508 + SAVE (0); /* INSTS */
  509 + SAVE (0); /* PLR */
  510 +
  511 + return ((uint8_t *)ptr - mem_buf);
  512 +}
  513 +
  514 +static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
  515 +{
  516 + uint32_t *ptr = (uint32_t *)mem_buf;
  517 + int i;
  518 +
  519 +#define LOAD(x) (x)=*ptr++;
  520 + for (i = 0; i < 16; i++) LOAD(env->gregs[i]);
  521 + LOAD (env->pc);
  522 + LOAD (env->pr);
  523 + LOAD (env->gbr);
  524 + LOAD (env->vbr);
  525 + LOAD (env->mach);
  526 + LOAD (env->macl);
  527 + LOAD (env->sr);
  528 +}
490 529 #else
491 530 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
492 531 {
... ... @@ -531,6 +570,8 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
531 570 env->npc = addr + 4;
532 571 #elif defined (TARGET_ARM)
533 572 env->regs[15] = addr;
  573 +#elif defined (TARGET_SH4)
  574 + env->pc = addr;
534 575 #endif
535 576 }
536 577 #ifdef CONFIG_USER_ONLY
... ... @@ -551,6 +592,8 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
551 592 env->npc = addr + 4;
552 593 #elif defined (TARGET_ARM)
553 594 env->regs[15] = addr;
  595 +#elif defined (TARGET_SH4)
  596 + env->pc = addr;
554 597 #endif
555 598 }
556 599 cpu_single_step(env, 1);
... ...
linux-user/elfload.c
  View file @fdf9b3e
... ... @@ -274,6 +274,30 @@ static inline void init_thread(struct target_pt_regs *regs, struct image_info *i
274 274  
275 275 #endif /* TARGET_MIPS */
276 276  
  277 +#ifdef TARGET_SH4
  278 +
  279 +#define ELF_START_MMAP 0x80000000
  280 +
  281 +#define elf_check_arch(x) ( (x) == EM_SH )
  282 +
  283 +#define ELF_CLASS ELFCLASS32
  284 +#define ELF_DATA ELFDATA2LSB
  285 +#define ELF_ARCH EM_SH
  286 +
  287 +#define ELF_PLAT_INIT(_r) /* XXXXX */
  288 +
  289 +static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop)
  290 +{
  291 + /* Check other registers XXXXX */
  292 + regs->pc = infop->entry;
  293 + regs->regs[15] = infop->start_stack - 16 * 4;
  294 +}
  295 +
  296 +#define USE_ELF_CORE_DUMP
  297 +#define ELF_EXEC_PAGESIZE 4096
  298 +
  299 +#endif
  300 +
277 301 #ifndef ELF_PLATFORM
278 302 #define ELF_PLATFORM (NULL)
279 303 #endif
... ...
linux-user/main.c
  View file @fdf9b3e
... ... @@ -1387,6 +1387,38 @@ void cpu_loop(CPUMIPSState *env)
1387 1387 }
1388 1388 #endif
1389 1389  
  1390 +#ifdef TARGET_SH4
  1391 +void cpu_loop (CPUState *env)
  1392 +{
  1393 + int trapnr, ret;
  1394 + // target_siginfo_t info;
  1395 +
  1396 + while (1) {
  1397 + trapnr = cpu_sh4_exec (env);
  1398 +
  1399 + switch (trapnr) {
  1400 + case 0x160:
  1401 + ret = do_syscall(env,
  1402 + env->gregs[0x13],
  1403 + env->gregs[0x14],
  1404 + env->gregs[0x15],
  1405 + env->gregs[0x16],
  1406 + env->gregs[0x17],
  1407 + env->gregs[0x10],
  1408 + 0);
  1409 + env->gregs[0x10] = ret;
  1410 + env->pc += 2;
  1411 + break;
  1412 + default:
  1413 + printf ("Unhandled trap: 0x%x\n", trapnr);
  1414 + cpu_dump_state(env, stderr, fprintf, 0);
  1415 + exit (1);
  1416 + }
  1417 + process_pending_signals (env);
  1418 + }
  1419 +}
  1420 +#endif
  1421 +
1390 1422 void usage(void)
1391 1423 {
1392 1424 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION ", Copyright (c) 2003-2005 Fabrice Bellard\n"
... ... @@ -1665,6 +1697,15 @@ int main(int argc, char **argv)
1665 1697 }
1666 1698 env->PC = regs->cp0_epc;
1667 1699 }
  1700 +#elif defined(TARGET_SH4)
  1701 + {
  1702 + int i;
  1703 +
  1704 + for(i = 0; i < 16; i++) {
  1705 + env->gregs[i] = regs->regs[i];
  1706 + }
  1707 + env->pc = regs->pc;
  1708 + }
1668 1709 #else
1669 1710 #error unsupported target CPU
1670 1711 #endif
... ...
linux-user/sh4/syscall.h 0 → 100644
  View file @fdf9b3e
  1 +struct target_pt_regs {
  2 + unsigned long regs[16];
  3 + unsigned long pc;
  4 + unsigned long pr;
  5 + unsigned long sr;
  6 + unsigned long gbr;
  7 + unsigned long mach;
  8 + unsigned long macl;
  9 + long tra;
  10 +};
  11 +
  12 +#define UNAME_MACHINE "sh4"
... ...
linux-user/sh4/syscall_nr.h 0 → 100644
  View file @fdf9b3e
  1 +/*
  2 + * This file contains the system call numbers.
  3 + */
  4 +
  5 +#define TARGET_NR_restart_syscall 0
  6 +#define TARGET_NR_exit 1
  7 +#define TARGET_NR_fork 2
  8 +#define TARGET_NR_read 3
  9 +#define TARGET_NR_write 4
  10 +#define TARGET_NR_open 5
  11 +#define TARGET_NR_close 6
  12 +#define TARGET_NR_waitpid 7
  13 +#define TARGET_NR_creat 8
  14 +#define TARGET_NR_link 9
  15 +#define TARGET_NR_unlink 10
  16 +#define TARGET_NR_execve 11
  17 +#define TARGET_NR_chdir 12
  18 +#define TARGET_NR_time 13
  19 +#define TARGET_NR_mknod 14
  20 +#define TARGET_NR_chmod 15
  21 +#define TARGET_NR_lchown 16
  22 +#define TARGET_NR_break 17
  23 +#define TARGET_NR_oldstat 18
  24 +#define TARGET_NR_lseek 19
  25 +#define TARGET_NR_getpid 20
  26 +#define TARGET_NR_mount 21
  27 +#define TARGET_NR_umount 22
  28 +#define TARGET_NR_setuid 23
  29 +#define TARGET_NR_getuid 24
  30 +#define TARGET_NR_stime 25
  31 +#define TARGET_NR_ptrace 26
  32 +#define TARGET_NR_alarm 27
  33 +#define TARGET_NR_oldfstat 28
  34 +#define TARGET_NR_pause 29
  35 +#define TARGET_NR_utime 30
  36 +#define TARGET_NR_stty 31
  37 +#define TARGET_NR_gtty 32
  38 +#define TARGET_NR_access 33
  39 +#define TARGET_NR_nice 34
  40 +#define TARGET_NR_ftime 35
  41 +#define TARGET_NR_sync 36
  42 +#define TARGET_NR_kill 37
  43 +#define TARGET_NR_rename 38
  44 +#define TARGET_NR_mkdir 39
  45 +#define TARGET_NR_rmdir 40
  46 +#define TARGET_NR_dup 41
  47 +#define TARGET_NR_pipe 42
  48 +#define TARGET_NR_times 43
  49 +#define TARGET_NR_prof 44
  50 +#define TARGET_NR_brk 45
  51 +#define TARGET_NR_setgid 46
  52 +#define TARGET_NR_getgid 47
  53 +#define TARGET_NR_signal 48
  54 +#define TARGET_NR_geteuid 49
  55 +#define TARGET_NR_getegid 50
  56 +#define TARGET_NR_acct 51
  57 +#define TARGET_NR_umount2 52
  58 +#define TARGET_NR_lock 53
  59 +#define TARGET_NR_ioctl 54
  60 +#define TARGET_NR_fcntl 55
  61 +#define TARGET_NR_mpx 56
  62 +#define TARGET_NR_setpgid 57
  63 +#define TARGET_NR_ulimit 58
  64 +#define TARGET_NR_oldolduname 59
  65 +#define TARGET_NR_umask 60
  66 +#define TARGET_NR_chroot 61
  67 +#define TARGET_NR_ustat 62
  68 +#define TARGET_NR_dup2 63
  69 +#define TARGET_NR_getppid 64
  70 +#define TARGET_NR_getpgrp 65
  71 +#define TARGET_NR_setsid 66
  72 +#define TARGET_NR_sigaction 67
  73 +#define TARGET_NR_sgetmask 68
  74 +#define TARGET_NR_ssetmask 69
  75 +#define TARGET_NR_setreuid 70
  76 +#define TARGET_NR_setregid 71
  77 +#define TARGET_NR_sigsuspend 72
  78 +#define TARGET_NR_sigpending 73
  79 +#define TARGET_NR_sethostname 74
  80 +#define TARGET_NR_setrlimit 75
  81 +#define TARGET_NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
  82 +#define TARGET_NR_getrusage 77
  83 +#define TARGET_NR_gettimeofday 78
  84 +#define TARGET_NR_settimeofday 79
  85 +#define TARGET_NR_getgroups 80
  86 +#define TARGET_NR_setgroups 81
  87 +#define TARGET_NR_select 82
  88 +#define TARGET_NR_symlink 83
  89 +#define TARGET_NR_oldlstat 84
  90 +#define TARGET_NR_readlink 85
  91 +#define TARGET_NR_uselib 86
  92 +#define TARGET_NR_swapon 87
  93 +#define TARGET_NR_reboot 88
  94 +#define TARGET_NR_readdir 89
  95 +#define TARGET_NR_mmap 90
  96 +#define TARGET_NR_munmap 91
  97 +#define TARGET_NR_truncate 92
  98 +#define TARGET_NR_ftruncate 93
  99 +#define TARGET_NR_fchmod 94
  100 +#define TARGET_NR_fchown 95
  101 +#define TARGET_NR_getpriority 96
  102 +#define TARGET_NR_setpriority 97
  103 +#define TARGET_NR_profil 98
  104 +#define TARGET_NR_statfs 99
  105 +#define TARGET_NR_fstatfs 100
  106 +#define TARGET_NR_ioperm 101
  107 +#define TARGET_NR_socketcall 102
  108 +#define TARGET_NR_syslog 103
  109 +#define TARGET_NR_setitimer 104
  110 +#define TARGET_NR_getitimer 105
  111 +#define TARGET_NR_stat 106
  112 +#define TARGET_NR_lstat 107
  113 +#define TARGET_NR_fstat 108
  114 +#define TARGET_NR_olduname 109
  115 +#define TARGET_NR_iopl 110
  116 +#define TARGET_NR_vhangup 111
  117 +#define TARGET_NR_idle 112
  118 +#define TARGET_NR_vm86old 113
  119 +#define TARGET_NR_wait4 114
  120 +#define TARGET_NR_swapoff 115
  121 +#define TARGET_NR_sysinfo 116
  122 +#define TARGET_NR_ipc 117
  123 +#define TARGET_NR_fsync 118
  124 +#define TARGET_NR_sigreturn 119
  125 +#define TARGET_NR_clone 120
  126 +#define TARGET_NR_setdomainname 121
  127 +#define TARGET_NR_uname 122
  128 +#define TARGET_NR_modify_ldt 123
  129 +#define TARGET_NR_adjtimex 124
  130 +#define TARGET_NR_mprotect 125
  131 +#define TARGET_NR_sigprocmask 126
  132 +#define TARGET_NR_create_module 127
  133 +#define TARGET_NR_init_module 128
  134 +#define TARGET_NR_delete_module 129
  135 +#define TARGET_NR_get_kernel_syms 130
  136 +#define TARGET_NR_quotactl 131
  137 +#define TARGET_NR_getpgid 132
  138 +#define TARGET_NR_fchdir 133
  139 +#define TARGET_NR_bdflush 134
  140 +#define TARGET_NR_sysfs 135
  141 +#define TARGET_NR_personality 136
  142 +#define TARGET_NR_afs_syscall 137 /* Syscall for Andrew File System */
  143 +#define TARGET_NR_setfsuid 138
  144 +#define TARGET_NR_setfsgid 139
  145 +#define TARGET_NR__llseek 140
  146 +#define TARGET_NR_getdents 141
  147 +#define TARGET_NR__newselect 142
  148 +#define TARGET_NR_flock 143
  149 +#define TARGET_NR_msync 144
  150 +#define TARGET_NR_readv 145
  151 +#define TARGET_NR_writev 146
  152 +#define TARGET_NR_getsid 147
  153 +#define TARGET_NR_fdatasync 148
  154 +#define TARGET_NR__sysctl 149
  155 +#define TARGET_NR_mlock 150
  156 +#define TARGET_NR_munlock 151
  157 +#define TARGET_NR_mlockall 152
  158 +#define TARGET_NR_munlockall 153
  159 +#define TARGET_NR_sched_setparam 154
  160 +#define TARGET_NR_sched_getparam 155
  161 +#define TARGET_NR_sched_setscheduler 156
  162 +#define TARGET_NR_sched_getscheduler 157
  163 +#define TARGET_NR_sched_yield 158
  164 +#define TARGET_NR_sched_get_priority_max 159
  165 +#define TARGET_NR_sched_get_priority_min 160
  166 +#define TARGET_NR_sched_rr_get_interval 161
  167 +#define TARGET_NR_nanosleep 162
  168 +#define TARGET_NR_mremap 163
  169 +#define TARGET_NR_setresuid 164
  170 +#define TARGET_NR_getresuid 165
  171 +#define TARGET_NR_vm86 166
  172 +#define TARGET_NR_query_module 167
  173 +#define TARGET_NR_poll 168
  174 +#define TARGET_NR_nfsservctl 169
  175 +#define TARGET_NR_setresgid 170
  176 +#define TARGET_NR_getresgid 171
  177 +#define TARGET_NR_prctl 172
  178 +#define TARGET_NR_rt_sigreturn 173
  179 +#define TARGET_NR_rt_sigaction 174
  180 +#define TARGET_NR_rt_sigprocmask 175
  181 +#define TARGET_NR_rt_sigpending 176
  182 +#define TARGET_NR_rt_sigtimedwait 177
  183 +#define TARGET_NR_rt_sigqueueinfo 178
  184 +#define TARGET_NR_rt_sigsuspend 179
  185 +#define TARGET_NR_pread64 180
  186 +#define TARGET_NR_pwrite64 181
  187 +#define TARGET_NR_chown 182
  188 +#define TARGET_NR_getcwd 183
  189 +#define TARGET_NR_capget 184
  190 +#define TARGET_NR_capset 185
  191 +#define TARGET_NR_sigaltstack 186
  192 +#define TARGET_NR_sendfile 187
  193 +#define TARGET_NR_streams1 188 /* some people actually want it */
  194 +#define TARGET_NR_streams2 189 /* some people actually want it */
  195 +#define TARGET_NR_vfork 190
  196 +#define TARGET_NR_ugetrlimit 191 /* SuS compliant getrlimit */
  197 +#define TARGET_NR_mmap2 192
  198 +#define TARGET_NR_truncate64 193
  199 +#define TARGET_NR_ftruncate64 194
  200 +#define TARGET_NR_stat64 195
  201 +#define TARGET_NR_lstat64 196
  202 +#define TARGET_NR_fstat64 197
  203 +#define TARGET_NR_lchown32 198
  204 +#define TARGET_NR_getuid32 199
  205 +#define TARGET_NR_getgid32 200
  206 +#define TARGET_NR_geteuid32 201
  207 +#define TARGET_NR_getegid32 202
  208 +#define TARGET_NR_setreuid32 203
  209 +#define TARGET_NR_setregid32 204
  210 +#define TARGET_NR_getgroups32 205
  211 +#define TARGET_NR_setgroups32 206
  212 +#define TARGET_NR_fchown32 207
  213 +#define TARGET_NR_setresuid32 208
  214 +#define TARGET_NR_getresuid32 209
  215 +#define TARGET_NR_setresgid32 210
  216 +#define TARGET_NR_getresgid32 211
  217 +#define TARGET_NR_chown32 212
  218 +#define TARGET_NR_setuid32 213
  219 +#define TARGET_NR_setgid32 214
  220 +#define TARGET_NR_setfsuid32 215
  221 +#define TARGET_NR_setfsgid32 216
  222 +#define TARGET_NR_pivot_root 217
  223 +#define TARGET_NR_mincore 218
  224 +#define TARGET_NR_madvise 219
  225 +#define TARGET_NR_getdents64 220
  226 +#define TARGET_NR_fcntl64 221
  227 +/* 223 is unused */
  228 +#define TARGET_NR_gettid 224
  229 +#define TARGET_NR_setxattr 226
  230 +#define TARGET_NR_lsetxattr 227
  231 +#define TARGET_NR_fsetxattr 228
  232 +#define TARGET_NR_getxattr 229
  233 +#define TARGET_NR_lgetxattr 230
  234 +#define TARGET_NR_fgetxattr 231
  235 +#define TARGET_NR_listxattr 232
  236 +#define TARGET_NR_llistxattr 233
  237 +#define TARGET_NR_flistxattr 234
  238 +#define TARGET_NR_removexattr 235
  239 +#define TARGET_NR_lremovexattr 236
  240 +#define TARGET_NR_fremovexattr 237
  241 +#define TARGET_NR_tkill 238
  242 +#define TARGET_NR_sendfile64 239
  243 +#define TARGET_NR_futex 240
  244 +#define TARGET_NR_sched_setaffinity 241
  245 +#define TARGET_NR_sched_getaffinity 242
  246 +#define TARGET_NR_set_thread_area 243
  247 +#define TARGET_NR_get_thread_area 244
  248 +#define TARGET_NR_io_setup 245
  249 +#define TARGET_NR_io_destroy 246
  250 +#define TARGET_NR_io_getevents 247
  251 +#define TARGET_NR_io_submit 248
  252 +#define TARGET_NR_io_cancel 249
  253 +#define TARGET_NR_fadvise64 250
  254 +
  255 +#define TARGET_NR_exit_group 252
  256 +#define TARGET_NR_lookup_dcookie 253
  257 +#define TARGET_NR_epoll_create 254
  258 +#define TARGET_NR_epoll_ctl 255
  259 +#define TARGET_NR_epoll_wait 256
  260 +#define TARGET_NR_remap_file_pages 257
  261 +#define TARGET_NR_set_tid_address 258
  262 +#define TARGET_NR_timer_create 259
  263 +#define TARGET_NR_timer_settime (TARGET_NR_timer_create+1)
  264 +#define TARGET_NR_timer_gettime (TARGET_NR_timer_create+2)
  265 +#define TARGET_NR_timer_getoverrun (TARGET_NR_timer_create+3)
  266 +#define TARGET_NR_timer_delete (TARGET_NR_timer_create+4)
  267 +#define TARGET_NR_clock_settime (TARGET_NR_timer_create+5)
  268 +#define TARGET_NR_clock_gettime (TARGET_NR_timer_create+6)
  269 +#define TARGET_NR_clock_getres (TARGET_NR_timer_create+7)
  270 +#define TARGET_NR_clock_nanosleep (TARGET_NR_timer_create+8)
  271 +#define TARGET_NR_statfs64 268
  272 +#define TARGET_NR_fstatfs64 269
  273 +#define TARGET_NR_tgkill 270
  274 +#define TARGET_NR_utimes 271
  275 +#define TARGET_NR_fadvise64_64 272
  276 +#define TARGET_NR_vserver 273
  277 +#define TARGET_NR_mbind 274
  278 +#define TARGET_NR_get_mempolicy 275
  279 +#define TARGET_NR_set_mempolicy 276
  280 +#define TARGET_NR_mq_open 277
  281 +#define TARGET_NR_mq_unlink (TARGET_NR_mq_open+1)
  282 +#define TARGET_NR_mq_timedsend (TARGET_NR_mq_open+2)
  283 +#define TARGET_NR_mq_timedreceive (TARGET_NR_mq_open+3)
  284 +#define TARGET_NR_mq_notify (TARGET_NR_mq_open+4)
  285 +#define TARGET_NR_mq_getsetattr (TARGET_NR_mq_open+5)
  286 +#define TARGET_NR_sys_kexec_load 283
  287 +#define TARGET_NR_waitid 284
  288 +#define TARGET_NR_add_key 285
  289 +#define TARGET_NR_request_key 286
  290 +#define TARGET_NR_keyctl 287
  291 +
  292 +#define TARGET_NR_readahead 225 /* XXXXX */
... ...
linux-user/sh4/termbits.h 0 → 100644
  View file @fdf9b3e
  1 +/* from asm/termbits.h */
  2 +
  3 +#define TARGET_NCCS 19
  4 +
  5 +struct target_termios {
  6 + unsigned int c_iflag; /* input mode flags */
  7 + unsigned int c_oflag; /* output mode flags */
  8 + unsigned int c_cflag; /* control mode flags */
  9 + unsigned int c_lflag; /* local mode flags */
  10 + unsigned char c_line; /* line discipline */
  11 + unsigned char c_cc[TARGET_NCCS]; /* control characters */
  12 +};
  13 +
  14 +/* c_cc characters */
  15 +#define TARGET_VINTR 0
  16 +#define TARGET_VQUIT 1
  17 +#define TARGET_VERASE 2
  18 +#define TARGET_VKILL 3
  19 +#define TARGET_VEOF 4
  20 +#define TARGET_VTIME 5
  21 +#define TARGET_VMIN 6
  22 +#define TARGET_VSWTC 7
  23 +#define TARGET_VSTART 8
  24 +#define TARGET_VSTOP 9
  25 +#define TARGET_VSUSP 10
  26 +#define TARGET_VEOL 11
  27 +#define TARGET_VREPRINT 12
  28 +#define TARGET_VDISCARD 13
  29 +#define TARGET_VWERASE 14
  30 +#define TARGET_VLNEXT 15
  31 +#define TARGET_VEOL2 16
  32 +
  33 +/* c_iflag bits */
  34 +#define TARGET_IGNBRK 0000001
  35 +#define TARGET_BRKINT 0000002
  36 +#define TARGET_IGNPAR 0000004
  37 +#define TARGET_PARMRK 0000010
  38 +#define TARGET_INPCK 0000020
  39 +#define TARGET_ISTRIP 0000040
  40 +#define TARGET_INLCR 0000100
  41 +#define TARGET_IGNCR 0000200
  42 +#define TARGET_ICRNL 0000400
  43 +#define TARGET_IUCLC 0001000
  44 +#define TARGET_IXON 0002000
  45 +#define TARGET_IXANY 0004000
  46 +#define TARGET_IXOFF 0010000
  47 +#define TARGET_IMAXBEL 0020000
  48 +#define TARGET_IUTF8 0040000
  49 +
  50 +/* c_oflag bits */
  51 +#define TARGET_OPOST 0000001
  52 +#define TARGET_OLCUC 0000002
  53 +#define TARGET_ONLCR 0000004
  54 +#define TARGET_OCRNL 0000010
  55 +#define TARGET_ONOCR 0000020
  56 +#define TARGET_ONLRET 0000040
  57 +#define TARGET_OFILL 0000100
  58 +#define TARGET_OFDEL 0000200
  59 +#define TARGET_NLDLY 0000400
  60 +#define TARGET_NL0 0000000
  61 +#define TARGET_NL1 0000400
  62 +#define TARGET_CRDLY 0003000
  63 +#define TARGET_CR0 0000000
  64 +#define TARGET_CR1 0001000
  65 +#define TARGET_CR2 0002000
  66 +#define TARGET_CR3 0003000
  67 +#define TARGET_TABDLY 0014000
  68 +#define TARGET_TAB0 0000000
  69 +#define TARGET_TAB1 0004000
  70 +#define TARGET_TAB2 0010000
  71 +#define TARGET_TAB3 0014000
  72 +#define TARGET_XTABS 0014000
  73 +#define TARGET_BSDLY 0020000
  74 +#define TARGET_BS0 0000000
  75 +#define TARGET_BS1 0020000
  76 +#define TARGET_VTDLY 0040000
  77 +#define TARGET_VT0 0000000
  78 +#define TARGET_VT1 0040000
  79 +#define TARGET_FFDLY 0100000
  80 +#define TARGET_FF0 0000000
  81 +#define TARGET_FF1 0100000
  82 +
  83 +/* c_cflag bit meaning */
  84 +#define TARGET_CBAUD 0010017
  85 +#define TARGET_B0 0000000 /* hang up */
  86 +#define TARGET_B50 0000001
  87 +#define TARGET_B75 0000002
  88 +#define TARGET_B110 0000003
  89 +#define TARGET_B134 0000004
  90 +#define TARGET_B150 0000005
  91 +#define TARGET_B200 0000006
  92 +#define TARGET_B300 0000007
  93 +#define TARGET_B600 0000010
  94 +#define TARGET_B1200 0000011
  95 +#define TARGET_B1800 0000012
  96 +#define TARGET_B2400 0000013
  97 +#define TARGET_B4800 0000014
  98 +#define TARGET_B9600 0000015
  99 +#define TARGET_B19200 0000016
  100 +#define TARGET_B38400 0000017
  101 +#define TARGET_EXTA B19200
  102 +#define TARGET_EXTB B38400
  103 +#define TARGET_CSIZE 0000060
  104 +#define TARGET_CS5 0000000
  105 +#define TARGET_CS6 0000020
  106 +#define TARGET_CS7 0000040
  107 +#define TARGET_CS8 0000060
  108 +#define TARGET_CSTOPB 0000100
  109 +#define TARGET_CREAD 0000200
  110 +#define TARGET_PARENB 0000400
  111 +#define TARGET_PARODD 0001000
  112 +#define TARGET_HUPCL 0002000
  113 +#define TARGET_CLOCAL 0004000
  114 +#define TARGET_CBAUDEX 0010000
  115 +#define TARGET_B57600 0010001
  116 +#define TARGET_B115200 0010002
  117 +#define TARGET_B230400 0010003
  118 +#define TARGET_B460800 0010004
  119 +#define TARGET_B500000 0010005
  120 +#define TARGET_B576000 0010006
  121 +#define TARGET_B921600 0010007
  122 +#define TARGET_B1000000 0010010
  123 +#define TARGET_B1152000 0010011
  124 +#define TARGET_B1500000 0010012
  125 +#define TARGET_B2000000 0010013
  126 +#define TARGET_B2500000 0010014
  127 +#define TARGET_B3000000 0010015
  128 +#define TARGET_B3500000 0010016
  129 +#define TARGET_B4000000 0010017
  130 +#define TARGET_CIBAUD 002003600000 /* input baud rate (not used) */
  131 +#define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */
  132 +#define TARGET_CRTSCTS 020000000000 /* flow control */
  133 +
  134 +/* c_lflag bits */
  135 +#define TARGET_ISIG 0000001
  136 +#define TARGET_ICANON 0000002
  137 +#define TARGET_XCASE 0000004
  138 +#define TARGET_ECHO 0000010
  139 +#define TARGET_ECHOE 0000020
  140 +#define TARGET_ECHOK 0000040
  141 +#define TARGET_ECHONL 0000100
  142 +#define TARGET_NOFLSH 0000200
  143 +#define TARGET_TOSTOP 0000400
  144 +#define TARGET_ECHOCTL 0001000
  145 +#define TARGET_ECHOPRT 0002000
  146 +#define TARGET_ECHOKE 0004000
  147 +#define TARGET_FLUSHO 0010000
  148 +#define TARGET_PENDIN 0040000
  149 +#define TARGET_IEXTEN 0100000
  150 +
  151 +/* tcflow() and TCXONC use these */
  152 +#define TARGET_TCOOFF 0
  153 +#define TARGET_TCOON 1
  154 +#define TARGET_TCIOFF 2
  155 +#define TARGET_TCION 3
  156 +
  157 +/* tcflush() and TCFLSH use these */
  158 +#define TARGET_TCIFLUSH 0
  159 +#define TARGET_TCOFLUSH 1
  160 +#define TARGET_TCIOFLUSH 2
  161 +
  162 +/* tcsetattr uses these */
  163 +#define TARGET_TCSANOW 0
  164 +#define TARGET_TCSADRAIN 1
  165 +#define TARGET_TARGET_TCSAFLUSH 2
  166 +
  167 +/* ioctl */
  168 +#define TARGET_FIOCLEX TARGET_IO('f', 1)
  169 +#define TARGET_FIONCLEX TARGET_IO('f', 2)
  170 +#define TARGET_FIOASYNC TARGET_IOW('f', 125, int)
  171 +#define TARGET_FIONBIO TARGET_IOW('f', 126, int)
  172 +#define TARGET_FIONREAD TARGET_IOR('f', 127, int)
  173 +#define TARGET_TIOCINQ TARGET_FIONREAD
  174 +#define TARGET_FIOQSIZE TARGET_IOR('f', 128, loff_t)
  175 +#define TARGET_TCGETS 0x5401
  176 +#define TARGET_TCSETS 0x5402
  177 +#define TARGET_TCSETSW 0x5403
  178 +#define TARGET_TCSETSF 0x5404
  179 +#define TARGET_TCGETA TARGET_IOR('t', 23, struct termio)
  180 +#define TARGET_TIOCSWINSZ TARGET_IOW('t', 103, struct winsize)
  181 +#define TARGET_TIOCGWINSZ TARGET_IOR('t', 104, struct winsize)
  182 +#define TARGET_TIOCSTART TARGET_IO('t', 110) /* start output, like ^Q */
  183 +#define TARGET_TIOCSTOP TARGET_IO('t', 111) /* stop output, like ^S */
  184 +#define TARGET_TIOCOUTQ TARGET_IOR('t', 115, int) /* output queue size */
  185 +
  186 +#define TARGET_TIOCSPGRP TARGET_IOW('t', 118, int)
  187 +#define TARGET_TIOCGPGRP TARGET_IOR('t', 119, int)
  188 +
  189 +#define TARGET_TCSETA TARGET_IOW('t', 24, struct termio)
  190 +#define TARGET_TCSETAW TARGET_IOW('t', 25, struct termio)
  191 +#define TARGET_TCSETAF TARGET_IOW('t', 28, struct termio)
  192 +#define TARGET_TCSBRK TARGET_IO('t', 29)
  193 +#define TARGET_TCXONC TARGET_IO('t', 30)
  194 +#define TARGET_TCFLSH TARGET_IO('t', 31)
  195 +
  196 +#define TARGET_TIOCSWINSZ TARGET_IOW('t', 103, struct winsize)
  197 +#define TARGET_TIOCGWINSZ TARGET_IOR('t', 104, struct winsize)
  198 +#define TARGET_TIOCSTART TARGET_IO('t', 110) /* start output, like ^Q */
  199 +#define TARGET_TIOCSTOP TARGET_IO('t', 111) /* stop output, like ^S */
  200 +#define TARGET_TIOCOUTQ TARGET_IOR('t', 115, int) /* output queue size */
  201 +
  202 +#define TARGET_TIOCSPGRP TARGET_IOW('t', 118, int)
  203 +#define TARGET_TIOCGPGRP TARGET_IOR('t', 119, int)
  204 +#define TARGET_TIOCEXCL TARGET_IO('T', 12) /* 0x540C */
  205 +#define TARGET_TIOCNXCL TARGET_IO('T', 13) /* 0x540D */
  206 +#define TARGET_TIOCSCTTY TARGET_IO('T', 14) /* 0x540E */
  207 +
  208 +#define TARGET_TIOCSTI TARGET_IOW('T', 18, char) /* 0x5412 */
  209 +#define TARGET_TIOCMGET TARGET_IOR('T', 21, unsigned int) /* 0x5415 */
  210 +#define TARGET_TIOCMBIS TARGET_IOW('T', 22, unsigned int) /* 0x5416 */
  211 +#define TARGET_TIOCMBIC TARGET_IOW('T', 23, unsigned int) /* 0x5417 */
  212 +#define TARGET_TIOCMSET TARGET_IOW('T', 24, unsigned int) /* 0x5418 */
  213 +#define TARGET_TIOCM_LE 0x001
  214 +#define TARGET_TIOCM_DTR 0x002
  215 +#define TARGET_TIOCM_RTS 0x004
  216 +#define TARGET_TIOCM_ST 0x008
  217 +#define TARGET_TIOCM_SR 0x010
  218 +#define TARGET_TIOCM_CTS 0x020
  219 +#define TARGET_TIOCM_CAR 0x040
  220 +#define TARGET_TIOCM_RNG 0x080
  221 +#define TARGET_TIOCM_DSR 0x100
  222 +#define TARGET_TIOCM_CD TARGET_TIOCM_CAR
  223 +#define TARGET_TIOCM_RI TARGET_TIOCM_RNG
  224 +
  225 +#define TARGET_TIOCGSOFTCAR TARGET_IOR('T', 25, unsigned int) /* 0x5419 */
  226 +#define TARGET_TIOCSSOFTCAR TARGET_IOW('T', 26, unsigned int) /* 0x541A */
  227 +#define TARGET_TIOCLINUX TARGET_IOW('T', 28, char) /* 0x541C */
  228 +#define TARGET_TIOCCONS TARGET_IO('T', 29) /* 0x541D */
  229 +#define TARGET_TIOCGSERIAL TARGET_IOR('T', 30, int) /* 0x541E */
  230 +#define TARGET_TIOCSSERIAL TARGET_IOW('T', 31, int) /* 0x541F */
  231 +#define TARGET_TIOCPKT TARGET_IOW('T', 32, int) /* 0x5420 */
  232 +#define TARGET_TIOCPKT_DATA 0
  233 +#define TARGET_TIOCPKT_FLUSHREAD 1
  234 +#define TARGET_TIOCPKT_FLUSHWRITE 2
  235 +#define TARGET_TIOCPKT_STOP 4
  236 +#define TARGET_TIOCPKT_START 8
  237 +#define TARGET_TIOCPKT_NOSTOP 16
  238 +#define TARGET_TIOCPKT_DOSTOP 32
  239 +
  240 +
  241 +#define TARGET_TIOCNOTTY TARGET_IO('T', 34) /* 0x5422 */
  242 +#define TARGET_TIOCSETD TARGET_IOW('T', 35, int) /* 0x5423 */
  243 +#define TARGET_TIOCGETD TARGET_IOR('T', 36, int) /* 0x5424 */
  244 +#define TARGET_TCSBRKP TARGET_IOW('T', 37, int) /* 0x5425 */ /* Needed for POSIX tcse
  245 +ndbreak() */
  246 +#define TARGET_TIOCSBRK TARGET_IO('T', 39) /* 0x5427 */ /* BSD compatibility */
  247 +#define TARGET_TIOCCBRK TARGET_IO('T', 40) /* 0x5428 */ /* BSD compatibility */
  248 +#define TARGET_TIOCGSID TARGET_IOR('T', 41, pid_t) /* 0x5429 */ /* Return the session
  249 +ID of FD */
  250 +#define TARGET_TIOCGPTN TARGET_IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-m
  251 +ux device) */
  252 +#define TARGET_TIOCSPTLCK TARGET_IOW('T',0x31, int) /* Lock/unlock Pty */
  253 +
  254 +
  255 +#define TARGET_TIOCSERCONFIG TARGET_IO('T', 83) /* 0x5453 */
  256 +#define TARGET_TIOCSERGWILD TARGET_IOR('T', 84, int) /* 0x5454 */
  257 +#define TARGET_TIOCSERSWILD TARGET_IOW('T', 85, int) /* 0x5455 */
  258 +#define TARGET_TIOCGLCKTRMIOS 0x5456
  259 +#define TARGET_TIOCSLCKTRMIOS 0x5457
  260 +#define TARGET_TIOCSERGSTRUCT TARGET_IOR('T', 88, int) /* 0x5458 */ /* For d
  261 +ebugging only */
  262 +#define TARGET_TIOCSERGETLSR TARGET_IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line sta
  263 +tus register */
  264 + /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
  265 +# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
  266 +#define TARGET_TIOCSERGETMULTI TARGET_IOR('T', 90, int) /* 0x545A
  267 +*/ /* Get multiport config */
  268 +#define TARGET_TIOCSERSETMULTI TARGET_IOW('T', 91, int) /* 0x545B
  269 +*/ /* Set multiport config */
  270 +
  271 +#define TARGET_TIOCMIWAIT TARGET_IO('T', 92) /* 0x545C */ /* wait for a change on
  272 +serial input line(s) */
  273 +#define TARGET_TIOCGICOUNT TARGET_IOR('T', 93, int) /* 0x545D */ /* read
  274 +serial port inline interrupt counts */
... ...
linux-user/syscall.c
  View file @fdf9b3e
... ... @@ -1618,6 +1618,11 @@ int do_fork(CPUState *env, unsigned int flags, unsigned long newsp)
1618 1618 for (i = 7; i < 32; i++)
1619 1619 new_env->gpr[i] = 0;
1620 1620 }
  1621 +#elif defined(TARGET_SH4)
  1622 + if (!newsp)
  1623 + newsp = env->gregs[15];
  1624 + new_env->gregs[15] = newsp;
  1625 + /* XXXXX */
1621 1626 #else
1622 1627 #error unsupported target CPU
1623 1628 #endif
... ...
linux-user/syscall_defs.h
  View file @fdf9b3e
... ... @@ -48,7 +48,7 @@
48 48 #define TARGET_IOC_NRBITS 8
49 49 #define TARGET_IOC_TYPEBITS 8
50 50  
51   -#if defined(TARGET_I386) || defined(TARGET_ARM)
  51 +#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SH4)
52 52  
53 53 #define TARGET_IOC_SIZEBITS 14
54 54 #define TARGET_IOC_DIRBITS 2
... ... @@ -293,7 +293,7 @@ struct target_sigaction;
293 293 int do_sigaction(int sig, const struct target_sigaction *act,
294 294 struct target_sigaction *oact);
295 295  
296   -#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_PPC) || defined(TARGET_MIPS)
  296 +#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_PPC) || defined(TARGET_MIPS) || defined (TARGET_SH4)
297 297  
298 298 #if defined(TARGET_SPARC)
299 299 #define TARGET_SA_NOCLDSTOP 8u
... ... @@ -863,7 +863,7 @@ struct target_winsize {
863 863 #define TARGET_MAP_NORESERVE 0x4000 /* don't check for reservations */
864 864 #endif
865 865  
866   -#if defined(TARGET_I386) || defined(TARGET_ARM)
  866 +#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SH4)
867 867 struct target_stat {
868 868 unsigned short st_dev;
869 869 unsigned short __pad1;
... ...
sh4-dis.c 0 → 100644
  View file @fdf9b3e
  1 +/* Disassemble SH instructions.
  2 + Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004
  3 + Free Software Foundation, Inc.
  4 +
  5 + This program is free software; you can redistribute it and/or modify
  6 + it under the terms of the GNU General Public License as published by
  7 + the Free Software Foundation; either version 2 of the License, or
  8 + (at your option) any later version.
  9 +
  10 + This program is distributed in the hope that it will be useful,
  11 + but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + GNU General Public License for more details.
  14 +
  15 + You should have received a copy of the GNU General Public License
  16 + along with this program; if not, write to the Free Software
  17 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  18 +
  19 +#include <stdio.h>
  20 +#include "dis-asm.h"
  21 +
  22 +#define DEFINE_TABLE
  23 +
  24 +typedef enum
  25 + {
  26 + HEX_0,
  27 + HEX_1,
  28 + HEX_2,
  29 + HEX_3,
  30 + HEX_4,
  31 + HEX_5,
  32 + HEX_6,
  33 + HEX_7,
  34 + HEX_8,
  35 + HEX_9,
  36 + HEX_A,
  37 + HEX_B,
  38 + HEX_C,
  39 + HEX_D,
  40 + HEX_E,
  41 + HEX_F,
  42 + HEX_XX00,
  43 + HEX_00YY,
  44 + REG_N,
  45 + REG_N_D, /* nnn0 */
  46 + REG_N_B01, /* nn01 */
  47 + REG_M,
  48 + SDT_REG_N,
  49 + REG_NM,
  50 + REG_B,
  51 + BRANCH_12,
  52 + BRANCH_8,
  53 + IMM0_4,
  54 + IMM0_4BY2,
  55 + IMM0_4BY4,
  56 + IMM1_4,
  57 + IMM1_4BY2,
  58 + IMM1_4BY4,
  59 + PCRELIMM_8BY2,
  60 + PCRELIMM_8BY4,
  61 + IMM0_8,
  62 + IMM0_8BY2,
  63 + IMM0_8BY4,
  64 + IMM1_8,
  65 + IMM1_8BY2,
  66 + IMM1_8BY4,
  67 + PPI,
  68 + NOPX,
  69 + NOPY,
  70 + MOVX,
  71 + MOVY,
  72 + MOVX_NOPY,
  73 + MOVY_NOPX,
  74 + PSH,
  75 + PMUL,
  76 + PPI3,
  77 + PPI3NC,
  78 + PDC,
  79 + PPIC,
  80 + REPEAT,
  81 + IMM0_3c, /* xxxx 0iii */
  82 + IMM0_3s, /* xxxx 1iii */
  83 + IMM0_3Uc, /* 0iii xxxx */
  84 + IMM0_3Us, /* 1iii xxxx */
  85 + IMM0_20_4,
  86 + IMM0_20, /* follows IMM0_20_4 */
  87 + IMM0_20BY8, /* follows IMM0_20_4 */
  88 + DISP0_12,
  89 + DISP0_12BY2,
  90 + DISP0_12BY4,
  91 + DISP0_12BY8,
  92 + DISP1_12,
  93 + DISP1_12BY2,
  94 + DISP1_12BY4,
  95 + DISP1_12BY8
  96 + }
  97 +sh_nibble_type;
  98 +
  99 +typedef enum
  100 + {
  101 + A_END,
  102 + A_BDISP12,
  103 + A_BDISP8,
  104 + A_DEC_M,
  105 + A_DEC_N,
  106 + A_DISP_GBR,
  107 + A_PC,
  108 + A_DISP_PC,
  109 + A_DISP_PC_ABS,
  110 + A_DISP_REG_M,
  111 + A_DISP_REG_N,
  112 + A_GBR,
  113 + A_IMM,
  114 + A_INC_M,
  115 + A_INC_N,
  116 + A_IND_M,
  117 + A_IND_N,
  118 + A_IND_R0_REG_M,
  119 + A_IND_R0_REG_N,
  120 + A_MACH,
  121 + A_MACL,
  122 + A_PR,
  123 + A_R0,
  124 + A_R0_GBR,
  125 + A_REG_M,
  126 + A_REG_N,
  127 + A_REG_B,
  128 + A_SR,
  129 + A_VBR,
  130 + A_TBR,
  131 + A_DISP_TBR,
  132 + A_DISP2_TBR,
  133 + A_DEC_R15,
  134 + A_INC_R15,
  135 + A_MOD,
  136 + A_RE,
  137 + A_RS,
  138 + A_DSR,
  139 + DSP_REG_M,
  140 + DSP_REG_N,
  141 + DSP_REG_X,
  142 + DSP_REG_Y,
  143 + DSP_REG_E,
  144 + DSP_REG_F,
  145 + DSP_REG_G,
  146 + DSP_REG_A_M,
  147 + DSP_REG_AX,
  148 + DSP_REG_XY,
  149 + DSP_REG_AY,
  150 + DSP_REG_YX,
  151 + AX_INC_N,
  152 + AY_INC_N,
  153 + AXY_INC_N,
  154 + AYX_INC_N,
  155 + AX_IND_N,
  156 + AY_IND_N,
  157 + AXY_IND_N,
  158 + AYX_IND_N,
  159 + AX_PMOD_N,
  160 + AXY_PMOD_N,
  161 + AY_PMOD_N,
  162 + AYX_PMOD_N,
  163 + AS_DEC_N,
  164 + AS_INC_N,
  165 + AS_IND_N,
  166 + AS_PMOD_N,
  167 + A_A0,
  168 + A_X0,
  169 + A_X1,
  170 + A_Y0,
  171 + A_Y1,
  172 + A_SSR,
  173 + A_SPC,
  174 + A_SGR,
  175 + A_DBR,
  176 + F_REG_N,
  177 + F_REG_M,
  178 + D_REG_N,
  179 + D_REG_M,
  180 + X_REG_N, /* Only used for argument parsing. */
  181 + X_REG_M, /* Only used for argument parsing. */
  182 + DX_REG_N,
  183 + DX_REG_M,
  184 + V_REG_N,
  185 + V_REG_M,
  186 + XMTRX_M4,
  187 + F_FR0,
  188 + FPUL_N,
  189 + FPUL_M,
  190 + FPSCR_N,
  191 + FPSCR_M
  192 + }
  193 +sh_arg_type;
  194 +
  195 +typedef enum
  196 + {
  197 + A_A1_NUM = 5,
  198 + A_A0_NUM = 7,
  199 + A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM,
  200 + A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM
  201 + }
  202 +sh_dsp_reg_nums;
  203 +
  204 +#define arch_sh1_base 0x0001
  205 +#define arch_sh2_base 0x0002
  206 +#define arch_sh3_base 0x0004
  207 +#define arch_sh4_base 0x0008
  208 +#define arch_sh4a_base 0x0010
  209 +#define arch_sh2a_base 0x0020
  210 +
  211 +/* This is an annotation on instruction types, but we abuse the arch
  212 + field in instructions to denote it. */
  213 +#define arch_op32 0x00100000 /* This is a 32-bit opcode. */
  214 +
  215 +#define arch_sh_no_mmu 0x04000000
  216 +#define arch_sh_has_mmu 0x08000000
  217 +#define arch_sh_no_co 0x10000000 /* neither FPU nor DSP co-processor */
  218 +#define arch_sh_sp_fpu 0x20000000 /* single precision FPU */
  219 +#define arch_sh_dp_fpu 0x40000000 /* double precision FPU */
  220 +#define arch_sh_has_dsp 0x80000000
  221 +
  222 +
  223 +#define arch_sh_base_mask 0x0000003f
  224 +#define arch_opann_mask 0x00100000
  225 +#define arch_sh_mmu_mask 0x0c000000
  226 +#define arch_sh_co_mask 0xf0000000
  227 +
  228 +
  229 +#define arch_sh1 (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co)
  230 +#define arch_sh2 (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co)
  231 +#define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)
  232 +#define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
  233 +#define arch_sh2e (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)
  234 +#define arch_sh_dsp (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp)
  235 +#define arch_sh3_nommu (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co)
  236 +#define arch_sh3 (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co)
  237 +#define arch_sh3e (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu)
  238 +#define arch_sh3_dsp (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp)
  239 +#define arch_sh4 (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu)
  240 +#define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu)
  241 +#define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp)
  242 +#define arch_sh4_nofpu (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co)
  243 +#define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co)
  244 +#define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co)
  245 +
  246 +#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
  247 +#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
  248 +#define SH_VALID_MMU_ARCH_SET(SET) (((SET) & arch_sh_mmu_mask) != 0)
  249 +#define SH_VALID_CO_ARCH_SET(SET) (((SET) & arch_sh_co_mask) != 0)
  250 +#define SH_VALID_ARCH_SET(SET) \
  251 + (SH_VALID_BASE_ARCH_SET (SET) \
  252 + && SH_VALID_MMU_ARCH_SET (SET) \
  253 + && SH_VALID_CO_ARCH_SET (SET))
  254 +#define SH_MERGE_ARCH_SET_VALID(SET1, SET2) \
  255 + SH_VALID_ARCH_SET (SH_MERGE_ARCH_SET (SET1, SET2))
  256 +
  257 +#define SH_ARCH_SET_HAS_FPU(SET) \
  258 + (((SET) & (arch_sh_sp_fpu | arch_sh_dp_fpu)) != 0)
  259 +#define SH_ARCH_SET_HAS_DSP(SET) \
  260 + (((SET) & arch_sh_has_dsp) != 0)
  261 +
  262 +/* This is returned from the functions below when an error occurs
  263 + (in addition to a call to BFD_FAIL). The value should allow
  264 + the tools to continue to function in most cases - there may
  265 + be some confusion between DSP and FPU etc. */
  266 +#define SH_ARCH_UNKNOWN_ARCH 0xffffffff
  267 +
  268 +/* These are defined in bfd/cpu-sh.c . */
  269 +unsigned int sh_get_arch_from_bfd_mach (unsigned long mach);
  270 +unsigned int sh_get_arch_up_from_bfd_mach (unsigned long mach);
  271 +unsigned long sh_get_bfd_mach_from_arch_set (unsigned int arch_set);
  272 +/* bfd_boolean sh_merge_bfd_arch (bfd *ibfd, bfd *obfd); */
  273 +
  274 +/* Below are the 'architecture sets'.
  275 + They describe the following inheritance graph:
  276 +
  277 + SH1
  278 + |
  279 + SH2
  280 + .------------'|`--------------------.
  281 + / | \
  282 +SH-DSP SH3-nommu SH2E
  283 + | |`--------. |
  284 + | | \ |
  285 + | SH3 SH4-nommu-nofpu |
  286 + | | | |
  287 + | .------------'|`----------+---------. |
  288 + |/ / \|
  289 + | | .-------' |
  290 + | |/ |
  291 +SH3-dsp SH4-nofpu SH3E
  292 + | |`--------------------. |
  293 + | | \|
  294 + | SH4A-nofpu SH4
  295 + | .------------' `--------------------. |
  296 + |/ \|
  297 +SH4AL-dsp SH4A
  298 +
  299 +*/
  300 +
  301 +/* Central branches */
  302 +#define arch_sh1_up (arch_sh1 | arch_sh2_up)
  303 +#define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up)
  304 +#define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up)
  305 +#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up)
  306 +#define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
  307 +#define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
  308 +#define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
  309 +
  310 +/* Right branch */
  311 +#define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up)
  312 +#define arch_sh3e_up (arch_sh3e | arch_sh4_up)
  313 +#define arch_sh4_up (arch_sh4 | arch_sh4a_up)
  314 +#define arch_sh4a_up (arch_sh4a)
  315 +
  316 +/* Left branch */
  317 +#define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up)
  318 +#define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
  319 +#define arch_sh4al_dsp_up (arch_sh4al_dsp)
  320 +
  321 +/* SH 2a branched off SH2e, adding a lot but not all of SH4 and SH4a. */
  322 +#define arch_sh2a_up (arch_sh2a)
  323 +#define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up)
  324 +
  325 +
  326 +typedef struct
  327 +{
  328 + char *name;
  329 + sh_arg_type arg[4];
  330 + sh_nibble_type nibbles[9];
  331 + unsigned int arch;
  332 +} sh_opcode_info;
  333 +
  334 +#ifdef DEFINE_TABLE
  335 +
  336 +const sh_opcode_info sh_table[] =
  337 + {
  338 +/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up},
  339 +
  340 +/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up},
  341 +
  342 +/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up},
  343 +
  344 +/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up},
  345 +
  346 +/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up},
  347 +
  348 +/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up},
  349 +
  350 +/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up},
  351 +
  352 +/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up},
  353 +
  354 +/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up},
  355 +
  356 +/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up},
  357 +
  358 +/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up},
  359 +
  360 +/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},
  361 +
  362 +/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},
  363 +
  364 +/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
  365 +
  366 +/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
  367 +
  368 +/* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up},
  369 +
  370 +/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up},
  371 +
  372 +/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up},
  373 +
  374 +/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up},
  375 +
  376 +/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up},
  377 +
  378 +/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up},
  379 +
  380 +/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up},
  381 +
  382 +/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up},
  383 +
  384 +/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up},
  385 +
  386 +/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up},
  387 +
  388 +/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up},
  389 +
  390 +/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up},
  391 +
  392 +/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up},
  393 +
  394 +/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up},
  395 +
  396 +/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up},
  397 +
  398 +/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up},
  399 +
  400 +/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up},
  401 +
  402 +/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up},
  403 +
  404 +/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up},
  405 +
  406 +/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up},
  407 +
  408 +/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up},
  409 +
  410 +/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up},
  411 +
  412 +/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up},
  413 +
  414 +/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up},
  415 +
  416 +/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up},
  417 +
  418 +/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
  419 +
  420 +/* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up},
  421 +
  422 +/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up},
  423 +
  424 +/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up},
  425 +
  426 +/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up},
  427 +
  428 +/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up},
  429 +
  430 +/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up},
  431 +
  432 +/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up},
  433 +
  434 +/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
  435 +
  436 +/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up},
  437 +
  438 +/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up},
  439 +
  440 +/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up},
  441 +
  442 +/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up},
  443 +
  444 +/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up},
  445 +
  446 +/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up},
  447 +
  448 +/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up},
  449 +
  450 +/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up},
  451 +
  452 +/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up},
  453 +
  454 +/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up},
  455 +
  456 +/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up},
  457 +
  458 +/* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up},
  459 +
  460 +/* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up},
  461 +/* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up},
  462 +
  463 +/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},
  464 +
  465 +/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up},
  466 +
  467 +/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up},
  468 +
  469 +/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up},
  470 +
  471 +/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up},
  472 +
  473 +/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},
  474 +
  475 +/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},
  476 +
  477 +/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},
  478 +
  479 +/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},
  480 +
  481 +/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},
  482 +
  483 +/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
  484 +
  485 +/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up},
  486 +
  487 +/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up},
  488 +
  489 +/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up},
  490 +
  491 +/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up},
  492 +
  493 +/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up},
  494 +
  495 +/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up},
  496 +
  497 +/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up},
  498 +
  499 +/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up},
  500 +
  501 +/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up},
  502 +
  503 +/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up},
  504 +
  505 +/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up},
  506 +
  507 +/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up},
  508 +
  509 +/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
  510 +
  511 +/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
  512 +
  513 +/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up},
  514 +
  515 +/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up},
  516 +
  517 +/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up},
  518 +
  519 +/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up},
  520 +
  521 +/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up},
  522 +
  523 +/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up},
  524 +
  525 +/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up},
  526 +
  527 +/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up},
  528 +
  529 +/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up},
  530 +
  531 +/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up},
  532 +
  533 +/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up},
  534 +
  535 +/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up},
  536 +
  537 +/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up},
  538 +
  539 +/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up},
  540 +/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up},
  541 +/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */
  542 +{"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  543 +/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */
  544 +{"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
  545 +/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up},
  546 +
  547 +/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up},
  548 +
  549 +/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up},
  550 +
  551 +/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up},
  552 +
  553 +/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up},
  554 +
  555 +/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up},
  556 +
  557 +/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up},
  558 +
  559 +/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up},
  560 +
  561 +/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up},
  562 +
  563 +/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up},
  564 +
  565 +/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up},
  566 +
  567 +/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up},
  568 +/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up},
  569 +/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */
  570 +{"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32},
  571 +/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */
  572 +{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32},
  573 +/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up},
  574 +
  575 +/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up},
  576 +
  577 +/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up},
  578 +
  579 +/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up},
  580 +
  581 +/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up},
  582 +
  583 +/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up},
  584 +
  585 +/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up},
  586 +
  587 +/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up},
  588 +
  589 +/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up},
  590 +
  591 +/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up},
  592 +
  593 +/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
  594 +
  595 +/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up},
  596 +/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up},
  597 +/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */
  598 +{"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32},
  599 +/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */
  600 +{"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
  601 +/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
  602 +/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up},
  603 +
  604 +/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up},
  605 +/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up},
  606 +
  607 +/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up},
  608 +
  609 +/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up},
  610 +/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up},
  611 +
  612 +/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
  613 +/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
  614 +
  615 +/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up},
  616 +
  617 +/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up},
  618 +/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up},
  619 +
  620 +/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up},
  621 +
  622 +/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up},
  623 +
  624 +/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up},
  625 +
  626 +/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up},
  627 +/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up},
  628 +
  629 +/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up},
  630 +
  631 +/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up},
  632 +
  633 +
  634 +/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
  635 +
  636 +/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up},
  637 +
  638 +/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
  639 +
  640 +/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up},
  641 +
  642 +/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
  643 +
  644 +/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up},
  645 +
  646 +/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up},
  647 +
  648 +/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up},
  649 +
  650 +/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up},
  651 +
  652 +/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up},
  653 +
  654 +/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up},
  655 +
  656 +/* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up},
  657 +/* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up},
  658 +
  659 +/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up},
  660 +/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up},
  661 +
  662 +/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
  663 +
  664 +/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up},
  665 +
  666 +/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
  667 +
  668 +/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
  669 +
  670 +/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
  671 +
  672 +/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
  673 +
  674 +/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up},
  675 +
  676 +/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up},
  677 +
  678 +/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up},
  679 +
  680 +/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up},
  681 +
  682 +/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up},
  683 +
  684 +/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up},
  685 +
  686 +/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up},
  687 +
  688 +/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up},
  689 +
  690 +/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up},
  691 +
  692 +/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up},
  693 +
  694 +/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up},
  695 +
  696 +/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up},
  697 +
  698 +/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up},
  699 +
  700 +/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up},
  701 +
  702 +/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up},
  703 +
  704 +/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up},
  705 +
  706 +/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up},
  707 +
  708 +/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up},
  709 +
  710 +/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up},
  711 +
  712 +/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
  713 +
  714 +/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
  715 +
  716 +/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up},
  717 +
  718 +/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up},
  719 +
  720 +/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up},
  721 +
  722 +/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up},
  723 +
  724 +/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up},
  725 +
  726 +/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up},
  727 +
  728 +/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up},
  729 +
  730 +/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up},
  731 +
  732 +/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up},
  733 +
  734 +/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
  735 +
  736 +/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up},
  737 +
  738 +/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up},
  739 +
  740 +/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up},
  741 +
  742 +/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up},
  743 +
  744 +/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up},
  745 +
  746 +/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up},
  747 +
  748 +/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},
  749 +
  750 +/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},
  751 +
  752 +/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},
  753 +
  754 +/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},
  755 +
  756 +/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},
  757 +
  758 +/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
  759 +
  760 +/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up},
  761 +
  762 +/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up},
  763 +
  764 +/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up},
  765 +
  766 +/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up},
  767 +
  768 +/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up},
  769 +
  770 +/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up},
  771 +
  772 +/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up},
  773 +
  774 +/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up},
  775 +
  776 +/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up},
  777 +
  778 +/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up},
  779 +
  780 +/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up},
  781 +
  782 +/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up},
  783 +
  784 +/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up},
  785 +
  786 +/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up},
  787 +
  788 +/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up},
  789 +
  790 +/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up},
  791 +
  792 +/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up},
  793 +
  794 +/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up},
  795 +
  796 +/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up},
  797 +
  798 +/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up},
  799 +
  800 +/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up},
  801 +
  802 +/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up},
  803 +
  804 +/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up},
  805 +
  806 +/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up},
  807 +
  808 +/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up},
  809 +
  810 +/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up},
  811 +
  812 +/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up},
  813 +
  814 +/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up},
  815 +
  816 +/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up},
  817 +
  818 +/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up},
  819 +
  820 +/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up},
  821 +
  822 +/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up},
  823 +
  824 +/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up},
  825 +
  826 +/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up},
  827 +
  828 +/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up},
  829 +
  830 +/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up},
  831 +
  832 +/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up},
  833 +
  834 +/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up},
  835 +
  836 +/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
  837 +
  838 +/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up},
  839 +
  840 +/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up},
  841 +
  842 +/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up},
  843 +
  844 +/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
  845 +
  846 +/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up},
  847 +
  848 +/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up},
  849 +
  850 +/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up},
  851 +
  852 +/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
  853 +
  854 +/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up},
  855 +
  856 +/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up},
  857 +
  858 +/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up},
  859 +
  860 +/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up},
  861 +
  862 +/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up},
  863 +/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up},
  864 +/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up},
  865 +/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up},
  866 +/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up},
  867 +/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up},
  868 +/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up},
  869 +/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up},
  870 +
  871 +/* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up},
  872 +/* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up},
  873 +/* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up},
  874 +/* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up},
  875 +/* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up},
  876 +/* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up},
  877 +
  878 +/* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up},
  879 +/* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up},
  880 +/* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up},
  881 +/* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up},
  882 +/* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up},
  883 +/* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up},
  884 +
  885 +/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up},
  886 +/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up},
  887 +/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up},
  888 +/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up},
  889 +/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up},
  890 +/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up},
  891 +
  892 +/* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up},
  893 +/* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up},
  894 +/* nnmm000011 movy.w @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up},
  895 +/* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up},
  896 +/* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up},
  897 +/* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up},
  898 +
  899 +/* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up},
  900 +/* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up},
  901 +/* nnmm100011 movy.l @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up},
  902 +/* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up},
  903 +/* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up},
  904 +/* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up},
  905 +
  906 +/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up},
  907 +/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  908 +{"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up},
  909 +/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  910 +{"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up},
  911 +/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */
  912 +{"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up},
  913 +/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  914 +{"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up},
  915 +/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  916 +{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up},
  917 +/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */
  918 +{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up},
  919 +/* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */
  920 +{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up},
  921 +/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
  922 +{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up},
  923 +/* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
  924 +{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up},
  925 +/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
  926 +{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up},
  927 +/* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */
  928 +{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up},
  929 +/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
  930 +{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up},
  931 +/* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
  932 +{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up},
  933 +
  934 +{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},
  935 +{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},
  936 +
  937 +/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  938 +{"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up},
  939 +/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up},
  940 +/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  941 +{"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up},
  942 +/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
  943 +/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  944 +{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up},
  945 +/* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */
  946 +{"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up},
  947 +/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  948 +{"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up},
  949 +/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  950 +{"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up},
  951 +/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  952 +{"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up},
  953 +/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
  954 +{"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up},
  955 +/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */
  956 +{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up},
  957 +/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */
  958 +{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up},
  959 +/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */
  960 +{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up},
  961 +/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
  962 +{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up},
  963 +/* 10001101xxyynnnn pclr <DSP_REG_N> */
  964 +{"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up},
  965 +/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */
  966 +{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up},
  967 +/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */
  968 +{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up},
  969 +/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */
  970 +{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up},
  971 +/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */
  972 +{"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up},
  973 +/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */
  974 +{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up},
  975 +/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */
  976 +{"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up},
  977 +/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */
  978 +{"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up},
  979 +/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */
  980 +{"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up},
  981 +/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */
  982 +{"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up},
  983 +/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */
  984 +{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
  985 +/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */
  986 +{"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up},
  987 +/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */
  988 +{"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up},
  989 +
  990 +/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
  991 +/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up},
  992 +
  993 +/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up},
  994 +/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up},
  995 +
  996 +/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up},
  997 +/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up},
  998 +
  999 +/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up},
  1000 +/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up},
  1001 +
  1002 +/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up},
  1003 +
  1004 +/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up},
  1005 +
  1006 +/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up},
  1007 +/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up},
  1008 +
  1009 +/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up},
  1010 +
  1011 +/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up},
  1012 +
  1013 +/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up},
  1014 +
  1015 +/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up},
  1016 +
  1017 +/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up},
  1018 +/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up},
  1019 +
  1020 +/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up},
  1021 +
  1022 +/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up},
  1023 +/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up},
  1024 +
  1025 +/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
  1026 +/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
  1027 +
  1028 +/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
  1029 +/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
  1030 +
  1031 +/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
  1032 +/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
  1033 +
  1034 +/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
  1035 +/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
  1036 +
  1037 +/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
  1038 +/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
  1039 +
  1040 +/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
  1041 +/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
  1042 +
  1043 +/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
  1044 +
  1045 +/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
  1046 +
  1047 +/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
  1048 +
  1049 +/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
  1050 +
  1051 +/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
  1052 +
  1053 +/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
  1054 +/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */
  1055 +{"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
  1056 +/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */
  1057 +{"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32},
  1058 +
  1059 +/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
  1060 +
  1061 +/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
  1062 +
  1063 +/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
  1064 +
  1065 +/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
  1066 +
  1067 +/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
  1068 +
  1069 +/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
  1070 +/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */
  1071 +{"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32},
  1072 +/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),F_REG_N */
  1073 +{"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
  1074 +
  1075 +/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up},
  1076 +/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up},
  1077 +
  1078 +/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
  1079 +/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up},
  1080 +
  1081 +/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up},
  1082 +
  1083 +/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up},
  1084 +
  1085 +/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up},
  1086 +
  1087 +/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up},
  1088 +
  1089 +/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up},
  1090 +/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up},
  1091 +
  1092 +/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up},
  1093 +
  1094 +/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
  1095 +
  1096 +/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
  1097 +/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up},
  1098 +
  1099 +/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up},
  1100 +/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up},
  1101 +
  1102 +/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up},
  1103 +
  1104 + /* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up},
  1105 + /* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */
  1106 +{"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  1107 + /* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up},
  1108 + /* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */
  1109 +{"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  1110 + /* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up},
  1111 + /* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */
  1112 +{"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  1113 + /* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up},
  1114 + /* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */
  1115 +{"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  1116 + /* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up},
  1117 + /* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up},
  1118 + /* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up},
  1119 + /* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up},
  1120 + /* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up},
  1121 + /* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up},
  1122 + /* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up},
  1123 + /* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up},
  1124 + /* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up},
  1125 + /* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up},
  1126 + /* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up},
  1127 + /* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up},
  1128 + /* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up},
  1129 + /* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up},
  1130 + /* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up},
  1131 + /* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up},
  1132 + /* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up},
  1133 + /* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up},
  1134 + /* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up},
  1135 + /* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up},
  1136 +
  1137 +/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */
  1138 +{"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  1139 +/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */
  1140 +{"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  1141 +/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */
  1142 +{"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  1143 +/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */
  1144 +{"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  1145 +/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */
  1146 +{"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  1147 +/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */
  1148 +{"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
  1149 +/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */
  1150 +{"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32},
  1151 +/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */
  1152 +{"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32},
  1153 +/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */
  1154 +{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
  1155 +/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
  1156 +{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
  1157 +
  1158 +{ 0, {0}, {0}, 0 }
  1159 +};
  1160 +
  1161 +#endif
  1162 +
  1163 +#ifdef ARCH_all
  1164 +#define INCLUDE_SHMEDIA
  1165 +#endif
  1166 +
  1167 +static void print_movxy
  1168 + PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *));
  1169 +static void print_insn_ddt PARAMS ((int, struct disassemble_info *));
  1170 +static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *));
  1171 +static void print_insn_ppi PARAMS ((int, struct disassemble_info *));
  1172 +
  1173 +static void
  1174 +print_movxy (op, rn, rm, fprintf_fn, stream)
  1175 + const sh_opcode_info *op;
  1176 + int rn, rm;
  1177 + fprintf_ftype fprintf_fn;
  1178 + void *stream;
  1179 +{
  1180 + int n;
  1181 +
  1182 + fprintf_fn (stream, "%s\t", op->name);
  1183 + for (n = 0; n < 2; n++)
  1184 + {
  1185 + switch (op->arg[n])
  1186 + {
  1187 + case A_IND_N:
  1188 + case AX_IND_N:
  1189 + case AXY_IND_N:
  1190 + case AY_IND_N:
  1191 + case AYX_IND_N:
  1192 + fprintf_fn (stream, "@r%d", rn);
  1193 + break;
  1194 + case A_INC_N:
  1195 + case AX_INC_N:
  1196 + case AXY_INC_N:
  1197 + case AY_INC_N:
  1198 + case AYX_INC_N:
  1199 + fprintf_fn (stream, "@r%d+", rn);
  1200 + break;
  1201 + case AX_PMOD_N:
  1202 + case AXY_PMOD_N:
  1203 + fprintf_fn (stream, "@r%d+r8", rn);
  1204 + break;
  1205 + case AY_PMOD_N:
  1206 + case AYX_PMOD_N:
  1207 + fprintf_fn (stream, "@r%d+r9", rn);
  1208 + break;
  1209 + case DSP_REG_A_M:
  1210 + fprintf_fn (stream, "a%c", '0' + rm);
  1211 + break;
  1212 + case DSP_REG_X:
  1213 + fprintf_fn (stream, "x%c", '0' + rm);
  1214 + break;
  1215 + case DSP_REG_Y:
  1216 + fprintf_fn (stream, "y%c", '0' + rm);
  1217 + break;
  1218 + case DSP_REG_AX:
  1219 + fprintf_fn (stream, "%c%c",
  1220 + (rm & 1) ? 'x' : 'a',
  1221 + (rm & 2) ? '1' : '0');
  1222 + break;
  1223 + case DSP_REG_XY:
  1224 + fprintf_fn (stream, "%c%c",
  1225 + (rm & 1) ? 'y' : 'x',
  1226 + (rm & 2) ? '1' : '0');
  1227 + break;
  1228 + case DSP_REG_AY:
  1229 + fprintf_fn (stream, "%c%c",
  1230 + (rm & 2) ? 'y' : 'a',
  1231 + (rm & 1) ? '1' : '0');
  1232 + break;
  1233 + case DSP_REG_YX:
  1234 + fprintf_fn (stream, "%c%c",
  1235 + (rm & 2) ? 'x' : 'y',
  1236 + (rm & 1) ? '1' : '0');
  1237 + break;
  1238 + default:
  1239 + abort ();
  1240 + }
  1241 + if (n == 0)
  1242 + fprintf_fn (stream, ",");
  1243 + }
  1244 +}
  1245 +
  1246 +/* Print a double data transfer insn. INSN is just the lower three
  1247 + nibbles of the insn, i.e. field a and the bit that indicates if
  1248 + a parallel processing insn follows.
  1249 + Return nonzero if a field b of a parallel processing insns follows. */
  1250 +
  1251 +static void
  1252 +print_insn_ddt (insn, info)
  1253 + int insn;
  1254 + struct disassemble_info *info;
  1255 +{
  1256 + fprintf_ftype fprintf_fn = info->fprintf_func;
  1257 + void *stream = info->stream;
  1258 +
  1259 + /* If this is just a nop, make sure to emit something. */
  1260 + if (insn == 0x000)
  1261 + fprintf_fn (stream, "nopx\tnopy");
  1262 +
  1263 + /* If a parallel processing insn was printed before,
  1264 + and we got a non-nop, emit a tab. */
  1265 + if ((insn & 0x800) && (insn & 0x3ff))
  1266 + fprintf_fn (stream, "\t");
  1267 +
  1268 + /* Check if either the x or y part is invalid. */
  1269 + if (((insn & 0xc) == 0 && (insn & 0x2a0))
  1270 + || ((insn & 3) == 0 && (insn & 0x150)))
  1271 + if (info->mach != bfd_mach_sh_dsp
  1272 + && info->mach != bfd_mach_sh3_dsp)
  1273 + {
  1274 + static const sh_opcode_info *first_movx, *first_movy;
  1275 + const sh_opcode_info *op;
  1276 + int is_movy;
  1277 +
  1278 + if (! first_movx)
  1279 + {
  1280 + for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;)
  1281 + first_movx++;
  1282 + for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;)
  1283 + first_movy++;
  1284 + }
  1285 +
  1286 + is_movy = ((insn & 3) != 0);
  1287 +
  1288 + if (is_movy)
  1289 + op = first_movy;
  1290 + else
  1291 + op = first_movx;
  1292 +
  1293 + while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3)
  1294 + || op->nibbles[3] != (unsigned) (insn & 0xf))
  1295 + op++;
  1296 +
  1297 + print_movxy (op,
  1298 + (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0)
  1299 + + 2 * is_movy
  1300 + + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)),
  1301 + (insn >> 6) & 3,
  1302 + fprintf_fn, stream);
  1303 + }
  1304 + else
  1305 + fprintf_fn (stream, ".word 0x%x", insn);
  1306 + else
  1307 + {
  1308 + static const sh_opcode_info *first_movx, *first_movy;
  1309 + const sh_opcode_info *opx, *opy;
  1310 + unsigned int insn_x, insn_y;
  1311 +
  1312 + if (! first_movx)
  1313 + {
  1314 + for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
  1315 + first_movx++;
  1316 + for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
  1317 + first_movy++;
  1318 + }
  1319 + insn_x = (insn >> 2) & 0xb;
  1320 + if (insn_x)
  1321 + {
  1322 + for (opx = first_movx; opx->nibbles[2] != insn_x;)
  1323 + opx++;
  1324 + print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
  1325 + fprintf_fn, stream);
  1326 + }
  1327 + insn_y = (insn & 3) | ((insn >> 1) & 8);
  1328 + if (insn_y)
  1329 + {
  1330 + if (insn_x)
  1331 + fprintf_fn (stream, "\t");
  1332 + for (opy = first_movy; opy->nibbles[2] != insn_y;)
  1333 + opy++;
  1334 + print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
  1335 + fprintf_fn, stream);
  1336 + }
  1337 + }
  1338 +}
  1339 +
  1340 +static void
  1341 +print_dsp_reg (rm, fprintf_fn, stream)
  1342 + int rm;
  1343 + fprintf_ftype fprintf_fn;
  1344 + void *stream;
  1345 +{
  1346 + switch (rm)
  1347 + {
  1348 + case A_A1_NUM:
  1349 + fprintf_fn (stream, "a1");
  1350 + break;
  1351 + case A_A0_NUM:
  1352 + fprintf_fn (stream, "a0");
  1353 + break;
  1354 + case A_X0_NUM:
  1355 + fprintf_fn (stream, "x0");
  1356 + break;
  1357 + case A_X1_NUM:
  1358 + fprintf_fn (stream, "x1");
  1359 + break;
  1360 + case A_Y0_NUM:
  1361 + fprintf_fn (stream, "y0");
  1362 + break;
  1363 + case A_Y1_NUM:
  1364 + fprintf_fn (stream, "y1");
  1365 + break;
  1366 + case A_M0_NUM:
  1367 + fprintf_fn (stream, "m0");
  1368 + break;
  1369 + case A_A1G_NUM:
  1370 + fprintf_fn (stream, "a1g");
  1371 + break;
  1372 + case A_M1_NUM:
  1373 + fprintf_fn (stream, "m1");
  1374 + break;
  1375 + case A_A0G_NUM:
  1376 + fprintf_fn (stream, "a0g");
  1377 + break;
  1378 + default:
  1379 + fprintf_fn (stream, "0x%x", rm);
  1380 + break;
  1381 + }
  1382 +}
  1383 +
  1384 +static void
  1385 +print_insn_ppi (field_b, info)
  1386 + int field_b;
  1387 + struct disassemble_info *info;
  1388 +{
  1389 + static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
  1390 + static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
  1391 + fprintf_ftype fprintf_fn = info->fprintf_func;
  1392 + void *stream = info->stream;
  1393 + unsigned int nib1, nib2, nib3;
  1394 + unsigned int altnib1, nib4;
  1395 + char *dc = NULL;
  1396 + const sh_opcode_info *op;
  1397 +
  1398 + if ((field_b & 0xe800) == 0)
  1399 + {
  1400 + fprintf_fn (stream, "psh%c\t#%d,",
  1401 + field_b & 0x1000 ? 'a' : 'l',
  1402 + (field_b >> 4) & 127);
  1403 + print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
  1404 + return;
  1405 + }
  1406 + if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
  1407 + {
  1408 + static char *du_tab[] = { "x0", "y0", "a0", "a1" };
  1409 + static char *se_tab[] = { "x0", "x1", "y0", "a1" };
  1410 + static char *sf_tab[] = { "y0", "y1", "x0", "a1" };
  1411 + static char *sg_tab[] = { "m0", "m1", "a0", "a1" };
  1412 +
  1413 + if (field_b & 0x2000)
  1414 + {
  1415 + fprintf_fn (stream, "p%s %s,%s,%s\t",
  1416 + (field_b & 0x1000) ? "add" : "sub",
  1417 + sx_tab[(field_b >> 6) & 3],
  1418 + sy_tab[(field_b >> 4) & 3],
  1419 + du_tab[(field_b >> 0) & 3]);
  1420 + }
  1421 + else if ((field_b & 0xf0) == 0x10
  1422 + && info->mach != bfd_mach_sh_dsp
  1423 + && info->mach != bfd_mach_sh3_dsp)
  1424 + {
  1425 + fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]);
  1426 + }
  1427 + else if ((field_b & 0xf3) != 0)
  1428 + {
  1429 + fprintf_fn (stream, ".word 0x%x\t", field_b);
  1430 + }
  1431 + fprintf_fn (stream, "pmuls%c%s,%s,%s",
  1432 + field_b & 0x2000 ? ' ' : '\t',
  1433 + se_tab[(field_b >> 10) & 3],
  1434 + sf_tab[(field_b >> 8) & 3],
  1435 + sg_tab[(field_b >> 2) & 3]);
  1436 + return;
  1437 + }
  1438 +
  1439 + nib1 = PPIC;
  1440 + nib2 = field_b >> 12 & 0xf;
  1441 + nib3 = field_b >> 8 & 0xf;
  1442 + nib4 = field_b >> 4 & 0xf;
  1443 + switch (nib3 & 0x3)
  1444 + {
  1445 + case 0:
  1446 + dc = "";
  1447 + nib1 = PPI3;
  1448 + break;
  1449 + case 1:
  1450 + dc = "";
  1451 + break;
  1452 + case 2:
  1453 + dc = "dct ";
  1454 + nib3 -= 1;
  1455 + break;
  1456 + case 3:
  1457 + dc = "dcf ";
  1458 + nib3 -= 2;
  1459 + break;
  1460 + }
  1461 + if (nib1 == PPI3)
  1462 + altnib1 = PPI3NC;
  1463 + else
  1464 + altnib1 = nib1;
  1465 + for (op = sh_table; op->name; op++)
  1466 + {
  1467 + if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1)
  1468 + && op->nibbles[2] == nib2
  1469 + && op->nibbles[3] == nib3)
  1470 + {
  1471 + int n;
  1472 +
  1473 + switch (op->nibbles[4])
  1474 + {
  1475 + case HEX_0:
  1476 + break;
  1477 + case HEX_XX00:
  1478 + if ((nib4 & 3) != 0)
  1479 + continue;
  1480 + break;
  1481 + case HEX_1:
  1482 + if ((nib4 & 3) != 1)
  1483 + continue;
  1484 + break;
  1485 + case HEX_00YY:
  1486 + if ((nib4 & 0xc) != 0)
  1487 + continue;
  1488 + break;
  1489 + case HEX_4:
  1490 + if ((nib4 & 0xc) != 4)
  1491 + continue;
  1492 + break;
  1493 + default:
  1494 + abort ();
  1495 + }
  1496 + fprintf_fn (stream, "%s%s\t", dc, op->name);
  1497 + for (n = 0; n < 3 && op->arg[n] != A_END; n++)
  1498 + {
  1499 + if (n && op->arg[1] != A_END)
  1500 + fprintf_fn (stream, ",");
  1501 + switch (op->arg[n])
  1502 + {
  1503 + case DSP_REG_N:
  1504 + print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
  1505 + break;
  1506 + case DSP_REG_X:
  1507 + fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
  1508 + break;
  1509 + case DSP_REG_Y:
  1510 + fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
  1511 + break;
  1512 + case A_MACH:
  1513 + fprintf_fn (stream, "mach");
  1514 + break;
  1515 + case A_MACL:
  1516 + fprintf_fn (stream, "macl");
  1517 + break;
  1518 + default:
  1519 + abort ();
  1520 + }
  1521 + }
  1522 + return;
  1523 + }
  1524 + }
  1525 + /* Not found. */
  1526 + fprintf_fn (stream, ".word 0x%x", field_b);
  1527 +}
  1528 +
  1529 +/* FIXME mvs: movx insns print as ".word 0x%03x", insn & 0xfff
  1530 + (ie. the upper nibble is missing). */
  1531 +int
  1532 +print_insn_sh (memaddr, info)
  1533 + bfd_vma memaddr;
  1534 + struct disassemble_info *info;
  1535 +{
  1536 + fprintf_ftype fprintf_fn = info->fprintf_func;
  1537 + void *stream = info->stream;
  1538 + unsigned char insn[4];
  1539 + unsigned char nibs[8];
  1540 + int status;
  1541 + bfd_vma relmask = ~(bfd_vma) 0;
  1542 + const sh_opcode_info *op;
  1543 + unsigned int target_arch;
  1544 + int allow_op32;
  1545 +
  1546 + switch (info->mach)
  1547 + {
  1548 + case bfd_mach_sh:
  1549 + target_arch = arch_sh1;
  1550 + break;
  1551 + case bfd_mach_sh4:
  1552 + target_arch = arch_sh4;
  1553 + break;
  1554 + case bfd_mach_sh5:
  1555 +#ifdef INCLUDE_SHMEDIA
  1556 + status = print_insn_sh64 (memaddr, info);
  1557 + if (status != -2)
  1558 + return status;
  1559 +#endif
  1560 + /* When we get here for sh64, it's because we want to disassemble
  1561 + SHcompact, i.e. arch_sh4. */
  1562 + target_arch = arch_sh4;
  1563 + break;
  1564 + default:
  1565 + fprintf (stderr, "sh architecture not supported\n");
  1566 + return -1;
  1567 + }
  1568 +
  1569 + status = info->read_memory_func (memaddr, insn, 2, info);
  1570 +
  1571 + if (status != 0)
  1572 + {
  1573 + info->memory_error_func (status, memaddr, info);
  1574 + return -1;
  1575 + }
  1576 +
  1577 + if (info->endian == BFD_ENDIAN_LITTLE)
  1578 + {
  1579 + nibs[0] = (insn[1] >> 4) & 0xf;
  1580 + nibs[1] = insn[1] & 0xf;
  1581 +
  1582 + nibs[2] = (insn[0] >> 4) & 0xf;
  1583 + nibs[3] = insn[0] & 0xf;
  1584 + }
  1585 + else
  1586 + {
  1587 + nibs[0] = (insn[0] >> 4) & 0xf;
  1588 + nibs[1] = insn[0] & 0xf;
  1589 +
  1590 + nibs[2] = (insn[1] >> 4) & 0xf;
  1591 + nibs[3] = insn[1] & 0xf;
  1592 + }
  1593 + status = info->read_memory_func (memaddr + 2, insn + 2, 2, info);
  1594 + if (status != 0)
  1595 + allow_op32 = 0;
  1596 + else
  1597 + {
  1598 + allow_op32 = 1;
  1599 +
  1600 + if (info->endian == BFD_ENDIAN_LITTLE)
  1601 + {
  1602 + nibs[4] = (insn[3] >> 4) & 0xf;
  1603 + nibs[5] = insn[3] & 0xf;
  1604 +
  1605 + nibs[6] = (insn[2] >> 4) & 0xf;
  1606 + nibs[7] = insn[2] & 0xf;
  1607 + }
  1608 + else
  1609 + {
  1610 + nibs[4] = (insn[2] >> 4) & 0xf;
  1611 + nibs[5] = insn[2] & 0xf;
  1612 +
  1613 + nibs[6] = (insn[3] >> 4) & 0xf;
  1614 + nibs[7] = insn[3] & 0xf;
  1615 + }
  1616 + }
  1617 +
  1618 + if (nibs[0] == 0xf && (nibs[1] & 4) == 0
  1619 + && SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up))
  1620 + {
  1621 + if (nibs[1] & 8)
  1622 + {
  1623 + int field_b;
  1624 +
  1625 + status = info->read_memory_func (memaddr + 2, insn, 2, info);
  1626 +
  1627 + if (status != 0)
  1628 + {
  1629 + info->memory_error_func (status, memaddr + 2, info);
  1630 + return -1;
  1631 + }
  1632 +
  1633 + if (info->endian == BFD_ENDIAN_LITTLE)
  1634 + field_b = insn[1] << 8 | insn[0];
  1635 + else
  1636 + field_b = insn[0] << 8 | insn[1];
  1637 +
  1638 + print_insn_ppi (field_b, info);
  1639 + print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
  1640 + return 4;
  1641 + }
  1642 + print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
  1643 + return 2;
  1644 + }
  1645 + for (op = sh_table; op->name; op++)
  1646 + {
  1647 + int n;
  1648 + int imm = 0;
  1649 + int rn = 0;
  1650 + int rm = 0;
  1651 + int rb = 0;
  1652 + int disp_pc;
  1653 + bfd_vma disp_pc_addr = 0;
  1654 + int disp = 0;
  1655 + int has_disp = 0;
  1656 + int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4;
  1657 +
  1658 + if (!allow_op32
  1659 + && SH_MERGE_ARCH_SET (op->arch, arch_op32))
  1660 + goto fail;
  1661 +
  1662 + if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch))
  1663 + goto fail;
  1664 + for (n = 0; n < max_n; n++)
  1665 + {
  1666 + int i = op->nibbles[n];
  1667 +
  1668 + if (i < 16)
  1669 + {
  1670 + if (nibs[n] == i)
  1671 + continue;
  1672 + goto fail;
  1673 + }
  1674 + switch (i)
  1675 + {
  1676 + case BRANCH_8:
  1677 + imm = (nibs[2] << 4) | (nibs[3]);
  1678 + if (imm & 0x80)
  1679 + imm |= ~0xff;
  1680 + imm = ((char) imm) * 2 + 4;
  1681 + goto ok;
  1682 + case BRANCH_12:
  1683 + imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
  1684 + if (imm & 0x800)
  1685 + imm |= ~0xfff;
  1686 + imm = imm * 2 + 4;
  1687 + goto ok;
  1688 + case IMM0_3c:
  1689 + if (nibs[3] & 0x8)
  1690 + goto fail;
  1691 + imm = nibs[3] & 0x7;
  1692 + break;
  1693 + case IMM0_3s:
  1694 + if (!(nibs[3] & 0x8))
  1695 + goto fail;
  1696 + imm = nibs[3] & 0x7;
  1697 + break;
  1698 + case IMM0_3Uc:
  1699 + if (nibs[2] & 0x8)
  1700 + goto fail;
  1701 + imm = nibs[2] & 0x7;
  1702 + break;
  1703 + case IMM0_3Us:
  1704 + if (!(nibs[2] & 0x8))
  1705 + goto fail;
  1706 + imm = nibs[2] & 0x7;
  1707 + break;
  1708 + case DISP0_12:
  1709 + case DISP1_12:
  1710 + disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7];
  1711 + has_disp = 1;
  1712 + goto ok;
  1713 + case DISP0_12BY2:
  1714 + case DISP1_12BY2:
  1715 + disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1;
  1716 + relmask = ~(bfd_vma) 1;
  1717 + has_disp = 1;
  1718 + goto ok;
  1719 + case DISP0_12BY4:
  1720 + case DISP1_12BY4:
  1721 + disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2;
  1722 + relmask = ~(bfd_vma) 3;
  1723 + has_disp = 1;
  1724 + goto ok;
  1725 + case DISP0_12BY8:
  1726 + case DISP1_12BY8:
  1727 + disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3;
  1728 + relmask = ~(bfd_vma) 7;
  1729 + has_disp = 1;
  1730 + goto ok;
  1731 + case IMM0_20_4:
  1732 + break;
  1733 + case IMM0_20:
  1734 + imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
  1735 + | (nibs[6] << 4) | nibs[7]);
  1736 + if (imm & 0x80000)
  1737 + imm -= 0x100000;
  1738 + goto ok;
  1739 + case IMM0_20BY8:
  1740 + imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
  1741 + | (nibs[6] << 4) | nibs[7]);
  1742 + imm <<= 8;
  1743 + if (imm & 0x8000000)
  1744 + imm -= 0x10000000;
  1745 + goto ok;
  1746 + case IMM0_4:
  1747 + case IMM1_4:
  1748 + imm = nibs[3];
  1749 + goto ok;
  1750 + case IMM0_4BY2:
  1751 + case IMM1_4BY2:
  1752 + imm = nibs[3] << 1;
  1753 + goto ok;
  1754 + case IMM0_4BY4:
  1755 + case IMM1_4BY4:
  1756 + imm = nibs[3] << 2;
  1757 + goto ok;
  1758 + case IMM0_8:
  1759 + case IMM1_8:
  1760 + imm = (nibs[2] << 4) | nibs[3];
  1761 + disp = imm;
  1762 + has_disp = 1;
  1763 + if (imm & 0x80)
  1764 + imm -= 0x100;
  1765 + goto ok;
  1766 + case PCRELIMM_8BY2:
  1767 + imm = ((nibs[2] << 4) | nibs[3]) << 1;
  1768 + relmask = ~(bfd_vma) 1;
  1769 + goto ok;
  1770 + case PCRELIMM_8BY4:
  1771 + imm = ((nibs[2] << 4) | nibs[3]) << 2;
  1772 + relmask = ~(bfd_vma) 3;
  1773 + goto ok;
  1774 + case IMM0_8BY2:
  1775 + case IMM1_8BY2:
  1776 + imm = ((nibs[2] << 4) | nibs[3]) << 1;
  1777 + goto ok;
  1778 + case IMM0_8BY4:
  1779 + case IMM1_8BY4:
  1780 + imm = ((nibs[2] << 4) | nibs[3]) << 2;
  1781 + goto ok;
  1782 + case REG_N_D:
  1783 + if ((nibs[n] & 1) != 0)
  1784 + goto fail;
  1785 + /* fall through */
  1786 + case REG_N:
  1787 + rn = nibs[n];
  1788 + break;
  1789 + case REG_M:
  1790 + rm = nibs[n];
  1791 + break;
  1792 + case REG_N_B01:
  1793 + if ((nibs[n] & 0x3) != 1 /* binary 01 */)
  1794 + goto fail;
  1795 + rn = (nibs[n] & 0xc) >> 2;
  1796 + break;
  1797 + case REG_NM:
  1798 + rn = (nibs[n] & 0xc) >> 2;
  1799 + rm = (nibs[n] & 0x3);
  1800 + break;
  1801 + case REG_B:
  1802 + rb = nibs[n] & 0x07;
  1803 + break;
  1804 + case SDT_REG_N:
  1805 + /* sh-dsp: single data transfer. */
  1806 + rn = nibs[n];
  1807 + if ((rn & 0xc) != 4)
  1808 + goto fail;
  1809 + rn = rn & 0x3;
  1810 + rn |= (!(rn & 2)) << 2;
  1811 + break;
  1812 + case PPI:
  1813 + case REPEAT:
  1814 + goto fail;
  1815 + default:
  1816 + abort ();
  1817 + }
  1818 + }
  1819 +
  1820 + ok:
  1821 + /* sh2a has D_REG but not X_REG. We don't know the pattern
  1822 + doesn't match unless we check the output args to see if they
  1823 + make sense. */
  1824 + if (target_arch == arch_sh2a
  1825 + && ((op->arg[0] == DX_REG_M && (rm & 1) != 0)
  1826 + || (op->arg[1] == DX_REG_N && (rn & 1) != 0)))
  1827 + goto fail;
  1828 +
  1829 + fprintf_fn (stream, "%s\t", op->name);
  1830 + disp_pc = 0;
  1831 + for (n = 0; n < 3 && op->arg[n] != A_END; n++)
  1832 + {
  1833 + if (n && op->arg[1] != A_END)
  1834 + fprintf_fn (stream, ",");
  1835 + switch (op->arg[n])
  1836 + {
  1837 + case A_IMM:
  1838 + fprintf_fn (stream, "#%d", imm);
  1839 + break;
  1840 + case A_R0:
  1841 + fprintf_fn (stream, "r0");
  1842 + break;
  1843 + case A_REG_N:
  1844 + fprintf_fn (stream, "r%d", rn);
  1845 + break;
  1846 + case A_INC_N:
  1847 + case AS_INC_N:
  1848 + fprintf_fn (stream, "@r%d+", rn);
  1849 + break;
  1850 + case A_DEC_N:
  1851 + case AS_DEC_N:
  1852 + fprintf_fn (stream, "@-r%d", rn);
  1853 + break;
  1854 + case A_IND_N:
  1855 + case AS_IND_N:
  1856 + fprintf_fn (stream, "@r%d", rn);
  1857 + break;
  1858 + case A_DISP_REG_N:
  1859 + fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn);
  1860 + break;
  1861 + case AS_PMOD_N:
  1862 + fprintf_fn (stream, "@r%d+r8", rn);
  1863 + break;
  1864 + case A_REG_M:
  1865 + fprintf_fn (stream, "r%d", rm);
  1866 + break;
  1867 + case A_INC_M:
  1868 + fprintf_fn (stream, "@r%d+", rm);
  1869 + break;
  1870 + case A_DEC_M:
  1871 + fprintf_fn (stream, "@-r%d", rm);
  1872 + break;
  1873 + case A_IND_M:
  1874 + fprintf_fn (stream, "@r%d", rm);
  1875 + break;
  1876 + case A_DISP_REG_M:
  1877 + fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm);
  1878 + break;
  1879 + case A_REG_B:
  1880 + fprintf_fn (stream, "r%d_bank", rb);
  1881 + break;
  1882 + case A_DISP_PC:
  1883 + disp_pc = 1;
  1884 + disp_pc_addr = imm + 4 + (memaddr & relmask);
  1885 + (*info->print_address_func) (disp_pc_addr, info);
  1886 + break;
  1887 + case A_IND_R0_REG_N:
  1888 + fprintf_fn (stream, "@(r0,r%d)", rn);
  1889 + break;
  1890 + case A_IND_R0_REG_M:
  1891 + fprintf_fn (stream, "@(r0,r%d)", rm);
  1892 + break;
  1893 + case A_DISP_GBR:
  1894 + fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm);
  1895 + break;
  1896 + case A_TBR:
  1897 + fprintf_fn (stream, "tbr");
  1898 + break;
  1899 + case A_DISP2_TBR:
  1900 + fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm);
  1901 + break;
  1902 + case A_INC_R15:
  1903 + fprintf_fn (stream, "@r15+");
  1904 + break;
  1905 + case A_DEC_R15:
  1906 + fprintf_fn (stream, "@-r15");
  1907 + break;
  1908 + case A_R0_GBR:
  1909 + fprintf_fn (stream, "@(r0,gbr)");
  1910 + break;
  1911 + case A_BDISP12:
  1912 + case A_BDISP8:
  1913 + {
  1914 + bfd_vma addr;
  1915 + addr = imm + memaddr;
  1916 + (*info->print_address_func) (addr, info);
  1917 + }
  1918 + break;
  1919 + case A_SR:
  1920 + fprintf_fn (stream, "sr");
  1921 + break;
  1922 + case A_GBR:
  1923 + fprintf_fn (stream, "gbr");
  1924 + break;
  1925 + case A_VBR:
  1926 + fprintf_fn (stream, "vbr");
  1927 + break;
  1928 + case A_DSR:
  1929 + fprintf_fn (stream, "dsr");
  1930 + break;
  1931 + case A_MOD:
  1932 + fprintf_fn (stream, "mod");
  1933 + break;
  1934 + case A_RE:
  1935 + fprintf_fn (stream, "re");
  1936 + break;
  1937 + case A_RS:
  1938 + fprintf_fn (stream, "rs");
  1939 + break;
  1940 + case A_A0:
  1941 + fprintf_fn (stream, "a0");
  1942 + break;
  1943 + case A_X0:
  1944 + fprintf_fn (stream, "x0");
  1945 + break;
  1946 + case A_X1:
  1947 + fprintf_fn (stream, "x1");
  1948 + break;
  1949 + case A_Y0:
  1950 + fprintf_fn (stream, "y0");
  1951 + break;
  1952 + case A_Y1:
  1953 + fprintf_fn (stream, "y1");
  1954 + break;
  1955 + case DSP_REG_M:
  1956 + print_dsp_reg (rm, fprintf_fn, stream);
  1957 + break;
  1958 + case A_SSR:
  1959 + fprintf_fn (stream, "ssr");
  1960 + break;
  1961 + case A_SPC:
  1962 + fprintf_fn (stream, "spc");
  1963 + break;
  1964 + case A_MACH:
  1965 + fprintf_fn (stream, "mach");
  1966 + break;
  1967 + case A_MACL:
  1968 + fprintf_fn (stream, "macl");
  1969 + break;
  1970 + case A_PR:
  1971 + fprintf_fn (stream, "pr");
  1972 + break;
  1973 + case A_SGR:
  1974 + fprintf_fn (stream, "sgr");
  1975 + break;
  1976 + case A_DBR:
  1977 + fprintf_fn (stream, "dbr");
  1978 + break;
  1979 + case F_REG_N:
  1980 + fprintf_fn (stream, "fr%d", rn);
  1981 + break;
  1982 + case F_REG_M:
  1983 + fprintf_fn (stream, "fr%d", rm);
  1984 + break;
  1985 + case DX_REG_N:
  1986 + if (rn & 1)
  1987 + {
  1988 + fprintf_fn (stream, "xd%d", rn & ~1);
  1989 + break;
  1990 + }
  1991 + case D_REG_N:
  1992 + fprintf_fn (stream, "dr%d", rn);
  1993 + break;
  1994 + case DX_REG_M:
  1995 + if (rm & 1)
  1996 + {
  1997 + fprintf_fn (stream, "xd%d", rm & ~1);
  1998 + break;
  1999 + }
  2000 + case D_REG_M:
  2001 + fprintf_fn (stream, "dr%d", rm);
  2002 + break;
  2003 + case FPSCR_M:
  2004 + case FPSCR_N:
  2005 + fprintf_fn (stream, "fpscr");
  2006 + break;
  2007 + case FPUL_M:
  2008 + case FPUL_N:
  2009 + fprintf_fn (stream, "fpul");
  2010 + break;
  2011 + case F_FR0:
  2012 + fprintf_fn (stream, "fr0");
  2013 + break;
  2014 + case V_REG_N:
  2015 + fprintf_fn (stream, "fv%d", rn * 4);
  2016 + break;
  2017 + case V_REG_M:
  2018 + fprintf_fn (stream, "fv%d", rm * 4);
  2019 + break;
  2020 + case XMTRX_M4:
  2021 + fprintf_fn (stream, "xmtrx");
  2022 + break;
  2023 + default:
  2024 + abort ();
  2025 + }
  2026 + }
  2027 +
  2028 +#if 0
  2029 + /* This code prints instructions in delay slots on the same line
  2030 + as the instruction which needs the delay slots. This can be
  2031 + confusing, since other disassembler don't work this way, and
  2032 + it means that the instructions are not all in a line. So I
  2033 + disabled it. Ian. */
  2034 + if (!(info->flags & 1)
  2035 + && (op->name[0] == 'j'
  2036 + || (op->name[0] == 'b'
  2037 + && (op->name[1] == 'r'
  2038 + || op->name[1] == 's'))
  2039 + || (op->name[0] == 'r' && op->name[1] == 't')
  2040 + || (op->name[0] == 'b' && op->name[2] == '.')))
  2041 + {
  2042 + info->flags |= 1;
  2043 + fprintf_fn (stream, "\t(slot ");
  2044 + print_insn_sh (memaddr + 2, info);
  2045 + info->flags &= ~1;
  2046 + fprintf_fn (stream, ")");
  2047 + return 4;
  2048 + }
  2049 +#endif
  2050 +
  2051 + if (disp_pc && strcmp (op->name, "mova") != 0)
  2052 + {
  2053 + int size;
  2054 + bfd_byte bytes[4];
  2055 +
  2056 + if (relmask == ~(bfd_vma) 1)
  2057 + size = 2;
  2058 + else
  2059 + size = 4;
  2060 + status = info->read_memory_func (disp_pc_addr, bytes, size, info);
  2061 + if (status == 0)
  2062 + {
  2063 + unsigned int val;
  2064 +
  2065 + if (size == 2)
  2066 + {
  2067 + if (info->endian == BFD_ENDIAN_LITTLE)
  2068 + val = bfd_getl16 (bytes);
  2069 + else
  2070 + val = bfd_getb16 (bytes);
  2071 + }
  2072 + else
  2073 + {
  2074 + if (info->endian == BFD_ENDIAN_LITTLE)
  2075 + val = bfd_getl32 (bytes);
  2076 + else
  2077 + val = bfd_getb32 (bytes);
  2078 + }
  2079 + if ((*info->symbol_at_address_func) (val, info))
  2080 + {
  2081 + fprintf_fn (stream, "\t! 0x");
  2082 + (*info->print_address_func) (val, info);
  2083 + }
  2084 + else
  2085 + fprintf_fn (stream, "\t! 0x%x", val);
  2086 + }
  2087 + }
  2088 +
  2089 + return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2;
  2090 + fail:
  2091 + ;
  2092 +
  2093 + }
  2094 + fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
  2095 + return 2;
  2096 +}
... ...
softmmu_header.h
  View file @fdf9b3e
... ... @@ -61,6 +61,8 @@
61 61 #define CPU_MEM_INDEX ((env->psrs) == 0)
62 62 #elif defined (TARGET_ARM)
63 63 #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
  64 +#elif defined (TARGET_SH4)
  65 +#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
64 66 #else
65 67 #error unsupported CPU
66 68 #endif
... ... @@ -78,6 +80,8 @@
78 80 #define CPU_MEM_INDEX ((env->psrs) == 0)
79 81 #elif defined (TARGET_ARM)
80 82 #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
  83 +#elif defined (TARGET_SH4)
  84 +#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
81 85 #else
82 86 #error unsupported CPU
83 87 #endif
... ...
target-sh4/cpu.h 0 → 100644
  View file @fdf9b3e
  1 +/*
  2 + * SH4 emulation
  3 + *
  4 + * Copyright (c) 2005 Samuel Tardieu
  5 + *
  6 + * This library is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU Lesser General Public
  8 + * License as published by the Free Software Foundation; either
  9 + * version 2 of the License, or (at your option) any later version.
  10 + *
  11 + * This library is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14 + * Lesser General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU Lesser General Public
  17 + * License along with this library; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19 + */
  20 +#ifndef _CPU_SH4_H
  21 +#define _CPU_SH4_H
  22 +
  23 +#include "config.h"
  24 +
  25 +#define TARGET_LONG_BITS 32
  26 +#define TARGET_HAS_ICE 1
  27 +
  28 +#include "cpu-defs.h"
  29 +
  30 +#define TARGET_PAGE_BITS 12 /* 4k XXXXX */
  31 +
  32 +#define SR_MD (1 << 30)
  33 +#define SR_RB (1 << 29)
  34 +#define SR_BL (1 << 28)
  35 +#define SR_FD (1 << 15)
  36 +#define SR_M (1 << 9)
  37 +#define SR_Q (1 << 8)
  38 +#define SR_S (1 << 1)
  39 +#define SR_T (1 << 0)
  40 +
  41 +#define FPSCR_FR (1 << 21)
  42 +#define FPSCR_SZ (1 << 20)
  43 +#define FPSCR_PR (1 << 19)
  44 +#define FPSCR_DN (1 << 18)
  45 +
  46 +#define DELAY_SLOT (1 << 0)
  47 +#define DELAY_SLOT_CONDITIONAL (1 << 1)
  48 +/* Those are used in contexts only */
  49 +#define BRANCH (1 << 2)
  50 +#define BRANCH_CONDITIONAL (1 << 3)
  51 +#define MODE_CHANGE (1 << 4) /* Potential MD|RB change */
  52 +#define BRANCH_EXCEPTION (1 << 5) /* Branch after exception */
  53 +
  54 +/* XXXXX The structure could be made more compact */
  55 +typedef struct tlb_t {
  56 + uint8_t asid; /* address space identifier */
  57 + uint32_t vpn; /* virtual page number */
  58 + uint8_t v; /* validity */
  59 + uint32_t ppn; /* physical page number */
  60 + uint8_t sz; /* page size */
  61 + uint32_t size; /* cached page size in bytes */
  62 + uint8_t sh; /* share status */
  63 + uint8_t c; /* cacheability */
  64 + uint8_t pr; /* protection key */
  65 + uint8_t d; /* dirty */
  66 + uint8_t wt; /* write through */
  67 + uint8_t sa; /* space attribute (PCMCIA) */
  68 + uint8_t tc; /* timing control */
  69 +} tlb_t;
  70 +
  71 +#define UTLB_SIZE 64
  72 +#define ITLB_SIZE 4
  73 +
  74 +typedef struct CPUSH4State {
  75 + uint32_t flags; /* general execution flags */
  76 + uint32_t gregs[24]; /* general registers */
  77 + uint32_t fregs[32]; /* floating point registers */
  78 + uint32_t sr; /* status register */
  79 + uint32_t ssr; /* saved status register */
  80 + uint32_t spc; /* saved program counter */
  81 + uint32_t gbr; /* global base register */
  82 + uint32_t vbr; /* vector base register */
  83 + uint32_t sgr; /* saved global register 15 */
  84 + uint32_t dbr; /* debug base register */
  85 + uint32_t pc; /* program counter */
  86 + uint32_t delayed_pc; /* target of delayed jump */
  87 + uint32_t mach; /* multiply and accumulate high */
  88 + uint32_t macl; /* multiply and accumulate low */
  89 + uint32_t pr; /* procedure register */
  90 + uint32_t fpscr; /* floating point status/control register */
  91 + uint32_t fpul; /* floating point communication register */
  92 +
  93 + /* Those belong to the specific unit (SH7750) but are handled here */
  94 + uint32_t mmucr; /* MMU control register */
  95 + uint32_t pteh; /* page table entry high register */
  96 + uint32_t ptel; /* page table entry low register */
  97 + uint32_t ptea; /* page table entry assistance register */
  98 + uint32_t ttb; /* tranlation table base register */
  99 + uint32_t tea; /* TLB exception address register */
  100 + uint32_t tra; /* TRAPA exception register */
  101 + uint32_t expevt; /* exception event register */
  102 + uint32_t intevt; /* interrupt event register */
  103 +
  104 + jmp_buf jmp_env;
  105 + int user_mode_only;
  106 + int interrupt_request;
  107 + int exception_index;
  108 + CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
  109 + tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
  110 +} CPUSH4State;
  111 +
  112 +CPUSH4State *cpu_sh4_init(void);
  113 +int cpu_sh4_exec(CPUSH4State * s);
  114 +struct siginfo;
  115 +int cpu_sh4_signal_handler(int hostsignum, struct siginfo *info,
  116 + void *puc);
  117 +
  118 +#include "softfloat.h"
  119 +
  120 +#include "cpu-all.h"
  121 +
  122 +/* Memory access type */
  123 +enum {
  124 + /* Privilege */
  125 + ACCESS_PRIV = 0x01,
  126 + /* Direction */
  127 + ACCESS_WRITE = 0x02,
  128 + /* Type of instruction */
  129 + ACCESS_CODE = 0x10,
  130 + ACCESS_INT = 0x20
  131 +};
  132 +
  133 +/* MMU control register */
  134 +#define MMUCR 0x1F000010
  135 +#define MMUCR_AT (1<<0)
  136 +#define MMUCR_SV (1<<8)
  137 +
  138 +#endif /* _CPU_SH4_H */
... ...
target-sh4/exec.h 0 → 100644
  View file @fdf9b3e
  1 +/*
  2 + * SH4 emulation
  3 + *
  4 + * Copyright (c) 2005 Samuel Tardieu
  5 + *
  6 + * This library is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU Lesser General Public
  8 + * License as published by the Free Software Foundation; either
  9 + * version 2 of the License, or (at your option) any later version.
  10 + *
  11 + * This library is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14 + * Lesser General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU Lesser General Public
  17 + * License along with this library; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19 + */
  20 +#ifndef _EXEC_SH4_H
  21 +#define _EXEC_SH4_H
  22 +
  23 +#include "config.h"
  24 +#include "dyngen-exec.h"
  25 +
  26 +register struct CPUSH4State *env asm(AREG0);
  27 +register uint32_t T0 asm(AREG1);
  28 +register uint32_t T1 asm(AREG2);
  29 +register uint32_t T2 asm(AREG3);
  30 +
  31 +#include "cpu.h"
  32 +#include "exec-all.h"
  33 +
  34 +#ifndef CONFIG_USER_ONLY
  35 +#include "softmmu_exec.h"
  36 +#endif
  37 +
  38 +#define RETURN() __asm__ __volatile__("")
  39 +
  40 +static inline void regs_to_env(void)
  41 +{
  42 + /* XXXXX */
  43 +}
  44 +
  45 +static inline void env_to_regs(void)
  46 +{
  47 + /* XXXXX */
  48 +}
  49 +
  50 +int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
  51 + int is_user, int is_softmmu);
  52 +
  53 +int find_itlb_entry(CPUState * env, target_ulong address,
  54 + int use_asid, int update);
  55 +int find_utlb_entry(CPUState * env, target_ulong address, int use_asid);
  56 +
  57 +void helper_addc_T0_T1(void);
  58 +void helper_addv_T0_T1(void);
  59 +void helper_div1_T0_T1(void);
  60 +void helper_dmulsl_T0_T1(void);
  61 +void helper_dmulul_T0_T1(void);
  62 +void helper_macl_T0_T1(void);
  63 +void helper_macw_T0_T1(void);
  64 +void helper_negc_T0(void);
  65 +void helper_subc_T0_T1(void);
  66 +void helper_subv_T0_T1(void);
  67 +void helper_rotcl(uint32_t * addr);
  68 +void helper_rotcr(uint32_t * addr);
  69 +
  70 +void do_interrupt(CPUState * env);
  71 +
  72 +void cpu_loop_exit(void);
  73 +void do_raise_exception(void);
  74 +
  75 +#endif /* _EXEC_SH4_H */
... ...
target-sh4/helper.c 0 → 100644
  View file @fdf9b3e
  1 +/*
  2 + * SH4 emulation
  3 + *
  4 + * Copyright (c) 2005 Samuel Tardieu
  5 + *
  6 + * This library is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU Lesser General Public
  8 + * License as published by the Free Software Foundation; either
  9 + * version 2 of the License, or (at your option) any later version.
  10 + *
  11 + * This library is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14 + * Lesser General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU Lesser General Public
  17 + * License along with this library; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19 + */
  20 +#include <stdarg.h>
  21 +#include <stdlib.h>
  22 +#include <stdio.h>
  23 +#include <string.h>
  24 +#include <inttypes.h>
  25 +#include <signal.h>
  26 +#include <assert.h>
  27 +
  28 +#include "cpu.h"
  29 +#include "exec-all.h"
  30 +
  31 +#define MMU_OK 0
  32 +#define MMU_ITLB_MISS (-1)
  33 +#define MMU_ITLB_MULTIPLE (-2)
  34 +#define MMU_ITLB_VIOLATION (-3)
  35 +#define MMU_DTLB_MISS_READ (-4)
  36 +#define MMU_DTLB_MISS_WRITE (-5)
  37 +#define MMU_DTLB_INITIAL_WRITE (-6)
  38 +#define MMU_DTLB_VIOLATION_READ (-7)
  39 +#define MMU_DTLB_VIOLATION_WRITE (-8)
  40 +#define MMU_DTLB_MULTIPLE (-9)
  41 +#define MMU_DTLB_MISS (-10)
  42 +
  43 +void do_interrupt(CPUState * env)
  44 +{
  45 + if (loglevel & CPU_LOG_INT) {
  46 + const char *expname;
  47 + switch (env->exception_index) {
  48 + case 0x0e0:
  49 + expname = "addr_error";
  50 + break;
  51 + case 0x040:
  52 + expname = "tlb_miss";
  53 + break;
  54 + case 0x0a0:
  55 + expname = "tlb_violation";
  56 + break;
  57 + case 0x180:
  58 + expname = "illegal_instruction";
  59 + break;
  60 + case 0x1a0:
  61 + expname = "slot_illegal_instruction";
  62 + break;
  63 + case 0x800:
  64 + expname = "fpu_disable";
  65 + break;
  66 + case 0x820:
  67 + expname = "slot_fpu";
  68 + break;
  69 + case 0x100:
  70 + expname = "data_write";
  71 + break;
  72 + case 0x060:
  73 + expname = "dtlb_miss_write";
  74 + break;
  75 + case 0x0c0:
  76 + expname = "dtlb_violation_write";
  77 + break;
  78 + case 0x120:
  79 + expname = "fpu_exception";
  80 + break;
  81 + case 0x080:
  82 + expname = "initial_page_write";
  83 + break;
  84 + case 0x160:
  85 + expname = "trapa";
  86 + break;
  87 + default:
  88 + expname = "???";
  89 + break;
  90 + }
  91 + fprintf(logfile, "exception 0x%03x [%s] raised\n",
  92 + env->exception_index, expname);
  93 + cpu_dump_state(env, logfile, fprintf, 0);
  94 + }
  95 +
  96 + env->ssr = env->sr;
  97 + env->spc = env->spc;
  98 + env->sgr = env->gregs[15];
  99 + env->sr |= SR_BL | SR_MD | SR_RB;
  100 +
  101 + env->expevt = env->exception_index & 0x7ff;
  102 + switch (env->exception_index) {
  103 + case 0x040:
  104 + case 0x060:
  105 + case 0x080:
  106 + env->pc = env->vbr + 0x400;
  107 + break;
  108 + case 0x140:
  109 + env->pc = 0xa0000000;
  110 + break;
  111 + default:
  112 + env->pc = env->vbr + 0x100;
  113 + break;
  114 + }
  115 +}
  116 +
  117 +static void update_itlb_use(CPUState * env, int itlbnb)
  118 +{
  119 + uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
  120 +
  121 + switch (itlbnb) {
  122 + case 0:
  123 + and_mask = 0x7f;
  124 + break;
  125 + case 1:
  126 + and_mask = 0xe7;
  127 + or_mask = 0x80;
  128 + break;
  129 + case 2:
  130 + and_mask = 0xfb;
  131 + or_mask = 0x50;
  132 + break;
  133 + case 3:
  134 + or_mask = 0x2c;
  135 + break;
  136 + }
  137 +
  138 + env->mmucr &= (and_mask << 24);
  139 + env->mmucr |= (or_mask << 24);
  140 +}
  141 +
  142 +static int itlb_replacement(CPUState * env)
  143 +{
  144 + if ((env->mmucr & 0xe0000000) == 0xe0000000)
  145 + return 0;
  146 + if ((env->mmucr & 0x98000000) == 0x08000000)
  147 + return 1;
  148 + if ((env->mmucr & 0x54000000) == 0x04000000)
  149 + return 2;
  150 + if ((env->mmucr & 0x2c000000) == 0x00000000)
  151 + return 3;
  152 + assert(0);
  153 +}
  154 +
  155 +/* Find the corresponding entry in the right TLB
  156 + Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
  157 +*/
  158 +static int find_tlb_entry(CPUState * env, target_ulong address,
  159 + tlb_t * entries, uint8_t nbtlb, int use_asid)
  160 +{
  161 + int match = MMU_DTLB_MISS;
  162 + uint32_t start, end;
  163 + uint8_t asid;
  164 + int i;
  165 +
  166 + asid = env->pteh & 0xff;
  167 +
  168 + for (i = 0; i < nbtlb; i++) {
  169 + if (!entries[i].v)
  170 + continue; /* Invalid entry */
  171 + if (use_asid && entries[i].asid != asid && !entries[i].sh)
  172 + continue; /* Bad ASID */
  173 +#if 0
  174 + switch (entries[i].sz) {
  175 + case 0:
  176 + size = 1024; /* 1kB */
  177 + break;
  178 + case 1:
  179 + size = 4 * 1024; /* 4kB */
  180 + break;
  181 + case 2:
  182 + size = 64 * 1024; /* 64kB */
  183 + break;
  184 + case 3:
  185 + size = 1024 * 1024; /* 1MB */
  186 + break;
  187 + default:
  188 + assert(0);
  189 + }
  190 +#endif
  191 + start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
  192 + end = start + entries[i].size - 1;
  193 + if (address >= start && address <= end) { /* Match */
  194 + if (match != -1)
  195 + return MMU_DTLB_MULTIPLE; /* Multiple match */
  196 + match = i;
  197 + }
  198 + }
  199 + return match;
  200 +}
  201 +
  202 +/* Find itlb entry - update itlb from utlb if necessary and asked for
  203 + Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
  204 + Update the itlb from utlb if update is not 0
  205 +*/
  206 +int find_itlb_entry(CPUState * env, target_ulong address,
  207 + int use_asid, int update)
  208 +{
  209 + int e, n;
  210 +
  211 + e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
  212 + if (e == MMU_DTLB_MULTIPLE)
  213 + e = MMU_ITLB_MULTIPLE;
  214 + else if (e == MMU_DTLB_MISS && update) {
  215 + e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
  216 + if (e >= 0) {
  217 + n = itlb_replacement(env);
  218 + env->itlb[n] = env->utlb[e];
  219 + e = n;
  220 + }
  221 + }
  222 + if (e >= 0)
  223 + update_itlb_use(env, e);
  224 + return e;
  225 +}
  226 +
  227 +/* Find utlb entry
  228 + Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
  229 +int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
  230 +{
  231 + uint8_t urb, urc;
  232 +
  233 + /* Increment URC */
  234 + urb = ((env->mmucr) >> 18) & 0x3f;
  235 + urc = ((env->mmucr) >> 10) & 0x3f;
  236 + urc++;
  237 + if (urc == urb || urc == UTLB_SIZE - 1)
  238 + urc = 0;
  239 + env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
  240 +
  241 + /* Return entry */
  242 + return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
  243 +}
  244 +
  245 +/* Match address against MMU
  246 + Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
  247 + MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
  248 + MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
  249 + MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
  250 +*/
  251 +static int get_mmu_address(CPUState * env, target_ulong * physical,
  252 + int *prot, target_ulong address,
  253 + int rw, int access_type)
  254 +{
  255 + int use_asid, is_code, n;
  256 + tlb_t *matching = NULL;
  257 +
  258 + use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
  259 + is_code = env->pc == address; /* Hack */
  260 +
  261 + /* Use a hack to find if this is an instruction or data access */
  262 + if (env->pc == address && !(rw & PAGE_WRITE)) {
  263 + n = find_itlb_entry(env, address, use_asid, 1);
  264 + if (n >= 0) {
  265 + matching = &env->itlb[n];
  266 + if ((env->sr & SR_MD) & !(matching->pr & 2))
  267 + n = MMU_ITLB_VIOLATION;
  268 + else
  269 + *prot = PAGE_READ;
  270 + }
  271 + } else {
  272 + n = find_utlb_entry(env, address, use_asid);
  273 + if (n >= 0) {
  274 + matching = &env->utlb[n];
  275 + switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
  276 + case 0: /* 000 */
  277 + case 2: /* 010 */
  278 + n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
  279 + MMU_DTLB_VIOLATION_READ;
  280 + break;
  281 + case 1: /* 001 */
  282 + case 4: /* 100 */
  283 + case 5: /* 101 */
  284 + if (rw & PAGE_WRITE)
  285 + n = MMU_DTLB_VIOLATION_WRITE;
  286 + else
  287 + *prot = PAGE_READ;
  288 + break;
  289 + case 3: /* 011 */
  290 + case 6: /* 110 */
  291 + case 7: /* 111 */
  292 + *prot = rw & (PAGE_READ | PAGE_WRITE);
  293 + break;
  294 + }
  295 + } else if (n == MMU_DTLB_MISS) {
  296 + n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
  297 + MMU_DTLB_MISS_READ;
  298 + }
  299 + }
  300 + if (n >= 0) {
  301 + *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
  302 + (address & (matching->size - 1));
  303 + if ((rw & PAGE_WRITE) & !matching->d)
  304 + n = MMU_DTLB_INITIAL_WRITE;
  305 + else
  306 + n = MMU_OK;
  307 + }
  308 + return n;
  309 +}
  310 +
  311 +int get_physical_address(CPUState * env, target_ulong * physical,
  312 + int *prot, target_ulong address,
  313 + int rw, int access_type)
  314 +{
  315 + /* P1, P2 and P4 areas do not use translation */
  316 + if ((address >= 0x80000000 && address < 0xc0000000) ||
  317 + address >= 0xe0000000) {
  318 + if (!(env->sr & SR_MD)
  319 + && (address < 0xe0000000 || address > 0xe4000000)) {
  320 + /* Unauthorized access in user mode (only store queues are available) */
  321 + fprintf(stderr, "Unauthorized access\n");
  322 + return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
  323 + MMU_DTLB_MISS_READ;
  324 + }
  325 + /* Mask upper 3 bits */
  326 + *physical = address & 0x1FFFFFFF;
  327 + *prot = PAGE_READ | PAGE_WRITE;
  328 + return MMU_OK;
  329 + }
  330 +
  331 + /* If MMU is disabled, return the corresponding physical page */
  332 + if (!env->mmucr & MMUCR_AT) {
  333 + *physical = address & 0x1FFFFFFF;
  334 + *prot = PAGE_READ | PAGE_WRITE;
  335 + return MMU_OK;
  336 + }
  337 +
  338 + /* We need to resort to the MMU */
  339 + return get_mmu_address(env, physical, prot, address, rw, access_type);
  340 +}
  341 +
  342 +int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
  343 + int is_user, int is_softmmu)
  344 +{
  345 + target_ulong physical, page_offset, page_size;
  346 + int prot, ret, access_type;
  347 +
  348 + /* XXXXX */
  349 +#if 0
  350 + fprintf(stderr, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
  351 + __func__, env->pc, address, rw, is_user, is_softmmu);
  352 +#endif
  353 +
  354 + access_type = ACCESS_INT;
  355 + ret =
  356 + get_physical_address(env, &physical, &prot, address, rw,
  357 + access_type);
  358 +
  359 + if (ret != MMU_OK) {
  360 + env->tea = address;
  361 + switch (ret) {
  362 + case MMU_ITLB_MISS:
  363 + case MMU_DTLB_MISS_READ:
  364 + env->exception_index = 0x040;
  365 + break;
  366 + case MMU_DTLB_MULTIPLE:
  367 + case MMU_ITLB_MULTIPLE:
  368 + env->exception_index = 0x140;
  369 + break;
  370 + case MMU_ITLB_VIOLATION:
  371 + env->exception_index = 0x0a0;
  372 + break;
  373 + case MMU_DTLB_MISS_WRITE:
  374 + env->exception_index = 0x060;
  375 + break;
  376 + case MMU_DTLB_INITIAL_WRITE:
  377 + env->exception_index = 0x080;
  378 + break;
  379 + case MMU_DTLB_VIOLATION_READ:
  380 + env->exception_index = 0x0a0;
  381 + break;
  382 + case MMU_DTLB_VIOLATION_WRITE:
  383 + env->exception_index = 0x0c0;
  384 + break;
  385 + default:
  386 + assert(0);
  387 + }
  388 + return 1;
  389 + }
  390 +
  391 + page_size = TARGET_PAGE_SIZE;
  392 + page_offset =
  393 + (address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
  394 + address = (address & TARGET_PAGE_MASK) + page_offset;
  395 + physical = (physical & TARGET_PAGE_MASK) + page_offset;
  396 +
  397 + return tlb_set_page(env, address, physical, prot, is_user, is_softmmu);
  398 +}
... ...
target-sh4/op.c 0 → 100644
  View file @fdf9b3e
  1 +/*
  2 + * SH4 emulation
  3 + *
  4 + * Copyright (c) 2005 Samuel Tardieu
  5 + *
  6 + * This library is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU Lesser General Public
  8 + * License as published by the Free Software Foundation; either
  9 + * version 2 of the License, or (at your option) any later version.
  10 + *
  11 + * This library is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14 + * Lesser General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU Lesser General Public
  17 + * License along with this library; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19 + */
  20 +#include "exec.h"
  21 +
  22 +static inline void set_flag(uint32_t flag)
  23 +{
  24 + env->flags |= flag;
  25 +}
  26 +
  27 +static inline void clr_flag(uint32_t flag)
  28 +{
  29 + env->flags &= ~flag;
  30 +}
  31 +
  32 +static inline void set_t(void)
  33 +{
  34 + env->sr |= SR_T;
  35 +}
  36 +
  37 +static inline void clr_t(void)
  38 +{
  39 + env->sr &= ~SR_T;
  40 +}
  41 +
  42 +static inline void cond_t(int cond)
  43 +{
  44 + if (cond)
  45 + set_t();
  46 + else
  47 + clr_t();
  48 +}
  49 +
  50 +void OPPROTO op_movl_imm_T0(void)
  51 +{
  52 + T0 = (uint32_t) PARAM1;
  53 + RETURN();
  54 +}
  55 +
  56 +void OPPROTO op_movl_imm_T1(void)
  57 +{
  58 + T0 = (uint32_t) PARAM1;
  59 + RETURN();
  60 +}
  61 +
  62 +void OPPROTO op_movl_imm_T2(void)
  63 +{
  64 + T0 = (uint32_t) PARAM1;
  65 + RETURN();
  66 +}
  67 +
  68 +void OPPROTO op_cmp_eq_imm_T0(void)
  69 +{
  70 + cond_t((int32_t) T0 == (int32_t) PARAM1);
  71 + RETURN();
  72 +}
  73 +
  74 +void OPPROTO op_cmd_eq_T0_T1(void)
  75 +{
  76 + cond_t(T0 == T1);
  77 + RETURN();
  78 +}
  79 +
  80 +void OPPROTO op_cmd_hs_T0_T1(void)
  81 +{
  82 + cond_t((uint32_t) T0 <= (uint32_t) T1);
  83 + RETURN();
  84 +}
  85 +
  86 +void OPPROTO op_cmd_ge_T0_T1(void)
  87 +{
  88 + cond_t((int32_t) T0 <= (int32_t) T1);
  89 + RETURN();
  90 +}
  91 +
  92 +void OPPROTO op_cmd_hi_T0_T1(void)
  93 +{
  94 + cond_t((uint32_t) T0 < (uint32_t) T1);
  95 + RETURN();
  96 +}
  97 +
  98 +void OPPROTO op_cmd_gt_T0_T1(void)
  99 +{
  100 + cond_t((int32_t) T0 < (int32_t) T1);
  101 + RETURN();
  102 +}
  103 +
  104 +void OPPROTO op_not_T0(void)
  105 +{
  106 + T0 = ~T0;
  107 + RETURN();
  108 +}
  109 +
  110 +void OPPROTO op_bf_s(void)
  111 +{
  112 + T2 = ~env->sr;
  113 + env->delayed_pc = PARAM1;
  114 + set_flag(DELAY_SLOT_CONDITIONAL);
  115 + RETURN();
  116 +}
  117 +
  118 +void OPPROTO op_bt_s(void)
  119 +{
  120 + T2 = env->sr;
  121 + env->delayed_pc = PARAM1;
  122 + set_flag(DELAY_SLOT_CONDITIONAL);
  123 + RETURN();
  124 +}
  125 +
  126 +void OPPROTO op_bra(void)
  127 +{
  128 + env->delayed_pc = PARAM1;
  129 + set_flag(DELAY_SLOT);
  130 + RETURN();
  131 +}
  132 +
  133 +void OPPROTO op_braf_T0(void)
  134 +{
  135 + env->delayed_pc = PARAM1 + T0;
  136 + set_flag(DELAY_SLOT);
  137 + RETURN();
  138 +}
  139 +
  140 +void OPPROTO op_bsr(void)
  141 +{
  142 + env->pr = PARAM1;
  143 + env->delayed_pc = PARAM2;
  144 + set_flag(DELAY_SLOT);
  145 + RETURN();
  146 +}
  147 +
  148 +void OPPROTO op_bsrf_T0(void)
  149 +{
  150 + env->pr = PARAM1;
  151 + env->delayed_pc = PARAM1 + T0;
  152 + set_flag(DELAY_SLOT);
  153 + RETURN();
  154 +}
  155 +
  156 +void OPPROTO op_jsr_T0(void)
  157 +{
  158 + env->pr = PARAM1;
  159 + env->delayed_pc = T0;
  160 + set_flag(DELAY_SLOT);
  161 + RETURN();
  162 +}
  163 +
  164 +void OPPROTO op_rts(void)
  165 +{
  166 + env->delayed_pc = env->pr;
  167 + set_flag(DELAY_SLOT);
  168 + RETURN();
  169 +}
  170 +
  171 +void OPPROTO op_clr_delay_slot(void)
  172 +{
  173 + clr_flag(DELAY_SLOT);
  174 + RETURN();
  175 +}
  176 +
  177 +void OPPROTO op_clr_delay_slot_conditional(void)
  178 +{
  179 + clr_flag(DELAY_SLOT_CONDITIONAL);
  180 + RETURN();
  181 +}
  182 +
  183 +void OPPROTO op_exit_tb(void)
  184 +{
  185 + EXIT_TB();
  186 + RETURN();
  187 +}
  188 +
  189 +void OPPROTO op_addl_imm_T0(void)
  190 +{
  191 + T0 += PARAM1;
  192 + RETURN();
  193 +}
  194 +
  195 +void OPPROTO op_addl_imm_T1(void)
  196 +{
  197 + T1 += PARAM1;
  198 + RETURN();
  199 +}
  200 +
  201 +void OPPROTO op_clrmac(void)
  202 +{
  203 + env->mach = env->macl = 0;
  204 + RETURN();
  205 +}
  206 +
  207 +void OPPROTO op_clrs(void)
  208 +{
  209 + env->sr &= ~SR_S;
  210 + RETURN();
  211 +}
  212 +
  213 +void OPPROTO op_clrt(void)
  214 +{
  215 + env->sr &= ~SR_T;
  216 + RETURN();
  217 +}
  218 +
  219 +void OPPROTO op_sets(void)
  220 +{
  221 + env->sr |= SR_S;
  222 + RETURN();
  223 +}
  224 +
  225 +void OPPROTO op_sett(void)
  226 +{
  227 + env->sr |= SR_T;
  228 + RETURN();
  229 +}
  230 +
  231 +void OPPROTO op_rte(void)
  232 +{
  233 + env->sr = env->ssr;
  234 + env->delayed_pc = env->spc;
  235 + set_flag(DELAY_SLOT);
  236 + RETURN();
  237 +}
  238 +
  239 +void OPPROTO op_swapb_T0(void)
  240 +{
  241 + T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff);
  242 + RETURN();
  243 +}
  244 +
  245 +void OPPROTO op_swapw_T0(void)
  246 +{
  247 + T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff);
  248 + RETURN();
  249 +}
  250 +
  251 +void OPPROTO op_xtrct_T0_T1(void)
  252 +{
  253 + T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff);
  254 + RETURN();
  255 +}
  256 +
  257 +void OPPROTO op_addc_T0_T1(void)
  258 +{
  259 + helper_addc_T0_T1();
  260 + RETURN();
  261 +}
  262 +
  263 +void OPPROTO op_addv_T0_T1(void)
  264 +{
  265 + helper_addv_T0_T1();
  266 + RETURN();
  267 +}
  268 +
  269 +void OPPROTO op_cmp_eq_T0_T1(void)
  270 +{
  271 + cond_t(T1 == T0);
  272 + RETURN();
  273 +}
  274 +
  275 +void OPPROTO op_cmp_ge_T0_T1(void)
  276 +{
  277 + cond_t((int32_t) T1 >= (int32_t) T0);
  278 + RETURN();
  279 +}
  280 +
  281 +void OPPROTO op_cmp_gt_T0_T1(void)
  282 +{
  283 + cond_t((int32_t) T1 > (int32_t) T0);
  284 + RETURN();
  285 +}
  286 +
  287 +void OPPROTO op_cmp_hi_T0_T1(void)
  288 +{
  289 + cond_t((uint32_t) T1 > (uint32_t) T0);
  290 + RETURN();
  291 +}
  292 +
  293 +void OPPROTO op_cmp_hs_T0_T1(void)
  294 +{
  295 + cond_t((uint32_t) T1 >= (uint32_t) T0);
  296 + RETURN();
  297 +}
  298 +
  299 +void OPPROTO op_cmp_str_T0_T1(void)
  300 +{
  301 + cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) ||
  302 + (T0 & 0x0000ff00) == (T1 & 0x0000ff00) ||
  303 + (T0 & 0x00ff0000) == (T1 & 0x00ff0000) ||
  304 + (T0 & 0xff000000) == (T1 & 0xff000000));
  305 + RETURN();
  306 +}
  307 +
  308 +void OPPROTO op_tst_T0_T1(void)
  309 +{
  310 + cond_t((T1 & T0) == 0);
  311 + RETURN();
  312 +}
  313 +
  314 +void OPPROTO op_div0s_T0_T1(void)
  315 +{
  316 + if (T1 & 0x80000000)
  317 + env->sr |= SR_Q;
  318 + else
  319 + env->sr &= ~SR_Q;
  320 + if (T0 & 0x80000000)
  321 + env->sr |= SR_M;
  322 + else
  323 + env->sr &= ~SR_M;
  324 + cond_t((T1 ^ T0) & 0x80000000);
  325 + RETURN();
  326 +}
  327 +
  328 +void OPPROTO op_div0u(void)
  329 +{
  330 + env->sr &= ~(SR_M | SR_Q | SR_T);
  331 + RETURN();
  332 +}
  333 +
  334 +void OPPROTO op_div1_T0_T1(void)
  335 +{
  336 + helper_div1_T0_T1();
  337 + RETURN();
  338 +}
  339 +
  340 +void OPPROTO op_dmulsl_T0_T1(void)
  341 +{
  342 + helper_dmulsl_T0_T1();
  343 + RETURN();
  344 +}
  345 +
  346 +void OPPROTO op_dmulul_T0_T1(void)
  347 +{
  348 + helper_dmulul_T0_T1();
  349 + RETURN();
  350 +}
  351 +
  352 +void OPPROTO op_macl_T0_T1(void)
  353 +{
  354 + helper_macl_T0_T1();
  355 + RETURN();
  356 +}
  357 +
  358 +void OPPROTO op_macw_T0_T1(void)
  359 +{
  360 + helper_macw_T0_T1();
  361 + RETURN();
  362 +}
  363 +
  364 +void OPPROTO op_mull_T0_T1(void)
  365 +{
  366 + env->macl = (T0 * T1) & 0xffffffff;
  367 + RETURN();
  368 +}
  369 +
  370 +void OPPROTO op_mulsw_T0_T1(void)
  371 +{
  372 + env->macl = (int32_t) T0 *(int32_t) T1;
  373 + RETURN();
  374 +}
  375 +
  376 +void OPPROTO op_muluw_T0_T1(void)
  377 +{
  378 + env->macl = (uint32_t) T0 *(uint32_t) T1;
  379 + RETURN();
  380 +}
  381 +
  382 +void OPPROTO op_neg_T0(void)
  383 +{
  384 + T0 = -T0;
  385 + RETURN();
  386 +}
  387 +
  388 +void OPPROTO op_negc_T0(void)
  389 +{
  390 + helper_negc_T0();
  391 + RETURN();
  392 +}
  393 +
  394 +void OPPROTO op_shad_T0_T1(void)
  395 +{
  396 + if ((T0 & 0x80000000) == 0)
  397 + T1 <<= (T0 & 0x1f);
  398 + else if ((T0 & 0x1f) == 0)
  399 + T1 = 0;
  400 + else
  401 + T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1);
  402 + RETURN();
  403 +}
  404 +
  405 +void OPPROTO op_shld_T0_T1(void)
  406 +{
  407 + if ((T0 & 0x80000000) == 0)
  408 + T1 <<= (T0 & 0x1f);
  409 + else if ((T0 & 0x1f) == 0)
  410 + T1 = 0;
  411 + else
  412 + T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1);
  413 + RETURN();
  414 +}
  415 +
  416 +void OPPROTO op_subc_T0_T1(void)
  417 +{
  418 + helper_subc_T0_T1();
  419 + RETURN();
  420 +}
  421 +
  422 +void OPPROTO op_subv_T0_T1(void)
  423 +{
  424 + helper_subv_T0_T1();
  425 + RETURN();
  426 +}
  427 +
  428 +void OPPROTO op_trapa(void)
  429 +{
  430 + env->tra = PARAM1 * 2;
  431 + env->exception_index = 0x160;
  432 + do_raise_exception();
  433 + RETURN();
  434 +}
  435 +
  436 +void OPPROTO op_cmp_pl_T0(void)
  437 +{
  438 + cond_t((int32_t) T0 > 0);
  439 + RETURN();
  440 +}
  441 +
  442 +void OPPROTO op_cmp_pz_T0(void)
  443 +{
  444 + cond_t((int32_t) T0 >= 0);
  445 + RETURN();
  446 +}
  447 +
  448 +void OPPROTO op_jmp_T0(void)
  449 +{
  450 + env->delayed_pc = T0;
  451 + set_flag(DELAY_SLOT);
  452 + RETURN();
  453 +}
  454 +
  455 +void OPPROTO op_movl_rN_rN(void)
  456 +{
  457 + env->gregs[PARAM2] = env->gregs[PARAM1];
  458 + RETURN();
  459 +}
  460 +
  461 +void OPPROTO op_ldcl_rMplus_rN_bank(void)
  462 +{
  463 + env->gregs[PARAM2] = env->gregs[PARAM1];
  464 + env->gregs[PARAM1] += 4;
  465 + RETURN();
  466 +}
  467 +
  468 +#define LDSTOPS(target,load,store) \
  469 +void OPPROTO op_##load##_T0_##target (void) \
  470 +{ env ->target = T0; RETURN(); \
  471 +} \
  472 +void OPPROTO op_##store##_##target##_T0 (void) \
  473 +{ T0 = env->target; RETURN(); \
  474 +} \
  475 +
  476 +LDSTOPS(sr, ldc, stc)
  477 + LDSTOPS(gbr, ldc, stc)
  478 + LDSTOPS(vbr, ldc, stc)
  479 + LDSTOPS(ssr, ldc, stc)
  480 + LDSTOPS(spc, ldc, stc)
  481 + LDSTOPS(sgr, ldc, stc)
  482 + LDSTOPS(dbr, ldc, stc)
  483 + LDSTOPS(mach, lds, sts)
  484 + LDSTOPS(macl, lds, sts)
  485 + LDSTOPS(pr, lds, sts)
  486 +
  487 +void OPPROTO op_movt_rN(void)
  488 +{
  489 + env->gregs[PARAM1] = env->sr & SR_T;
  490 + RETURN();
  491 +}
  492 +
  493 +void OPPROTO op_rotcl_Rn(void)
  494 +{
  495 + helper_rotcl(&env->gregs[PARAM1]);
  496 + RETURN();
  497 +}
  498 +
  499 +void OPPROTO op_rotcr_Rn(void)
  500 +{
  501 + helper_rotcr(&env->gregs[PARAM1]);
  502 + RETURN();
  503 +}
  504 +
  505 +void OPPROTO op_rotl_Rn(void)
  506 +{
  507 + cond_t(env->gregs[PARAM1] & 0x80000000);
  508 + env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
  509 + RETURN();
  510 +}
  511 +
  512 +void OPPROTO op_rotr_Rn(void)
  513 +{
  514 + cond_t(env->gregs[PARAM1] & 1);
  515 + env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
  516 + ((env->sr & SR_T) ? 0x80000000 : 0);
  517 + RETURN();
  518 +}
  519 +
  520 +void OPPROTO op_shal_Rn(void)
  521 +{
  522 + cond_t(env->gregs[PARAM1] & 0x80000000);
  523 + env->gregs[PARAM1] <<= 1;
  524 + RETURN();
  525 +}
  526 +
  527 +void OPPROTO op_shar_Rn(void)
  528 +{
  529 + cond_t(env->gregs[PARAM1] & 1);
  530 + *(int32_t *) & env->gregs[PARAM1] >>= 1;
  531 + RETURN();
  532 +}
  533 +
  534 +void OPPROTO op_shlr_Rn(void)
  535 +{
  536 + cond_t(env->gregs[PARAM1] & 1);
  537 + *(uint32_t *) & env->gregs[PARAM1] >>= 1;
  538 + RETURN();
  539 +}
  540 +
  541 +void OPPROTO op_shll2_Rn(void)
  542 +{
  543 + env->gregs[PARAM1] <<= 2;
  544 + RETURN();
  545 +}
  546 +
  547 +void OPPROTO op_shll8_Rn(void)
  548 +{
  549 + env->gregs[PARAM1] <<= 8;
  550 + RETURN();
  551 +}
  552 +
  553 +void OPPROTO op_shll16_Rn(void)
  554 +{
  555 + env->gregs[PARAM1] <<= 16;
  556 + RETURN();
  557 +}
  558 +
  559 +void OPPROTO op_shlr2_Rn(void)
  560 +{
  561 + *(uint32_t *) & env->gregs[PARAM1] >>= 2;
  562 + RETURN();
  563 +}
  564 +
  565 +void OPPROTO op_shlr8_Rn(void)
  566 +{
  567 + *(uint32_t *) & env->gregs[PARAM1] >>= 8;
  568 + RETURN();
  569 +}
  570 +
  571 +void OPPROTO op_shlr16_Rn(void)
  572 +{
  573 + *(uint32_t *) & env->gregs[PARAM1] >>= 16;
  574 + RETURN();
  575 +}
  576 +
  577 +void OPPROTO op_tasb_rN(void)
  578 +{
  579 + cond_t(*(int8_t *) env->gregs[PARAM1] == 0);
  580 + *(int8_t *) env->gregs[PARAM1] |= 0x80;
  581 + RETURN();
  582 +}
  583 +
  584 +void OPPROTO op_movl_T0_rN(void)
  585 +{
  586 + env->gregs[PARAM1] = T0;
  587 + RETURN();
  588 +}
  589 +
  590 +void OPPROTO op_movl_T1_rN(void)
  591 +{
  592 + env->gregs[PARAM1] = T1;
  593 + RETURN();
  594 +}
  595 +
  596 +void OPPROTO op_movb_rN_T0(void)
  597 +{
  598 + T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
  599 + RETURN();
  600 +}
  601 +
  602 +void OPPROTO op_movub_rN_T0(void)
  603 +{
  604 + T0 = env->gregs[PARAM1] & 0xff;
  605 + RETURN();
  606 +}
  607 +
  608 +void OPPROTO op_movw_rN_T0(void)
  609 +{
  610 + T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
  611 + RETURN();
  612 +}
  613 +
  614 +void OPPROTO op_movuw_rN_T0(void)
  615 +{
  616 + T0 = env->gregs[PARAM1] & 0xffff;
  617 + RETURN();
  618 +}
  619 +
  620 +void OPPROTO op_movl_rN_T0(void)
  621 +{
  622 + T0 = env->gregs[PARAM1];
  623 + RETURN();
  624 +}
  625 +
  626 +void OPPROTO op_movb_rN_T1(void)
  627 +{
  628 + T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
  629 + RETURN();
  630 +}
  631 +
  632 +void OPPROTO op_movub_rN_T1(void)
  633 +{
  634 + T1 = env->gregs[PARAM1] & 0xff;
  635 + RETURN();
  636 +}
  637 +
  638 +void OPPROTO op_movw_rN_T1(void)
  639 +{
  640 + T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
  641 + RETURN();
  642 +}
  643 +
  644 +void OPPROTO op_movuw_rN_T1(void)
  645 +{
  646 + T1 = env->gregs[PARAM1] & 0xffff;
  647 + RETURN();
  648 +}
  649 +
  650 +void OPPROTO op_movl_rN_T1(void)
  651 +{
  652 + T1 = env->gregs[PARAM1];
  653 + RETURN();
  654 +}
  655 +
  656 +void OPPROTO op_movl_imm_rN(void)
  657 +{
  658 + env->gregs[PARAM2] = PARAM1;
  659 + RETURN();
  660 +}
  661 +
  662 +void OPPROTO op_dec1_rN(void)
  663 +{
  664 + env->gregs[PARAM1] -= 1;
  665 + RETURN();
  666 +}
  667 +
  668 +void OPPROTO op_dec2_rN(void)
  669 +{
  670 + env->gregs[PARAM1] -= 2;
  671 + RETURN();
  672 +}
  673 +
  674 +void OPPROTO op_dec4_rN(void)
  675 +{
  676 + env->gregs[PARAM1] -= 4;
  677 + RETURN();
  678 +}
  679 +
  680 +void OPPROTO op_inc1_rN(void)
  681 +{
  682 + env->gregs[PARAM1] += 1;
  683 + RETURN();
  684 +}
  685 +
  686 +void OPPROTO op_inc2_rN(void)
  687 +{
  688 + env->gregs[PARAM1] += 2;
  689 + RETURN();
  690 +}
  691 +
  692 +void OPPROTO op_inc4_rN(void)
  693 +{
  694 + env->gregs[PARAM1] += 4;
  695 + RETURN();
  696 +}
  697 +
  698 +void OPPROTO op_add_T0_rN(void)
  699 +{
  700 + env->gregs[PARAM1] += T0;
  701 + RETURN();
  702 +}
  703 +
  704 +void OPPROTO op_sub_T0_rN(void)
  705 +{
  706 + env->gregs[PARAM1] -= T0;
  707 + RETURN();
  708 +}
  709 +
  710 +void OPPROTO op_and_T0_rN(void)
  711 +{
  712 + env->gregs[PARAM1] &= T0;
  713 + RETURN();
  714 +}
  715 +
  716 +void OPPROTO op_or_T0_rN(void)
  717 +{
  718 + env->gregs[PARAM1] |= T0;
  719 + RETURN();
  720 +}
  721 +
  722 +void OPPROTO op_xor_T0_rN(void)
  723 +{
  724 + env->gregs[PARAM1] ^= T0;
  725 + RETURN();
  726 +}
  727 +
  728 +void OPPROTO op_add_rN_T0(void)
  729 +{
  730 + T0 += env->gregs[PARAM1];
  731 + RETURN();
  732 +}
  733 +
  734 +void OPPROTO op_add_rN_T1(void)
  735 +{
  736 + T1 += env->gregs[PARAM1];
  737 + RETURN();
  738 +}
  739 +
  740 +void OPPROTO op_add_imm_rN(void)
  741 +{
  742 + env->gregs[PARAM2] += PARAM1;
  743 + RETURN();
  744 +}
  745 +
  746 +void OPPROTO op_and_imm_rN(void)
  747 +{
  748 + env->gregs[PARAM2] &= PARAM1;
  749 + RETURN();
  750 +}
  751 +
  752 +void OPPROTO op_or_imm_rN(void)
  753 +{
  754 + env->gregs[PARAM2] |= PARAM1;
  755 + RETURN();
  756 +}
  757 +
  758 +void OPPROTO op_xor_imm_rN(void)
  759 +{
  760 + env->gregs[PARAM2] ^= PARAM1;
  761 + RETURN();
  762 +}
  763 +
  764 +void OPPROTO op_dt_rN(void)
  765 +{
  766 + cond_t((--env->gregs[PARAM1]) == 0);
  767 + RETURN();
  768 +}
  769 +
  770 +void OPPROTO op_tst_imm_rN(void)
  771 +{
  772 + cond_t((env->gregs[PARAM2] & PARAM1) == 0);
  773 + RETURN();
  774 +}
  775 +
  776 +void OPPROTO op_movl_T0_T1(void)
  777 +{
  778 + T1 = T0;
  779 + RETURN();
  780 +}
  781 +
  782 +void OPPROTO op_goto_tb0(void)
  783 +{
  784 + GOTO_TB(op_goto_tb0, PARAM1, 0);
  785 + RETURN();
  786 +}
  787 +
  788 +void OPPROTO op_goto_tb1(void)
  789 +{
  790 + GOTO_TB(op_goto_tb1, PARAM1, 1);
  791 + RETURN();
  792 +}
  793 +
  794 +void OPPROTO op_movl_imm_PC(void)
  795 +{
  796 + env->pc = PARAM1;
  797 + RETURN();
  798 +}
  799 +
  800 +void OPPROTO op_jT(void)
  801 +{
  802 + if (env->sr & SR_T)
  803 + GOTO_LABEL_PARAM(1);
  804 + RETURN();
  805 +}
  806 +
  807 +void OPPROTO op_jTT2(void)
  808 +{
  809 + if (T2 & SR_T)
  810 + GOTO_LABEL_PARAM(1);
  811 + RETURN();
  812 +}
  813 +
  814 +void OPPROTO op_movl_delayed_pc_PC(void)
  815 +{
  816 + env->pc = env->delayed_pc;
  817 + RETURN();
  818 +}
  819 +
  820 +void OPPROTO op_addl_GBR_T0(void)
  821 +{
  822 + T0 += env->gbr;
  823 + RETURN();
  824 +}
  825 +
  826 +void OPPROTO op_and_imm_T0(void)
  827 +{
  828 + T0 &= PARAM1;
  829 + RETURN();
  830 +}
  831 +
  832 +void OPPROTO op_or_imm_T0(void)
  833 +{
  834 + T0 |= PARAM1;
  835 + RETURN();
  836 +}
  837 +
  838 +void OPPROTO op_xor_imm_T0(void)
  839 +{
  840 + T0 ^= PARAM1;
  841 + RETURN();
  842 +}
  843 +
  844 +void OPPROTO op_tst_imm_T0(void)
  845 +{
  846 + cond_t((T0 & PARAM1) == 0);
  847 + RETURN();
  848 +}
  849 +
  850 +void OPPROTO op_raise_illegal_instruction(void)
  851 +{
  852 + env->exception_index = 0x180;
  853 + do_raise_exception();
  854 + RETURN();
  855 +}
  856 +
  857 +void OPPROTO op_raise_slot_illegal_instruction(void)
  858 +{
  859 + env->exception_index = 0x1a0;
  860 + do_raise_exception();
  861 + RETURN();
  862 +}
  863 +
  864 +void OPPROTO op_debug(void)
  865 +{
  866 + env->exception_index = EXCP_DEBUG;
  867 + cpu_loop_exit();
  868 +}
  869 +
  870 +/* Load and store */
  871 +#define MEMSUFFIX _raw
  872 +#include "op_mem.c"
  873 +#undef MEMSUFFIX
  874 +#if !defined(CONFIG_USER_ONLY)
  875 +#define MEMSUFFIX _user
  876 +#include "op_mem.c"
  877 +#undef MEMSUFFIX
  878 +
  879 +#define MEMSUFFIX _kernel
  880 +#include "op_mem.c"
  881 +#undef MEMSUFFIX
  882 +#endif
... ...