gwj / at91sam9263 · Commits

Commit fde7d5bd733fd64bdbf9600d1d5d83c96d004a62

Authored by ths
1 parent 5c2b87e3

Gallileo GT64xxx support, by Aurelien Jarno. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2318 c046a42c-6fe2-441c-8c8c-71466251a162
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hw/gt64xxx.c 0 → 100644
  View file @fde7d5b
  1 +/*
  2 + * QEMU GT64120 PCI host
  3 + *
  4 + * Copyright (c) 2006 Aurelien Jarno
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +
  25 +#include "vl.h"
  26 +typedef target_phys_addr_t pci_addr_t;
  27 +#include "pci_host.h"
  28 +
  29 +#define GT_REGS (0x1000 >> 2)
  30 +
  31 +/* CPU Configuration */
  32 +#define GT_CPU (0x000 >> 2)
  33 +#define GT_MULTI (0x120 >> 2)
  34 +
  35 +/* CPU Address Decode */
  36 +#define GT_SCS10LD (0x008 >> 2)
  37 +#define GT_SCS10HD (0x010 >> 2)
  38 +#define GT_SCS32LD (0x018 >> 2)
  39 +#define GT_SCS32HD (0x020 >> 2)
  40 +#define GT_CS20LD (0x028 >> 2)
  41 +#define GT_CS20HD (0x030 >> 2)
  42 +#define GT_CS3BOOTLD (0x038 >> 2)
  43 +#define GT_CS3BOOTHD (0x040 >> 2)
  44 +#define GT_PCI0IOLD (0x048 >> 2)
  45 +#define GT_PCI0IOHD (0x050 >> 2)
  46 +#define GT_PCI0M0LD (0x058 >> 2)
  47 +#define GT_PCI0M0HD (0x060 >> 2)
  48 +#define GT_ISD (0x068 >> 2)
  49 +
  50 +#define GT_PCI0M1LD (0x080 >> 2)
  51 +#define GT_PCI0M1HD (0x088 >> 2)
  52 +#define GT_PCI1IOLD (0x090 >> 2)
  53 +#define GT_PCI1IOHD (0x098 >> 2)
  54 +#define GT_PCI1M0LD (0x0a0 >> 2)
  55 +#define GT_PCI1M0HD (0x0a8 >> 2)
  56 +#define GT_PCI1M1LD (0x0b0 >> 2)
  57 +#define GT_PCI1M1HD (0x0b8 >> 2)
  58 +#define GT_PCI1M1LD (0x0b0 >> 2)
  59 +#define GT_PCI1M1HD (0x0b8 >> 2)
  60 +
  61 +#define GT_SCS10AR (0x0d0 >> 2)
  62 +#define GT_SCS32AR (0x0d8 >> 2)
  63 +#define GT_CS20R (0x0e0 >> 2)
  64 +#define GT_CS3BOOTR (0x0e8 >> 2)
  65 +
  66 +#define GT_PCI0IOREMAP (0x0f0 >> 2)
  67 +#define GT_PCI0M0REMAP (0x0f8 >> 2)
  68 +#define GT_PCI0M1REMAP (0x100 >> 2)
  69 +#define GT_PCI1IOREMAP (0x108 >> 2)
  70 +#define GT_PCI1M0REMAP (0x110 >> 2)
  71 +#define GT_PCI1M1REMAP (0x118 >> 2)
  72 +
  73 +/* CPU Error Report */
  74 +#define GT_CPUERR_ADDRLO (0x070 >> 2)
  75 +#define GT_CPUERR_ADDRHI (0x078 >> 2)
  76 +#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
  77 +#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
  78 +#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
  79 +
  80 +/* CPU Sync Barrier */
  81 +#define GT_PCI0SYNC (0x0c0 >> 2)
  82 +#define GT_PCI1SYNC (0x0c8 >> 2)
  83 +
  84 +/* SDRAM and Device Address Decode */
  85 +#define GT_SCS0LD (0x400 >> 2)
  86 +#define GT_SCS0HD (0x404 >> 2)
  87 +#define GT_SCS1LD (0x408 >> 2)
  88 +#define GT_SCS1HD (0x40c >> 2)
  89 +#define GT_SCS2LD (0x410 >> 2)
  90 +#define GT_SCS2HD (0x414 >> 2)
  91 +#define GT_SCS3LD (0x418 >> 2)
  92 +#define GT_SCS3HD (0x41c >> 2)
  93 +#define GT_CS0LD (0x420 >> 2)
  94 +#define GT_CS0HD (0x424 >> 2)
  95 +#define GT_CS1LD (0x428 >> 2)
  96 +#define GT_CS1HD (0x42c >> 2)
  97 +#define GT_CS2LD (0x430 >> 2)
  98 +#define GT_CS2HD (0x434 >> 2)
  99 +#define GT_CS3LD (0x438 >> 2)
  100 +#define GT_CS3HD (0x43c >> 2)
  101 +#define GT_BOOTLD (0x440 >> 2)
  102 +#define GT_BOOTHD (0x444 >> 2)
  103 +#define GT_ADERR (0x470 >> 2)
  104 +
  105 +/* SDRAM Configuration */
  106 +#define GT_SDRAM_CFG (0x448 >> 2)
  107 +#define GT_SDRAM_OPMODE (0x474 >> 2)
  108 +#define GT_SDRAM_BM (0x478 >> 2)
  109 +#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
  110 +
  111 +/* SDRAM Parameters */
  112 +#define GT_SDRAM_B0 (0x44c >> 2)
  113 +#define GT_SDRAM_B1 (0x450 >> 2)
  114 +#define GT_SDRAM_B2 (0x454 >> 2)
  115 +#define GT_SDRAM_B3 (0x458 >> 2)
  116 +
  117 +/* Device Parameters */
  118 +#define GT_DEV_B0 (0x45c >> 2)
  119 +#define GT_DEV_B1 (0x460 >> 2)
  120 +#define GT_DEV_B2 (0x464 >> 2)
  121 +#define GT_DEV_B3 (0x468 >> 2)
  122 +#define GT_DEV_BOOT (0x46c >> 2)
  123 +
  124 +/* ECC */
  125 +#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
  126 +#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
  127 +#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
  128 +#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
  129 +#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
  130 +
  131 +/* DMA Record */
  132 +#define GT_DMA0_CNT (0x800 >> 2)
  133 +#define GT_DMA1_CNT (0x804 >> 2)
  134 +#define GT_DMA2_CNT (0x808 >> 2)
  135 +#define GT_DMA3_CNT (0x80c >> 2)
  136 +#define GT_DMA0_SA (0x810 >> 2)
  137 +#define GT_DMA1_SA (0x814 >> 2)
  138 +#define GT_DMA2_SA (0x818 >> 2)
  139 +#define GT_DMA3_SA (0x81c >> 2)
  140 +#define GT_DMA0_DA (0x820 >> 2)
  141 +#define GT_DMA1_DA (0x824 >> 2)
  142 +#define GT_DMA2_DA (0x828 >> 2)
  143 +#define GT_DMA3_DA (0x82c >> 2)
  144 +#define GT_DMA0_NEXT (0x830 >> 2)
  145 +#define GT_DMA1_NEXT (0x834 >> 2)
  146 +#define GT_DMA2_NEXT (0x838 >> 2)
  147 +#define GT_DMA3_NEXT (0x83c >> 2)
  148 +#define GT_DMA0_CUR (0x870 >> 2)
  149 +#define GT_DMA1_CUR (0x874 >> 2)
  150 +#define GT_DMA2_CUR (0x878 >> 2)
  151 +#define GT_DMA3_CUR (0x87c >> 2)
  152 +
  153 +/* DMA Channel Control */
  154 +#define GT_DMA0_CTRL (0x840 >> 2)
  155 +#define GT_DMA1_CTRL (0x844 >> 2)
  156 +#define GT_DMA2_CTRL (0x848 >> 2)
  157 +#define GT_DMA3_CTRL (0x84c >> 2)
  158 +
  159 +/* DMA Arbiter */
  160 +#define GT_DMA_ARB (0x860 >> 2)
  161 +
  162 +/* Timer/Counter */
  163 +#define GT_TC0 (0x850 >> 2)
  164 +#define GT_TC1 (0x854 >> 2)
  165 +#define GT_TC2 (0x858 >> 2)
  166 +#define GT_TC3 (0x85c >> 2)
  167 +#define GT_TC_CONTROL (0x864 >> 2)
  168 +
  169 +/* PCI Internal */
  170 +#define GT_PCI0_CMD (0xc00 >> 2)
  171 +#define GT_PCI0_TOR (0xc04 >> 2)
  172 +#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
  173 +#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
  174 +#define GT_PCI0_BS_CS20 (0xc10 >> 2)
  175 +#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
  176 +#define GT_PCI1_IACK (0xc30 >> 2)
  177 +#define GT_PCI0_IACK (0xc34 >> 2)
  178 +#define GT_PCI0_BARE (0xc3c >> 2)
  179 +#define GT_PCI0_PREFMBR (0xc40 >> 2)
  180 +#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
  181 +#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
  182 +#define GT_PCI0_CS20_BAR (0xc50 >> 2)
  183 +#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
  184 +#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
  185 +#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
  186 +#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
  187 +#define GT_PCI1_CMD (0xc80 >> 2)
  188 +#define GT_PCI1_TOR (0xc84 >> 2)
  189 +#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
  190 +#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
  191 +#define GT_PCI1_BS_CS20 (0xc90 >> 2)
  192 +#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
  193 +#define GT_PCI1_BARE (0xcbc >> 2)
  194 +#define GT_PCI1_PREFMBR (0xcc0 >> 2)
  195 +#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
  196 +#define GT_PCI1_SCS32_BAR (0xccc >> 2)
  197 +#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
  198 +#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
  199 +#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
  200 +#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
  201 +#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
  202 +#define GT_PCI1_CFGADDR (0xcf0 >> 2)
  203 +#define GT_PCI1_CFGDATA (0xcf4 >> 2)
  204 +#define GT_PCI0_CFGADDR (0xcf8 >> 2)
  205 +#define GT_PCI0_CFGDATA (0xcfc >> 2)
  206 +
  207 +/* Interrupts */
  208 +#define GT_INTRCAUSE (0xc18 >> 2)
  209 +#define GT_INTRMASK (0xc1c >> 2)
  210 +#define GT_PCI0_ICMASK (0xc24 >> 2)
  211 +#define GT_PCI0_SERR0MASK (0xc28 >> 2)
  212 +#define GT_CPU_INTSEL (0xc70 >> 2)
  213 +#define GT_PCI0_INTSEL (0xc74 >> 2)
  214 +#define GT_HINTRCAUSE (0xc98 >> 2)
  215 +#define GT_HINTRMASK (0xc9c >> 2)
  216 +#define GT_PCI0_HICMASK (0xca4 >> 2)
  217 +#define GT_PCI1_SERR1MASK (0xca8 >> 2)
  218 +
  219 +
  220 +typedef PCIHostState GT64120PCIState;
  221 +
  222 +typedef struct GT64120State {
  223 + GT64120PCIState *pci;
  224 + uint32_t regs[GT_REGS];
  225 +} GT64120State;
  226 +
  227 +static void gt64120_pci_mapping(GT64120State *s)
  228 +{
  229 + target_phys_addr_t start, length;
  230 +
  231 + /* Update IO mapping */
  232 + start = s->regs[GT_PCI0IOLD] << 21;
  233 + length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
  234 + isa_mmio_init(start, length);
  235 +}
  236 +
  237 +static void gt64120_writel (void *opaque, target_phys_addr_t addr,
  238 + uint32_t val)
  239 +{
  240 + GT64120State *s = opaque;
  241 + uint32_t saddr;
  242 +
  243 + saddr = (addr & 0xfff) >> 2;
  244 + switch (saddr) {
  245 + /* CPU Configuration Register */
  246 + case GT_CPU:
  247 + s->regs[GT_CPU] = val;
  248 + gt64120_pci_mapping(s);
  249 + break;
  250 + case GT_MULTI:
  251 + break;
  252 +
  253 + /* CPU Address Decode */
  254 + case GT_PCI0IOLD:
  255 + s->regs[GT_PCI0IOLD] = val & 0x00007fff;
  256 + s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
  257 + gt64120_pci_mapping(s);
  258 + break;
  259 + case GT_PCI0M0LD:
  260 + s->regs[GT_PCI0M0LD] = val & 0x00007fff;
  261 + s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
  262 + gt64120_pci_mapping(s);
  263 + break;
  264 + case GT_PCI0M1LD:
  265 + s->regs[GT_PCI0M1LD] = val & 0x00007fff;
  266 + s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
  267 + gt64120_pci_mapping(s);
  268 + break;
  269 + case GT_PCI1IOLD:
  270 + s->regs[GT_PCI1IOLD] = val & 0x00007fff;
  271 + s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
  272 + gt64120_pci_mapping(s);
  273 + break;
  274 + case GT_PCI1M0LD:
  275 + s->regs[GT_PCI1M0LD] = val & 0x00007fff;
  276 + s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
  277 + gt64120_pci_mapping(s);
  278 + break;
  279 + case GT_PCI1M1LD:
  280 + s->regs[GT_PCI1M1LD] = val & 0x00007fff;
  281 + s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
  282 + gt64120_pci_mapping(s);
  283 + break;
  284 + case GT_PCI0IOHD:
  285 + case GT_PCI0M0HD:
  286 + case GT_PCI0M1HD:
  287 + case GT_PCI1IOHD:
  288 + case GT_PCI1M0HD:
  289 + case GT_PCI1M1HD:
  290 + s->regs[saddr] = val & 0x0000007f;
  291 + gt64120_pci_mapping(s);
  292 + break;
  293 + case GT_PCI0IOREMAP:
  294 + case GT_PCI0M0REMAP:
  295 + case GT_PCI0M1REMAP:
  296 + case GT_PCI1IOREMAP:
  297 + case GT_PCI1M0REMAP:
  298 + case GT_PCI1M1REMAP:
  299 + s->regs[saddr] = val & 0x000007ff;
  300 + gt64120_pci_mapping(s);
  301 + break;
  302 +
  303 + /* CPU Error Report */
  304 + case GT_CPUERR_ADDRLO:
  305 + case GT_CPUERR_ADDRHI:
  306 + case GT_CPUERR_DATALO:
  307 + case GT_CPUERR_DATAHI:
  308 + case GT_CPUERR_PARITY:
  309 + break;
  310 +
  311 + /* ECC */
  312 + case GT_ECC_ERRDATALO:
  313 + case GT_ECC_ERRDATAHI:
  314 + case GT_ECC_MEM:
  315 + case GT_ECC_CALC:
  316 + case GT_ECC_ERRADDR:
  317 + break;
  318 +
  319 + /* PCI Internal */
  320 + case GT_PCI0_CMD:
  321 + case GT_PCI1_CMD:
  322 + s->regs[saddr] = val & 0x0401fc0f;
  323 + break;
  324 + case GT_PCI0_CFGADDR:
  325 + s->pci->config_reg = val & 0x80fffffc;
  326 + break;
  327 + case GT_PCI0_CFGDATA:
  328 + pci_host_data_writel(s->pci, 0, val);
  329 + break;
  330 +
  331 + default:
  332 +#if 0
  333 + printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
  334 +#endif
  335 + break;
  336 + }
  337 +}
  338 +
  339 +static uint32_t gt64120_readl (void *opaque,
  340 + target_phys_addr_t addr)
  341 +{
  342 + GT64120State *s = opaque;
  343 + uint32_t val;
  344 + uint32_t saddr;
  345 +
  346 + val = 0;
  347 + saddr = (addr & 0xfff) >> 2;
  348 +
  349 + switch (saddr) {
  350 +
  351 + /* CPU Error Report */
  352 + case GT_CPUERR_ADDRLO:
  353 + case GT_CPUERR_ADDRHI:
  354 + case GT_CPUERR_DATALO:
  355 + case GT_CPUERR_DATAHI:
  356 + case GT_CPUERR_PARITY:
  357 + return 0;
  358 + break;
  359 +
  360 + /* ECC */
  361 + case GT_ECC_ERRDATALO:
  362 + case GT_ECC_ERRDATAHI:
  363 + case GT_ECC_MEM:
  364 + case GT_ECC_CALC:
  365 + case GT_ECC_ERRADDR:
  366 + return 0;
  367 + break;
  368 +
  369 + case GT_CPU:
  370 + case GT_MULTI:
  371 + case GT_PCI0IOLD:
  372 + case GT_PCI0M0LD:
  373 + case GT_PCI0M1LD:
  374 + case GT_PCI1IOLD:
  375 + case GT_PCI1M0LD:
  376 + case GT_PCI1M1LD:
  377 + case GT_PCI0IOHD:
  378 + case GT_PCI0M0HD:
  379 + case GT_PCI0M1HD:
  380 + case GT_PCI1IOHD:
  381 + case GT_PCI1M0HD:
  382 + case GT_PCI1M1HD:
  383 + case GT_PCI0_CMD:
  384 + case GT_PCI1_CMD:
  385 + case GT_PCI0IOREMAP:
  386 + case GT_PCI0M0REMAP:
  387 + case GT_PCI0M1REMAP:
  388 + case GT_PCI1IOREMAP:
  389 + case GT_PCI1M0REMAP:
  390 + case GT_PCI1M1REMAP:
  391 + val = s->regs[saddr];
  392 + break;
  393 + case GT_PCI0_IACK:
  394 + val = pic_intack_read(isa_pic);
  395 + break;
  396 +
  397 + /* PCI Internal */
  398 + case GT_PCI0_CFGADDR:
  399 + val = s->pci->config_reg;
  400 + break;
  401 + case GT_PCI0_CFGDATA:
  402 + val = pci_host_data_readl(s->pci, 0);
  403 + break;
  404 +
  405 + default:
  406 + val = s->regs[saddr];
  407 +#if 0
  408 + printf ("gt64120_readl: Bad register offset 0x%x\n", (int)addr);
  409 +#endif
  410 + break;
  411 + }
  412 +
  413 + return val;
  414 +}
  415 +
  416 +static CPUWriteMemoryFunc *gt64120_write[] = {
  417 + &gt64120_writel,
  418 + &gt64120_writel,
  419 + &gt64120_writel,
  420 +};
  421 +
  422 +static CPUReadMemoryFunc *gt64120_read[] = {
  423 + &gt64120_readl,
  424 + &gt64120_readl,
  425 + &gt64120_readl,
  426 +};
  427 +
  428 +static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
  429 +{
  430 + int slot;
  431 +
  432 + slot = (pci_dev->devfn >> 3);
  433 +
  434 + switch (slot) {
  435 + /* PIIX4 USB */
  436 + case 10:
  437 + return 3;
  438 + /* AMD 79C973 Ethernet */
  439 + case 11:
  440 + return 0;
  441 + /* Crystal 4281 Sound */
  442 + case 12:
  443 + return 0;
  444 + /* PCI slot 1 to 4 */
  445 + case 18 ... 21:
  446 + return ((slot - 18) + irq_num) & 0x03;
  447 + /* Unknown device, don't do any translation */
  448 + default:
  449 + return irq_num;
  450 + }
  451 +}
  452 +
  453 +extern PCIDevice *piix4_dev;
  454 +static int pci_irq_levels[4];
  455 +
  456 +static void pci_gt64120_set_irq(void *pic, int irq_num, int level)
  457 +{
  458 + int i, pic_irq, pic_level;
  459 +
  460 + pci_irq_levels[irq_num] = level;
  461 +
  462 + /* now we change the pic irq level according to the piix irq mappings */
  463 + /* XXX: optimize */
  464 + pic_irq = piix4_dev->config[0x60 + irq_num];
  465 + if (pic_irq < 16) {
  466 + /* The pic level is the logical OR of all the PCI irqs mapped
  467 + to it */
  468 + pic_level = 0;
  469 + for (i = 0; i < 4; i++) {
  470 + if (pic_irq == piix4_dev->config[0x60 + i])
  471 + pic_level |= pci_irq_levels[i];
  472 + }
  473 + pic_set_irq(pic_irq, pic_level);
  474 + }
  475 +}
  476 +
  477 +
  478 +void gt64120_reset(void *opaque)
  479 +{
  480 + GT64120State *s = opaque;
  481 +
  482 + /* CPU Configuration */
  483 +#ifdef TARGET_WORDS_BIGENDIAN
  484 + s->regs[GT_CPU] = 0x00000000;
  485 +#else
  486 + s->regs[GT_CPU] = 0x00000800;
  487 +#endif
  488 + s->regs[GT_MULTI] = 0x00000000;
  489 +
  490 + /* CPU Address decode FIXME: not complete*/
  491 + s->regs[GT_PCI0IOLD] = 0x00000080;
  492 + s->regs[GT_PCI0IOHD] = 0x0000000f;
  493 + s->regs[GT_PCI0M0LD] = 0x00000090;
  494 + s->regs[GT_PCI0M0HD] = 0x0000001f;
  495 + s->regs[GT_PCI0M1LD] = 0x00000790;
  496 + s->regs[GT_PCI0M1HD] = 0x0000001f;
  497 + s->regs[GT_PCI1IOLD] = 0x00000100;
  498 + s->regs[GT_PCI1IOHD] = 0x0000000f;
  499 + s->regs[GT_PCI1M0LD] = 0x00000110;
  500 + s->regs[GT_PCI1M0HD] = 0x0000001f;
  501 + s->regs[GT_PCI1M1LD] = 0x00000120;
  502 + s->regs[GT_PCI1M1HD] = 0x0000002f;
  503 + s->regs[GT_PCI0IOREMAP] = 0x00000080;
  504 + s->regs[GT_PCI0M0REMAP] = 0x00000090;
  505 + s->regs[GT_PCI0M1REMAP] = 0x00000790;
  506 + s->regs[GT_PCI1IOREMAP] = 0x00000100;
  507 + s->regs[GT_PCI1M0REMAP] = 0x00000110;
  508 + s->regs[GT_PCI1M1REMAP] = 0x00000120;
  509 +
  510 + /* CPU Error Report */
  511 + s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
  512 + s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
  513 + s->regs[GT_CPUERR_DATALO] = 0xffffffff;
  514 + s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
  515 + s->regs[GT_CPUERR_PARITY] = 0x000000ff;
  516 +
  517 + /* ECC */
  518 + s->regs[GT_ECC_ERRDATALO] = 0x00000000;
  519 + s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
  520 + s->regs[GT_ECC_MEM] = 0x00000000;
  521 + s->regs[GT_ECC_CALC] = 0x00000000;
  522 + s->regs[GT_ECC_ERRADDR] = 0x00000000;
  523 +
  524 + /* PCI Internal FIXME: not complete*/
  525 +#ifdef TARGET_WORDS_BIGENDIAN
  526 + s->regs[GT_PCI0_CMD] = 0x00000000;
  527 + s->regs[GT_PCI1_CMD] = 0x00000000;
  528 +#else
  529 + s->regs[GT_PCI0_CMD] = 0x00010001;
  530 + s->regs[GT_PCI1_CMD] = 0x00010001;
  531 +#endif
  532 + s->regs[GT_PCI0_IACK] = 0x00000000;
  533 + s->regs[GT_PCI1_IACK] = 0x00000000;
  534 +
  535 + gt64120_pci_mapping(s);
  536 +}
  537 +
  538 +PCIBus *pci_gt64120_init(void *pic)
  539 +{
  540 + GT64120State *s;
  541 + PCIDevice *d;
  542 + int gt64120;
  543 +
  544 + s = qemu_mallocz(sizeof(GT64120State));
  545 + s->pci = qemu_mallocz(sizeof(GT64120PCIState));
  546 + gt64120_reset(s);
  547 +
  548 + s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
  549 + pic, 144, 4);
  550 +
  551 + gt64120 = cpu_register_io_memory(0, gt64120_read,
  552 + gt64120_write, s);
  553 + cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120);
  554 +
  555 + d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
  556 + 0, NULL, NULL);
  557 +
  558 + d->config[0x00] = 0xab; // vendor_id
  559 + d->config[0x01] = 0x11;
  560 + d->config[0x02] = 0x46; // device_id
  561 + d->config[0x03] = 0x20;
  562 + d->config[0x04] = 0x06;
  563 + d->config[0x05] = 0x00;
  564 + d->config[0x06] = 0x80;
  565 + d->config[0x07] = 0xa2;
  566 + d->config[0x08] = 0x10;
  567 + d->config[0x09] = 0x00;
  568 + d->config[0x0A] = 0x80;
  569 + d->config[0x0B] = 0x05;
  570 + d->config[0x0C] = 0x08;
  571 + d->config[0x0D] = 0x40;
  572 + d->config[0x0E] = 0x00;
  573 + d->config[0x0F] = 0x00;
  574 + d->config[0x17] = 0x08;
  575 + d->config[0x1B] = 0x1c;
  576 + d->config[0x1F] = 0x1f;
  577 + d->config[0x23] = 0x14;
  578 + d->config[0x27] = 0x14;
  579 + d->config[0x3D] = 0x01;
  580 +
  581 + return s->pci->bus;
  582 +}
@@ -835,6 +835,9 @@ typedef struct HeathrowPICS HeathrowPICS; @@ -835,6 +835,9 @@ typedef struct HeathrowPICS HeathrowPICS;
835 void heathrow_pic_set_irq(void *opaque, int num, int level); 835 void heathrow_pic_set_irq(void *opaque, int num, int level);
836 HeathrowPICS *heathrow_pic_init(int *pmem_index); 836 HeathrowPICS *heathrow_pic_init(int *pmem_index);
837 837
  838 +/* gt64xxx.c */
  839 +PCIBus *pci_gt64120_init(void *pic);
  840 +
838 #ifdef HAS_AUDIO 841 #ifdef HAS_AUDIO
839 struct soundhw { 842 struct soundhw {
840 const char *name; 843 const char *name;