gwj / at91sam9263 · Commits

Commit fdce4963ea58ec2405e87b2edf96f8c93275d919

Authored by aurel32
1 parent 0045734a

target-ppc: use the new subfi wrapper 

(...and fix rldnm)

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5600 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 4 additions and 8 deletions
target-ppc/translate.c
  View file @fdce496
@@ -1747,7 +1747,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) @@ -1747,7 +1747,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1747 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) 1747 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1748 { 1748 {
1749 uint32_t mb, me; 1749 uint32_t mb, me;
1750 - TCGv t0, t1, t2, t3; 1750 + TCGv t0, t1, t2;
1751 1751
1752 mb = MB(ctx->opcode); 1752 mb = MB(ctx->opcode);
1753 me = ME(ctx->opcode); 1753 me = ME(ctx->opcode);
@@ -1757,9 +1757,7 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) @@ -1757,9 +1757,7 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1757 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); 1757 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1758 t2 = tcg_temp_new(TCG_TYPE_TL); 1758 t2 = tcg_temp_new(TCG_TYPE_TL);
1759 tcg_gen_shl_tl(t2, t1, t0); 1759 tcg_gen_shl_tl(t2, t1, t0);
1760 - t3 = tcg_const_tl(32);  
1761 - tcg_gen_sub_tl(t0, t3, t0);  
1762 - tcg_temp_free(t3); 1760 + tcg_gen_subfi_tl(t0, 32, t0);
1763 tcg_gen_shr_tl(t1, t1, t0); 1761 tcg_gen_shr_tl(t1, t1, t0);
1764 tcg_temp_free(t0); 1762 tcg_temp_free(t0);
1765 tcg_gen_or_tl(t2, t2, t1); 1763 tcg_gen_or_tl(t2, t2, t1);
@@ -1872,7 +1870,7 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04); @@ -1872,7 +1870,7 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04);
1872 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, 1870 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1873 uint32_t me) 1871 uint32_t me)
1874 { 1872 {
1875 - TCGv t0, t1, t2; 1873 + TCGv t0, t1;
1876 1874
1877 mb = MB(ctx->opcode); 1875 mb = MB(ctx->opcode);
1878 me = ME(ctx->opcode); 1876 me = ME(ctx->opcode);
@@ -1880,9 +1878,7 @@ static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, @@ -1880,9 +1878,7 @@ static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1880 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); 1878 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1881 t1 = tcg_temp_new(TCG_TYPE_TL); 1879 t1 = tcg_temp_new(TCG_TYPE_TL);
1882 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t0); 1880 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t0);
1883 - t2 = tcg_const_tl(32);  
1884 - tcg_gen_sub_tl(t0, t2, t0);  
1885 - tcg_temp_free(t2); 1881 + tcg_gen_subfi_tl(t0, 64, t0);
1886 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 1882 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1887 tcg_gen_or_tl(t1, t1, t0); 1883 tcg_gen_or_tl(t1, t1, t0);
1888 tcg_temp_free(t0); 1884 tcg_temp_free(t0);