gwj / at91sam9263 · Commits

Commit fd6dc90ba0932f082ac8284cc957dd7efd89d014

Authored by Edgar E. Iglesias
1 parent 96d7ddde

cris: First shot at qdev for CRIS interrupts. 

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Inline Side-by-side
Showing 6 changed files with 114 additions and 48 deletions
Makefile.target
  View file @fd6dc90
... ... @@ -615,7 +615,7 @@ CPPFLAGS += -DHAS_AUDIO -DHAS_AUDIO_CHOICE
615 615 endif
616 616 ifeq ($(TARGET_BASE_ARCH), cris)
617 617 # Boards
618   -OBJS+= etraxfs.o axis_dev88.o
  618 +OBJS+= cris_pic_cpu.o etraxfs.o axis_dev88.o
619 619  
620 620 # IO blocks
621 621 OBJS+= etraxfs_dma.o
... ...
hw/axis_dev88.c
  View file @fd6dc90
... ... @@ -254,7 +254,9 @@ void axisdev88_init (ram_addr_t ram_size,
254 254 const char *initrd_filename, const char *cpu_model)
255 255 {
256 256 CPUState *env;
257   - qemu_irq *irq, *nmi;
  257 + DeviceState *dev;
  258 + SysBusDevice *s;
  259 + qemu_irq irq[30], nmi[2], *cpu_irq;
258 260 void *etraxfs_dmac;
259 261 struct etraxfs_dma_client *eth[2] = {NULL, NULL};
260 262 int kernel_size;
... ... @@ -292,8 +294,20 @@ void axisdev88_init (ram_addr_t ram_size,
292 294 cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
293 295  
294 296  
295   - irq = etraxfs_pic_init(env, 0x3001c000);
296   - nmi = irq + 30;
  297 + cpu_irq = cris_pic_init_cpu(env);
  298 + dev = qdev_create(NULL, "etraxfs,pic");
  299 + /* FIXME: Is there a proper way to signal vectors to the CPU core? */
  300 + qdev_set_prop_ptr(dev, "interrupt_vector", &env->interrupt_vector);
  301 + qdev_init(dev);
  302 + s = sysbus_from_qdev(dev);
  303 + sysbus_mmio_map(s, 0, 0x3001c000);
  304 + sysbus_connect_irq(s, 0, cpu_irq[0]);
  305 + sysbus_connect_irq(s, 1, cpu_irq[1]);
  306 + for (i = 0; i < 30; i++) {
  307 + irq[i] = qdev_get_irq_sink(dev, i);
  308 + }
  309 + nmi[0] = qdev_get_irq_sink(dev, 30);
  310 + nmi[1] = qdev_get_irq_sink(dev, 31);
297 311  
298 312 etraxfs_dmac = etraxfs_dmac_init(env, 0x30000000, 10);
299 313 for (i = 0; i < 10; i++) {
... ...
hw/cris_pic_cpu.c 0 → 100644
  View file @fd6dc90
  1 +/*
  2 + * QEMU CRIS CPU interrupt wrapper logic.
  3 + *
  4 + * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +
  25 +#include "hw.h"
  26 +#include "pc.h"
  27 +#include "etraxfs.h"
  28 +
  29 +#define D(x)
  30 +
  31 +void pic_info(Monitor *mon)
  32 +{}
  33 +void irq_info(Monitor *mon)
  34 +{}
  35 +
  36 +static void cris_pic_cpu_handler(void *opaque, int irq, int level)
  37 +{
  38 + CPUState *env = (CPUState *)opaque;
  39 + int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
  40 +
  41 + if (level)
  42 + cpu_interrupt(env, type);
  43 + else
  44 + cpu_reset_interrupt(env, type);
  45 +}
  46 +
  47 +qemu_irq *cris_pic_init_cpu(CPUState *env)
  48 +{
  49 + return qemu_allocate_irqs(cris_pic_cpu_handler, env, 2);
  50 +}
... ...
hw/etraxfs.c
  View file @fd6dc90
... ... @@ -48,8 +48,9 @@ void bareetraxfs_init (ram_addr_t ram_size,
48 48 const char *kernel_filename, const char *kernel_cmdline,
49 49 const char *initrd_filename, const char *cpu_model)
50 50 {
  51 + DeviceState *dev;
51 52 CPUState *env;
52   - qemu_irq *irq, *nmi;
  53 + qemu_irq irq[30], nmi[2], *cpu_irq;
53 54 void *etraxfs_dmac;
54 55 struct etraxfs_dma_client *eth[2] = {NULL, NULL};
55 56 int kernel_size;
... ... @@ -83,8 +84,16 @@ void bareetraxfs_init (ram_addr_t ram_size,
83 84 FLASH_SIZE >> 16,
84 85 1, 2, 0x0000, 0x0000, 0x0000, 0x0000,
85 86 0x555, 0x2aa);
86   - irq = etraxfs_pic_init(env, 0x3001c000);
87   - nmi = irq + 30;
  87 + cpu_irq = cris_pic_init_cpu(env);
  88 + dev = sysbus_create_varargs("etraxfs,pic", 0x3001c000,
  89 + cpu_irq[0], cpu_irq[1], NULL);
  90 + /* FIXME: Is there a proper way to signal vectors to the CPU core? */
  91 + qdev_set_prop_ptr(dev, "interrupt_vector", &env->interrupt_vector);
  92 + for (i = 0; i < 30; i++) {
  93 + irq[i] = qdev_get_irq_sink(dev, i);
  94 + }
  95 + nmi[0] = qdev_get_irq_sink(dev, 30);
  96 + nmi[1] = qdev_get_irq_sink(dev, 31);
88 97  
89 98 etraxfs_dmac = etraxfs_dmac_init(env, 0x30000000, 10);
90 99 for (i = 0; i < 10; i++) {
... ...
hw/etraxfs.h
  View file @fd6dc90
... ... @@ -24,6 +24,6 @@
24 24  
25 25 #include "etraxfs_dma.h"
26 26  
27   -qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base);
  27 +qemu_irq *cris_pic_init_cpu(CPUState *env);
28 28 void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
29 29 target_phys_addr_t base, int phyaddr);
... ...
hw/etraxfs_pic.c
  View file @fd6dc90
... ... @@ -22,7 +22,7 @@
22 22 * THE SOFTWARE.
23 23 */
24 24  
25   -#include <stdio.h>
  25 +#include "sysbus.h"
26 26 #include "hw.h"
27 27 #include "pc.h"
28 28 #include "etraxfs.h"
... ... @@ -36,15 +36,17 @@
36 36 #define R_R_GURU 4
37 37 #define R_MAX 5
38 38  
39   -struct fs_pic_state
  39 +struct etrax_pic
40 40 {
41   - CPUState *env;
  41 + SysBusDevice busdev;
  42 + uint32_t *interrupt_vector;
  43 + qemu_irq parent_irq;
  44 + qemu_irq parent_nmi;
42 45 uint32_t regs[R_MAX];
43 46 };
44 47  
45   -static void pic_update(struct fs_pic_state *fs)
  48 +static void pic_update(struct etrax_pic *fs)
46 49 {
47   - CPUState *env = fs->env;
48 50 uint32_t vector = 0;
49 51 int i;
50 52  
... ... @@ -66,21 +68,17 @@ static void pic_update(struct fs_pic_state *fs)
66 68 }
67 69 mv >>= 1;
68 70 }
69   - if (vector) {
70   - env->interrupt_vector = vector;
71   - D(printf("%s vector=%x\n", __func__, vector));
72   - cpu_interrupt(env, CPU_INTERRUPT_HARD);
73   - }
74   - } else {
75   - env->interrupt_vector = 0;
76   - cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
77   - D(printf("%s reset irqs\n", __func__));
78 71 }
  72 +
  73 + if (fs->interrupt_vector) {
  74 + *fs->interrupt_vector = vector;
  75 + }
  76 + qemu_set_irq(fs->parent_irq, !!vector);
79 77 }
80 78  
81 79 static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
82 80 {
83   - struct fs_pic_state *fs = opaque;
  81 + struct etrax_pic *fs = opaque;
84 82 uint32_t rval;
85 83  
86 84 rval = fs->regs[addr >> 2];
... ... @@ -91,7 +89,7 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
91 89 static void
92 90 pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
93 91 {
94   - struct fs_pic_state *fs = opaque;
  92 + struct etrax_pic *fs = opaque;
95 93 D(printf("%s addr=%x val=%x\n", __func__, addr, value));
96 94  
97 95 if (addr == R_RW_MASK) {
... ... @@ -110,18 +108,9 @@ static CPUWriteMemoryFunc *pic_write[] = {
110 108 &pic_writel,
111 109 };
112 110  
113   -void pic_info(Monitor *mon)
114   -{
115   -}
116   -
117   -void irq_info(Monitor *mon)
118   -{
119   -}
120   -
121 111 static void nmi_handler(void *opaque, int irq, int level)
122 112 {
123   - struct fs_pic_state *fs = (void *)opaque;
124   - CPUState *env = fs->env;
  113 + struct etrax_pic *fs = (void *)opaque;
125 114 uint32_t mask;
126 115  
127 116 mask = 1 << irq;
... ... @@ -130,15 +119,12 @@ static void nmi_handler(void *opaque, int irq, int level)
130 119 else
131 120 fs->regs[R_R_NMI] &= ~mask;
132 121  
133   - if (fs->regs[R_R_NMI])
134   - cpu_interrupt(env, CPU_INTERRUPT_NMI);
135   - else
136   - cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
  122 + qemu_set_irq(fs->parent_nmi, !!fs->regs[R_R_NMI]);
137 123 }
138 124  
139 125 static void irq_handler(void *opaque, int irq, int level)
140 126 {
141   - struct fs_pic_state *fs = (void *)opaque;
  127 + struct etrax_pic *fs = (void *)opaque;
142 128  
143 129 if (irq >= 30)
144 130 return nmi_handler(opaque, irq, level);
... ... @@ -149,17 +135,24 @@ static void irq_handler(void *opaque, int irq, int level)
149 135 pic_update(fs);
150 136 }
151 137  
152   -qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
  138 +static void etraxfs_pic_init(SysBusDevice *dev)
153 139 {
154   - struct fs_pic_state *fs = NULL;
155   - qemu_irq *irq;
  140 + struct etrax_pic *s = FROM_SYSBUS(typeof (*s), dev);
156 141 int intr_vect_regs;
157 142  
158   - fs = qemu_mallocz(sizeof *fs);
159   - fs->env = env;
160   - irq = qemu_allocate_irqs(irq_handler, fs, 32);
  143 + s->interrupt_vector = qdev_get_prop_ptr(&dev->qdev, "interrupt_vector");
  144 + qdev_init_irq_sink(&dev->qdev, irq_handler, 32);
  145 + sysbus_init_irq(dev, &s->parent_irq);
  146 + sysbus_init_irq(dev, &s->parent_nmi);
161 147  
162   - intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
163   - cpu_register_physical_memory(base, R_MAX * 4, intr_vect_regs);
164   - return irq;
  148 + intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, s);
  149 + sysbus_init_mmio(dev, R_MAX * 4, intr_vect_regs);
165 150 }
  151 +
  152 +static void etraxfs_pic_register(void)
  153 +{
  154 + sysbus_register_dev("etraxfs,pic", sizeof (struct etrax_pic),
  155 + etraxfs_pic_init);
  156 +}
  157 +
  158 +device_init(etraxfs_pic_register)
... ...