gwj / at91sam9263 · Commits

Commit fd56059fb612090f5fab049d44e39760ac8fe523

Authored by balrog
1 parent 38453b93

Optimize clear insns by treating support reg P0 specially and 

add missing micro-op RETURN's (Edgar E. Iglesias).


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3913 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 30 additions and 19 deletions
target-cris/op.c
  View file @fd56059
... ... @@ -205,6 +205,7 @@ void OPPROTO op_ccs_lshift (void)
205 205 ccs = env->pregs[SR_CCS];
206 206 ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2);
207 207 env->pregs[SR_CCS] = ccs;
  208 + RETURN();
208 209 }
209 210 void OPPROTO op_ccs_rshift (void)
210 211 {
... ... @@ -214,6 +215,7 @@ void OPPROTO op_ccs_rshift (void)
214 215 ccs = env->pregs[SR_CCS];
215 216 ccs = (ccs & 0xc0000000) | (ccs >> 10);
216 217 env->pregs[SR_CCS] = ccs;
  218 + RETURN();
217 219 }
218 220  
219 221 void OPPROTO op_setf (void)
... ...
target-cris/translate.c
  View file @fd56059
... ... @@ -110,15 +110,6 @@ typedef struct DisasContext {
110 110 unsigned int mode;
111 111 unsigned int postinc;
112 112  
113   -
114   - struct
115   - {
116   - int op;
117   - int size;
118   - unsigned int mask;
119   - } cc_state[3];
120   - int cc_i;
121   -
122 113 int update_cc;
123 114 int cc_op;
124 115 int cc_size;
... ... @@ -183,6 +174,10 @@ static void gen_vr_read(void) {
183 174 gen_op_movl_T0_im(32);
184 175 }
185 176  
  177 +static void gen_movl_T0_p0(void) {
  178 + gen_op_movl_T0_im(0);
  179 +}
  180 +
186 181 static void gen_ccs_read(void) {
187 182 gen_op_movl_T0_p13();
188 183 }
... ... @@ -209,7 +204,7 @@ static GenOpFunc *gen_movl_preg_T0[16] =
209 204 };
210 205 static GenOpFunc *gen_movl_T0_preg[16] =
211 206 {
212   - gen_op_movl_T0_p0,
  207 + gen_movl_T0_p0,
213 208 gen_vr_read,
214 209 gen_op_movl_T0_p2, gen_op_movl_T0_p3,
215 210 gen_op_movl_T0_p4, gen_op_movl_T0_p5,
... ... @@ -345,6 +340,8 @@ static void cris_cc_mask(DisasContext *dc, unsigned int mask)
345 340 {
346 341 uint32_t ovl;
347 342  
  343 + /* Check if we need to evaluate the condition codes due to
  344 + CC overlaying. */
348 345 ovl = (dc->cc_mask ^ mask) & ~mask;
349 346 if (ovl) {
350 347 /* TODO: optimize this case. It trigs all the time. */
... ... @@ -987,7 +984,6 @@ static unsigned int dec_btstq(DisasContext *dc)
987 984 {
988 985 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
989 986 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
990   - cris_evaluate_flags(dc);
991 987 cris_cc_mask(dc, CC_MASK_NZ);
992 988 gen_movl_T0_reg[dc->op2]();
993 989 gen_op_movl_T1_im(dc->op1);
... ... @@ -1333,7 +1329,6 @@ static unsigned int dec_btst_r(DisasContext *dc)
1333 1329 {
1334 1330 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1335 1331 dc->op1, dc->op2));
1336   - cris_evaluate_flags(dc);
1337 1332 cris_cc_mask(dc, CC_MASK_NZ);
1338 1333 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1339 1334 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
... ... @@ -1518,8 +1513,14 @@ static unsigned int dec_move_pr(DisasContext *dc)
1518 1513 {
1519 1514 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
1520 1515 cris_cc_mask(dc, 0);
1521   - gen_movl_T0_preg[dc->op2]();
1522   - gen_op_movl_T1_T0();
  1516 + /* Support register 0 is hardwired to zero.
  1517 + Treat it specially. */
  1518 + if (dc->op2 == 0)
  1519 + gen_op_movl_T1_im(0);
  1520 + else {
  1521 + gen_movl_T0_preg[dc->op2]();
  1522 + gen_op_movl_T1_T0();
  1523 + }
1523 1524 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1524 1525 return 2;
1525 1526 }
... ... @@ -1846,13 +1847,21 @@ static unsigned int dec_move_pm(DisasContext *dc)
1846 1847  
1847 1848 memsize = preg_sizes[dc->op2];
1848 1849  
1849   - DIS(fprintf (logfile, "move.%d $p%u, [$r%u%s\n",
1850   - memsize, dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
  1850 + DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
  1851 + memsize_char(memsize),
  1852 + dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
1851 1853  
1852 1854 cris_cc_mask(dc, 0);
1853   - /* prepare store. */
1854   - gen_movl_T0_preg[dc->op2]();
1855   - gen_op_movl_T1_T0();
  1855 + /* prepare store. Address in T0, value in T1. */
  1856 + /* Support register 0 is hardwired to zero.
  1857 + Treat it specially. */
  1858 + if (dc->op2 == 0)
  1859 + gen_op_movl_T1_im(0);
  1860 + else
  1861 + {
  1862 + gen_movl_T0_preg[dc->op2]();
  1863 + gen_op_movl_T1_T0();
  1864 + }
1856 1865 gen_movl_T0_reg[dc->op1]();
1857 1866 gen_store_T0_T1(dc, memsize);
1858 1867 if (dc->postinc)
... ...