gwj / at91sam9263 · Commits

Commit fcdd25ab56ac2e78552559853591947717b34c6e

Authored by aliguori
1 parent 334c0241

Ignore IDE command if issued while IDE is busy (Gleb Natapov) 

Feature, Sector Count, LBA Low/Mid/High and Device registers should be
written only when both BSY and DRQ are cleared to zero.
Command register shall only be written when BSY and DRQ are set to zero
for all commands except DEVICE RESET.
Data Port register shall be accessed for host PIO data transfer only when
DRQ is set to one.

Signed-off-by: Gleb Natapov <gleb@qumranet.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5060 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 26 additions and 0 deletions
hw/ide.c
  View file @fcdd25a
... ... @@ -1981,6 +1981,11 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1981 1981 #endif
1982 1982  
1983 1983 addr &= 7;
  1984 +
  1985 + /* ignore writes to command block while busy with previous command */
  1986 + if (addr != 7 && (ide_if->cur_drive->status & (BUSY_STAT|DRQ_STAT)))
  1987 + return;
  1988 +
1984 1989 switch(addr) {
1985 1990 case 0:
1986 1991 break;
... ... @@ -2040,6 +2045,10 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2040 2045 if (s != ide_if && !s->bs)
2041 2046 break;
2042 2047  
  2048 + /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
  2049 + if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
  2050 + break;
  2051 +
2043 2052 switch(val) {
2044 2053 case WIN_IDENTIFY:
2045 2054 if (s->bs && !s->is_cdrom) {
... ... @@ -2498,6 +2507,10 @@ static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
2498 2507 IDEState *s = ((IDEState *)opaque)->cur_drive;
2499 2508 uint8_t *p;
2500 2509  
  2510 + /* PIO data access allowed only when DRQ bit is set */
  2511 + if (!(s->status & DRQ_STAT))
  2512 + return;
  2513 +
2501 2514 p = s->data_ptr;
2502 2515 *(uint16_t *)p = le16_to_cpu(val);
2503 2516 p += 2;
... ... @@ -2511,6 +2524,11 @@ static uint32_t ide_data_readw(void *opaque, uint32_t addr)
2511 2524 IDEState *s = ((IDEState *)opaque)->cur_drive;
2512 2525 uint8_t *p;
2513 2526 int ret;
  2527 +
  2528 + /* PIO data access allowed only when DRQ bit is set */
  2529 + if (!(s->status & DRQ_STAT))
  2530 + return 0;
  2531 +
2514 2532 p = s->data_ptr;
2515 2533 ret = cpu_to_le16(*(uint16_t *)p);
2516 2534 p += 2;
... ... @@ -2525,6 +2543,10 @@ static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2525 2543 IDEState *s = ((IDEState *)opaque)->cur_drive;
2526 2544 uint8_t *p;
2527 2545  
  2546 + /* PIO data access allowed only when DRQ bit is set */
  2547 + if (!(s->status & DRQ_STAT))
  2548 + return;
  2549 +
2528 2550 p = s->data_ptr;
2529 2551 *(uint32_t *)p = le32_to_cpu(val);
2530 2552 p += 4;
... ... @@ -2539,6 +2561,10 @@ static uint32_t ide_data_readl(void *opaque, uint32_t addr)
2539 2561 uint8_t *p;
2540 2562 int ret;
2541 2563  
  2564 + /* PIO data access allowed only when DRQ bit is set */
  2565 + if (!(s->status & DRQ_STAT))
  2566 + return 0;
  2567 +
2542 2568 p = s->data_ptr;
2543 2569 ret = cpu_to_le32(*(uint32_t *)p);
2544 2570 p += 4;
... ...