gwj / at91sam9263 · Commits

Commit fcc72045e8f2494a78fc6afc3e51aaa9b5221f75

Authored by blueswir1
1 parent 65fe7b09

Fix Sparc co-processor ops (Aurelien Jarno) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2567 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 27 additions and 1 deletions
target-sparc/cpu.h
  View file @fcc7204
@@ -40,6 +40,7 @@ @@ -40,6 +40,7 @@
40 #define TT_TOVF 0x0a 40 #define TT_TOVF 0x0a
41 #define TT_EXTINT 0x10 41 #define TT_EXTINT 0x10
42 #define TT_DIV_ZERO 0x2a 42 #define TT_DIV_ZERO 0x2a
  43 +#define TT_NCP_INSN 0x24
43 #define TT_TRAP 0x80 44 #define TT_TRAP 0x80
44 #else 45 #else
45 #define TT_TFAULT 0x08 46 #define TT_TFAULT 0x08
target-sparc/translate.c
  View file @fcc7204
@@ -1746,7 +1746,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1746,7 +1746,7 @@ static void disas_sparc_insn(DisasContext * dc)
1746 gen_op_sra(); 1746 gen_op_sra();
1747 gen_movl_T0_reg(rd); 1747 gen_movl_T0_reg(rd);
1748 #endif 1748 #endif
1749 - } else if (xop < 0x38) { 1749 + } else if (xop < 0x36) {
1750 rs1 = GET_FIELD(insn, 13, 17); 1750 rs1 = GET_FIELD(insn, 13, 17);
1751 gen_movl_reg_T0(rs1); 1751 gen_movl_reg_T0(rs1);
1752 if (IS_IMM) { /* immediate */ 1752 if (IS_IMM) { /* immediate */
@@ -2162,6 +2162,14 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2162,6 +2162,14 @@ static void disas_sparc_insn(DisasContext * dc)
2162 goto illegal_insn; 2162 goto illegal_insn;
2163 } 2163 }
2164 } 2164 }
  2165 + } else if (xop == 0x36 || xop == 0x37) { /* CPop1 & CPop2,
  2166 + V9 impdep1 &
  2167 + impdep2 */
  2168 +#ifdef TARGET_SPARC64
  2169 + goto illegal_insn;
  2170 +#else
  2171 + goto ncp_insn;
  2172 +#endif
2165 #ifdef TARGET_SPARC64 2173 #ifdef TARGET_SPARC64
2166 } else if (xop == 0x39) { /* V9 return */ 2174 } else if (xop == 0x39) { /* V9 return */
2167 rs1 = GET_FIELD(insn, 13, 17); 2175 rs1 = GET_FIELD(insn, 13, 17);
@@ -2410,6 +2418,15 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2410,6 +2418,15 @@ static void disas_sparc_insn(DisasContext * dc)
2410 break; 2418 break;
2411 2419
2412 #ifndef TARGET_SPARC64 2420 #ifndef TARGET_SPARC64
  2421 + case 0x30: /* ldc */
  2422 + case 0x31: /* ldcsr */
  2423 + case 0x33: /* lddc */
  2424 + case 0x34: /* stc */
  2425 + case 0x35: /* stcsr */
  2426 + case 0x36: /* stdcq */
  2427 + case 0x37: /* stdc */
  2428 + goto ncp_insn;
  2429 + break;
2413 /* avoid warnings */ 2430 /* avoid warnings */
2414 (void) &gen_op_stfa; 2431 (void) &gen_op_stfa;
2415 (void) &gen_op_stdfa; 2432 (void) &gen_op_stdfa;
@@ -2618,6 +2635,14 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2618,6 +2635,14 @@ static void disas_sparc_insn(DisasContext * dc)
2618 save_state(dc); 2635 save_state(dc);
2619 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); 2636 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
2620 dc->is_br = 1; 2637 dc->is_br = 1;
  2638 + return;
  2639 +#ifndef TARGET_SPARC64
  2640 + ncp_insn:
  2641 + save_state(dc);
  2642 + gen_op_exception(TT_NCP_INSN);
  2643 + dc->is_br = 1;
  2644 + return;
  2645 +#endif
2621 } 2646 }
2622 2647
2623 static inline int gen_intermediate_code_internal(TranslationBlock * tb, 2648 static inline int gen_intermediate_code_internal(TranslationBlock * tb,