gwj / at91sam9263 · Commits

Commit fbd265b681e831892c57445bfc5751c3439cf30c

Authored by aurel32
1 parent 0f6fbcbc

Rename spe_status to vec_status 

Only one of Altivec and SPE will be available on a given chip.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6506 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 59 additions and 57 deletions
target-ppc/cpu.h
  View file @fbd265b
... ... @@ -611,8 +611,10 @@ struct CPUPPCState {
611 611 uint32_t vscr;
612 612 /* SPE registers */
613 613 uint64_t spe_acc;
614   - float_status spe_status;
615 614 uint32_t spe_fscr;
  615 + /* SPE and Altivec can share a status since they will never be used
  616 + * simultaneously */
  617 + float_status vec_status;
616 618  
617 619 /* Internal devices resources */
618 620 /* Time base and decrementer */
... ...
target-ppc/op_helper.c
  View file @fbd265b
... ... @@ -2861,7 +2861,7 @@ static always_inline uint32_t efscfsi (uint32_t val)
2861 2861 {
2862 2862 CPU_FloatU u;
2863 2863  
2864   - u.f = int32_to_float32(val, &env->spe_status);
  2864 + u.f = int32_to_float32(val, &env->vec_status);
2865 2865  
2866 2866 return u.l;
2867 2867 }
... ... @@ -2870,7 +2870,7 @@ static always_inline uint32_t efscfui (uint32_t val)
2870 2870 {
2871 2871 CPU_FloatU u;
2872 2872  
2873   - u.f = uint32_to_float32(val, &env->spe_status);
  2873 + u.f = uint32_to_float32(val, &env->vec_status);
2874 2874  
2875 2875 return u.l;
2876 2876 }
... ... @@ -2884,7 +2884,7 @@ static always_inline int32_t efsctsi (uint32_t val)
2884 2884 if (unlikely(float32_is_nan(u.f)))
2885 2885 return 0;
2886 2886  
2887   - return float32_to_int32(u.f, &env->spe_status);
  2887 + return float32_to_int32(u.f, &env->vec_status);
2888 2888 }
2889 2889  
2890 2890 static always_inline uint32_t efsctui (uint32_t val)
... ... @@ -2896,7 +2896,7 @@ static always_inline uint32_t efsctui (uint32_t val)
2896 2896 if (unlikely(float32_is_nan(u.f)))
2897 2897 return 0;
2898 2898  
2899   - return float32_to_uint32(u.f, &env->spe_status);
  2899 + return float32_to_uint32(u.f, &env->vec_status);
2900 2900 }
2901 2901  
2902 2902 static always_inline uint32_t efsctsiz (uint32_t val)
... ... @@ -2908,7 +2908,7 @@ static always_inline uint32_t efsctsiz (uint32_t val)
2908 2908 if (unlikely(float32_is_nan(u.f)))
2909 2909 return 0;
2910 2910  
2911   - return float32_to_int32_round_to_zero(u.f, &env->spe_status);
  2911 + return float32_to_int32_round_to_zero(u.f, &env->vec_status);
2912 2912 }
2913 2913  
2914 2914 static always_inline uint32_t efsctuiz (uint32_t val)
... ... @@ -2920,7 +2920,7 @@ static always_inline uint32_t efsctuiz (uint32_t val)
2920 2920 if (unlikely(float32_is_nan(u.f)))
2921 2921 return 0;
2922 2922  
2923   - return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
  2923 + return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
2924 2924 }
2925 2925  
2926 2926 static always_inline uint32_t efscfsf (uint32_t val)
... ... @@ -2928,9 +2928,9 @@ static always_inline uint32_t efscfsf (uint32_t val)
2928 2928 CPU_FloatU u;
2929 2929 float32 tmp;
2930 2930  
2931   - u.f = int32_to_float32(val, &env->spe_status);
2932   - tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2933   - u.f = float32_div(u.f, tmp, &env->spe_status);
  2931 + u.f = int32_to_float32(val, &env->vec_status);
  2932 + tmp = int64_to_float32(1ULL << 32, &env->vec_status);
  2933 + u.f = float32_div(u.f, tmp, &env->vec_status);
2934 2934  
2935 2935 return u.l;
2936 2936 }
... ... @@ -2940,9 +2940,9 @@ static always_inline uint32_t efscfuf (uint32_t val)
2940 2940 CPU_FloatU u;
2941 2941 float32 tmp;
2942 2942  
2943   - u.f = uint32_to_float32(val, &env->spe_status);
2944   - tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2945   - u.f = float32_div(u.f, tmp, &env->spe_status);
  2943 + u.f = uint32_to_float32(val, &env->vec_status);
  2944 + tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
  2945 + u.f = float32_div(u.f, tmp, &env->vec_status);
2946 2946  
2947 2947 return u.l;
2948 2948 }
... ... @@ -2956,10 +2956,10 @@ static always_inline uint32_t efsctsf (uint32_t val)
2956 2956 /* NaN are not treated the same way IEEE 754 does */
2957 2957 if (unlikely(float32_is_nan(u.f)))
2958 2958 return 0;
2959   - tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2960   - u.f = float32_mul(u.f, tmp, &env->spe_status);
  2959 + tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
  2960 + u.f = float32_mul(u.f, tmp, &env->vec_status);
2961 2961  
2962   - return float32_to_int32(u.f, &env->spe_status);
  2962 + return float32_to_int32(u.f, &env->vec_status);
2963 2963 }
2964 2964  
2965 2965 static always_inline uint32_t efsctuf (uint32_t val)
... ... @@ -2971,10 +2971,10 @@ static always_inline uint32_t efsctuf (uint32_t val)
2971 2971 /* NaN are not treated the same way IEEE 754 does */
2972 2972 if (unlikely(float32_is_nan(u.f)))
2973 2973 return 0;
2974   - tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2975   - u.f = float32_mul(u.f, tmp, &env->spe_status);
  2974 + tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
  2975 + u.f = float32_mul(u.f, tmp, &env->vec_status);
2976 2976  
2977   - return float32_to_uint32(u.f, &env->spe_status);
  2977 + return float32_to_uint32(u.f, &env->vec_status);
2978 2978 }
2979 2979  
2980 2980 #define HELPER_SPE_SINGLE_CONV(name) \
... ... @@ -3036,7 +3036,7 @@ static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
3036 3036 CPU_FloatU u1, u2;
3037 3037 u1.l = op1;
3038 3038 u2.l = op2;
3039   - u1.f = float32_add(u1.f, u2.f, &env->spe_status);
  3039 + u1.f = float32_add(u1.f, u2.f, &env->vec_status);
3040 3040 return u1.l;
3041 3041 }
3042 3042  
... ... @@ -3045,7 +3045,7 @@ static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
3045 3045 CPU_FloatU u1, u2;
3046 3046 u1.l = op1;
3047 3047 u2.l = op2;
3048   - u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
  3048 + u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
3049 3049 return u1.l;
3050 3050 }
3051 3051  
... ... @@ -3054,7 +3054,7 @@ static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
3054 3054 CPU_FloatU u1, u2;
3055 3055 u1.l = op1;
3056 3056 u2.l = op2;
3057   - u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
  3057 + u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
3058 3058 return u1.l;
3059 3059 }
3060 3060  
... ... @@ -3063,7 +3063,7 @@ static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
3063 3063 CPU_FloatU u1, u2;
3064 3064 u1.l = op1;
3065 3065 u2.l = op2;
3066   - u1.f = float32_div(u1.f, u2.f, &env->spe_status);
  3066 + u1.f = float32_div(u1.f, u2.f, &env->vec_status);
3067 3067 return u1.l;
3068 3068 }
3069 3069  
... ... @@ -3102,7 +3102,7 @@ static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
3102 3102 CPU_FloatU u1, u2;
3103 3103 u1.l = op1;
3104 3104 u2.l = op2;
3105   - return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
  3105 + return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
3106 3106 }
3107 3107  
3108 3108 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
... ... @@ -3110,7 +3110,7 @@ static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
3110 3110 CPU_FloatU u1, u2;
3111 3111 u1.l = op1;
3112 3112 u2.l = op2;
3113   - return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
  3113 + return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
3114 3114 }
3115 3115  
3116 3116 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
... ... @@ -3118,7 +3118,7 @@ static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
3118 3118 CPU_FloatU u1, u2;
3119 3119 u1.l = op1;
3120 3120 u2.l = op2;
3121   - return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
  3121 + return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
3122 3122 }
3123 3123  
3124 3124 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
... ... @@ -3185,7 +3185,7 @@ uint64_t helper_efdcfsi (uint32_t val)
3185 3185 {
3186 3186 CPU_DoubleU u;
3187 3187  
3188   - u.d = int32_to_float64(val, &env->spe_status);
  3188 + u.d = int32_to_float64(val, &env->vec_status);
3189 3189  
3190 3190 return u.ll;
3191 3191 }
... ... @@ -3194,7 +3194,7 @@ uint64_t helper_efdcfsid (uint64_t val)
3194 3194 {
3195 3195 CPU_DoubleU u;
3196 3196  
3197   - u.d = int64_to_float64(val, &env->spe_status);
  3197 + u.d = int64_to_float64(val, &env->vec_status);
3198 3198  
3199 3199 return u.ll;
3200 3200 }
... ... @@ -3203,7 +3203,7 @@ uint64_t helper_efdcfui (uint32_t val)
3203 3203 {
3204 3204 CPU_DoubleU u;
3205 3205  
3206   - u.d = uint32_to_float64(val, &env->spe_status);
  3206 + u.d = uint32_to_float64(val, &env->vec_status);
3207 3207  
3208 3208 return u.ll;
3209 3209 }
... ... @@ -3212,7 +3212,7 @@ uint64_t helper_efdcfuid (uint64_t val)
3212 3212 {
3213 3213 CPU_DoubleU u;
3214 3214  
3215   - u.d = uint64_to_float64(val, &env->spe_status);
  3215 + u.d = uint64_to_float64(val, &env->vec_status);
3216 3216  
3217 3217 return u.ll;
3218 3218 }
... ... @@ -3226,7 +3226,7 @@ uint32_t helper_efdctsi (uint64_t val)
3226 3226 if (unlikely(float64_is_nan(u.d)))
3227 3227 return 0;
3228 3228  
3229   - return float64_to_int32(u.d, &env->spe_status);
  3229 + return float64_to_int32(u.d, &env->vec_status);
3230 3230 }
3231 3231  
3232 3232 uint32_t helper_efdctui (uint64_t val)
... ... @@ -3238,7 +3238,7 @@ uint32_t helper_efdctui (uint64_t val)
3238 3238 if (unlikely(float64_is_nan(u.d)))
3239 3239 return 0;
3240 3240  
3241   - return float64_to_uint32(u.d, &env->spe_status);
  3241 + return float64_to_uint32(u.d, &env->vec_status);
3242 3242 }
3243 3243  
3244 3244 uint32_t helper_efdctsiz (uint64_t val)
... ... @@ -3250,7 +3250,7 @@ uint32_t helper_efdctsiz (uint64_t val)
3250 3250 if (unlikely(float64_is_nan(u.d)))
3251 3251 return 0;
3252 3252  
3253   - return float64_to_int32_round_to_zero(u.d, &env->spe_status);
  3253 + return float64_to_int32_round_to_zero(u.d, &env->vec_status);
3254 3254 }
3255 3255  
3256 3256 uint64_t helper_efdctsidz (uint64_t val)
... ... @@ -3262,7 +3262,7 @@ uint64_t helper_efdctsidz (uint64_t val)
3262 3262 if (unlikely(float64_is_nan(u.d)))
3263 3263 return 0;
3264 3264  
3265   - return float64_to_int64_round_to_zero(u.d, &env->spe_status);
  3265 + return float64_to_int64_round_to_zero(u.d, &env->vec_status);
3266 3266 }
3267 3267  
3268 3268 uint32_t helper_efdctuiz (uint64_t val)
... ... @@ -3274,7 +3274,7 @@ uint32_t helper_efdctuiz (uint64_t val)
3274 3274 if (unlikely(float64_is_nan(u.d)))
3275 3275 return 0;
3276 3276  
3277   - return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
  3277 + return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
3278 3278 }
3279 3279  
3280 3280 uint64_t helper_efdctuidz (uint64_t val)
... ... @@ -3286,7 +3286,7 @@ uint64_t helper_efdctuidz (uint64_t val)
3286 3286 if (unlikely(float64_is_nan(u.d)))
3287 3287 return 0;
3288 3288  
3289   - return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
  3289 + return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
3290 3290 }
3291 3291  
3292 3292 uint64_t helper_efdcfsf (uint32_t val)
... ... @@ -3294,9 +3294,9 @@ uint64_t helper_efdcfsf (uint32_t val)
3294 3294 CPU_DoubleU u;
3295 3295 float64 tmp;
3296 3296  
3297   - u.d = int32_to_float64(val, &env->spe_status);
3298   - tmp = int64_to_float64(1ULL << 32, &env->spe_status);
3299   - u.d = float64_div(u.d, tmp, &env->spe_status);
  3297 + u.d = int32_to_float64(val, &env->vec_status);
  3298 + tmp = int64_to_float64(1ULL << 32, &env->vec_status);
  3299 + u.d = float64_div(u.d, tmp, &env->vec_status);
3300 3300  
3301 3301 return u.ll;
3302 3302 }
... ... @@ -3306,9 +3306,9 @@ uint64_t helper_efdcfuf (uint32_t val)
3306 3306 CPU_DoubleU u;
3307 3307 float64 tmp;
3308 3308  
3309   - u.d = uint32_to_float64(val, &env->spe_status);
3310   - tmp = int64_to_float64(1ULL << 32, &env->spe_status);
3311   - u.d = float64_div(u.d, tmp, &env->spe_status);
  3309 + u.d = uint32_to_float64(val, &env->vec_status);
  3310 + tmp = int64_to_float64(1ULL << 32, &env->vec_status);
  3311 + u.d = float64_div(u.d, tmp, &env->vec_status);
3312 3312  
3313 3313 return u.ll;
3314 3314 }
... ... @@ -3322,10 +3322,10 @@ uint32_t helper_efdctsf (uint64_t val)
3322 3322 /* NaN are not treated the same way IEEE 754 does */
3323 3323 if (unlikely(float64_is_nan(u.d)))
3324 3324 return 0;
3325   - tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
3326   - u.d = float64_mul(u.d, tmp, &env->spe_status);
  3325 + tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
  3326 + u.d = float64_mul(u.d, tmp, &env->vec_status);
3327 3327  
3328   - return float64_to_int32(u.d, &env->spe_status);
  3328 + return float64_to_int32(u.d, &env->vec_status);
3329 3329 }
3330 3330  
3331 3331 uint32_t helper_efdctuf (uint64_t val)
... ... @@ -3337,10 +3337,10 @@ uint32_t helper_efdctuf (uint64_t val)
3337 3337 /* NaN are not treated the same way IEEE 754 does */
3338 3338 if (unlikely(float64_is_nan(u.d)))
3339 3339 return 0;
3340   - tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
3341   - u.d = float64_mul(u.d, tmp, &env->spe_status);
  3340 + tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
  3341 + u.d = float64_mul(u.d, tmp, &env->vec_status);
3342 3342  
3343   - return float64_to_uint32(u.d, &env->spe_status);
  3343 + return float64_to_uint32(u.d, &env->vec_status);
3344 3344 }
3345 3345  
3346 3346 uint32_t helper_efscfd (uint64_t val)
... ... @@ -3349,7 +3349,7 @@ uint32_t helper_efscfd (uint64_t val)
3349 3349 CPU_FloatU u2;
3350 3350  
3351 3351 u1.ll = val;
3352   - u2.f = float64_to_float32(u1.d, &env->spe_status);
  3352 + u2.f = float64_to_float32(u1.d, &env->vec_status);
3353 3353  
3354 3354 return u2.l;
3355 3355 }
... ... @@ -3360,7 +3360,7 @@ uint64_t helper_efdcfs (uint32_t val)
3360 3360 CPU_FloatU u1;
3361 3361  
3362 3362 u1.l = val;
3363   - u2.d = float32_to_float64(u1.f, &env->spe_status);
  3363 + u2.d = float32_to_float64(u1.f, &env->vec_status);
3364 3364  
3365 3365 return u2.ll;
3366 3366 }
... ... @@ -3371,7 +3371,7 @@ uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
3371 3371 CPU_DoubleU u1, u2;
3372 3372 u1.ll = op1;
3373 3373 u2.ll = op2;
3374   - u1.d = float64_add(u1.d, u2.d, &env->spe_status);
  3374 + u1.d = float64_add(u1.d, u2.d, &env->vec_status);
3375 3375 return u1.ll;
3376 3376 }
3377 3377  
... ... @@ -3380,7 +3380,7 @@ uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
3380 3380 CPU_DoubleU u1, u2;
3381 3381 u1.ll = op1;
3382 3382 u2.ll = op2;
3383   - u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
  3383 + u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
3384 3384 return u1.ll;
3385 3385 }
3386 3386  
... ... @@ -3389,7 +3389,7 @@ uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
3389 3389 CPU_DoubleU u1, u2;
3390 3390 u1.ll = op1;
3391 3391 u2.ll = op2;
3392   - u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
  3392 + u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
3393 3393 return u1.ll;
3394 3394 }
3395 3395  
... ... @@ -3398,7 +3398,7 @@ uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
3398 3398 CPU_DoubleU u1, u2;
3399 3399 u1.ll = op1;
3400 3400 u2.ll = op2;
3401   - u1.d = float64_div(u1.d, u2.d, &env->spe_status);
  3401 + u1.d = float64_div(u1.d, u2.d, &env->vec_status);
3402 3402 return u1.ll;
3403 3403 }
3404 3404  
... ... @@ -3408,7 +3408,7 @@ uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
3408 3408 CPU_DoubleU u1, u2;
3409 3409 u1.ll = op1;
3410 3410 u2.ll = op2;
3411   - return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
  3411 + return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
3412 3412 }
3413 3413  
3414 3414 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
... ... @@ -3416,7 +3416,7 @@ uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
3416 3416 CPU_DoubleU u1, u2;
3417 3417 u1.ll = op1;
3418 3418 u2.ll = op2;
3419   - return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
  3419 + return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
3420 3420 }
3421 3421  
3422 3422 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
... ... @@ -3424,7 +3424,7 @@ uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
3424 3424 CPU_DoubleU u1, u2;
3425 3425 u1.ll = op1;
3426 3426 u2.ll = op2;
3427   - return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
  3427 + return float64_eq(u1.d, u2.d, &env->vec_status) ? 4 : 0;
3428 3428 }
3429 3429  
3430 3430 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
... ...