Commit f9fdea6b85a6b95701aaeedad2ac3087e4b6b438
1 parent
2c1ee068
Make PowerPC hypervisor resources able to compile, even if not enabled for now.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3446 c046a42c-6fe2-441c-8c8c-71466251a162
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1 changed file
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18 additions
and
6 deletions
target-ppc/helper.c
... | ... | @@ -2002,6 +2002,12 @@ static always_inline void powerpc_excp (CPUState *env, |
2002 | 2002 | { |
2003 | 2003 | target_ulong msr, new_msr, vector; |
2004 | 2004 | int srr0, srr1, asrr0, asrr1; |
2005 | +#if defined(TARGET_PPC64H) | |
2006 | + int lpes0, lpes1, lev; | |
2007 | + | |
2008 | + lpes0 = (env->spr[SPR_LPCR] >> 1) & 1; | |
2009 | + lpes1 = (env->spr[SPR_LPCR] >> 2) & 1; | |
2010 | +#endif | |
2005 | 2011 | |
2006 | 2012 | if (loglevel & CPU_LOG_INT) { |
2007 | 2013 | fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", |
... | ... | @@ -2201,6 +2207,7 @@ static always_inline void powerpc_excp (CPUState *env, |
2201 | 2207 | } |
2202 | 2208 | new_msr &= ~((target_ulong)1 << MSR_RI); |
2203 | 2209 | #if defined(TARGET_PPC64H) |
2210 | + lev = env->error_code; | |
2204 | 2211 | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
2205 | 2212 | new_msr |= (target_ulong)1 << MSR_HV; |
2206 | 2213 | #endif |
... | ... | @@ -2322,7 +2329,7 @@ static always_inline void powerpc_excp (CPUState *env, |
2322 | 2329 | #if defined(TARGET_PPC64H) |
2323 | 2330 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
2324 | 2331 | srr0 = SPR_HSRR0; |
2325 | - srr1 = SPR_HSSR1; | |
2332 | + srr1 = SPR_HSRR1; | |
2326 | 2333 | new_msr |= (target_ulong)1 << MSR_HV; |
2327 | 2334 | goto store_next; |
2328 | 2335 | #endif |
... | ... | @@ -2336,22 +2343,22 @@ static always_inline void powerpc_excp (CPUState *env, |
2336 | 2343 | #if defined(TARGET_PPC64H) |
2337 | 2344 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
2338 | 2345 | srr0 = SPR_HSRR0; |
2339 | - srr1 = SPR_HSSR1; | |
2346 | + srr1 = SPR_HSRR1; | |
2340 | 2347 | new_msr |= (target_ulong)1 << MSR_HV; |
2341 | 2348 | goto store_next; |
2342 | 2349 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
2343 | 2350 | srr0 = SPR_HSRR0; |
2344 | - srr1 = SPR_HSSR1; | |
2351 | + srr1 = SPR_HSRR1; | |
2345 | 2352 | new_msr |= (target_ulong)1 << MSR_HV; |
2346 | 2353 | goto store_next; |
2347 | 2354 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
2348 | 2355 | srr0 = SPR_HSRR0; |
2349 | - srr1 = SPR_HSSR1; | |
2356 | + srr1 = SPR_HSRR1; | |
2350 | 2357 | new_msr |= (target_ulong)1 << MSR_HV; |
2351 | 2358 | goto store_next; |
2352 | 2359 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
2353 | 2360 | srr0 = SPR_HSRR0; |
2354 | - srr1 = SPR_HSSR1; | |
2361 | + srr1 = SPR_HSRR1; | |
2355 | 2362 | new_msr |= (target_ulong)1 << MSR_HV; |
2356 | 2363 | goto store_next; |
2357 | 2364 | #endif /* defined(TARGET_PPC64H) */ |
... | ... | @@ -2633,6 +2640,10 @@ void do_interrupt (CPUState *env) |
2633 | 2640 | |
2634 | 2641 | void ppc_hw_interrupt (CPUPPCState *env) |
2635 | 2642 | { |
2643 | +#if defined(TARGET_PPC64H) | |
2644 | + int hdice; | |
2645 | +#endif | |
2646 | + | |
2636 | 2647 | #if 0 |
2637 | 2648 | if (loglevel & CPU_LOG_INT) { |
2638 | 2649 | fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n", |
... | ... | @@ -2661,7 +2672,8 @@ void ppc_hw_interrupt (CPUPPCState *env) |
2661 | 2672 | } |
2662 | 2673 | #endif |
2663 | 2674 | #if defined(TARGET_PPC64H) |
2664 | - if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) & hdice != 0) { | |
2675 | + hdice = env->spr[SPR_LPCR] & 1; | |
2676 | + if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { | |
2665 | 2677 | /* Hypervisor decrementer exception */ |
2666 | 2678 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { |
2667 | 2679 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); | ... | ... |