Commit f9bf298717ef9ac3b0ebf2924f4fdd8d56d258f1
1 parent
60e26a91
Preliminary MacOS X on PPC32 support
Big thanks to BlueSwirl for Sparc failure analysis. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4984 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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41 additions
and
10 deletions
tcg/ppc/tcg-target.c
| ... | ... | @@ -24,6 +24,14 @@ |
| 24 | 24 | |
| 25 | 25 | static uint8_t *tb_ret_addr; |
| 26 | 26 | |
| 27 | +#ifdef __APPLE__ | |
| 28 | +#define LINKAGE_AREA_SIZE 12 | |
| 29 | +#define BACK_CHAIN_OFFSET 8 | |
| 30 | +#else | |
| 31 | +#define LINKAGE_AREA_SIZE 8 | |
| 32 | +#define BACK_CHAIN_OFFSET 4 | |
| 33 | +#endif | |
| 34 | + | |
| 27 | 35 | #define FAST_PATH |
| 28 | 36 | #if TARGET_PHYS_ADDR_BITS <= 32 |
| 29 | 37 | #define ADDEND_OFFSET 0 |
| ... | ... | @@ -81,6 +89,9 @@ static const int tcg_target_reg_alloc_order[] = { |
| 81 | 89 | TCG_REG_R29, |
| 82 | 90 | TCG_REG_R30, |
| 83 | 91 | TCG_REG_R31, |
| 92 | +#ifdef __APPLE__ | |
| 93 | + TCG_REG_R2, | |
| 94 | +#endif | |
| 84 | 95 | TCG_REG_R3, |
| 85 | 96 | TCG_REG_R4, |
| 86 | 97 | TCG_REG_R5, |
| ... | ... | @@ -89,7 +100,9 @@ static const int tcg_target_reg_alloc_order[] = { |
| 89 | 100 | TCG_REG_R8, |
| 90 | 101 | TCG_REG_R9, |
| 91 | 102 | TCG_REG_R10, |
| 103 | +#ifndef __APPLE__ | |
| 92 | 104 | TCG_REG_R11, |
| 105 | +#endif | |
| 93 | 106 | TCG_REG_R12, |
| 94 | 107 | TCG_REG_R13, |
| 95 | 108 | TCG_REG_R0, |
| ... | ... | @@ -118,6 +131,10 @@ static const int tcg_target_call_oarg_regs[2] = { |
| 118 | 131 | }; |
| 119 | 132 | |
| 120 | 133 | static const int tcg_target_callee_save_regs[] = { |
| 134 | +#ifdef __APPLE__ | |
| 135 | + TCG_REG_R11, | |
| 136 | + TCG_REG_R13, | |
| 137 | +#endif | |
| 121 | 138 | TCG_REG_R14, |
| 122 | 139 | TCG_REG_R15, |
| 123 | 140 | TCG_REG_R16, |
| ... | ... | @@ -710,7 +727,11 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) |
| 710 | 727 | #else |
| 711 | 728 | tcg_out_mov (s, 3, addr_reg2); |
| 712 | 729 | tcg_out_mov (s, 4, addr_reg); |
| 730 | +#ifdef TCG_TARGET_CALL_ALIGN_ARGS | |
| 713 | 731 | ir = 5; |
| 732 | +#else | |
| 733 | + ir = 4; | |
| 734 | +#endif | |
| 714 | 735 | #endif |
| 715 | 736 | |
| 716 | 737 | switch (opc) { |
| ... | ... | @@ -734,9 +755,11 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) |
| 734 | 755 | tcg_out_mov (s, ir, data_reg); |
| 735 | 756 | break; |
| 736 | 757 | case 3: |
| 737 | - tcg_out_mov (s, 5, data_reg2); | |
| 738 | - tcg_out_mov (s, 6, data_reg); | |
| 739 | - ir = 6; | |
| 758 | +#ifdef TCG_TARGET_CALL_ALIGN_ARGS | |
| 759 | + ir = 5; | |
| 760 | +#endif | |
| 761 | + tcg_out_mov (s, ir++, data_reg2); | |
| 762 | + tcg_out_mov (s, ir, data_reg); | |
| 740 | 763 | break; |
| 741 | 764 | } |
| 742 | 765 | ir++; |
| ... | ... | @@ -806,8 +829,7 @@ void tcg_target_qemu_prologue (TCGContext *s) |
| 806 | 829 | int i, frame_size; |
| 807 | 830 | |
| 808 | 831 | frame_size = 0 |
| 809 | - + 4 /* back chain */ | |
| 810 | - + 4 /* LR */ | |
| 832 | + + LINKAGE_AREA_SIZE | |
| 811 | 833 | + TCG_STATIC_CALL_ARGS_SIZE |
| 812 | 834 | + ARRAY_SIZE (tcg_target_callee_save_regs) * 4 |
| 813 | 835 | ; |
| ... | ... | @@ -819,10 +841,10 @@ void tcg_target_qemu_prologue (TCGContext *s) |
| 819 | 841 | tcg_out32 (s, (STW |
| 820 | 842 | | RS (tcg_target_callee_save_regs[i]) |
| 821 | 843 | | RA (1) |
| 822 | - | (i * 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE) | |
| 844 | + | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE) | |
| 823 | 845 | ) |
| 824 | 846 | ); |
| 825 | - tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + 4)); | |
| 847 | + tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + BACK_CHAIN_OFFSET)); | |
| 826 | 848 | |
| 827 | 849 | tcg_out32 (s, MTSPR | RS (3) | CTR); |
| 828 | 850 | tcg_out32 (s, BCCTR | BO_ALWAYS); |
| ... | ... | @@ -832,10 +854,10 @@ void tcg_target_qemu_prologue (TCGContext *s) |
| 832 | 854 | tcg_out32 (s, (LWZ |
| 833 | 855 | | RT (tcg_target_callee_save_regs[i]) |
| 834 | 856 | | RA (1) |
| 835 | - | (i * 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE) | |
| 857 | + | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE) | |
| 836 | 858 | ) |
| 837 | 859 | ); |
| 838 | - tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + 4)); | |
| 860 | + tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + BACK_CHAIN_OFFSET)); | |
| 839 | 861 | tcg_out32 (s, MTSPR | RS (0) | LR); |
| 840 | 862 | tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size); |
| 841 | 863 | tcg_out32 (s, BCLR | BO_ALWAYS); |
| ... | ... | @@ -1438,6 +1460,9 @@ void tcg_target_init(TCGContext *s) |
| 1438 | 1460 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
| 1439 | 1461 | tcg_regset_set32(tcg_target_call_clobber_regs, 0, |
| 1440 | 1462 | (1 << TCG_REG_R0) | |
| 1463 | +#ifdef __APPLE__ | |
| 1464 | + (1 << TCG_REG_R2) | | |
| 1465 | +#endif | |
| 1441 | 1466 | (1 << TCG_REG_R3) | |
| 1442 | 1467 | (1 << TCG_REG_R4) | |
| 1443 | 1468 | (1 << TCG_REG_R5) | |
| ... | ... | @@ -1453,7 +1478,9 @@ void tcg_target_init(TCGContext *s) |
| 1453 | 1478 | tcg_regset_clear(s->reserved_regs); |
| 1454 | 1479 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); |
| 1455 | 1480 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); |
| 1481 | +#ifndef __APPLE__ | |
| 1456 | 1482 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); |
| 1483 | +#endif | |
| 1457 | 1484 | |
| 1458 | 1485 | tcg_add_target_add_op_defs(ppc_op_defs); |
| 1459 | 1486 | } | ... | ... |
tcg/ppc/tcg-target.h
| ... | ... | @@ -65,8 +65,12 @@ enum { |
| 65 | 65 | /* used for function call generation */ |
| 66 | 66 | #define TCG_REG_CALL_STACK TCG_REG_R1 |
| 67 | 67 | #define TCG_TARGET_STACK_ALIGN 16 |
| 68 | -#define TCG_TARGET_CALL_STACK_OFFSET 8 | |
| 68 | +#ifdef __APPLE__ | |
| 69 | +#define TCG_TARGET_CALL_STACK_OFFSET 12 | |
| 70 | +#else | |
| 69 | 71 | #define TCG_TARGET_CALL_ALIGN_ARGS 1 |
| 72 | +#define TCG_TARGET_CALL_STACK_OFFSET 8 | |
| 73 | +#endif | |
| 70 | 74 | |
| 71 | 75 | /* optional instructions */ |
| 72 | 76 | #define TCG_TARGET_HAS_neg_i32 | ... | ... |