fix spi: add interrupt support, increase size, so

linux can boot now

fix spi: add interrupt support, increase size, so
linux can boot now
Evgeniy Dushistov
1 parent 34f64942
Showing 5 changed files with 93 additions and 25 deletions
hw/at91.h
hw/at91_pdc.c
hw/at91_spi.c
hw/at91sam9.c
hw/spi_flash.c
@@ -39,7 +39,19 @@ typedef int (*pdc_start_transfer_t)(void *opaque,
                                      unsigned int rx_len,
                                      int last_transfer);
-PDCState *at91_pdc_init(void *opaque, pdc_start_transfer_t start_transfer);
+#define PDCF_ENDRX      1
+#define PDCF_ENDTX      2
+#define PDCF_RXFULL     4
+#define PDCF_TXFULL     8
+#define PDCF_NOT_ENDRX  16
+#define PDCF_NOT_RXFULL 32
+#define PDCF_NOT_ENDTX  64
+#define PDCF_NOT_TXFULL 128
+
+typedef void (*pdc_state_changed_t)(void *opaque, unsigned int state);
+
+PDCState *at91_pdc_init(void *opaque, pdc_start_transfer_t start_transfer,
+                            pdc_state_changed_t state_changed);
 extern void at91_pdc_reset(PDCState *s);
 extern void at91_pdc_write(void *opaque, target_phys_addr_t offset, uint32_t val);
 extern uint32_t at91_pdc_read(void *opaque, target_phys_addr_t offset);
@@ -46,15 +46,18 @@ struct PDCState {
     uint16_t tncr;
     void *opaque;
     pdc_start_transfer_t start_transfer;
+    pdc_state_changed_t state_changed;
 };
-PDCState *at91_pdc_init(void *opaque, pdc_start_transfer_t start_transfer)
+PDCState *at91_pdc_init(void *opaque, pdc_start_transfer_t start_transfer,
+                        pdc_state_changed_t state_changed)
 {
     PDCState *s;
     s = qemu_mallocz(sizeof(PDCState));
     s->opaque = opaque;
     s->start_transfer = start_transfer;
+    s->state_changed = state_changed;
     return s;
 }
@@ -62,6 +65,7 @@ void at91_pdc_write(void *opaque, target_phys_addr_t offset, uint32_t val)
 {
     PDCState *s = opaque;
     int last_transfer = 1;
+    unsigned int state = 0;
     switch (offset) {
     case PDC_PTCR:
@@ -71,25 +75,15 @@ void at91_pdc_write(void *opaque, target_phys_addr_t offset, uint32_t val)
                 s->ptsr & PDC_PTCR_RXTEN ? "enable recieve" : "<>", 
                 s->ptsr & PDC_PTCR_TXTEN ? "enable transfer" : "<>");
-        if (val & PDC_PTCR_RXTEN) {
-            s->ptsr |= PDC_PTCR_RXTEN;
-        }
-
-        if (val & PDC_PTCR_RXTDIS) {
-            s->ptsr &= ~PDC_PTCR_RXTEN;
-        }
+        s->ptsr |= (val & PDC_PTCR_RXTEN) ? PDC_PTCR_RXTEN : 0;
+        s->ptsr &= ~((val & PDC_PTCR_RXTDIS) ? PDC_PTCR_RXTEN : 0);
         if (s->ptsr & PDC_PTCR_RXTEN) {
           last_transfer = s->rncr == 0;
         }
-        if (val & PDC_PTCR_TXTEN) {
-            s->ptsr |= PDC_PTCR_TXTEN;         
-        }
-
-        if (val & PDC_PTCR_TXTDIS) {
-            s->ptsr &= ~PDC_PTCR_TXTEN;
-        }
+        s->ptsr |= (val & PDC_PTCR_TXTEN) ? PDC_PTCR_TXTEN : 0;
+        s->ptsr &= ~((val & PDC_PTCR_TXTDIS) ? PDC_PTCR_TXTEN : 0);
         if (s->ptsr & PDC_PTCR_TXTEN) {
             last_transfer |= s->tncr == 0;
@@ -103,9 +97,15 @@ void at91_pdc_write(void *opaque, target_phys_addr_t offset, uint32_t val)
             if (ret == 0) {
                 if (s->ptsr & PDC_PTCR_RXTEN) {
+                    if (s->rcr) {
+                        state |= PDCF_ENDRX;
+                    }
                     s->rcr = 0;
                 }
                 if (s->ptsr & PDC_PTCR_TXTEN) {
+                    if (s->tcr) {
+                        state |= PDCF_ENDTX;
+                    }
                     s->tcr = 0;
                 }
@@ -136,7 +136,15 @@ void at91_pdc_write(void *opaque, target_phys_addr_t offset, uint32_t val)
                 }
             }
         }
-
+        if (s->rcr == 0 && s->rncr == 0) {
+            state |= PDCF_RXFULL;
+        }
+        if (s->tcr == 0 && s->tncr == 0) {
+            state |= PDCF_TXFULL;
+        }
+        if (state != 0) {
+            s->state_changed(s->opaque, state);
+        }
         break;
     case PDC_RPR:
         s->rpr = val;
@@ -146,21 +154,33 @@ void at91_pdc_write(void *opaque, target_phys_addr_t offset, uint32_t val)
         break;
     case PDC_RCR:
         s->rcr = val;
+        if (s->rcr != 0) {
+            s->state_changed(s->opaque, PDCF_NOT_ENDRX | PDCF_NOT_RXFULL);
+        }
         break;
     case PDC_TCR:
         s->tcr = val;
+        if (s->tcr != 0) {
+            s->state_changed(s->opaque, PDCF_NOT_ENDTX | PDCF_NOT_TXFULL);
+        }
         break;
     case PDC_RNPR:
         s->rnpr = val;
         break;
     case PDC_RNCR:
         s->rncr = val;
+        if (s->rncr != 0) {
+            s->state_changed(s->opaque, PDCF_NOT_RXFULL);
+        }
         break;
     case PDC_TNPR:
         s->tnpr = val;
         break;
     case PDC_TNCR:
         s->tncr = val;
+        if (s->tncr != 0) {
+            s->state_changed(s->opaque, PDCF_NOT_TXFULL);
+        }
         break;
     default:
         DPRINTF("ignore write of %X to %X\n", val, offset);
@@ -84,6 +84,8 @@ static uint32_t at91_spi_mem_read(void *opaque, target_phys_addr_t offset)
         return s->sr;
     case SPI_RDR:
         return s->rdr;
+    case SPI_IMR:
+        return s->imr;
     case SPI_CSR0 ... SPI_CSR3:
         return s->csr[(offset - SPI_CSR0) / sizeof(s->csr[0])];
     case 0x100 ... 0x124:
@@ -109,6 +111,12 @@ static void at91_spi_mem_write(void *opaque, target_phys_addr_t offset,
         if (value & SPI_CR_SPIDIS)
             s->sr &= ~SPI_SR_SPIENS;
         break;
+    case SPI_IER:
+        s->imr |= value;
+        break;
+    case SPI_IDR:
+        s->imr &= ~value;
+        break;
     case SPI_MR:
         s->mr = value;
         break;
@@ -137,6 +145,24 @@ static CPUWriteMemoryFunc *at91_spi_writefn[] = {
     at91_spi_mem_write,
 };
+static void pdc_state_changed(void *opaque, unsigned int state)
+{
+    SPIState *s = opaque;
+
+    s->sr |= (state & PDCF_ENDRX) ? SPI_SR_ENDRX : 0;
+    s->sr &= ~((state & PDCF_NOT_ENDRX) ? SPI_SR_ENDRX : 0);
+    s->sr |= (state & PDCF_ENDTX) ? SPI_SR_ENDTX : 0;
+    s->sr &= ~((state & PDCF_NOT_ENDTX) ? SPI_SR_ENDTX : 0);
+
+    s->sr |= (state & PDCF_RXFULL) ? SPI_SR_RXBUFF : 0;
+    s->sr &= ~((state & PDCF_NOT_RXFULL) ? SPI_SR_RXBUFF : 0);
+
+    s->sr |= (state & PDCF_TXFULL) ? SPI_SR_TXBUFE : 0;
+    s->sr &= ~((state & PDCF_NOT_TXFULL) ? SPI_SR_TXBUFE : 0);
+
+    qemu_set_irq(s->irq, !!(s->sr & s->imr));
+}
+
 static int pdc_start_transfer(void *opaque,
                                target_phys_addr_t tx,
                                unsigned int tx_len,
@@ -176,14 +202,23 @@ static int pdc_start_transfer(void *opaque,
             --rx_len;
         }
     }
+#if 0
     if (flags & 1) {//tx
-        s->sr |= SPI_SR_ENDTX | SPI_SR_TXBUFE;
+        s->sr |= SPI_SR_ENDTX;
+        if (last_transfer) {
+            s->sr |= SPI_SR_TXBUFE;
+        }
     }
     if (flags & 2) {//rx
-        s->sr |= SPI_SR_RXBUFF | SPI_SR_ENDRX;
+        s->sr |= SPI_SR_ENDRX;
+        if (last_transfer) {
+            s->sr |= SPI_SR_RXBUFF;
+        }
     }
-    if (last_transfer)
+#endif
+    if (last_transfer) {        
         s->spi_control->set_chipselect(s->spi_control->opaque, 0);
+    }
     return 0;
 }
@@ -193,7 +228,7 @@ static void at91_spi_reset(void *opaque)
     s->mr = 0;
     s->rdr = 0;
-    s->sr = 0xf0;
+    s->sr = SPI_SR_ENDRX | SPI_SR_ENDTX | SPI_SR_RXBUFF | SPI_SR_TXBUFE;
     s->imr = 0;
     memset(s->csr, 0, sizeof(s->csr));
     at91_pdc_reset(s->pdc_state);
@@ -204,7 +239,7 @@ static void at91_spi_init(SysBusDevice *dev)
     SPIState *s = FROM_SYSBUS(typeof(*s), dev);
     int spi_regs;
-    s->pdc_state = at91_pdc_init(s, pdc_start_transfer);
+    s->pdc_state = at91_pdc_init(s, pdc_start_transfer, pdc_state_changed);
     sysbus_init_irq(dev, &s->irq);
     spi_regs = cpu_register_io_memory(at91_spi_readfn, at91_spi_writefn, s);
     sysbus_init_mmio(dev, SPI_SIZE, spi_regs);
@@ -344,7 +344,7 @@ static void at91sam9_init(ram_addr_t ram_size,
     dinfo = drive_get(IF_PFLASH, 0, 0);
     if (dinfo) {
         if (bms) {
-            if (spi_flash_register(dinfo->bdrv, 2 * 1024 * 1024, cs0_spi_handler) < 0) {
+            if (spi_flash_register(dinfo->bdrv, 4 * 1024 * 1024, cs0_spi_handler) < 0) {
                 fprintf(stderr, "init of spi flash failed\n");
                 exit(EXIT_FAILURE);
             }
@@ -12,7 +12,7 @@ typedef struct SPIFlash {
     BlockDriverState *bs;
 } SPIFlash;
-#define AT91_SPI_FLASH_DEBUG
+//#define AT91_SPI_FLASH_DEBUG
 #ifdef AT91_SPI_FLASH_DEBUG
 #define DPRINTF(fmt, ...)                           \
     do {                                            \
@@ -67,7 +67,8 @@ static uint32_t spi_flash_txrx(void *opaque, uint32_t val, int len)
     case 0xD7:
         spi_flash_reset_state(s);
         DPRINTF("return id\n");
-        return (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7);
+        return /*(1 << 2) | (1 << 3) | (1 << 5) | (1 << 7) AT45.*16*/
+            (1 << 2) | (1 << 4) | (1 << 5) | (1 << 7);
     default:
         DPRINTF("Unknown cmd\n");
         return 0;