gwj / at91sam9263 · Commits

Commit f8cc85341531b4c9cacd2fc199f984b09a073258

Authored by aurel32
1 parent 75fc9c0c

Document which IPR are used by 21264 

Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6927 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 65 additions and 31 deletions
target-alpha/cpu.h
  View file @f8cc853
@@ -144,51 +144,85 @@ enum { @@ -144,51 +144,85 @@ enum {
144 /* XXX: TOFIX: most of those registers are implementation dependant */ 144 /* XXX: TOFIX: most of those registers are implementation dependant */
145 enum { 145 enum {
146 /* Ebox IPRs */ 146 /* Ebox IPRs */
147 - IPR_CC = 0xC0,  
148 - IPR_CC_CTL = 0xC1,  
149 - IPR_VA = 0xC2,  
150 - IPR_VA_CTL = 0xC4,  
151 - IPR_VA_FORM = 0xC3, 147 + IPR_CC = 0xC0, /* 21264 */
  148 + IPR_CC_CTL = 0xC1, /* 21264 */
  149 +#define IPR_CC_CTL_ENA_SHIFT 32
  150 +#define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL
  151 + IPR_VA = 0xC2, /* 21264 */
  152 + IPR_VA_CTL = 0xC4, /* 21264 */
  153 +#define IPR_VA_CTL_VA_48_SHIFT 1
  154 +#define IPR_VA_CTL_VPTB_SHIFT 30
  155 + IPR_VA_FORM = 0xC3, /* 21264 */
152 /* Ibox IPRs */ 156 /* Ibox IPRs */
153 - IPR_ITB_TAG = 0x00,  
154 - IPR_ITB_PTE = 0x01,  
155 - IPT_ITB_IAP = 0x02,  
156 - IPT_ITB_IA = 0x03,  
157 - IPT_ITB_IS = 0x04, 157 + IPR_ITB_TAG = 0x00, /* 21264 */
  158 + IPR_ITB_PTE = 0x01, /* 21264 */
  159 + IPR_ITB_IAP = 0x02,
  160 + IPR_ITB_IA = 0x03, /* 21264 */
  161 + IPR_ITB_IS = 0x04,
158 IPR_PMPC = 0x05, 162 IPR_PMPC = 0x05,
159 - IPR_EXC_ADDR = 0x06,  
160 - IPR_IVA_FORM = 0x07,  
161 - IPR_CM = 0x09,  
162 - IPR_IER = 0x0A,  
163 - IPR_SIRR = 0x0C,  
164 - IPR_ISUM = 0x0D,  
165 - IPR_HW_INT_CLR = 0x0E, 163 + IPR_EXC_ADDR = 0x06, /* 21264 */
  164 + IPR_IVA_FORM = 0x07, /* 21264 */
  165 + IPR_CM = 0x09, /* 21264 */
  166 +#define IPR_CM_SHIFT 3
  167 +#define IPR_CM_MASK (3ULL << IPR_CM_SHIFT) /* 21264 */
  168 + IPR_IER = 0x0A, /* 21264 */
  169 +#define IPR_IER_MASK 0x0000007fffffe000ULL
  170 + IPR_IER_CM = 0x0B, /* 21264: = CM | IER */
  171 + IPR_SIRR = 0x0C, /* 21264 */
  172 +#define IPR_SIRR_SHIFT 14
  173 +#define IPR_SIRR_MASK 0x7fff
  174 + IPR_ISUM = 0x0D, /* 21264 */
  175 + IPR_HW_INT_CLR = 0x0E, /* 21264 */
166 IPR_EXC_SUM = 0x0F, 176 IPR_EXC_SUM = 0x0F,
167 IPR_PAL_BASE = 0x10, 177 IPR_PAL_BASE = 0x10,
168 IPR_I_CTL = 0x11, 178 IPR_I_CTL = 0x11,
169 - IPR_I_STAT = 0x16,  
170 - IPR_IC_FLUSH = 0x13,  
171 - IPR_IC_FLUSH_ASM = 0x12, 179 +#define IPR_I_CTL_CHIP_ID_SHIFT 24 /* 21264 */
  180 +#define IPR_I_CTL_BIST_FAIL (1 << 23) /* 21264 */
  181 +#define IPR_I_CTL_IC_EN_SHIFT 2 /* 21264 */
  182 +#define IPR_I_CTL_SDE1_SHIFT 7 /* 21264 */
  183 +#define IPR_I_CTL_HWE_SHIFT 12 /* 21264 */
  184 +#define IPR_I_CTL_VA_48_SHIFT 15 /* 21264 */
  185 +#define IPR_I_CTL_SPE_SHIFT 3 /* 21264 */
  186 +#define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */
  187 + IPR_I_STAT = 0x16, /* 21264 */
  188 + IPR_IC_FLUSH = 0x13, /* 21264 */
  189 + IPR_IC_FLUSH_ASM = 0x12, /* 21264 */
172 IPR_CLR_MAP = 0x15, 190 IPR_CLR_MAP = 0x15,
173 IPR_SLEEP = 0x17, 191 IPR_SLEEP = 0x17,
174 IPR_PCTX = 0x40, 192 IPR_PCTX = 0x40,
175 - IPR_PCTR_CTL = 0x14, 193 + IPR_PCTX_ASN = 0x01, /* field */
  194 +#define IPR_PCTX_ASN_SHIFT 39
  195 + IPR_PCTX_ASTER = 0x02, /* field */
  196 +#define IPR_PCTX_ASTER_SHIFT 5
  197 + IPR_PCTX_ASTRR = 0x04, /* field */
  198 +#define IPR_PCTX_ASTRR_SHIFT 9
  199 + IPR_PCTX_PPCE = 0x08, /* field */
  200 +#define IPR_PCTX_PPCE_SHIFT 1
  201 + IPR_PCTX_FPE = 0x10, /* field */
  202 +#define IPR_PCTX_FPE_SHIFT 2
  203 + IPR_PCTX_ALL = 0x5f, /* all fields */
  204 + IPR_PCTR_CTL = 0x14, /* 21264 */
176 /* Mbox IPRs */ 205 /* Mbox IPRs */
177 - IPR_DTB_TAG0 = 0x20,  
178 - IPR_DTB_TAG1 = 0xA0,  
179 - IPR_DTB_PTE0 = 0x21,  
180 - IPR_DTB_PTE1 = 0xA1, 206 + IPR_DTB_TAG0 = 0x20, /* 21264 */
  207 + IPR_DTB_TAG1 = 0xA0, /* 21264 */
  208 + IPR_DTB_PTE0 = 0x21, /* 21264 */
  209 + IPR_DTB_PTE1 = 0xA1, /* 21264 */
181 IPR_DTB_ALTMODE = 0xA6, 210 IPR_DTB_ALTMODE = 0xA6,
  211 + IPR_DTB_ALTMODE0 = 0x26, /* 21264 */
  212 +#define IPR_DTB_ALTMODE_MASK 3
182 IPR_DTB_IAP = 0xA2, 213 IPR_DTB_IAP = 0xA2,
183 - IPR_DTB_IA = 0xA3, 214 + IPR_DTB_IA = 0xA3, /* 21264 */
184 IPR_DTB_IS0 = 0x24, 215 IPR_DTB_IS0 = 0x24,
185 IPR_DTB_IS1 = 0xA4, 216 IPR_DTB_IS1 = 0xA4,
186 - IPR_DTB_ASN0 = 0x25,  
187 - IPR_DTB_ASN1 = 0xA5,  
188 - IPR_MM_STAT = 0x27,  
189 - IPR_M_CTL = 0x28, 217 + IPR_DTB_ASN0 = 0x25, /* 21264 */
  218 + IPR_DTB_ASN1 = 0xA5, /* 21264 */
  219 +#define IPR_DTB_ASN_SHIFT 56
  220 + IPR_MM_STAT = 0x27, /* 21264 */
  221 + IPR_M_CTL = 0x28, /* 21264 */
  222 +#define IPR_M_CTL_SPE_SHIFT 1
  223 +#define IPR_M_CTL_SPE_MASK 7
190 IPR_DC_CTL = 0x29, 224 IPR_DC_CTL = 0x29,
191 - IPR_DC_STAT = 0x2A, 225 + IPR_DC_STAT = 0x2A, /* 21264 */
192 /* Cbox IPRs */ 226 /* Cbox IPRs */
193 IPR_C_DATA = 0x2B, 227 IPR_C_DATA = 0x2B,
194 IPR_C_SHIFT = 0x2C, 228 IPR_C_SHIFT = 0x2C,