Commit f82a3d488a41d706b21c6eb8ada1dfaf8f03fb35
1 parent
393e0768
Change some qualifiers to static
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5375 c046a42c-6fe2-441c-8c8c-71466251a162
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11 additions
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10 deletions
sparc-dis.c
| ... | ... | @@ -67,7 +67,7 @@ struct sparc_opcode_arch { |
| 67 | 67 | short supported; |
| 68 | 68 | }; |
| 69 | 69 | |
| 70 | -extern const struct sparc_opcode_arch sparc_opcode_archs[]; | |
| 70 | +static const struct sparc_opcode_arch sparc_opcode_archs[]; | |
| 71 | 71 | |
| 72 | 72 | /* Return the bitmask of supported architectures for ARCH. */ |
| 73 | 73 | #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) |
| ... | ... | @@ -212,13 +212,14 @@ The following chars are unused: (note: ,[] are used as punctuation) |
| 212 | 212 | #define RS1_G0 RS1(~0) |
| 213 | 213 | #define RS2_G0 RS2(~0) |
| 214 | 214 | |
| 215 | -extern const struct sparc_opcode sparc_opcodes[]; | |
| 216 | -extern const int sparc_num_opcodes; | |
| 215 | +static const struct sparc_opcode sparc_opcodes[]; | |
| 216 | +static const int sparc_num_opcodes; | |
| 217 | 217 | |
| 218 | -extern const char *sparc_decode_asi PARAMS ((int)); | |
| 219 | -extern const char *sparc_decode_membar PARAMS ((int)); | |
| 220 | -extern const char *sparc_decode_prefetch PARAMS ((int)); | |
| 221 | -extern const char *sparc_decode_sparclet_cpreg PARAMS ((int)); | |
| 218 | +static const char *sparc_decode_asi_v8 PARAMS ((int)); | |
| 219 | +static const char *sparc_decode_asi_v9 PARAMS ((int)); | |
| 220 | +static const char *sparc_decode_membar PARAMS ((int)); | |
| 221 | +static const char *sparc_decode_prefetch PARAMS ((int)); | |
| 222 | +static const char *sparc_decode_sparclet_cpreg PARAMS ((int)); | |
| 222 | 223 | |
| 223 | 224 | /* Some defines to make life easy. */ |
| 224 | 225 | #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) |
| ... | ... | @@ -262,7 +263,7 @@ extern const char *sparc_decode_sparclet_cpreg PARAMS ((int)); |
| 262 | 263 | /* Table of opcode architectures. |
| 263 | 264 | The order is defined in opcode/sparc.h. */ |
| 264 | 265 | |
| 265 | -const struct sparc_opcode_arch sparc_opcode_archs[] = { | |
| 266 | +static const struct sparc_opcode_arch sparc_opcode_archs[] = { | |
| 266 | 267 | { "v6", MASK_V6 }, |
| 267 | 268 | { "v7", MASK_V6 | MASK_V7 }, |
| 268 | 269 | { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, |
| ... | ... | @@ -349,7 +350,7 @@ const struct sparc_opcode_arch sparc_opcode_archs[] = { |
| 349 | 350 | { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ |
| 350 | 351 | { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } |
| 351 | 352 | |
| 352 | -const struct sparc_opcode sparc_opcodes[] = { | |
| 353 | +static const struct sparc_opcode sparc_opcodes[] = { | |
| 353 | 354 | |
| 354 | 355 | { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, |
| 355 | 356 | { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ |
| ... | ... | @@ -2030,7 +2031,7 @@ IMPDEP ("impdep2", 0x37), |
| 2030 | 2031 | |
| 2031 | 2032 | }; |
| 2032 | 2033 | |
| 2033 | -const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); | |
| 2034 | +static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); | |
| 2034 | 2035 | |
| 2035 | 2036 | /* Utilities for argument parsing. */ |
| 2036 | 2037 | ... | ... |