Commit f7cfb2a176208d3b5139a2e792b40edf1adb43b4
1 parent
fb82fea0
64bit MIPS FPUs have 32 registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2610 c046a42c-6fe2-441c-8c8c-71466251a162
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target-mips/cpu.h
| @@ -62,9 +62,8 @@ struct CPUMIPSState { | @@ -62,9 +62,8 @@ struct CPUMIPSState { | ||
| 62 | target_ulong t2; | 62 | target_ulong t2; |
| 63 | #endif | 63 | #endif |
| 64 | target_ulong HI, LO; | 64 | target_ulong HI, LO; |
| 65 | - uint32_t DCR; /* ? */ | ||
| 66 | /* Floating point registers */ | 65 | /* Floating point registers */ |
| 67 | - fpr_t fpr[16]; | 66 | + fpr_t fpr[32]; |
| 68 | #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2]) | 67 | #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2]) |
| 69 | #define FPR_FD(cpu, n) (FPR(cpu, n)->fd) | 68 | #define FPR_FD(cpu, n) (FPR(cpu, n)->fd) |
| 70 | #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX]) | 69 | #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX]) |