Commit f79f00fecc657ebabde8c744aa57049016d08d82
1 parent
ef3a8a34
AT91 Periodic Interval Timer
This patch implements the PIT used on AT91 microcontrollers. All documented features are implemented. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Makefile.target
@@ -431,7 +431,7 @@ obj-arm-y += framebuffer.o | @@ -431,7 +431,7 @@ obj-arm-y += framebuffer.o | ||
431 | obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o | 431 | obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o |
432 | obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o | 432 | obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o |
433 | obj-arm-y += syborg_virtio.o | 433 | obj-arm-y += syborg_virtio.o |
434 | -obj-arm-y += at91_aic.o at91_dbgu.o at91_pio.o at91_pmc.o | 434 | +obj-arm-y += at91_aic.o at91_dbgu.o at91_pio.o at91_pit.o at91_pmc.o |
435 | obj-arm-y += gpio_rotary.o gpio_keypad.o | 435 | obj-arm-y += gpio_rotary.o gpio_keypad.o |
436 | 436 | ||
437 | ifeq ($(TARGET_BASE_ARCH), arm) | 437 | ifeq ($(TARGET_BASE_ARCH), arm) |
hw/at91_pit.c
0 → 100644
1 | +/* | ||
2 | + * AT91 Periodic Interval Timer | ||
3 | + * | ||
4 | + * Copyright (c) 2009 Filip Navara | ||
5 | + * | ||
6 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
7 | + * of this software and associated documentation files (the "Software"), to deal | ||
8 | + * in the Software without restriction, including without limitation the rights | ||
9 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
10 | + * copies of the Software, and to permit persons to whom the Software is | ||
11 | + * furnished to do so, subject to the following conditions: | ||
12 | + * | ||
13 | + * The above copyright notice and this permission notice shall be included in | ||
14 | + * all copies or substantial portions of the Software. | ||
15 | + * | ||
16 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
21 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
22 | + * THE SOFTWARE. | ||
23 | + */ | ||
24 | + | ||
25 | +#include "sysbus.h" | ||
26 | +#include "qemu-timer.h" | ||
27 | +#include "at91.h" | ||
28 | + | ||
29 | +#define PIT_SIZE 0x10 | ||
30 | + | ||
31 | +#define PIT_MR 0x00 /* Mode Register */ | ||
32 | +#define PIT_SR 0x04 /* Status Register */ | ||
33 | +#define PIT_PIVR 0x08 /* Periodic Interval Value Register */ | ||
34 | +#define PIT_PIIR 0x0c /* Periodic Interval Image Register */ | ||
35 | + | ||
36 | +#define PIT_LIMIT(s) \ | ||
37 | + (((s)->mr & 0xfffff) + 1) | ||
38 | + | ||
39 | +typedef struct PITState { | ||
40 | + SysBusDevice busdev; | ||
41 | + qemu_irq irq; | ||
42 | + ptimer_state *timer; | ||
43 | + uint32_t mr; | ||
44 | + uint32_t sr; | ||
45 | + uint32_t picnt; | ||
46 | +} PITState; | ||
47 | + | ||
48 | +static void at91_pit_tick(void *opaque) | ||
49 | +{ | ||
50 | + PITState *s = opaque; | ||
51 | + | ||
52 | + s->sr |= 1; | ||
53 | + s->picnt++; | ||
54 | + if (s->mr & 0x2000000) { | ||
55 | + qemu_set_irq(s->irq, 1); | ||
56 | + } | ||
57 | +} | ||
58 | + | ||
59 | +static uint32_t at91_pit_mem_read(void *opaque, target_phys_addr_t offset) | ||
60 | +{ | ||
61 | + PITState *s = opaque; | ||
62 | + | ||
63 | + offset &= 0xf; | ||
64 | + switch (offset) { | ||
65 | + case PIT_MR: | ||
66 | + return s->mr; | ||
67 | + case PIT_SR: | ||
68 | + return s->sr; | ||
69 | + case PIT_PIVR: | ||
70 | + s->sr = 0; | ||
71 | + qemu_set_irq(s->irq, 0); | ||
72 | + /* Fall-through */ | ||
73 | + case PIT_PIIR: | ||
74 | + return | ||
75 | + ((PIT_LIMIT(s) - ptimer_get_count(s->timer)) & 0xfffff) | | ||
76 | + (s->picnt << 20); | ||
77 | + | ||
78 | + default: | ||
79 | + return 0; | ||
80 | + } | ||
81 | +} | ||
82 | + | ||
83 | +static void at91_pit_mem_write(void *opaque, target_phys_addr_t offset, | ||
84 | + uint32_t value) | ||
85 | +{ | ||
86 | + PITState *s = opaque; | ||
87 | + | ||
88 | + offset &= 0xf; | ||
89 | + if (offset == PIT_MR) { | ||
90 | + s->mr = value; | ||
91 | + if (value & 0x1000000) { | ||
92 | + ptimer_set_freq(s->timer, at91_master_clock_frequency / 16); | ||
93 | + ptimer_set_limit(s->timer, PIT_LIMIT(s), 1); | ||
94 | + ptimer_run(s->timer, 0); | ||
95 | + } else { | ||
96 | + ptimer_stop(s->timer); | ||
97 | + } | ||
98 | + } | ||
99 | +} | ||
100 | + | ||
101 | +static CPUReadMemoryFunc *at91_pit_readfn[] = { | ||
102 | + at91_pit_mem_read, | ||
103 | + at91_pit_mem_read, | ||
104 | + at91_pit_mem_read, | ||
105 | +}; | ||
106 | + | ||
107 | +static CPUWriteMemoryFunc *at91_pit_writefn[] = { | ||
108 | + at91_pit_mem_write, | ||
109 | + at91_pit_mem_write, | ||
110 | + at91_pit_mem_write, | ||
111 | +}; | ||
112 | + | ||
113 | +static void at91_pit_save(QEMUFile *f, void *opaque) | ||
114 | +{ | ||
115 | + PITState *s = opaque; | ||
116 | + | ||
117 | + qemu_put_be32(f, s->mr); | ||
118 | + qemu_put_be32(f, s->sr); | ||
119 | + qemu_put_be32(f, s->picnt); | ||
120 | + qemu_put_ptimer(f, s->timer); | ||
121 | +} | ||
122 | + | ||
123 | +static int at91_pit_load(QEMUFile *f, void *opaque, int version_id) | ||
124 | +{ | ||
125 | + PITState *s = opaque; | ||
126 | + | ||
127 | + if (version_id != 1) | ||
128 | + return -EINVAL; | ||
129 | + | ||
130 | + s->mr = qemu_get_be32(f); | ||
131 | + s->sr = qemu_get_be32(f); | ||
132 | + s->picnt = qemu_get_be32(f); | ||
133 | + qemu_get_ptimer(f, s->timer); | ||
134 | + | ||
135 | + return 0; | ||
136 | +} | ||
137 | + | ||
138 | +static void at91_pit_reset(void *opaque) | ||
139 | +{ | ||
140 | + PITState *s = opaque; | ||
141 | + | ||
142 | + s->mr = 0xfffff; | ||
143 | + s->sr = 0; | ||
144 | + s->picnt = 0; | ||
145 | + ptimer_stop(s->timer); | ||
146 | +} | ||
147 | + | ||
148 | +static void at91_pit_init(SysBusDevice *dev) | ||
149 | +{ | ||
150 | + PITState *s = FROM_SYSBUS(typeof (*s), dev); | ||
151 | + QEMUBH *pit_bh; | ||
152 | + int pit_regs; | ||
153 | + | ||
154 | + pit_bh = qemu_bh_new(at91_pit_tick, s); | ||
155 | + s->timer = ptimer_init(pit_bh); | ||
156 | + | ||
157 | + sysbus_init_irq(dev, &s->irq); | ||
158 | + pit_regs = cpu_register_io_memory(at91_pit_readfn, at91_pit_writefn, s); | ||
159 | + sysbus_init_mmio(dev, PIT_SIZE, pit_regs); | ||
160 | + | ||
161 | + at91_pit_reset(s); | ||
162 | + qemu_register_reset(at91_pit_reset, s); | ||
163 | + | ||
164 | + register_savevm("at91_pit", -1, 1, at91_pit_save, at91_pit_load, s); | ||
165 | +} | ||
166 | + | ||
167 | +static void at91_pit_register(void) | ||
168 | +{ | ||
169 | + sysbus_register_dev("at91,pit", sizeof(PITState), at91_pit_init); | ||
170 | +} | ||
171 | + | ||
172 | +device_init(at91_pit_register) |