gwj / at91sam9263 · Commits

Commit f78fb44e825421d386bc44090907d159a04839ef

Authored by aurel32
1 parent 4f821e17

ppc: Convert GPR moves to TCG 

Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].

For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers
gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5153 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 390 additions and 454 deletions
target-ppc/cpu.h
  View file @f78fb44
... ... @@ -33,17 +33,7 @@ typedef uint64_t ppc_gpr_t;
33 33  
34 34 #else /* defined (TARGET_PPC64) */
35 35 /* PowerPC 32 definitions */
36   -#if (HOST_LONG_BITS >= 64)
37   -/* When using 64 bits temporary registers,
38   - * we can use 64 bits GPR with no extra cost
39   - * It's even an optimization as this will prevent
40   - * the compiler to do unuseful masking in the micro-ops.
41   - */
42   -typedef uint64_t ppc_gpr_t;
43   -#else /* (HOST_LONG_BITS >= 64) */
44 36 typedef uint32_t ppc_gpr_t;
45   -#endif /* (HOST_LONG_BITS >= 64) */
46   -
47 37 #define TARGET_LONG_BITS 32
48 38  
49 39 #if defined(TARGET_PPCEMB)
... ... @@ -541,7 +531,7 @@ struct CPUPPCState {
541 531 /* First are the most commonly used resources
542 532 * during translated code execution
543 533 */
544   -#if (HOST_LONG_BITS == 32)
  534 +#if (TARGET_LONG_BITS > HOST_LONG_BITS) || !defined(TARGET_PPC64)
545 535 /* temporary fixed-point registers
546 536 * used to emulate 64 bits registers on 32 bits hosts
547 537 */
... ...
target-ppc/op_template.h
  View file @f78fb44
... ... @@ -18,91 +18,6 @@
18 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 */
20 20  
21   -/* General purpose registers moves */
22   -void OPPROTO glue(op_load_gpr_T0_gpr, REG) (void)
23   -{
24   - T0 = env->gpr[REG];
25   - RETURN();
26   -}
27   -
28   -void OPPROTO glue(op_load_gpr_T1_gpr, REG) (void)
29   -{
30   - T1 = env->gpr[REG];
31   - RETURN();
32   -}
33   -
34   -void OPPROTO glue(op_load_gpr_T2_gpr, REG) (void)
35   -{
36   - T2 = env->gpr[REG];
37   - RETURN();
38   -}
39   -
40   -void OPPROTO glue(op_store_T0_gpr_gpr, REG) (void)
41   -{
42   - env->gpr[REG] = T0;
43   - RETURN();
44   -}
45   -
46   -void OPPROTO glue(op_store_T1_gpr_gpr, REG) (void)
47   -{
48   - env->gpr[REG] = T1;
49   - RETURN();
50   -}
51   -
52   -#if 0 // unused
53   -void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
54   -{
55   - env->gpr[REG] = T2;
56   - RETURN();
57   -}
58   -#endif
59   -
60   -/* General purpose registers containing vector operands moves */
61   -#if !defined(TARGET_PPC64)
62   -void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
63   -{
64   - T0_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
65   - RETURN();
66   -}
67   -
68   -void OPPROTO glue(op_load_gpr64_T1_gpr, REG) (void)
69   -{
70   - T1_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
71   - RETURN();
72   -}
73   -
74   -#if 0 // unused
75   -void OPPROTO glue(op_load_gpr64_T2_gpr, REG) (void)
76   -{
77   - T2_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
78   - RETURN();
79   -}
80   -#endif
81   -
82   -void OPPROTO glue(op_store_T0_gpr64_gpr, REG) (void)
83   -{
84   - env->gpr[REG] = T0_64;
85   - env->gprh[REG] = T0_64 >> 32;
86   - RETURN();
87   -}
88   -
89   -void OPPROTO glue(op_store_T1_gpr64_gpr, REG) (void)
90   -{
91   - env->gpr[REG] = T1_64;
92   - env->gprh[REG] = T1_64 >> 32;
93   - RETURN();
94   -}
95   -
96   -#if 0 // unused
97   -void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
98   -{
99   - env->gpr[REG] = T2_64;
100   - env->gprh[REG] = T2_64 >> 32;
101   - RETURN();
102   -}
103   -#endif
104   -#endif /* !defined(TARGET_PPC64) */
105   -
106 21 /* Altivec registers moves */
107 22 void OPPROTO glue(op_load_avr_A0_avr, REG) (void)
108 23 {
... ...
target-ppc/translate.c
  View file @f78fb44
... ... @@ -44,15 +44,37 @@
44 44 /*****************************************************************************/
45 45 /* Code translation helpers */
46 46  
47   -static TCGv cpu_env, cpu_T[3];
  47 +/* global register indexes */
  48 +static TCGv cpu_env;
  49 +static char cpu_reg_names[10*3 + 22*4
  50 +#if !defined(TARGET_PPC64)
  51 + + 10*4 + 22*5
  52 +#endif
  53 +];
  54 +static TCGv cpu_gpr[32];
  55 +#if !defined(TARGET_PPC64)
  56 +static TCGv cpu_gprh[32];
  57 +#endif
  58 +
  59 +/* dyngen register indexes */
  60 +static TCGv cpu_T[3];
  61 +#if defined(TARGET_PPC64)
  62 +#define cpu_T64 cpu_T
  63 +#else
  64 +static TCGv cpu_T64[3];
  65 +#endif
48 66  
49 67 #include "gen-icount.h"
50 68  
51 69 void ppc_translate_init(void)
52 70 {
  71 + int i;
  72 + char* p;
53 73 static int done_init = 0;
  74 +
54 75 if (done_init)
55 76 return;
  77 +
56 78 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
57 79 #if TARGET_LONG_BITS > HOST_LONG_BITS
58 80 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
... ... @@ -66,6 +88,31 @@ void ppc_translate_init(void)
66 88 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
67 89 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
68 90 #endif
  91 +#if !defined(TARGET_PPC64)
  92 + cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
  93 + TCG_AREG0, offsetof(CPUState, t0),
  94 + "T0_64");
  95 + cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
  96 + TCG_AREG0, offsetof(CPUState, t1),
  97 + "T1_64");
  98 + cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
  99 + TCG_AREG0, offsetof(CPUState, t2),
  100 + "T2_64");
  101 +#endif
  102 +
  103 + p = cpu_reg_names;
  104 + for (i = 0; i < 32; i++) {
  105 + sprintf(p, "r%d", i);
  106 + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
  107 + offsetof(CPUState, gpr[i]), p);
  108 + p += (i < 10) ? 3 : 4;
  109 +#if !defined(TARGET_PPC64)
  110 + sprintf(p, "r%dH", i);
  111 + cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  112 + offsetof(CPUState, gprh[i]), p);
  113 + p += (i < 10) ? 4 : 5;
  114 +#endif
  115 + }
69 116  
70 117 /* register helpers */
71 118 #undef DEF_HELPER
... ... @@ -126,17 +173,6 @@ GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
126 173 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
127 174 #endif
128 175  
129   -/* General purpose registers moves */
130   -GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
131   -GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
132   -GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
133   -
134   -GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
135   -GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
136   -#if 0 // unused
137   -GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
138   -#endif
139   -
140 176 /* floating point registers moves */
141 177 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
142 178 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
... ... @@ -667,10 +703,10 @@ static opc_handler_t invalid_handler = {
667 703 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
668 704 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
669 705 { \
670   - gen_op_load_gpr_T0(rA(ctx->opcode)); \
671   - gen_op_load_gpr_T1(rB(ctx->opcode)); \
  706 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
  707 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
672 708 gen_op_##name(); \
673   - gen_op_store_T0_gpr(rD(ctx->opcode)); \
  709 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
674 710 if (unlikely(Rc(ctx->opcode) != 0)) \
675 711 gen_set_Rc0(ctx); \
676 712 }
... ... @@ -678,10 +714,10 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
678 714 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
679 715 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
680 716 { \
681   - gen_op_load_gpr_T0(rA(ctx->opcode)); \
682   - gen_op_load_gpr_T1(rB(ctx->opcode)); \
  717 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
  718 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
683 719 gen_op_##name(); \
684   - gen_op_store_T0_gpr(rD(ctx->opcode)); \
  720 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
685 721 if (unlikely(Rc(ctx->opcode) != 0)) \
686 722 gen_set_Rc0(ctx); \
687 723 }
... ... @@ -689,18 +725,18 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
689 725 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
690 726 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
691 727 { \
692   - gen_op_load_gpr_T0(rA(ctx->opcode)); \
  728 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
693 729 gen_op_##name(); \
694   - gen_op_store_T0_gpr(rD(ctx->opcode)); \
  730 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
695 731 if (unlikely(Rc(ctx->opcode) != 0)) \
696 732 gen_set_Rc0(ctx); \
697 733 }
698 734 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
699 735 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
700 736 { \
701   - gen_op_load_gpr_T0(rA(ctx->opcode)); \
  737 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
702 738 gen_op_##name(); \
703   - gen_op_store_T0_gpr(rD(ctx->opcode)); \
  739 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
704 740 if (unlikely(Rc(ctx->opcode) != 0)) \
705 741 gen_set_Rc0(ctx); \
706 742 }
... ... @@ -723,13 +759,13 @@ __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
723 759 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
724 760 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
725 761 { \
726   - gen_op_load_gpr_T0(rA(ctx->opcode)); \
727   - gen_op_load_gpr_T1(rB(ctx->opcode)); \
  762 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
  763 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
728 764 if (ctx->sf_mode) \
729 765 gen_op_##name##_64(); \
730 766 else \
731 767 gen_op_##name(); \
732   - gen_op_store_T0_gpr(rD(ctx->opcode)); \
  768 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
733 769 if (unlikely(Rc(ctx->opcode) != 0)) \
734 770 gen_set_Rc0(ctx); \
735 771 }
... ... @@ -737,13 +773,13 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
737 773 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
738 774 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
739 775 { \
740   - gen_op_load_gpr_T0(rA(ctx->opcode)); \
741   - gen_op_load_gpr_T1(rB(ctx->opcode)); \
  776 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
  777 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
742 778 if (ctx->sf_mode) \
743 779 gen_op_##name##_64(); \
744 780 else \
745 781 gen_op_##name(); \
746   - gen_op_store_T0_gpr(rD(ctx->opcode)); \
  782 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
747 783 if (unlikely(Rc(ctx->opcode) != 0)) \
748 784 gen_set_Rc0(ctx); \
749 785 }
... ... @@ -751,24 +787,24 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
751 787 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
752 788 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
753 789 { \
754   - gen_op_load_gpr_T0(rA(ctx->opcode)); \
  790 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
755 791 if (ctx->sf_mode) \
756 792 gen_op_##name##_64(); \
757 793 else \
758 794 gen_op_##name(); \
759   - gen_op_store_T0_gpr(rD(ctx->opcode)); \
  795 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
760 796 if (unlikely(Rc(ctx->opcode) != 0)) \
761 797 gen_set_Rc0(ctx); \
762 798 }
763 799 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
764 800 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
765 801 { \
766   - gen_op_load_gpr_T0(rA(ctx->opcode)); \
  802 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
767 803 if (ctx->sf_mode) \
768 804 gen_op_##name##_64(); \
769 805 else \
770 806 gen_op_##name(); \
771   - gen_op_store_T0_gpr(rD(ctx->opcode)); \
  807 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
772 808 if (unlikely(Rc(ctx->opcode) != 0)) \
773 809 gen_set_Rc0(ctx); \
774 810 }
... ... @@ -986,18 +1022,18 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
986 1022 /* li case */
987 1023 tcg_gen_movi_tl(cpu_T[0], simm);
988 1024 } else {
989   - gen_op_load_gpr_T0(rA(ctx->opcode));
  1025 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
990 1026 if (likely(simm != 0))
991 1027 gen_op_addi(simm);
992 1028 }
993   - gen_op_store_T0_gpr(rD(ctx->opcode));
  1029 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
994 1030 }
995 1031 /* addic */
996 1032 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
997 1033 {
998 1034 target_long simm = SIMM(ctx->opcode);
999 1035  
1000   - gen_op_load_gpr_T0(rA(ctx->opcode));
  1036 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1001 1037 if (likely(simm != 0)) {
1002 1038 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
1003 1039 gen_op_addi(simm);
... ... @@ -1010,14 +1046,14 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1010 1046 } else {
1011 1047 gen_op_clear_xer_ca();
1012 1048 }
1013   - gen_op_store_T0_gpr(rD(ctx->opcode));
  1049 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
1014 1050 }
1015 1051 /* addic. */
1016 1052 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1017 1053 {
1018 1054 target_long simm = SIMM(ctx->opcode);
1019 1055  
1020   - gen_op_load_gpr_T0(rA(ctx->opcode));
  1056 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1021 1057 if (likely(simm != 0)) {
1022 1058 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
1023 1059 gen_op_addi(simm);
... ... @@ -1030,7 +1066,7 @@ GEN_HANDLER2(addic_, &quot;addic.&quot;, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1030 1066 } else {
1031 1067 gen_op_clear_xer_ca();
1032 1068 }
1033   - gen_op_store_T0_gpr(rD(ctx->opcode));
  1069 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
1034 1070 gen_set_Rc0(ctx);
1035 1071 }
1036 1072 /* addis */
... ... @@ -1042,30 +1078,30 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1042 1078 /* lis case */
1043 1079 tcg_gen_movi_tl(cpu_T[0], simm << 16);
1044 1080 } else {
1045   - gen_op_load_gpr_T0(rA(ctx->opcode));
  1081 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1046 1082 if (likely(simm != 0))
1047 1083 gen_op_addi(simm << 16);
1048 1084 }
1049   - gen_op_store_T0_gpr(rD(ctx->opcode));
  1085 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
1050 1086 }
1051 1087 /* mulli */
1052 1088 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1053 1089 {
1054   - gen_op_load_gpr_T0(rA(ctx->opcode));
  1090 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1055 1091 gen_op_mulli(SIMM(ctx->opcode));
1056   - gen_op_store_T0_gpr(rD(ctx->opcode));
  1092 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
1057 1093 }
1058 1094 /* subfic */
1059 1095 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1060 1096 {
1061   - gen_op_load_gpr_T0(rA(ctx->opcode));
  1097 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1062 1098 #if defined(TARGET_PPC64)
1063 1099 if (ctx->sf_mode)
1064 1100 gen_op_subfic_64(SIMM(ctx->opcode));
1065 1101 else
1066 1102 #endif
1067 1103 gen_op_subfic(SIMM(ctx->opcode));
1068   - gen_op_store_T0_gpr(rD(ctx->opcode));
  1104 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
1069 1105 }
1070 1106  
1071 1107 #if defined(TARGET_PPC64)
... ... @@ -1086,8 +1122,8 @@ GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
1086 1122 #define GEN_CMP(name, opc, type) \
1087 1123 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1088 1124 { \
1089   - gen_op_load_gpr_T0(rA(ctx->opcode)); \
1090   - gen_op_load_gpr_T1(rB(ctx->opcode)); \
  1125 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
  1126 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
1091 1127 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
1092 1128 gen_op_##name##_64(); \
1093 1129 else \
... ... @@ -1098,8 +1134,8 @@ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1098 1134 #define GEN_CMP(name, opc, type) \
1099 1135 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1100 1136 { \
1101   - gen_op_load_gpr_T0(rA(ctx->opcode)); \
1102   - gen_op_load_gpr_T1(rB(ctx->opcode)); \
  1137 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
  1138 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
1103 1139 gen_op_##name(); \
1104 1140 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1105 1141 }
... ... @@ -1110,7 +1146,7 @@ GEN_CMP(cmp, 0x00, PPC_INTEGER);
1110 1146 /* cmpi */
1111 1147 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1112 1148 {
1113   - gen_op_load_gpr_T0(rA(ctx->opcode));
  1149 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1114 1150 #if defined(TARGET_PPC64)
1115 1151 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1116 1152 gen_op_cmpi_64(SIMM(ctx->opcode));
... ... @@ -1124,7 +1160,7 @@ GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1124 1160 /* cmpli */
1125 1161 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1126 1162 {
1127   - gen_op_load_gpr_T0(rA(ctx->opcode));
  1163 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1128 1164 #if defined(TARGET_PPC64)
1129 1165 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1130 1166 gen_op_cmpli_64(UIMM(ctx->opcode));
... ... @@ -1143,24 +1179,24 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
1143 1179 if (rA(ctx->opcode) == 0) {
1144 1180 tcg_gen_movi_tl(cpu_T[0], 0);
1145 1181 } else {
1146   - gen_op_load_gpr_T1(rA(ctx->opcode));
  1182 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
1147 1183 }
1148   - gen_op_load_gpr_T2(rB(ctx->opcode));
  1184 + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
1149 1185 mask = 1 << (3 - (bi & 0x03));
1150 1186 gen_op_load_crf_T0(bi >> 2);
1151 1187 gen_op_test_true(mask);
1152 1188 gen_op_isel();
1153   - gen_op_store_T0_gpr(rD(ctx->opcode));
  1189 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
1154 1190 }
1155 1191  
1156 1192 /*** Integer logical ***/
1157 1193 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1158 1194 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1159 1195 { \
1160   - gen_op_load_gpr_T0(rS(ctx->opcode)); \
1161   - gen_op_load_gpr_T1(rB(ctx->opcode)); \
  1196 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
  1197 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
1162 1198 gen_op_##name(); \
1163   - gen_op_store_T0_gpr(rA(ctx->opcode)); \
  1199 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
1164 1200 if (unlikely(Rc(ctx->opcode) != 0)) \
1165 1201 gen_set_Rc0(ctx); \
1166 1202 }
... ... @@ -1170,9 +1206,9 @@ __GEN_LOGICAL2(name, 0x1C, opc, type)
1170 1206 #define GEN_LOGICAL1(name, opc, type) \
1171 1207 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1172 1208 { \
1173   - gen_op_load_gpr_T0(rS(ctx->opcode)); \
  1209 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
1174 1210 gen_op_##name(); \
1175   - gen_op_store_T0_gpr(rA(ctx->opcode)); \
  1211 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
1176 1212 if (unlikely(Rc(ctx->opcode) != 0)) \
1177 1213 gen_set_Rc0(ctx); \
1178 1214 }
... ... @@ -1184,17 +1220,17 @@ GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1184 1220 /* andi. */
1185 1221 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1186 1222 {
1187   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1223 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1188 1224 gen_op_andi_T0(UIMM(ctx->opcode));
1189   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1225 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1190 1226 gen_set_Rc0(ctx);
1191 1227 }
1192 1228 /* andis. */
1193 1229 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1194 1230 {
1195   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1231 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1196 1232 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1197   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1233 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1198 1234 gen_set_Rc0(ctx);
1199 1235 }
1200 1236  
... ... @@ -1221,16 +1257,16 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1221 1257 rb = rB(ctx->opcode);
1222 1258 /* Optimisation for mr. ri case */
1223 1259 if (rs != ra || rs != rb) {
1224   - gen_op_load_gpr_T0(rs);
  1260 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
1225 1261 if (rs != rb) {
1226   - gen_op_load_gpr_T1(rb);
  1262 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
1227 1263 gen_op_or();
1228 1264 }
1229   - gen_op_store_T0_gpr(ra);
  1265 + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
1230 1266 if (unlikely(Rc(ctx->opcode) != 0))
1231 1267 gen_set_Rc0(ctx);
1232 1268 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1233   - gen_op_load_gpr_T0(rs);
  1269 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
1234 1270 gen_set_Rc0(ctx);
1235 1271 #if defined(TARGET_PPC64)
1236 1272 } else {
... ... @@ -1286,15 +1322,15 @@ GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1286 1322 /* xor & xor. */
1287 1323 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1288 1324 {
1289   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1325 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1290 1326 /* Optimisation for "set to zero" case */
1291 1327 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1292   - gen_op_load_gpr_T1(rB(ctx->opcode));
  1328 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
1293 1329 gen_op_xor();
1294 1330 } else {
1295 1331 tcg_gen_movi_tl(cpu_T[0], 0);
1296 1332 }
1297   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1333 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1298 1334 if (unlikely(Rc(ctx->opcode) != 0))
1299 1335 gen_set_Rc0(ctx);
1300 1336 }
... ... @@ -1308,10 +1344,10 @@ GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1308 1344 /* XXX: should handle special NOPs for POWER series */
1309 1345 return;
1310 1346 }
1311   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1347 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1312 1348 if (likely(uimm != 0))
1313 1349 gen_op_ori(uimm);
1314   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1350 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1315 1351 }
1316 1352 /* oris */
1317 1353 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
... ... @@ -1322,10 +1358,10 @@ GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1322 1358 /* NOP */
1323 1359 return;
1324 1360 }
1325   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1361 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1326 1362 if (likely(uimm != 0))
1327 1363 gen_op_ori(uimm << 16);
1328   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1364 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1329 1365 }
1330 1366 /* xori */
1331 1367 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
... ... @@ -1336,10 +1372,10 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1336 1372 /* NOP */
1337 1373 return;
1338 1374 }
1339   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1375 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1340 1376 if (likely(uimm != 0))
1341 1377 gen_op_xori(uimm);
1342   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1378 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1343 1379 }
1344 1380  
1345 1381 /* xoris */
... ... @@ -1351,23 +1387,23 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1351 1387 /* NOP */
1352 1388 return;
1353 1389 }
1354   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1390 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1355 1391 if (likely(uimm != 0))
1356 1392 gen_op_xori(uimm << 16);
1357   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1393 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1358 1394 }
1359 1395  
1360 1396 /* popcntb : PowerPC 2.03 specification */
1361 1397 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1362 1398 {
1363   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1399 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1364 1400 #if defined(TARGET_PPC64)
1365 1401 if (ctx->sf_mode)
1366 1402 gen_op_popcntb_64();
1367 1403 else
1368 1404 #endif
1369 1405 gen_op_popcntb();
1370   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1406 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1371 1407 }
1372 1408  
1373 1409 #if defined(TARGET_PPC64)
... ... @@ -1389,18 +1425,18 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1389 1425 sh = SH(ctx->opcode);
1390 1426 if (likely(sh == 0)) {
1391 1427 if (likely(mb == 0 && me == 31)) {
1392   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1428 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1393 1429 goto do_store;
1394 1430 } else if (likely(mb == 31 && me == 0)) {
1395   - gen_op_load_gpr_T0(rA(ctx->opcode));
  1431 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1396 1432 goto do_store;
1397 1433 }
1398   - gen_op_load_gpr_T0(rS(ctx->opcode));
1399   - gen_op_load_gpr_T1(rA(ctx->opcode));
  1434 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  1435 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
1400 1436 goto do_mask;
1401 1437 }
1402   - gen_op_load_gpr_T0(rS(ctx->opcode));
1403   - gen_op_load_gpr_T1(rA(ctx->opcode));
  1438 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  1439 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
1404 1440 gen_op_rotli32_T0(SH(ctx->opcode));
1405 1441 do_mask:
1406 1442 #if defined(TARGET_PPC64)
... ... @@ -1412,7 +1448,7 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1412 1448 gen_op_andi_T1(~mask);
1413 1449 gen_op_or();
1414 1450 do_store:
1415   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1451 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1416 1452 if (unlikely(Rc(ctx->opcode) != 0))
1417 1453 gen_set_Rc0(ctx);
1418 1454 }
... ... @@ -1424,7 +1460,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1424 1460 sh = SH(ctx->opcode);
1425 1461 mb = MB(ctx->opcode);
1426 1462 me = ME(ctx->opcode);
1427   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1463 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1428 1464 if (likely(sh == 0)) {
1429 1465 goto do_mask;
1430 1466 }
... ... @@ -1450,7 +1486,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1450 1486 #endif
1451 1487 gen_op_andi_T0(MASK(mb, me));
1452 1488 do_store:
1453   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1489 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1454 1490 if (unlikely(Rc(ctx->opcode) != 0))
1455 1491 gen_set_Rc0(ctx);
1456 1492 }
... ... @@ -1461,8 +1497,8 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1461 1497  
1462 1498 mb = MB(ctx->opcode);
1463 1499 me = ME(ctx->opcode);
1464   - gen_op_load_gpr_T0(rS(ctx->opcode));
1465   - gen_op_load_gpr_T1(rB(ctx->opcode));
  1500 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  1501 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
1466 1502 gen_op_rotl32_T0_T1();
1467 1503 if (unlikely(mb != 0 || me != 31)) {
1468 1504 #if defined(TARGET_PPC64)
... ... @@ -1471,7 +1507,7 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1471 1507 #endif
1472 1508 gen_op_andi_T0(MASK(mb, me));
1473 1509 }
1474   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1510 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1475 1511 if (unlikely(Rc(ctx->opcode) != 0))
1476 1512 gen_set_Rc0(ctx);
1477 1513 }
... ... @@ -1527,7 +1563,7 @@ static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1527 1563 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1528 1564 uint32_t me, uint32_t sh)
1529 1565 {
1530   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1566 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1531 1567 if (likely(sh == 0)) {
1532 1568 goto do_mask;
1533 1569 }
... ... @@ -1549,7 +1585,7 @@ static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1549 1585 do_mask:
1550 1586 gen_andi_T0_64(ctx, MASK(mb, me));
1551 1587 do_store:
1552   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1588 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1553 1589 if (unlikely(Rc(ctx->opcode) != 0))
1554 1590 gen_set_Rc0(ctx);
1555 1591 }
... ... @@ -1587,13 +1623,13 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04);
1587 1623 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1588 1624 uint32_t me)
1589 1625 {
1590   - gen_op_load_gpr_T0(rS(ctx->opcode));
1591   - gen_op_load_gpr_T1(rB(ctx->opcode));
  1626 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  1627 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
1592 1628 gen_op_rotl64_T0_T1();
1593 1629 if (unlikely(mb != 0 || me != 63)) {
1594 1630 gen_andi_T0_64(ctx, MASK(mb, me));
1595 1631 }
1596   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1632 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1597 1633 if (unlikely(Rc(ctx->opcode) != 0))
1598 1634 gen_set_Rc0(ctx);
1599 1635 }
... ... @@ -1627,15 +1663,15 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1627 1663 me = 63 - sh;
1628 1664 if (likely(sh == 0)) {
1629 1665 if (likely(mb == 0)) {
1630   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1666 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1631 1667 goto do_store;
1632 1668 }
1633   - gen_op_load_gpr_T0(rS(ctx->opcode));
1634   - gen_op_load_gpr_T1(rA(ctx->opcode));
  1669 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  1670 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
1635 1671 goto do_mask;
1636 1672 }
1637   - gen_op_load_gpr_T0(rS(ctx->opcode));
1638   - gen_op_load_gpr_T1(rA(ctx->opcode));
  1673 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  1674 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
1639 1675 gen_op_rotli64_T0(sh);
1640 1676 do_mask:
1641 1677 mask = MASK(mb, me);
... ... @@ -1643,7 +1679,7 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1643 1679 gen_andi_T1_64(ctx, ~mask);
1644 1680 gen_op_or();
1645 1681 do_store:
1646   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1682 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1647 1683 if (unlikely(Rc(ctx->opcode) != 0))
1648 1684 gen_set_Rc0(ctx);
1649 1685 }
... ... @@ -1659,7 +1695,7 @@ __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1659 1695 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1660 1696 {
1661 1697 int mb, me;
1662   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1698 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1663 1699 if (SH(ctx->opcode) != 0) {
1664 1700 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1665 1701 mb = 32 - SH(ctx->opcode);
... ... @@ -1670,7 +1706,7 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1670 1706 #endif
1671 1707 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1672 1708 }
1673   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1709 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1674 1710 if (unlikely(Rc(ctx->opcode) != 0))
1675 1711 gen_set_Rc0(ctx);
1676 1712 }
... ... @@ -1688,7 +1724,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n)
1688 1724 uint64_t mask;
1689 1725 int sh, mb, me;
1690 1726  
1691   - gen_op_load_gpr_T0(rS(ctx->opcode));
  1727 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1692 1728 sh = SH(ctx->opcode) + (n << 5);
1693 1729 if (sh != 0) {
1694 1730 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
... ... @@ -1697,7 +1733,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n)
1697 1733 mask = MASK(mb, me);
1698 1734 gen_op_sradi(sh, mask >> 32, mask);
1699 1735 }
1700   - gen_op_store_T0_gpr(rA(ctx->opcode));
  1736 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1701 1737 if (unlikely(Rc(ctx->opcode) != 0))
1702 1738 gen_set_Rc0(ctx);
1703 1739 }
... ... @@ -2082,7 +2118,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx,
2082 2118 if (rA(ctx->opcode) == 0) {
2083 2119 tcg_gen_movi_tl(cpu_T[0], simm);
2084 2120 } else {
2085   - gen_op_load_gpr_T0(rA(ctx->opcode));
  2121 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
2086 2122 if (likely(simm != 0))
2087 2123 gen_op_addi(simm);
2088 2124 }
... ... @@ -2094,10 +2130,10 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx,
2094 2130 static always_inline void gen_addr_reg_index (DisasContext *ctx)
2095 2131 {
2096 2132 if (rA(ctx->opcode) == 0) {
2097   - gen_op_load_gpr_T0(rB(ctx->opcode));
  2133 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
2098 2134 } else {
2099   - gen_op_load_gpr_T0(rA(ctx->opcode));
2100   - gen_op_load_gpr_T1(rB(ctx->opcode));
  2135 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  2136 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
2101 2137 gen_op_add();
2102 2138 }
2103 2139 #ifdef DEBUG_MEMORY_ACCESSES
... ... @@ -2110,7 +2146,7 @@ static always_inline void gen_addr_register (DisasContext *ctx)
2110 2146 if (rA(ctx->opcode) == 0) {
2111 2147 tcg_gen_movi_tl(cpu_T[0], 0);
2112 2148 } else {
2113   - gen_op_load_gpr_T0(rA(ctx->opcode));
  2149 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
2114 2150 }
2115 2151 #ifdef DEBUG_MEMORY_ACCESSES
2116 2152 gen_op_print_mem_EA();
... ... @@ -2181,7 +2217,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2181 2217 { \
2182 2218 gen_addr_imm_index(ctx, 0); \
2183 2219 op_ldst(l##width); \
2184   - gen_op_store_T1_gpr(rD(ctx->opcode)); \
  2220 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
2185 2221 }
2186 2222  
2187 2223 #define GEN_LDU(width, opc, type) \
... ... @@ -2197,8 +2233,8 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2197 2233 else \
2198 2234 gen_addr_imm_index(ctx, 0); \
2199 2235 op_ldst(l##width); \
2200   - gen_op_store_T1_gpr(rD(ctx->opcode)); \
2201   - gen_op_store_T0_gpr(rA(ctx->opcode)); \
  2236 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
  2237 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2202 2238 }
2203 2239  
2204 2240 #define GEN_LDUX(width, opc2, opc3, type) \
... ... @@ -2211,8 +2247,8 @@ GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2211 2247 } \
2212 2248 gen_addr_reg_index(ctx); \
2213 2249 op_ldst(l##width); \
2214   - gen_op_store_T1_gpr(rD(ctx->opcode)); \
2215   - gen_op_store_T0_gpr(rA(ctx->opcode)); \
  2250 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
  2251 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2216 2252 }
2217 2253  
2218 2254 #define GEN_LDX(width, opc2, opc3, type) \
... ... @@ -2220,7 +2256,7 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2220 2256 { \
2221 2257 gen_addr_reg_index(ctx); \
2222 2258 op_ldst(l##width); \
2223   - gen_op_store_T1_gpr(rD(ctx->opcode)); \
  2259 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
2224 2260 }
2225 2261  
2226 2262 #define GEN_LDS(width, op, type) \
... ... @@ -2266,9 +2302,9 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2266 2302 /* ld - ldu */
2267 2303 op_ldst(ld);
2268 2304 }
2269   - gen_op_store_T1_gpr(rD(ctx->opcode));
  2305 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
2270 2306 if (Rc(ctx->opcode))
2271   - gen_op_store_T0_gpr(rA(ctx->opcode));
  2307 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
2272 2308 }
2273 2309 /* lq */
2274 2310 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
... ... @@ -2296,10 +2332,10 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2296 2332 }
2297 2333 gen_addr_imm_index(ctx, 0x0F);
2298 2334 op_ldst(ld);
2299   - gen_op_store_T1_gpr(rd);
  2335 + tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]);
2300 2336 gen_op_addi(8);
2301 2337 op_ldst(ld);
2302   - gen_op_store_T1_gpr(rd + 1);
  2338 + tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]);
2303 2339 #endif
2304 2340 }
2305 2341 #endif
... ... @@ -2309,7 +2345,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2309 2345 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2310 2346 { \
2311 2347 gen_addr_imm_index(ctx, 0); \
2312   - gen_op_load_gpr_T1(rS(ctx->opcode)); \
  2348 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
2313 2349 op_ldst(st##width); \
2314 2350 }
2315 2351  
... ... @@ -2324,9 +2360,9 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2324 2360 gen_addr_imm_index(ctx, 0x03); \
2325 2361 else \
2326 2362 gen_addr_imm_index(ctx, 0); \
2327   - gen_op_load_gpr_T1(rS(ctx->opcode)); \
  2363 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
2328 2364 op_ldst(st##width); \
2329   - gen_op_store_T0_gpr(rA(ctx->opcode)); \
  2365 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2330 2366 }
2331 2367  
2332 2368 #define GEN_STUX(width, opc2, opc3, type) \
... ... @@ -2337,16 +2373,16 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2337 2373 return; \
2338 2374 } \
2339 2375 gen_addr_reg_index(ctx); \
2340   - gen_op_load_gpr_T1(rS(ctx->opcode)); \
  2376 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
2341 2377 op_ldst(st##width); \
2342   - gen_op_store_T0_gpr(rA(ctx->opcode)); \
  2378 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2343 2379 }
2344 2380  
2345 2381 #define GEN_STX(width, opc2, opc3, type) \
2346 2382 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2347 2383 { \
2348 2384 gen_addr_reg_index(ctx); \
2349   - gen_op_load_gpr_T1(rS(ctx->opcode)); \
  2385 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
2350 2386 op_ldst(st##width); \
2351 2387 }
2352 2388  
... ... @@ -2391,10 +2427,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2391 2427 return;
2392 2428 }
2393 2429 gen_addr_imm_index(ctx, 0x03);
2394   - gen_op_load_gpr_T1(rs);
  2430 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
2395 2431 op_ldst(std);
2396 2432 gen_op_addi(8);
2397   - gen_op_load_gpr_T1(rs + 1);
  2433 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]);
2398 2434 op_ldst(std);
2399 2435 #endif
2400 2436 } else {
... ... @@ -2406,10 +2442,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2406 2442 }
2407 2443 }
2408 2444 gen_addr_imm_index(ctx, 0x03);
2409   - gen_op_load_gpr_T1(rs);
  2445 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
2410 2446 op_ldst(std);
2411 2447 if (Rc(ctx->opcode))
2412   - gen_op_store_T0_gpr(rA(ctx->opcode));
  2448 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
2413 2449 }
2414 2450 }
2415 2451 #endif
... ... @@ -2590,7 +2626,7 @@ GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2590 2626 gen_update_nip(ctx, ctx->nip - 4);
2591 2627 gen_addr_reg_index(ctx);
2592 2628 op_lwarx();
2593   - gen_op_store_T1_gpr(rD(ctx->opcode));
  2629 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
2594 2630 }
2595 2631  
2596 2632 /* stwcx. */
... ... @@ -2599,7 +2635,7 @@ GEN_HANDLER2(stwcx_, &quot;stwcx.&quot;, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2599 2635 /* NIP cannot be restored if the memory exception comes from an helper */
2600 2636 gen_update_nip(ctx, ctx->nip - 4);
2601 2637 gen_addr_reg_index(ctx);
2602   - gen_op_load_gpr_T1(rS(ctx->opcode));
  2638 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
2603 2639 op_stwcx();
2604 2640 }
2605 2641  
... ... @@ -2620,7 +2656,7 @@ GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2620 2656 gen_update_nip(ctx, ctx->nip - 4);
2621 2657 gen_addr_reg_index(ctx);
2622 2658 op_ldarx();
2623   - gen_op_store_T1_gpr(rD(ctx->opcode));
  2659 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
2624 2660 }
2625 2661  
2626 2662 /* stdcx. */
... ... @@ -2629,7 +2665,7 @@ GEN_HANDLER2(stdcx_, &quot;stdcx.&quot;, 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2629 2665 /* NIP cannot be restored if the memory exception comes from an helper */
2630 2666 gen_update_nip(ctx, ctx->nip - 4);
2631 2667 gen_addr_reg_index(ctx);
2632   - gen_op_load_gpr_T1(rS(ctx->opcode));
  2668 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
2633 2669 op_stdcx();
2634 2670 }
2635 2671 #endif /* defined(TARGET_PPC64) */
... ... @@ -2674,7 +2710,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2674 2710 gen_addr_imm_index(ctx, 0); \
2675 2711 op_ldst(l##width); \
2676 2712 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2677   - gen_op_store_T0_gpr(rA(ctx->opcode)); \
  2713 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2678 2714 }
2679 2715  
2680 2716 #define GEN_LDUXF(width, opc, type) \
... ... @@ -2691,7 +2727,7 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2691 2727 gen_addr_reg_index(ctx); \
2692 2728 op_ldst(l##width); \
2693 2729 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2694   - gen_op_store_T0_gpr(rA(ctx->opcode)); \
  2730 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2695 2731 }
2696 2732  
2697 2733 #define GEN_LDXF(width, opc2, opc3, type) \
... ... @@ -2745,7 +2781,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2745 2781 gen_addr_imm_index(ctx, 0); \
2746 2782 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2747 2783 op_ldst(st##width); \
2748   - gen_op_store_T0_gpr(rA(ctx->opcode)); \
  2784 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2749 2785 }
2750 2786  
2751 2787 #define GEN_STUXF(width, opc, type) \
... ... @@ -2762,7 +2798,7 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2762 2798 gen_addr_reg_index(ctx); \
2763 2799 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2764 2800 op_ldst(st##width); \
2765   - gen_op_store_T0_gpr(rA(ctx->opcode)); \
  2801 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2766 2802 }
2767 2803  
2768 2804 #define GEN_STXF(width, opc2, opc3, type) \
... ... @@ -3154,8 +3190,8 @@ GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3154 3190 /* tw */
3155 3191 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3156 3192 {
3157   - gen_op_load_gpr_T0(rA(ctx->opcode));
3158   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3193 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  3194 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3159 3195 /* Update the nip since this might generate a trap exception */
3160 3196 gen_update_nip(ctx, ctx->nip);
3161 3197 gen_op_tw(TO(ctx->opcode));
... ... @@ -3164,7 +3200,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3164 3200 /* twi */
3165 3201 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3166 3202 {
3167   - gen_op_load_gpr_T0(rA(ctx->opcode));
  3203 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3168 3204 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3169 3205 /* Update the nip since this might generate a trap exception */
3170 3206 gen_update_nip(ctx, ctx->nip);
... ... @@ -3175,8 +3211,8 @@ GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3175 3211 /* td */
3176 3212 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3177 3213 {
3178   - gen_op_load_gpr_T0(rA(ctx->opcode));
3179   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3214 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  3215 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3180 3216 /* Update the nip since this might generate a trap exception */
3181 3217 gen_update_nip(ctx, ctx->nip);
3182 3218 gen_op_td(TO(ctx->opcode));
... ... @@ -3185,7 +3221,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3185 3221 /* tdi */
3186 3222 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3187 3223 {
3188   - gen_op_load_gpr_T0(rA(ctx->opcode));
  3224 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3189 3225 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3190 3226 /* Update the nip since this might generate a trap exception */
3191 3227 gen_update_nip(ctx, ctx->nip);
... ... @@ -3217,7 +3253,7 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3217 3253 } else {
3218 3254 gen_op_load_cr();
3219 3255 }
3220   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3256 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3221 3257 }
3222 3258  
3223 3259 /* mfmsr */
... ... @@ -3231,7 +3267,7 @@ GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3231 3267 return;
3232 3268 }
3233 3269 gen_op_load_msr();
3234   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3270 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3235 3271 #endif
3236 3272 }
3237 3273  
... ... @@ -3263,7 +3299,7 @@ static always_inline void gen_op_mfspr (DisasContext *ctx)
3263 3299 if (likely(read_cb != NULL)) {
3264 3300 if (likely(read_cb != SPR_NOACCESS)) {
3265 3301 (*read_cb)(ctx, sprn);
3266   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3302 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3267 3303 } else {
3268 3304 /* Privilege exception */
3269 3305 /* This is a hack to avoid warnings when running Linux:
... ... @@ -3309,7 +3345,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3309 3345 {
3310 3346 uint32_t crm, crn;
3311 3347  
3312   - gen_op_load_gpr_T0(rS(ctx->opcode));
  3348 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3313 3349 crm = CRM(ctx->opcode);
3314 3350 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3315 3351 crn = ffs(crm);
... ... @@ -3332,7 +3368,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3332 3368 GEN_EXCP_PRIVREG(ctx);
3333 3369 return;
3334 3370 }
3335   - gen_op_load_gpr_T0(rS(ctx->opcode));
  3371 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3336 3372 if (ctx->opcode & 0x00010000) {
3337 3373 /* Special form that does not need any synchronisation */
3338 3374 gen_op_update_riee();
... ... @@ -3360,7 +3396,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3360 3396 GEN_EXCP_PRIVREG(ctx);
3361 3397 return;
3362 3398 }
3363   - gen_op_load_gpr_T0(rS(ctx->opcode));
  3399 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3364 3400 if (ctx->opcode & 0x00010000) {
3365 3401 /* Special form that does not need any synchronisation */
3366 3402 gen_op_update_riee();
... ... @@ -3399,7 +3435,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3399 3435 write_cb = ctx->spr_cb[sprn].uea_write;
3400 3436 if (likely(write_cb != NULL)) {
3401 3437 if (likely(write_cb != SPR_NOACCESS)) {
3402   - gen_op_load_gpr_T0(rS(ctx->opcode));
  3438 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3403 3439 (*write_cb)(ctx, sprn);
3404 3440 } else {
3405 3441 /* Privilege exception */
... ... @@ -3614,7 +3650,7 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3614 3650 }
3615 3651 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3616 3652 gen_op_load_sr();
3617   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3653 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3618 3654 #endif
3619 3655 }
3620 3656  
... ... @@ -3628,10 +3664,10 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
3628 3664 GEN_EXCP_PRIVREG(ctx);
3629 3665 return;
3630 3666 }
3631   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3667 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3632 3668 gen_op_srli_T1(28);
3633 3669 gen_op_load_sr();
3634   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3670 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3635 3671 #endif
3636 3672 }
3637 3673  
... ... @@ -3645,7 +3681,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
3645 3681 GEN_EXCP_PRIVREG(ctx);
3646 3682 return;
3647 3683 }
3648   - gen_op_load_gpr_T0(rS(ctx->opcode));
  3684 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3649 3685 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3650 3686 gen_op_store_sr();
3651 3687 #endif
... ... @@ -3661,8 +3697,8 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
3661 3697 GEN_EXCP_PRIVREG(ctx);
3662 3698 return;
3663 3699 }
3664   - gen_op_load_gpr_T0(rS(ctx->opcode));
3665   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3700 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  3701 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3666 3702 gen_op_srli_T1(28);
3667 3703 gen_op_store_sr();
3668 3704 #endif
... ... @@ -3682,7 +3718,7 @@ GEN_HANDLER2(mfsr_64b, &quot;mfsr&quot;, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
3682 3718 }
3683 3719 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3684 3720 gen_op_load_slb();
3685   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3721 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3686 3722 #endif
3687 3723 }
3688 3724  
... ... @@ -3697,10 +3733,10 @@ GEN_HANDLER2(mfsrin_64b, &quot;mfsrin&quot;, 0x1F, 0x13, 0x14, 0x001F0001,
3697 3733 GEN_EXCP_PRIVREG(ctx);
3698 3734 return;
3699 3735 }
3700   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3736 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3701 3737 gen_op_srli_T1(28);
3702 3738 gen_op_load_slb();
3703   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3739 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3704 3740 #endif
3705 3741 }
3706 3742  
... ... @@ -3714,7 +3750,7 @@ GEN_HANDLER2(mtsr_64b, &quot;mtsr&quot;, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
3714 3750 GEN_EXCP_PRIVREG(ctx);
3715 3751 return;
3716 3752 }
3717   - gen_op_load_gpr_T0(rS(ctx->opcode));
  3753 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3718 3754 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3719 3755 gen_op_store_slb();
3720 3756 #endif
... ... @@ -3731,8 +3767,8 @@ GEN_HANDLER2(mtsrin_64b, &quot;mtsrin&quot;, 0x1F, 0x12, 0x07, 0x001F0001,
3731 3767 GEN_EXCP_PRIVREG(ctx);
3732 3768 return;
3733 3769 }
3734   - gen_op_load_gpr_T0(rS(ctx->opcode));
3735   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3770 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  3771 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3736 3772 gen_op_srli_T1(28);
3737 3773 gen_op_store_slb();
3738 3774 #endif
... ... @@ -3765,7 +3801,7 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
3765 3801 GEN_EXCP_PRIVOPC(ctx);
3766 3802 return;
3767 3803 }
3768   - gen_op_load_gpr_T0(rB(ctx->opcode));
  3804 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
3769 3805 #if defined(TARGET_PPC64)
3770 3806 if (ctx->sf_mode)
3771 3807 gen_op_tlbie_64();
... ... @@ -3817,7 +3853,7 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
3817 3853 GEN_EXCP_PRIVOPC(ctx);
3818 3854 return;
3819 3855 }
3820   - gen_op_load_gpr_T0(rB(ctx->opcode));
  3856 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
3821 3857 gen_op_slbie();
3822 3858 #endif
3823 3859 }
... ... @@ -3840,7 +3876,7 @@ GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
3840 3876 /* Should check EAR[E] & alignment ! */
3841 3877 gen_addr_reg_index(ctx);
3842 3878 op_eciwx();
3843   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3879 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3844 3880 }
3845 3881  
3846 3882 /* ecowx */
... ... @@ -3848,7 +3884,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
3848 3884 {
3849 3885 /* Should check EAR[E] & alignment ! */
3850 3886 gen_addr_reg_index(ctx);
3851   - gen_op_load_gpr_T1(rS(ctx->opcode));
  3887 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
3852 3888 op_ecowx();
3853 3889 }
3854 3890  
... ... @@ -3856,9 +3892,9 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
3856 3892 /* abs - abs. */
3857 3893 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
3858 3894 {
3859   - gen_op_load_gpr_T0(rA(ctx->opcode));
  3895 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3860 3896 gen_op_POWER_abs();
3861   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3897 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3862 3898 if (unlikely(Rc(ctx->opcode) != 0))
3863 3899 gen_set_Rc0(ctx);
3864 3900 }
... ... @@ -3866,9 +3902,9 @@ GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
3866 3902 /* abso - abso. */
3867 3903 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3868 3904 {
3869   - gen_op_load_gpr_T0(rA(ctx->opcode));
  3905 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3870 3906 gen_op_POWER_abso();
3871   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3907 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3872 3908 if (unlikely(Rc(ctx->opcode) != 0))
3873 3909 gen_set_Rc0(ctx);
3874 3910 }
... ... @@ -3876,19 +3912,19 @@ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3876 3912 /* clcs */
3877 3913 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
3878 3914 {
3879   - gen_op_load_gpr_T0(rA(ctx->opcode));
  3915 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3880 3916 gen_op_POWER_clcs();
3881 3917 /* Rc=1 sets CR0 to an undefined state */
3882   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3918 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3883 3919 }
3884 3920  
3885 3921 /* div - div. */
3886 3922 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
3887 3923 {
3888   - gen_op_load_gpr_T0(rA(ctx->opcode));
3889   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3924 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  3925 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3890 3926 gen_op_POWER_div();
3891   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3927 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3892 3928 if (unlikely(Rc(ctx->opcode) != 0))
3893 3929 gen_set_Rc0(ctx);
3894 3930 }
... ... @@ -3896,10 +3932,10 @@ GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
3896 3932 /* divo - divo. */
3897 3933 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
3898 3934 {
3899   - gen_op_load_gpr_T0(rA(ctx->opcode));
3900   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3935 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  3936 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3901 3937 gen_op_POWER_divo();
3902   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3938 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3903 3939 if (unlikely(Rc(ctx->opcode) != 0))
3904 3940 gen_set_Rc0(ctx);
3905 3941 }
... ... @@ -3907,10 +3943,10 @@ GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
3907 3943 /* divs - divs. */
3908 3944 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
3909 3945 {
3910   - gen_op_load_gpr_T0(rA(ctx->opcode));
3911   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3946 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  3947 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3912 3948 gen_op_POWER_divs();
3913   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3949 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3914 3950 if (unlikely(Rc(ctx->opcode) != 0))
3915 3951 gen_set_Rc0(ctx);
3916 3952 }
... ... @@ -3918,10 +3954,10 @@ GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
3918 3954 /* divso - divso. */
3919 3955 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
3920 3956 {
3921   - gen_op_load_gpr_T0(rA(ctx->opcode));
3922   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3957 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  3958 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3923 3959 gen_op_POWER_divso();
3924   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3960 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3925 3961 if (unlikely(Rc(ctx->opcode) != 0))
3926 3962 gen_set_Rc0(ctx);
3927 3963 }
... ... @@ -3929,10 +3965,10 @@ GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
3929 3965 /* doz - doz. */
3930 3966 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
3931 3967 {
3932   - gen_op_load_gpr_T0(rA(ctx->opcode));
3933   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3968 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  3969 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3934 3970 gen_op_POWER_doz();
3935   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3971 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3936 3972 if (unlikely(Rc(ctx->opcode) != 0))
3937 3973 gen_set_Rc0(ctx);
3938 3974 }
... ... @@ -3940,10 +3976,10 @@ GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
3940 3976 /* dozo - dozo. */
3941 3977 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
3942 3978 {
3943   - gen_op_load_gpr_T0(rA(ctx->opcode));
3944   - gen_op_load_gpr_T1(rB(ctx->opcode));
  3979 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  3980 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3945 3981 gen_op_POWER_dozo();
3946   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3982 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3947 3983 if (unlikely(Rc(ctx->opcode) != 0))
3948 3984 gen_set_Rc0(ctx);
3949 3985 }
... ... @@ -3951,10 +3987,10 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
3951 3987 /* dozi */
3952 3988 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
3953 3989 {
3954   - gen_op_load_gpr_T0(rA(ctx->opcode));
  3990 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3955 3991 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3956 3992 gen_op_POWER_doz();
3957   - gen_op_store_T0_gpr(rD(ctx->opcode));
  3993 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3958 3994 }
3959 3995  
3960 3996 /* As lscbx load from memory byte after byte, it's always endian safe.
... ... @@ -4001,10 +4037,10 @@ GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4001 4037 /* maskg - maskg. */
4002 4038 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4003 4039 {
4004   - gen_op_load_gpr_T0(rS(ctx->opcode));
4005   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4040 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4041 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4006 4042 gen_op_POWER_maskg();
4007   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4043 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4008 4044 if (unlikely(Rc(ctx->opcode) != 0))
4009 4045 gen_set_Rc0(ctx);
4010 4046 }
... ... @@ -4012,11 +4048,11 @@ GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4012 4048 /* maskir - maskir. */
4013 4049 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4014 4050 {
4015   - gen_op_load_gpr_T0(rA(ctx->opcode));
4016   - gen_op_load_gpr_T1(rS(ctx->opcode));
4017   - gen_op_load_gpr_T2(rB(ctx->opcode));
  4051 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  4052 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
  4053 + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4018 4054 gen_op_POWER_maskir();
4019   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4055 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4020 4056 if (unlikely(Rc(ctx->opcode) != 0))
4021 4057 gen_set_Rc0(ctx);
4022 4058 }
... ... @@ -4024,10 +4060,10 @@ GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4024 4060 /* mul - mul. */
4025 4061 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4026 4062 {
4027   - gen_op_load_gpr_T0(rA(ctx->opcode));
4028   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4063 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  4064 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4029 4065 gen_op_POWER_mul();
4030   - gen_op_store_T0_gpr(rD(ctx->opcode));
  4066 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4031 4067 if (unlikely(Rc(ctx->opcode) != 0))
4032 4068 gen_set_Rc0(ctx);
4033 4069 }
... ... @@ -4035,10 +4071,10 @@ GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4035 4071 /* mulo - mulo. */
4036 4072 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4037 4073 {
4038   - gen_op_load_gpr_T0(rA(ctx->opcode));
4039   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4074 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  4075 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4040 4076 gen_op_POWER_mulo();
4041   - gen_op_store_T0_gpr(rD(ctx->opcode));
  4077 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4042 4078 if (unlikely(Rc(ctx->opcode) != 0))
4043 4079 gen_set_Rc0(ctx);
4044 4080 }
... ... @@ -4046,9 +4082,9 @@ GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4046 4082 /* nabs - nabs. */
4047 4083 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4048 4084 {
4049   - gen_op_load_gpr_T0(rA(ctx->opcode));
  4085 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4050 4086 gen_op_POWER_nabs();
4051   - gen_op_store_T0_gpr(rD(ctx->opcode));
  4087 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4052 4088 if (unlikely(Rc(ctx->opcode) != 0))
4053 4089 gen_set_Rc0(ctx);
4054 4090 }
... ... @@ -4056,9 +4092,9 @@ GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4056 4092 /* nabso - nabso. */
4057 4093 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4058 4094 {
4059   - gen_op_load_gpr_T0(rA(ctx->opcode));
  4095 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4060 4096 gen_op_POWER_nabso();
4061   - gen_op_store_T0_gpr(rD(ctx->opcode));
  4097 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4062 4098 if (unlikely(Rc(ctx->opcode) != 0))
4063 4099 gen_set_Rc0(ctx);
4064 4100 }
... ... @@ -4070,11 +4106,11 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4070 4106  
4071 4107 mb = MB(ctx->opcode);
4072 4108 me = ME(ctx->opcode);
4073   - gen_op_load_gpr_T0(rS(ctx->opcode));
4074   - gen_op_load_gpr_T1(rA(ctx->opcode));
4075   - gen_op_load_gpr_T2(rB(ctx->opcode));
  4109 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4110 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
  4111 + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4076 4112 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4077   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4113 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4078 4114 if (unlikely(Rc(ctx->opcode) != 0))
4079 4115 gen_set_Rc0(ctx);
4080 4116 }
... ... @@ -4082,11 +4118,11 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4082 4118 /* rrib - rrib. */
4083 4119 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4084 4120 {
4085   - gen_op_load_gpr_T0(rS(ctx->opcode));
4086   - gen_op_load_gpr_T1(rA(ctx->opcode));
4087   - gen_op_load_gpr_T2(rB(ctx->opcode));
  4121 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4122 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
  4123 + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4088 4124 gen_op_POWER_rrib();
4089   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4125 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4090 4126 if (unlikely(Rc(ctx->opcode) != 0))
4091 4127 gen_set_Rc0(ctx);
4092 4128 }
... ... @@ -4094,10 +4130,10 @@ GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4094 4130 /* sle - sle. */
4095 4131 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4096 4132 {
4097   - gen_op_load_gpr_T0(rS(ctx->opcode));
4098   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4133 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4134 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4099 4135 gen_op_POWER_sle();
4100   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4136 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4101 4137 if (unlikely(Rc(ctx->opcode) != 0))
4102 4138 gen_set_Rc0(ctx);
4103 4139 }
... ... @@ -4105,10 +4141,10 @@ GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4105 4141 /* sleq - sleq. */
4106 4142 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4107 4143 {
4108   - gen_op_load_gpr_T0(rS(ctx->opcode));
4109   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4144 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4145 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4110 4146 gen_op_POWER_sleq();
4111   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4147 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4112 4148 if (unlikely(Rc(ctx->opcode) != 0))
4113 4149 gen_set_Rc0(ctx);
4114 4150 }
... ... @@ -4116,10 +4152,10 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4116 4152 /* sliq - sliq. */
4117 4153 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4118 4154 {
4119   - gen_op_load_gpr_T0(rS(ctx->opcode));
  4155 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4120 4156 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4121 4157 gen_op_POWER_sle();
4122   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4158 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4123 4159 if (unlikely(Rc(ctx->opcode) != 0))
4124 4160 gen_set_Rc0(ctx);
4125 4161 }
... ... @@ -4127,10 +4163,10 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4127 4163 /* slliq - slliq. */
4128 4164 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4129 4165 {
4130   - gen_op_load_gpr_T0(rS(ctx->opcode));
  4166 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4131 4167 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4132 4168 gen_op_POWER_sleq();
4133   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4169 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4134 4170 if (unlikely(Rc(ctx->opcode) != 0))
4135 4171 gen_set_Rc0(ctx);
4136 4172 }
... ... @@ -4138,10 +4174,10 @@ GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4138 4174 /* sllq - sllq. */
4139 4175 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4140 4176 {
4141   - gen_op_load_gpr_T0(rS(ctx->opcode));
4142   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4177 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4178 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4143 4179 gen_op_POWER_sllq();
4144   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4180 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4145 4181 if (unlikely(Rc(ctx->opcode) != 0))
4146 4182 gen_set_Rc0(ctx);
4147 4183 }
... ... @@ -4149,10 +4185,10 @@ GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4149 4185 /* slq - slq. */
4150 4186 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4151 4187 {
4152   - gen_op_load_gpr_T0(rS(ctx->opcode));
4153   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4188 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4189 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4154 4190 gen_op_POWER_slq();
4155   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4191 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4156 4192 if (unlikely(Rc(ctx->opcode) != 0))
4157 4193 gen_set_Rc0(ctx);
4158 4194 }
... ... @@ -4160,10 +4196,10 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4160 4196 /* sraiq - sraiq. */
4161 4197 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4162 4198 {
4163   - gen_op_load_gpr_T0(rS(ctx->opcode));
  4199 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4164 4200 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4165 4201 gen_op_POWER_sraq();
4166   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4202 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4167 4203 if (unlikely(Rc(ctx->opcode) != 0))
4168 4204 gen_set_Rc0(ctx);
4169 4205 }
... ... @@ -4171,10 +4207,10 @@ GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4171 4207 /* sraq - sraq. */
4172 4208 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4173 4209 {
4174   - gen_op_load_gpr_T0(rS(ctx->opcode));
4175   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4210 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4211 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4176 4212 gen_op_POWER_sraq();
4177   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4213 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4178 4214 if (unlikely(Rc(ctx->opcode) != 0))
4179 4215 gen_set_Rc0(ctx);
4180 4216 }
... ... @@ -4182,10 +4218,10 @@ GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4182 4218 /* sre - sre. */
4183 4219 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4184 4220 {
4185   - gen_op_load_gpr_T0(rS(ctx->opcode));
4186   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4221 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4222 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4187 4223 gen_op_POWER_sre();
4188   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4224 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4189 4225 if (unlikely(Rc(ctx->opcode) != 0))
4190 4226 gen_set_Rc0(ctx);
4191 4227 }
... ... @@ -4193,10 +4229,10 @@ GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4193 4229 /* srea - srea. */
4194 4230 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4195 4231 {
4196   - gen_op_load_gpr_T0(rS(ctx->opcode));
4197   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4232 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4233 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4198 4234 gen_op_POWER_srea();
4199   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4235 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4200 4236 if (unlikely(Rc(ctx->opcode) != 0))
4201 4237 gen_set_Rc0(ctx);
4202 4238 }
... ... @@ -4204,10 +4240,10 @@ GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4204 4240 /* sreq */
4205 4241 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4206 4242 {
4207   - gen_op_load_gpr_T0(rS(ctx->opcode));
4208   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4243 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4244 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4209 4245 gen_op_POWER_sreq();
4210   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4246 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4211 4247 if (unlikely(Rc(ctx->opcode) != 0))
4212 4248 gen_set_Rc0(ctx);
4213 4249 }
... ... @@ -4215,10 +4251,10 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4215 4251 /* sriq */
4216 4252 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4217 4253 {
4218   - gen_op_load_gpr_T0(rS(ctx->opcode));
  4254 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4219 4255 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4220 4256 gen_op_POWER_srq();
4221   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4257 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4222 4258 if (unlikely(Rc(ctx->opcode) != 0))
4223 4259 gen_set_Rc0(ctx);
4224 4260 }
... ... @@ -4226,11 +4262,11 @@ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4226 4262 /* srliq */
4227 4263 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4228 4264 {
4229   - gen_op_load_gpr_T0(rS(ctx->opcode));
4230   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4265 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4266 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4231 4267 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4232 4268 gen_op_POWER_srlq();
4233   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4269 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4234 4270 if (unlikely(Rc(ctx->opcode) != 0))
4235 4271 gen_set_Rc0(ctx);
4236 4272 }
... ... @@ -4238,10 +4274,10 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4238 4274 /* srlq */
4239 4275 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4240 4276 {
4241   - gen_op_load_gpr_T0(rS(ctx->opcode));
4242   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4277 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4278 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4243 4279 gen_op_POWER_srlq();
4244   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4280 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4245 4281 if (unlikely(Rc(ctx->opcode) != 0))
4246 4282 gen_set_Rc0(ctx);
4247 4283 }
... ... @@ -4249,10 +4285,10 @@ GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4249 4285 /* srq */
4250 4286 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4251 4287 {
4252   - gen_op_load_gpr_T0(rS(ctx->opcode));
4253   - gen_op_load_gpr_T1(rB(ctx->opcode));
  4288 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  4289 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4254 4290 gen_op_POWER_srq();
4255   - gen_op_store_T0_gpr(rA(ctx->opcode));
  4291 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4256 4292 if (unlikely(Rc(ctx->opcode) != 0))
4257 4293 gen_set_Rc0(ctx);
4258 4294 }
... ... @@ -4282,9 +4318,9 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4282 4318 GEN_EXCP_PRIVOPC(ctx);
4283 4319 return;
4284 4320 }
4285   - gen_op_load_gpr_T0(rA(ctx->opcode));
  4321 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4286 4322 gen_op_602_mfrom();
4287   - gen_op_store_T0_gpr(rD(ctx->opcode));
  4323 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4288 4324 #endif
4289 4325 }
4290 4326  
... ... @@ -4299,7 +4335,7 @@ GEN_HANDLER2(tlbld_6xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4299 4335 GEN_EXCP_PRIVOPC(ctx);
4300 4336 return;
4301 4337 }
4302   - gen_op_load_gpr_T0(rB(ctx->opcode));
  4338 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4303 4339 gen_op_6xx_tlbld();
4304 4340 #endif
4305 4341 }
... ... @@ -4314,7 +4350,7 @@ GEN_HANDLER2(tlbli_6xx, &quot;tlbli&quot;, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4314 4350 GEN_EXCP_PRIVOPC(ctx);
4315 4351 return;
4316 4352 }
4317   - gen_op_load_gpr_T0(rB(ctx->opcode));
  4353 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4318 4354 gen_op_6xx_tlbli();
4319 4355 #endif
4320 4356 }
... ... @@ -4330,7 +4366,7 @@ GEN_HANDLER2(tlbld_74xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4330 4366 GEN_EXCP_PRIVOPC(ctx);
4331 4367 return;
4332 4368 }
4333   - gen_op_load_gpr_T0(rB(ctx->opcode));
  4369 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4334 4370 gen_op_74xx_tlbld();
4335 4371 #endif
4336 4372 }
... ... @@ -4345,7 +4381,7 @@ GEN_HANDLER2(tlbli_74xx, &quot;tlbli&quot;, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4345 4381 GEN_EXCP_PRIVOPC(ctx);
4346 4382 return;
4347 4383 }
4348   - gen_op_load_gpr_T0(rB(ctx->opcode));
  4384 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4349 4385 gen_op_74xx_tlbli();
4350 4386 #endif
4351 4387 }
... ... @@ -4391,9 +4427,9 @@ GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4391 4427  
4392 4428 gen_addr_reg_index(ctx);
4393 4429 gen_op_POWER_mfsri();
4394   - gen_op_store_T0_gpr(rd);
  4430 + tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
4395 4431 if (ra != 0 && ra != rd)
4396   - gen_op_store_T1_gpr(ra);
  4432 + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
4397 4433 #endif
4398 4434 }
4399 4435  
... ... @@ -4408,7 +4444,7 @@ GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4408 4444 }
4409 4445 gen_addr_reg_index(ctx);
4410 4446 gen_op_POWER_rac();
4411   - gen_op_store_T0_gpr(rD(ctx->opcode));
  4447 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4412 4448 #endif
4413 4449 }
4414 4450  
... ... @@ -4479,7 +4515,7 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4479 4515 gen_op_store_FT0_fpr(rD(ctx->opcode));
4480 4516 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4481 4517 if (ra != 0)
4482   - gen_op_store_T0_gpr(ra);
  4518 + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
4483 4519 }
4484 4520  
4485 4521 /* lfqux */
... ... @@ -4494,7 +4530,7 @@ GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4494 4530 gen_op_store_FT0_fpr(rD(ctx->opcode));
4495 4531 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4496 4532 if (ra != 0)
4497   - gen_op_store_T0_gpr(ra);
  4533 + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
4498 4534 }
4499 4535  
4500 4536 /* lfqx */
... ... @@ -4531,7 +4567,7 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4531 4567 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4532 4568 op_POWER2_stfq();
4533 4569 if (ra != 0)
4534   - gen_op_store_T0_gpr(ra);
  4570 + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
4535 4571 }
4536 4572  
4537 4573 /* stfqux */
... ... @@ -4546,7 +4582,7 @@ GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4546 4582 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4547 4583 op_POWER2_stfq();
4548 4584 if (ra != 0)
4549   - gen_op_store_T0_gpr(ra);
  4585 + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
4550 4586 }
4551 4587  
4552 4588 /* stfqx */
... ... @@ -4594,8 +4630,8 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4594 4630 int opc2, int opc3,
4595 4631 int ra, int rb, int rt, int Rc)
4596 4632 {
4597   - gen_op_load_gpr_T0(ra);
4598   - gen_op_load_gpr_T1(rb);
  4633 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
  4634 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
4599 4635 switch (opc3 & 0x0D) {
4600 4636 case 0x05:
4601 4637 /* macchw - macchw. - macchwo - macchwo. */
... ... @@ -4646,7 +4682,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4646 4682 }
4647 4683 if (opc2 & 0x04) {
4648 4684 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4649   - gen_op_load_gpr_T2(rt);
  4685 + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
4650 4686 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
4651 4687 gen_op_405_add_T0_T2();
4652 4688 }
... ... @@ -4664,7 +4700,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4664 4700 else
4665 4701 gen_op_405_check_satu();
4666 4702 }
4667   - gen_op_store_T0_gpr(rt);
  4703 + tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
4668 4704 if (unlikely(Rc) != 0) {
4669 4705 /* Update Rc0 */
4670 4706 gen_set_Rc0(ctx);
... ... @@ -4778,7 +4814,7 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
4778 4814 }
4779 4815 tcg_gen_movi_tl(cpu_T[0], dcrn);
4780 4816 gen_op_load_dcr();
4781   - gen_op_store_T0_gpr(rD(ctx->opcode));
  4817 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4782 4818 #endif
4783 4819 }
4784 4820  
... ... @@ -4795,7 +4831,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
4795 4831 return;
4796 4832 }
4797 4833 tcg_gen_movi_tl(cpu_T[0], dcrn);
4798   - gen_op_load_gpr_T1(rS(ctx->opcode));
  4834 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4799 4835 gen_op_store_dcr();
4800 4836 #endif
4801 4837 }
... ... @@ -4811,9 +4847,9 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
4811 4847 GEN_EXCP_PRIVREG(ctx);
4812 4848 return;
4813 4849 }
4814   - gen_op_load_gpr_T0(rA(ctx->opcode));
  4850 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4815 4851 gen_op_load_dcr();
4816   - gen_op_store_T0_gpr(rD(ctx->opcode));
  4852 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4817 4853 /* Note: Rc update flag set leads to undefined state of Rc0 */
4818 4854 #endif
4819 4855 }
... ... @@ -4829,8 +4865,8 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
4829 4865 GEN_EXCP_PRIVREG(ctx);
4830 4866 return;
4831 4867 }
4832   - gen_op_load_gpr_T0(rA(ctx->opcode));
4833   - gen_op_load_gpr_T1(rS(ctx->opcode));
  4868 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  4869 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4834 4870 gen_op_store_dcr();
4835 4871 /* Note: Rc update flag set leads to undefined state of Rc0 */
4836 4872 #endif
... ... @@ -4839,17 +4875,17 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
4839 4875 /* mfdcrux (PPC 460) : user-mode access to DCR */
4840 4876 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
4841 4877 {
4842   - gen_op_load_gpr_T0(rA(ctx->opcode));
  4878 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4843 4879 gen_op_load_dcr();
4844   - gen_op_store_T0_gpr(rD(ctx->opcode));
  4880 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4845 4881 /* Note: Rc update flag set leads to undefined state of Rc0 */
4846 4882 }
4847 4883  
4848 4884 /* mtdcrux (PPC 460) : user-mode access to DCR */
4849 4885 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
4850 4886 {
4851   - gen_op_load_gpr_T0(rA(ctx->opcode));
4852   - gen_op_load_gpr_T1(rS(ctx->opcode));
  4887 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  4888 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4853 4889 gen_op_store_dcr();
4854 4890 /* Note: Rc update flag set leads to undefined state of Rc0 */
4855 4891 }
... ... @@ -4880,7 +4916,7 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
4880 4916 }
4881 4917 gen_addr_reg_index(ctx);
4882 4918 op_ldst(lwz);
4883   - gen_op_store_T0_gpr(rD(ctx->opcode));
  4919 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4884 4920 #endif
4885 4921 }
4886 4922  
... ... @@ -4998,14 +5034,14 @@ GEN_HANDLER2(tlbre_40x, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
4998 5034 }
4999 5035 switch (rB(ctx->opcode)) {
5000 5036 case 0:
5001   - gen_op_load_gpr_T0(rA(ctx->opcode));
  5037 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5002 5038 gen_op_4xx_tlbre_hi();
5003   - gen_op_store_T0_gpr(rD(ctx->opcode));
  5039 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5004 5040 break;
5005 5041 case 1:
5006   - gen_op_load_gpr_T0(rA(ctx->opcode));
  5042 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5007 5043 gen_op_4xx_tlbre_lo();
5008   - gen_op_store_T0_gpr(rD(ctx->opcode));
  5044 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5009 5045 break;
5010 5046 default:
5011 5047 GEN_EXCP_INVAL(ctx);
... ... @@ -5028,7 +5064,7 @@ GEN_HANDLER2(tlbsx_40x, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5028 5064 gen_op_4xx_tlbsx();
5029 5065 if (Rc(ctx->opcode))
5030 5066 gen_op_4xx_tlbsx_check();
5031   - gen_op_store_T0_gpr(rD(ctx->opcode));
  5067 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5032 5068 #endif
5033 5069 }
5034 5070  
... ... @@ -5044,13 +5080,13 @@ GEN_HANDLER2(tlbwe_40x, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5044 5080 }
5045 5081 switch (rB(ctx->opcode)) {
5046 5082 case 0:
5047   - gen_op_load_gpr_T0(rA(ctx->opcode));
5048   - gen_op_load_gpr_T1(rS(ctx->opcode));
  5083 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  5084 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5049 5085 gen_op_4xx_tlbwe_hi();
5050 5086 break;
5051 5087 case 1:
5052   - gen_op_load_gpr_T0(rA(ctx->opcode));
5053   - gen_op_load_gpr_T1(rS(ctx->opcode));
  5088 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  5089 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5054 5090 gen_op_4xx_tlbwe_lo();
5055 5091 break;
5056 5092 default:
... ... @@ -5075,9 +5111,9 @@ GEN_HANDLER2(tlbre_440, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5075 5111 case 0:
5076 5112 case 1:
5077 5113 case 2:
5078   - gen_op_load_gpr_T0(rA(ctx->opcode));
  5114 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5079 5115 gen_op_440_tlbre(rB(ctx->opcode));
5080   - gen_op_store_T0_gpr(rD(ctx->opcode));
  5116 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5081 5117 break;
5082 5118 default:
5083 5119 GEN_EXCP_INVAL(ctx);
... ... @@ -5100,7 +5136,7 @@ GEN_HANDLER2(tlbsx_440, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5100 5136 gen_op_440_tlbsx();
5101 5137 if (Rc(ctx->opcode))
5102 5138 gen_op_4xx_tlbsx_check();
5103   - gen_op_store_T0_gpr(rD(ctx->opcode));
  5139 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5104 5140 #endif
5105 5141 }
5106 5142  
... ... @@ -5118,8 +5154,8 @@ GEN_HANDLER2(tlbwe_440, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5118 5154 case 0:
5119 5155 case 1:
5120 5156 case 2:
5121   - gen_op_load_gpr_T0(rA(ctx->opcode));
5122   - gen_op_load_gpr_T1(rS(ctx->opcode));
  5157 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  5158 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5123 5159 gen_op_440_tlbwe(rB(ctx->opcode));
5124 5160 break;
5125 5161 default:
... ... @@ -5139,7 +5175,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
5139 5175 GEN_EXCP_PRIVOPC(ctx);
5140 5176 return;
5141 5177 }
5142   - gen_op_load_gpr_T0(rD(ctx->opcode));
  5178 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
5143 5179 gen_op_wrte();
5144 5180 /* Stop translation to have a chance to raise an exception
5145 5181 * if we just set msr_ee to 1
... ... @@ -5171,10 +5207,10 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
5171 5207 /* dlmzb */
5172 5208 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5173 5209 {
5174   - gen_op_load_gpr_T0(rS(ctx->opcode));
5175   - gen_op_load_gpr_T1(rB(ctx->opcode));
  5210 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
  5211 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
5176 5212 gen_op_440_dlmzb();
5177   - gen_op_store_T0_gpr(rA(ctx->opcode));
  5213 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
5178 5214 gen_op_store_xer_bc();
5179 5215 if (Rc(ctx->opcode)) {
5180 5216 gen_op_440_dlmzb_update_Rc();
... ... @@ -5263,36 +5299,31 @@ GEN_VR_STX(vxl, 0x07, 0x0F);
5263 5299  
5264 5300 /*** SPE extension ***/
5265 5301 /* Register moves */
5266   -#if !defined(TARGET_PPC64)
5267   -
5268   -GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5269   -GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5270   -#if 0 // unused
5271   -GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5272   -#endif
5273   -
5274   -GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5275   -GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5276   -#if 0 // unused
5277   -GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5278   -#endif
5279   -
5280   -#else /* !defined(TARGET_PPC64) */
5281 5302  
5282   -/* No specific load/store functions: GPRs are already 64 bits */
5283   -#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
5284   -#define gen_op_load_gpr64_T1 gen_op_load_gpr_T1
5285   -#if 0 // unused
5286   -#define gen_op_load_gpr64_T2 gen_op_load_gpr_T2
  5303 +static always_inline void gen_load_gpr64(TCGv t, int reg) {
  5304 +#if defined(TARGET_PPC64)
  5305 + tcg_gen_mov_i64(t, cpu_gpr[reg]);
  5306 +#else
  5307 + tcg_gen_extu_i32_i64(t, cpu_gprh[reg]);
  5308 + tcg_gen_shli_i64(t, t, 32);
  5309 + TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64);
  5310 + tcg_gen_extu_i32_i64(tmp, cpu_gpr[reg]);
  5311 + tcg_gen_or_i64(t, t, tmp);
  5312 + tcg_temp_free(tmp);
5287 5313 #endif
  5314 +}
5288 5315  
5289   -#define gen_op_store_T0_gpr64 gen_op_store_T0_gpr
5290   -#define gen_op_store_T1_gpr64 gen_op_store_T1_gpr
5291   -#if 0 // unused
5292   -#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
  5316 +static always_inline void gen_store_gpr64(int reg, TCGv t) {
  5317 +#if defined(TARGET_PPC64)
  5318 + tcg_gen_mov_i64(cpu_gpr[reg], t);
  5319 +#else
  5320 + tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
  5321 + TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64);
  5322 + tcg_gen_shri_i64(tmp, t, 32);
  5323 + tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
  5324 + tcg_temp_free(tmp);
5293 5325 #endif
5294   -
5295   -#endif /* !defined(TARGET_PPC64) */
  5326 +}
5296 5327  
5297 5328 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5298 5329 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
... ... @@ -5317,7 +5348,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5317 5348 if (rA(ctx->opcode) == 0) {
5318 5349 tcg_gen_movi_tl(cpu_T[0], simm << sh);
5319 5350 } else {
5320   - gen_op_load_gpr_T0(rA(ctx->opcode));
  5351 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5321 5352 if (likely(simm != 0))
5322 5353 gen_op_addi(simm << sh);
5323 5354 }
... ... @@ -5342,7 +5373,7 @@ static always_inline void gen_evl##name (DisasContext *ctx) \
5342 5373 } \
5343 5374 gen_addr_spe_imm_index(ctx, sh); \
5344 5375 op_spe_ldst(spe_l##name); \
5345   - gen_op_store_T1_gpr64(rD(ctx->opcode)); \
  5376 + gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
5346 5377 }
5347 5378  
5348 5379 #define GEN_SPE_LDX(name) \
... ... @@ -5354,7 +5385,7 @@ static always_inline void gen_evl##name##x (DisasContext *ctx) \
5354 5385 } \
5355 5386 gen_addr_reg_index(ctx); \
5356 5387 op_spe_ldst(spe_l##name); \
5357   - gen_op_store_T1_gpr64(rD(ctx->opcode)); \
  5388 + gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
5358 5389 }
5359 5390  
5360 5391 #define GEN_SPEOP_LD(name, sh) \
... ... @@ -5370,7 +5401,7 @@ static always_inline void gen_evst##name (DisasContext *ctx) \
5370 5401 return; \
5371 5402 } \
5372 5403 gen_addr_spe_imm_index(ctx, sh); \
5373   - gen_op_load_gpr64_T1(rS(ctx->opcode)); \
  5404 + gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
5374 5405 op_spe_ldst(spe_st##name); \
5375 5406 }
5376 5407  
... ... @@ -5382,7 +5413,7 @@ static always_inline void gen_evst##name##x (DisasContext *ctx) \
5382 5413 return; \
5383 5414 } \
5384 5415 gen_addr_reg_index(ctx); \
5385   - gen_op_load_gpr64_T1(rS(ctx->opcode)); \
  5416 + gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
5386 5417 op_spe_ldst(spe_st##name); \
5387 5418 }
5388 5419  
... ... @@ -5403,10 +5434,10 @@ static always_inline void gen_##name (DisasContext *ctx) \
5403 5434 GEN_EXCP_NO_AP(ctx); \
5404 5435 return; \
5405 5436 } \
5406   - gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5407   - gen_op_load_gpr64_T1(rB(ctx->opcode)); \
  5437 + gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
  5438 + gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
5408 5439 gen_op_##name(); \
5409   - gen_op_store_T0_gpr64(rD(ctx->opcode)); \
  5440 + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
5410 5441 }
5411 5442  
5412 5443 #define GEN_SPEOP_ARITH1(name) \
... ... @@ -5416,9 +5447,9 @@ static always_inline void gen_##name (DisasContext *ctx) \
5416 5447 GEN_EXCP_NO_AP(ctx); \
5417 5448 return; \
5418 5449 } \
5419   - gen_op_load_gpr64_T0(rA(ctx->opcode)); \
  5450 + gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5420 5451 gen_op_##name(); \
5421   - gen_op_store_T0_gpr64(rD(ctx->opcode)); \
  5452 + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
5422 5453 }
5423 5454  
5424 5455 #define GEN_SPEOP_COMP(name) \
... ... @@ -5428,8 +5459,8 @@ static always_inline void gen_##name (DisasContext *ctx) \
5428 5459 GEN_EXCP_NO_AP(ctx); \
5429 5460 return; \
5430 5461 } \
5431   - gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5432   - gen_op_load_gpr64_T1(rB(ctx->opcode)); \
  5462 + gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
  5463 + gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
5433 5464 gen_op_##name(); \
5434 5465 gen_op_store_T0_crf(crfD(ctx->opcode)); \
5435 5466 }
... ... @@ -5465,10 +5496,10 @@ GEN_SPEOP_ARITH1(evcntlsw);
5465 5496 static always_inline void gen_brinc (DisasContext *ctx)
5466 5497 {
5467 5498 /* Note: brinc is usable even if SPE is disabled */
5468   - gen_op_load_gpr_T0(rA(ctx->opcode));
5469   - gen_op_load_gpr_T1(rB(ctx->opcode));
  5499 + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
  5500 + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
5470 5501 gen_op_brinc();
5471   - gen_op_store_T0_gpr(rD(ctx->opcode));
  5502 + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5472 5503 }
5473 5504  
5474 5505 #define GEN_SPEOP_ARITH_IMM2(name) \
... ... @@ -5478,10 +5509,10 @@ static always_inline void gen_##name##i (DisasContext *ctx) \
5478 5509 GEN_EXCP_NO_AP(ctx); \
5479 5510 return; \
5480 5511 } \
5481   - gen_op_load_gpr64_T0(rB(ctx->opcode)); \
  5512 + gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
5482 5513 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5483 5514 gen_op_##name(); \
5484   - gen_op_store_T0_gpr64(rD(ctx->opcode)); \
  5515 + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
5485 5516 }
5486 5517  
5487 5518 #define GEN_SPEOP_LOGIC_IMM2(name) \
... ... @@ -5491,10 +5522,10 @@ static always_inline void gen_##name##i (DisasContext *ctx) \
5491 5522 GEN_EXCP_NO_AP(ctx); \
5492 5523 return; \
5493 5524 } \
5494   - gen_op_load_gpr64_T0(rA(ctx->opcode)); \
  5525 + gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5495 5526 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5496 5527 gen_op_##name(); \
5497   - gen_op_store_T0_gpr64(rD(ctx->opcode)); \
  5528 + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
5498 5529 }
5499 5530  
5500 5531 GEN_SPEOP_ARITH_IMM2(evaddw);
... ... @@ -5513,7 +5544,7 @@ static always_inline void gen_evsplati (DisasContext *ctx)
5513 5544 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5514 5545  
5515 5546 gen_op_splatwi_T0_64(imm);
5516   - gen_op_store_T0_gpr64(rD(ctx->opcode));
  5547 + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
5517 5548 }
5518 5549  
5519 5550 static always_inline void gen_evsplatfi (DisasContext *ctx)
... ... @@ -5521,7 +5552,7 @@ static always_inline void gen_evsplatfi (DisasContext *ctx)
5521 5552 uint32_t imm = rA(ctx->opcode) << 27;
5522 5553  
5523 5554 gen_op_splatwi_T0_64(imm);
5524   - gen_op_store_T0_gpr64(rD(ctx->opcode));
  5555 + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
5525 5556 }
5526 5557  
5527 5558 /* Comparison */
... ... @@ -5564,10 +5595,10 @@ static always_inline void gen_evsel (DisasContext *ctx)
5564 5595 return;
5565 5596 }
5566 5597 gen_op_load_crf_T0(ctx->opcode & 0x7);
5567   - gen_op_load_gpr64_T0(rA(ctx->opcode));
5568   - gen_op_load_gpr64_T1(rB(ctx->opcode));
  5598 + gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
  5599 + gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
5569 5600 gen_op_evsel();
5570   - gen_op_store_T0_gpr64(rD(ctx->opcode));
  5601 + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
5571 5602 }
5572 5603  
5573 5604 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
... ... @@ -5906,9 +5937,9 @@ GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
5906 5937 #define GEN_SPEFPUOP_CONV(name) \
5907 5938 static always_inline void gen_##name (DisasContext *ctx) \
5908 5939 { \
5909   - gen_op_load_gpr64_T0(rB(ctx->opcode)); \
  5940 + gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
5910 5941 gen_op_##name(); \
5911   - gen_op_store_T0_gpr64(rD(ctx->opcode)); \
  5942 + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
5912 5943 }
5913 5944  
5914 5945 /* Single precision floating-point vectors operations */
... ...