gwj / at91sam9263 · Commits

Commit f7350b47dab4b2c84b67fa8cc003494b3ef7a032

Authored by blueswir1
1 parent b115bb3f

Implement some Ultrasparc cache ASIs used by SILO 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4858 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 20 additions and 0 deletions
target-sparc/op_helper.c
  View file @f7350b4
... ... @@ -1687,6 +1687,16 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1687 1687 }
1688 1688 break;
1689 1689 }
  1690 + case 0x46: // D-cache data
  1691 + case 0x47: // D-cache tag access
  1692 + case 0x4e: // E-cache tag data
  1693 + case 0x66: // I-cache instruction access
  1694 + case 0x67: // I-cache tag access
  1695 + case 0x6e: // I-cache predecode
  1696 + case 0x6f: // I-cache LRU etc.
  1697 + case 0x76: // E-cache tag
  1698 + case 0x7e: // E-cache tag
  1699 + break;
1690 1700 case 0x59: // D-MMU 8k TSB pointer
1691 1701 case 0x5a: // D-MMU 64k TSB pointer
1692 1702 case 0x5b: // D-MMU data pointer
... ... @@ -2040,6 +2050,16 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
2040 2050 case 0x49: // Interrupt data receive
2041 2051 // XXX
2042 2052 return;
  2053 + case 0x46: // D-cache data
  2054 + case 0x47: // D-cache tag access
  2055 + case 0x4e: // E-cache tag data
  2056 + case 0x66: // I-cache instruction access
  2057 + case 0x67: // I-cache tag access
  2058 + case 0x6e: // I-cache predecode
  2059 + case 0x6f: // I-cache LRU etc.
  2060 + case 0x76: // E-cache tag
  2061 + case 0x7e: // E-cache tag
  2062 + return;
2043 2063 case 0x51: // I-MMU 8k TSB pointer, RO
2044 2064 case 0x52: // I-MMU 64k TSB pointer, RO
2045 2065 case 0x56: // I-MMU tag read, RO
... ...