Commit f6198371539d07cede52d654657b96eab54f9dce

Authored by aurel32
1 parent dd8edf01

target-sh4: check FD bit for FP instructions

Based on a patch from Vladimir Prus <vladimir@codesourcery.com>

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5970 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 23 additions and 6 deletions
target-sh4/translate.c
@@ -481,6 +481,7 @@ static void _decode_opc(DisasContext * ctx) @@ -481,6 +481,7 @@ static void _decode_opc(DisasContext * ctx)
481 #if 0 481 #if 0
482 fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); 482 fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
483 #endif 483 #endif
  484 +
484 switch (ctx->opcode) { 485 switch (ctx->opcode) {
485 case 0x0019: /* div0u */ 486 case 0x0019: /* div0u */
486 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); 487 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
@@ -998,6 +999,7 @@ static void _decode_opc(DisasContext * ctx) @@ -998,6 +999,7 @@ static void _decode_opc(DisasContext * ctx)
998 tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4)); 999 tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
999 return; 1000 return;
1000 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ 1001 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
  1002 + CHECK_FPU_ENABLED
1001 if (ctx->fpscr & FPSCR_SZ) { 1003 if (ctx->fpscr & FPSCR_SZ) {
1002 TCGv_i64 fp = tcg_temp_new_i64(); 1004 TCGv_i64 fp = tcg_temp_new_i64();
1003 gen_load_fpr64(fp, XREG(B7_4)); 1005 gen_load_fpr64(fp, XREG(B7_4));
@@ -1008,6 +1010,7 @@ static void _decode_opc(DisasContext * ctx) @@ -1008,6 +1010,7 @@ static void _decode_opc(DisasContext * ctx)
1008 } 1010 }
1009 return; 1011 return;
1010 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ 1012 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
  1013 + CHECK_FPU_ENABLED
1011 if (ctx->fpscr & FPSCR_SZ) { 1014 if (ctx->fpscr & FPSCR_SZ) {
1012 TCGv addr_hi = tcg_temp_new(); 1015 TCGv addr_hi = tcg_temp_new();
1013 int fr = XREG(B7_4); 1016 int fr = XREG(B7_4);
@@ -1020,6 +1023,7 @@ static void _decode_opc(DisasContext * ctx) @@ -1020,6 +1023,7 @@ static void _decode_opc(DisasContext * ctx)
1020 } 1023 }
1021 return; 1024 return;
1022 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ 1025 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
  1026 + CHECK_FPU_ENABLED
1023 if (ctx->fpscr & FPSCR_SZ) { 1027 if (ctx->fpscr & FPSCR_SZ) {
1024 TCGv addr_hi = tcg_temp_new(); 1028 TCGv addr_hi = tcg_temp_new();
1025 int fr = XREG(B11_8); 1029 int fr = XREG(B11_8);
@@ -1032,6 +1036,7 @@ static void _decode_opc(DisasContext * ctx) @@ -1032,6 +1036,7 @@ static void _decode_opc(DisasContext * ctx)
1032 } 1036 }
1033 return; 1037 return;
1034 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ 1038 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
  1039 + CHECK_FPU_ENABLED
1035 if (ctx->fpscr & FPSCR_SZ) { 1040 if (ctx->fpscr & FPSCR_SZ) {
1036 TCGv addr_hi = tcg_temp_new(); 1041 TCGv addr_hi = tcg_temp_new();
1037 int fr = XREG(B11_8); 1042 int fr = XREG(B11_8);
@@ -1046,6 +1051,7 @@ static void _decode_opc(DisasContext * ctx) @@ -1046,6 +1051,7 @@ static void _decode_opc(DisasContext * ctx)
1046 } 1051 }
1047 return; 1052 return;
1048 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ 1053 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
  1054 + CHECK_FPU_ENABLED
1049 if (ctx->fpscr & FPSCR_SZ) { 1055 if (ctx->fpscr & FPSCR_SZ) {
1050 TCGv addr = tcg_temp_new_i32(); 1056 TCGv addr = tcg_temp_new_i32();
1051 int fr = XREG(B7_4); 1057 int fr = XREG(B7_4);
@@ -1065,6 +1071,7 @@ static void _decode_opc(DisasContext * ctx) @@ -1065,6 +1071,7 @@ static void _decode_opc(DisasContext * ctx)
1065 } 1071 }
1066 return; 1072 return;
1067 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ 1073 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
  1074 + CHECK_FPU_ENABLED
1068 { 1075 {
1069 TCGv addr = tcg_temp_new_i32(); 1076 TCGv addr = tcg_temp_new_i32();
1070 tcg_gen_add_i32(addr, REG(B7_4), REG(0)); 1077 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
@@ -1080,6 +1087,7 @@ static void _decode_opc(DisasContext * ctx) @@ -1080,6 +1087,7 @@ static void _decode_opc(DisasContext * ctx)
1080 } 1087 }
1081 return; 1088 return;
1082 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ 1089 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
  1090 + CHECK_FPU_ENABLED
1083 { 1091 {
1084 TCGv addr = tcg_temp_new(); 1092 TCGv addr = tcg_temp_new();
1085 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); 1093 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
@@ -1101,6 +1109,7 @@ static void _decode_opc(DisasContext * ctx) @@ -1101,6 +1109,7 @@ static void _decode_opc(DisasContext * ctx)
1101 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ 1109 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1102 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ 1110 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1103 { 1111 {
  1112 + CHECK_FPU_ENABLED
1104 if (ctx->fpscr & FPSCR_PR) { 1113 if (ctx->fpscr & FPSCR_PR) {
1105 TCGv_i64 fp0, fp1; 1114 TCGv_i64 fp0, fp1;
1106 1115
@@ -1623,16 +1632,15 @@ static void _decode_opc(DisasContext * ctx) @@ -1623,16 +1632,15 @@ static void _decode_opc(DisasContext * ctx)
1623 } 1632 }
1624 return; 1633 return;
1625 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ 1634 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1626 - {  
1627 - tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);  
1628 - } 1635 + CHECK_FPU_ENABLED
  1636 + tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);
1629 return; 1637 return;
1630 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ 1638 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1631 - {  
1632 - tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);  
1633 - } 1639 + CHECK_FPU_ENABLED
  1640 + tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1634 return; 1641 return;
1635 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ 1642 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
  1643 + CHECK_FPU_ENABLED
1636 if (ctx->fpscr & FPSCR_PR) { 1644 if (ctx->fpscr & FPSCR_PR) {
1637 TCGv_i64 fp; 1645 TCGv_i64 fp;
1638 if (ctx->opcode & 0x0100) 1646 if (ctx->opcode & 0x0100)
@@ -1647,6 +1655,7 @@ static void _decode_opc(DisasContext * ctx) @@ -1647,6 +1655,7 @@ static void _decode_opc(DisasContext * ctx)
1647 } 1655 }
1648 return; 1656 return;
1649 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ 1657 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
  1658 + CHECK_FPU_ENABLED
1650 if (ctx->fpscr & FPSCR_PR) { 1659 if (ctx->fpscr & FPSCR_PR) {
1651 TCGv_i64 fp; 1660 TCGv_i64 fp;
1652 if (ctx->opcode & 0x0100) 1661 if (ctx->opcode & 0x0100)
@@ -1661,11 +1670,13 @@ static void _decode_opc(DisasContext * ctx) @@ -1661,11 +1670,13 @@ static void _decode_opc(DisasContext * ctx)
1661 } 1670 }
1662 return; 1671 return;
1663 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ 1672 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
  1673 + CHECK_FPU_ENABLED
1664 { 1674 {
1665 gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); 1675 gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1666 } 1676 }
1667 return; 1677 return;
1668 case 0xf05d: /* fabs FRn/DRn */ 1678 case 0xf05d: /* fabs FRn/DRn */
  1679 + CHECK_FPU_ENABLED
1669 if (ctx->fpscr & FPSCR_PR) { 1680 if (ctx->fpscr & FPSCR_PR) {
1670 if (ctx->opcode & 0x0100) 1681 if (ctx->opcode & 0x0100)
1671 break; /* illegal instruction */ 1682 break; /* illegal instruction */
@@ -1679,6 +1690,7 @@ static void _decode_opc(DisasContext * ctx) @@ -1679,6 +1690,7 @@ static void _decode_opc(DisasContext * ctx)
1679 } 1690 }
1680 return; 1691 return;
1681 case 0xf06d: /* fsqrt FRn */ 1692 case 0xf06d: /* fsqrt FRn */
  1693 + CHECK_FPU_ENABLED
1682 if (ctx->fpscr & FPSCR_PR) { 1694 if (ctx->fpscr & FPSCR_PR) {
1683 if (ctx->opcode & 0x0100) 1695 if (ctx->opcode & 0x0100)
1684 break; /* illegal instruction */ 1696 break; /* illegal instruction */
@@ -1692,18 +1704,22 @@ static void _decode_opc(DisasContext * ctx) @@ -1692,18 +1704,22 @@ static void _decode_opc(DisasContext * ctx)
1692 } 1704 }
1693 return; 1705 return;
1694 case 0xf07d: /* fsrra FRn */ 1706 case 0xf07d: /* fsrra FRn */
  1707 + CHECK_FPU_ENABLED
1695 break; 1708 break;
1696 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ 1709 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
  1710 + CHECK_FPU_ENABLED
1697 if (!(ctx->fpscr & FPSCR_PR)) { 1711 if (!(ctx->fpscr & FPSCR_PR)) {
1698 tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0); 1712 tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
1699 } 1713 }
1700 return; 1714 return;
1701 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ 1715 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
  1716 + CHECK_FPU_ENABLED
1702 if (!(ctx->fpscr & FPSCR_PR)) { 1717 if (!(ctx->fpscr & FPSCR_PR)) {
1703 tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000); 1718 tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
1704 } 1719 }
1705 return; 1720 return;
1706 case 0xf0ad: /* fcnvsd FPUL,DRn */ 1721 case 0xf0ad: /* fcnvsd FPUL,DRn */
  1722 + CHECK_FPU_ENABLED
1707 { 1723 {
1708 TCGv_i64 fp = tcg_temp_new_i64(); 1724 TCGv_i64 fp = tcg_temp_new_i64();
1709 gen_helper_fcnvsd_FT_DT(fp, cpu_fpul); 1725 gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
@@ -1712,6 +1728,7 @@ static void _decode_opc(DisasContext * ctx) @@ -1712,6 +1728,7 @@ static void _decode_opc(DisasContext * ctx)
1712 } 1728 }
1713 return; 1729 return;
1714 case 0xf0bd: /* fcnvds DRn,FPUL */ 1730 case 0xf0bd: /* fcnvds DRn,FPUL */
  1731 + CHECK_FPU_ENABLED
1715 { 1732 {
1716 TCGv_i64 fp = tcg_temp_new_i64(); 1733 TCGv_i64 fp = tcg_temp_new_i64();
1717 gen_load_fpr64(fp, DREG(B11_8)); 1734 gen_load_fpr64(fp, DREG(B11_8));