gwj / at91sam9263 · Commits

Commit f5cbc474e8d810c8fc176311a70252ceb2368f94

Authored by aurel32
1 parent 6b4079f8

ESCC: swap the two CharDriverState arguments 

Swap the two CharDriverState arguments so that the first argument
corresponds to the channel A and the second argument to the channel B.

Modify hw/sun4m.c accordingly.

This fixes the order of the serial ports on the PPC machines.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6284 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 8 additions and 8 deletions
hw/escc.c
  View file @f5cbc47
@@ -719,8 +719,8 @@ static int escc_load(QEMUFile *f, void *opaque, int version_id) @@ -719,8 +719,8 @@ static int escc_load(QEMUFile *f, void *opaque, int version_id)
719 719
720 } 720 }
721 721
722 -int escc_init(target_phys_addr_t base, qemu_irq irq, CharDriverState *chr1,  
723 - CharDriverState *chr2, int clock, int it_shift) 722 +int escc_init(target_phys_addr_t base, qemu_irq irq, CharDriverState *chrA,
  723 + CharDriverState *chrB, int clock, int it_shift)
724 { 724 {
725 int escc_io_memory, i; 725 int escc_io_memory, i;
726 SerialState *s; 726 SerialState *s;
@@ -737,8 +737,8 @@ int escc_init(target_phys_addr_t base, qemu_irq irq, CharDriverState *chr1, @@ -737,8 +737,8 @@ int escc_init(target_phys_addr_t base, qemu_irq irq, CharDriverState *chr1,
737 escc_io_memory); 737 escc_io_memory);
738 738
739 s->it_shift = it_shift; 739 s->it_shift = it_shift;
740 - s->chn[0].chr = chr1;  
741 - s->chn[1].chr = chr2; 740 + s->chn[0].chr = chrB;
  741 + s->chn[1].chr = chrA;
742 s->chn[0].disabled = 0; 742 s->chn[0].disabled = 0;
743 s->chn[1].disabled = 0; 743 s->chn[1].disabled = 0;
744 744
hw/escc.h
  View file @f5cbc47
1 /* escc.c */ 1 /* escc.c */
2 #define ESCC_SIZE 4 2 #define ESCC_SIZE 4
3 -int escc_init(target_phys_addr_t base, qemu_irq irq, CharDriverState *chr1,  
4 - CharDriverState *chr2, int clock, int it_shift); 3 +int escc_init(target_phys_addr_t base, qemu_irq irq, CharDriverState *chrA,
  4 + CharDriverState *chrB, int clock, int it_shift);
5 5
6 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq, 6 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
7 int disabled, int clock, int it_shift); 7 int disabled, int clock, int it_shift);
hw/sun4m.c
  View file @f5cbc47
@@ -1564,8 +1564,8 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, @@ -1564,8 +1564,8 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1564 nographic, ESCC_CLOCK, 1); 1564 nographic, ESCC_CLOCK, 1);
1565 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device 1565 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1566 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device 1566 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1567 - escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], serial_hds[1],  
1568 - serial_hds[0], ESCC_CLOCK, 1); 1567 + escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], serial_hds[0],
  1568 + serial_hds[1], ESCC_CLOCK, 1);
1569 1569
1570 slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0, 1570 slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0,
1571 slavio_irq[hwdef->me_irq], NULL, &fdc_tc); 1571 slavio_irq[hwdef->me_irq], NULL, &fdc_tc);