gwj / at91sam9263 · Commits

Commit f31e93706412e188a4164d1aaf65ad54b85fc951

Authored by aurel32
1 parent d42f183c

tcg: don't define TCG rotation ops if they are not supported 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6796 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 4 additions and 0 deletions
tcg/tcg-opc.h
  View file @f31e937
@@ -71,8 +71,10 @@ DEF2(xor_i32, 1, 2, 0, 0) @@ -71,8 +71,10 @@ DEF2(xor_i32, 1, 2, 0, 0)
71 DEF2(shl_i32, 1, 2, 0, 0) 71 DEF2(shl_i32, 1, 2, 0, 0)
72 DEF2(shr_i32, 1, 2, 0, 0) 72 DEF2(shr_i32, 1, 2, 0, 0)
73 DEF2(sar_i32, 1, 2, 0, 0) 73 DEF2(sar_i32, 1, 2, 0, 0)
  74 +#ifdef TCG_TARGET_HAS_rot_i32
74 DEF2(rotl_i32, 1, 2, 0, 0) 75 DEF2(rotl_i32, 1, 2, 0, 0)
75 DEF2(rotr_i32, 1, 2, 0, 0) 76 DEF2(rotr_i32, 1, 2, 0, 0)
  77 +#endif
76 78
77 DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 79 DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
78 #if TCG_TARGET_REG_BITS == 32 80 #if TCG_TARGET_REG_BITS == 32
@@ -126,8 +128,10 @@ DEF2(xor_i64, 1, 2, 0, 0) @@ -126,8 +128,10 @@ DEF2(xor_i64, 1, 2, 0, 0)
126 DEF2(shl_i64, 1, 2, 0, 0) 128 DEF2(shl_i64, 1, 2, 0, 0)
127 DEF2(shr_i64, 1, 2, 0, 0) 129 DEF2(shr_i64, 1, 2, 0, 0)
128 DEF2(sar_i64, 1, 2, 0, 0) 130 DEF2(sar_i64, 1, 2, 0, 0)
  131 +#ifdef TCG_TARGET_HAS_rot_i64
129 DEF2(rotl_i64, 1, 2, 0, 0) 132 DEF2(rotl_i64, 1, 2, 0, 0)
130 DEF2(rotr_i64, 1, 2, 0, 0) 133 DEF2(rotr_i64, 1, 2, 0, 0)
  134 +#endif
131 135
132 DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 136 DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
133 #ifdef TCG_TARGET_HAS_ext8s_i64 137 #ifdef TCG_TARGET_HAS_ext8s_i64