gwj / at91sam9263 · Commits

Commit f0aabd1aa335cecc01eddf16369c4be625df4d13

Authored by aurel32
1 parent e2be8d8d

PPC: convert SPE effective address computation to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5491 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 9 additions and 10 deletions
target-ppc/translate.c
  View file @f0aabd1
... ... @@ -5316,17 +5316,16 @@ static always_inline void gen_speundef (DisasContext *ctx)
5316 5316 }
5317 5317  
5318 5318 /* SPE load and stores */
5319   -static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
  5319 +static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
5320 5320 {
5321 5321 target_long simm = rB(ctx->opcode);
5322 5322  
5323   - if (rA(ctx->opcode) == 0) {
5324   - tcg_gen_movi_tl(cpu_T[0], simm << sh);
5325   - } else {
5326   - tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5327   - if (likely(simm != 0))
5328   - tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh);
5329   - }
  5323 + if (rA(ctx->opcode) == 0)
  5324 + tcg_gen_movi_tl(EA, simm << sh);
  5325 + else if (likely(simm != 0))
  5326 + tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
  5327 + else
  5328 + tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
5330 5329 }
5331 5330  
5332 5331 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
... ... @@ -5346,7 +5345,7 @@ static always_inline void gen_evl##name (DisasContext *ctx) \
5346 5345 GEN_EXCP_NO_AP(ctx); \
5347 5346 return; \
5348 5347 } \
5349   - gen_addr_spe_imm_index(ctx, sh); \
  5348 + gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
5350 5349 op_spe_ldst(spe_l##name); \
5351 5350 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
5352 5351 }
... ... @@ -5375,7 +5374,7 @@ static always_inline void gen_evst##name (DisasContext *ctx) \
5375 5374 GEN_EXCP_NO_AP(ctx); \
5376 5375 return; \
5377 5376 } \
5378   - gen_addr_spe_imm_index(ctx, sh); \
  5377 + gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
5379 5378 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
5380 5379 op_spe_ldst(spe_st##name); \
5381 5380 }
... ...