Commit f09111e0886d16425fa59ec11cfb3293095cb06c
1 parent
7b62f20c
Fix XHACK() macro and use FREG if possible, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2815 c046a42c-6fe2-441c-8c8c-71466251a162
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4 additions
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4 deletions
target-sh4/translate.c
| @@ -236,7 +236,7 @@ static void gen_delayed_conditional_jump(DisasContext * ctx) | @@ -236,7 +236,7 @@ static void gen_delayed_conditional_jump(DisasContext * ctx) | ||
| 236 | ? (x) + 16 : (x)) | 236 | ? (x) + 16 : (x)) |
| 237 | 237 | ||
| 238 | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) | 238 | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
| 239 | -#define XHACK(x) (((x) & 1 ) << 4 | ((x) & 0xe ) << 1) | 239 | +#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
| 240 | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) | 240 | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
| 241 | 241 | ||
| 242 | #define CHECK_NOT_DELAY_SLOT \ | 242 | #define CHECK_NOT_DELAY_SLOT \ |
| @@ -685,7 +685,7 @@ void decode_opc(DisasContext * ctx) | @@ -685,7 +685,7 @@ void decode_opc(DisasContext * ctx) | ||
| 685 | } else { | 685 | } else { |
| 686 | gen_op_movl_rN_T0(REG(B7_4)); | 686 | gen_op_movl_rN_T0(REG(B7_4)); |
| 687 | gen_op_ldfl_T0_FT0(ctx); | 687 | gen_op_ldfl_T0_FT0(ctx); |
| 688 | - gen_op_fmov_FT0_frN(XREG(B11_8)); | 688 | + gen_op_fmov_FT0_frN(FREG(B11_8)); |
| 689 | } | 689 | } |
| 690 | return; | 690 | return; |
| 691 | case 0xf009: /* fmov @Rm+,{F,D,X}Rn */ | 691 | case 0xf009: /* fmov @Rm+,{F,D,X}Rn */ |
| @@ -704,7 +704,7 @@ void decode_opc(DisasContext * ctx) | @@ -704,7 +704,7 @@ void decode_opc(DisasContext * ctx) | ||
| 704 | } else { | 704 | } else { |
| 705 | gen_op_movl_rN_T0(REG(B7_4)); | 705 | gen_op_movl_rN_T0(REG(B7_4)); |
| 706 | gen_op_ldfl_T0_FT0(ctx); | 706 | gen_op_ldfl_T0_FT0(ctx); |
| 707 | - gen_op_fmov_FT0_frN(XREG(B11_8)); | 707 | + gen_op_fmov_FT0_frN(FREG(B11_8)); |
| 708 | gen_op_inc4_rN(REG(B7_4)); | 708 | gen_op_inc4_rN(REG(B7_4)); |
| 709 | } | 709 | } |
| 710 | return; | 710 | return; |
| @@ -745,7 +745,7 @@ void decode_opc(DisasContext * ctx) | @@ -745,7 +745,7 @@ void decode_opc(DisasContext * ctx) | ||
| 745 | gen_op_movl_rN_T0(REG(B7_4)); | 745 | gen_op_movl_rN_T0(REG(B7_4)); |
| 746 | gen_op_add_rN_T0(REG(0)); | 746 | gen_op_add_rN_T0(REG(0)); |
| 747 | gen_op_ldfl_T0_FT0(ctx); | 747 | gen_op_ldfl_T0_FT0(ctx); |
| 748 | - gen_op_fmov_FT0_frN(XREG(B11_8)); | 748 | + gen_op_fmov_FT0_frN(FREG(B11_8)); |
| 749 | } | 749 | } |
| 750 | return; | 750 | return; |
| 751 | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) */ | 751 | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) */ |