gwj / at91sam9263 · Commits

Commit f0685f6e7a4179e75c4696de88de9657c6a86e95

Authored by j_mayer
1 parent dac454af

For consistency, align the address to the cache line before using it, 

when invalidating the instruction cache.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3449 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 2 additions and 2 deletions
target-ppc/op_helper_mem.h
  View file @f0685f6
... ... @@ -252,8 +252,8 @@ void glue(do_icbi, MEMSUFFIX) (void)
252 252 * (not a fetch) by the MMU. To be sure it will be so,
253 253 * do the load "by hand".
254 254 */
255   - tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
256 255 T0 &= ~(env->icache_line_size - 1);
  256 + tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
257 257 tb_invalidate_page_range((uint32_t)T0,
258 258 (uint32_t)(T0 + env->icache_line_size));
259 259 }
... ... @@ -267,8 +267,8 @@ void glue(do_icbi_64, MEMSUFFIX) (void)
267 267 * (not a fetch) by the MMU. To be sure it will be so,
268 268 * do the load "by hand".
269 269 */
270   - tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
271 270 T0 &= ~(env->icache_line_size - 1);
  271 + tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
272 272 tb_invalidate_page_range((uint64_t)T0,
273 273 (uint64_t)(T0 + env->icache_line_size));
274 274 }
... ...