gwj / at91sam9263 · Commits

Commit f01be154589f6e137195d9cc28d1296d885e4eea

Authored by ths
1 parent a1cf28f4

Move the active FPU registers into env again, and use more TCG registers 

to access them.

Signed-off-by: Thiemo Seufer <ths@networkno.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5252 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 7 changed files with 338 additions and 322 deletions
gdbstub.c
  View file @f01be15
@@ -731,16 +731,16 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) @@ -731,16 +731,16 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
731 for (i = 0; i < 32; i++) 731 for (i = 0; i < 32; i++)
732 { 732 {
733 if (env->CP0_Status & (1 << CP0St_FR)) 733 if (env->CP0_Status & (1 << CP0St_FR))
734 - *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d); 734 + *(target_ulong *)ptr = tswapl(env->active_fpu.fpr[i].d);
735 else 735 else
736 - *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]); 736 + *(target_ulong *)ptr = tswap32(env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]);
737 ptr += sizeof(target_ulong); 737 ptr += sizeof(target_ulong);
738 } 738 }
739 739
740 - *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31); 740 + *(target_ulong *)ptr = (int32_t)tswap32(env->active_fpu.fcr31);
741 ptr += sizeof(target_ulong); 741 ptr += sizeof(target_ulong);
742 742
743 - *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0); 743 + *(target_ulong *)ptr = (int32_t)tswap32(env->active_fpu.fcr0);
744 ptr += sizeof(target_ulong); 744 ptr += sizeof(target_ulong);
745 } 745 }
746 746
@@ -771,7 +771,7 @@ static unsigned int ieee_rm[] = @@ -771,7 +771,7 @@ static unsigned int ieee_rm[] =
771 float_round_down 771 float_round_down
772 }; 772 };
773 #define RESTORE_ROUNDING_MODE \ 773 #define RESTORE_ROUNDING_MODE \
774 - set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status) 774 + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
775 775
776 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) 776 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
777 { 777 {
@@ -808,13 +808,13 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) @@ -808,13 +808,13 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
808 for (i = 0; i < 32; i++) 808 for (i = 0; i < 32; i++)
809 { 809 {
810 if (env->CP0_Status & (1 << CP0St_FR)) 810 if (env->CP0_Status & (1 << CP0St_FR))
811 - env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr); 811 + env->active_fpu.fpr[i].d = tswapl(*(target_ulong *)ptr);
812 else 812 else
813 - env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr); 813 + env->active_fpu.fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
814 ptr += sizeof(target_ulong); 814 ptr += sizeof(target_ulong);
815 } 815 }
816 816
817 - env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF; 817 + env->active_fpu.fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
818 ptr += sizeof(target_ulong); 818 ptr += sizeof(target_ulong);
819 819
820 /* The remaining registers are assumed to be read-only. */ 820 /* The remaining registers are assumed to be read-only. */
target-mips/TODO
  View file @f01be15
@@ -30,11 +30,6 @@ General @@ -30,11 +30,6 @@ General
30 each ASID change. Using the MMU modes to implement ASIDs hinges on 30 each ASID change. Using the MMU modes to implement ASIDs hinges on
31 implementing the global bit efficiently. 31 implementing the global bit efficiently.
32 - save/restore of the CPU state is not implemented (see machine.c). 32 - save/restore of the CPU state is not implemented (see machine.c).
33 -- Improve cpu state handling:  
34 - Step 1) Collect all the TC state in a single struct, so we need only  
35 - a single global pointer for the active TC.  
36 - Step 2) Use only a single TC context as working context, and copy the  
37 - contexts on TC switch. Likewise for FPU contexts.  
38 33
39 MIPS64 34 MIPS64
40 ------ 35 ------
target-mips/cpu.h
  View file @f01be15
@@ -84,9 +84,9 @@ struct CPUMIPSFPUContext { @@ -84,9 +84,9 @@ struct CPUMIPSFPUContext {
84 #define FCR0_REV 0 84 #define FCR0_REV 0
85 /* fcsr */ 85 /* fcsr */
86 uint32_t fcr31; 86 uint32_t fcr31;
87 -#define SET_FP_COND(num,env) do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)  
88 -#define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)  
89 -#define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1)) 87 +#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  88 +#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  89 +#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
90 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 90 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
91 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 91 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
92 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 92 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
@@ -132,6 +132,7 @@ typedef struct mips_def_t mips_def_t; @@ -132,6 +132,7 @@ typedef struct mips_def_t mips_def_t;
132 132
133 #define MIPS_SHADOW_SET_MAX 16 133 #define MIPS_SHADOW_SET_MAX 16
134 #define MIPS_TC_MAX 5 134 #define MIPS_TC_MAX 5
  135 +#define MIPS_FPU_MAX 1
135 #define MIPS_DSP_ACC 4 136 #define MIPS_DSP_ACC 4
136 137
137 typedef struct TCState TCState; 138 typedef struct TCState TCState;
@@ -170,11 +171,12 @@ struct TCState { @@ -170,11 +171,12 @@ struct TCState {
170 typedef struct CPUMIPSState CPUMIPSState; 171 typedef struct CPUMIPSState CPUMIPSState;
171 struct CPUMIPSState { 172 struct CPUMIPSState {
172 TCState active_tc; 173 TCState active_tc;
  174 + CPUMIPSFPUContext active_fpu;
173 175
174 CPUMIPSMVPContext *mvp; 176 CPUMIPSMVPContext *mvp;
175 CPUMIPSTLBContext *tlb; 177 CPUMIPSTLBContext *tlb;
176 - CPUMIPSFPUContext *fpu;  
177 uint32_t current_tc; 178 uint32_t current_tc;
  179 + uint32_t current_fpu;
178 180
179 uint32_t SEGBITS; 181 uint32_t SEGBITS;
180 uint32_t PABITS; 182 uint32_t PABITS;
@@ -404,6 +406,7 @@ struct CPUMIPSState { @@ -404,6 +406,7 @@ struct CPUMIPSState {
404 int32_t CP0_DESAVE; 406 int32_t CP0_DESAVE;
405 /* We waste some space so we can handle shadow registers like TCs. */ 407 /* We waste some space so we can handle shadow registers like TCs. */
406 TCState tcs[MIPS_SHADOW_SET_MAX]; 408 TCState tcs[MIPS_SHADOW_SET_MAX];
  409 + CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
407 /* Qemu */ 410 /* Qemu */
408 int error_code; 411 int error_code;
409 uint32_t hflags; /* CPU State */ 412 uint32_t hflags; /* CPU State */
target-mips/exec.h
  View file @f01be15
@@ -86,7 +86,7 @@ static inline void compute_hflags(CPUState *env) @@ -86,7 +86,7 @@ static inline void compute_hflags(CPUState *env)
86 if (env->CP0_Status & (1 << CP0St_FR)) 86 if (env->CP0_Status & (1 << CP0St_FR))
87 env->hflags |= MIPS_HFLAG_F64; 87 env->hflags |= MIPS_HFLAG_F64;
88 if (env->insn_flags & ISA_MIPS32R2) { 88 if (env->insn_flags & ISA_MIPS32R2) {
89 - if (env->fpu->fcr0 & (1 << FCR0_F64)) 89 + if (env->active_fpu.fcr0 & (1 << FCR0_F64))
90 env->hflags |= MIPS_HFLAG_COP1X; 90 env->hflags |= MIPS_HFLAG_COP1X;
91 } else if (env->insn_flags & ISA_MIPS32) { 91 } else if (env->insn_flags & ISA_MIPS32) {
92 if (env->hflags & MIPS_HFLAG_64) 92 if (env->hflags & MIPS_HFLAG_64)
target-mips/op_helper.c
  View file @f01be15
@@ -1940,7 +1940,7 @@ unsigned int ieee_rm[] = { @@ -1940,7 +1940,7 @@ unsigned int ieee_rm[] = {
1940 }; 1940 };
1941 1941
1942 #define RESTORE_ROUNDING_MODE \ 1942 #define RESTORE_ROUNDING_MODE \
1943 - set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status) 1943 + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1944 1944
1945 target_ulong do_cfc1 (uint32_t reg) 1945 target_ulong do_cfc1 (uint32_t reg)
1946 { 1946 {
@@ -1948,19 +1948,19 @@ target_ulong do_cfc1 (uint32_t reg) @@ -1948,19 +1948,19 @@ target_ulong do_cfc1 (uint32_t reg)
1948 1948
1949 switch (reg) { 1949 switch (reg) {
1950 case 0: 1950 case 0:
1951 - t0 = (int32_t)env->fpu->fcr0; 1951 + t0 = (int32_t)env->active_fpu.fcr0;
1952 break; 1952 break;
1953 case 25: 1953 case 25:
1954 - t0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1); 1954 + t0 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
1955 break; 1955 break;
1956 case 26: 1956 case 26:
1957 - t0 = env->fpu->fcr31 & 0x0003f07c; 1957 + t0 = env->active_fpu.fcr31 & 0x0003f07c;
1958 break; 1958 break;
1959 case 28: 1959 case 28:
1960 - t0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4); 1960 + t0 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
1961 break; 1961 break;
1962 default: 1962 default:
1963 - t0 = (int32_t)env->fpu->fcr31; 1963 + t0 = (int32_t)env->active_fpu.fcr31;
1964 break; 1964 break;
1965 } 1965 }
1966 1966
@@ -1973,32 +1973,32 @@ void do_ctc1 (target_ulong t0, uint32_t reg) @@ -1973,32 +1973,32 @@ void do_ctc1 (target_ulong t0, uint32_t reg)
1973 case 25: 1973 case 25:
1974 if (t0 & 0xffffff00) 1974 if (t0 & 0xffffff00)
1975 return; 1975 return;
1976 - env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) | 1976 + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
1977 ((t0 & 0x1) << 23); 1977 ((t0 & 0x1) << 23);
1978 break; 1978 break;
1979 case 26: 1979 case 26:
1980 if (t0 & 0x007c0000) 1980 if (t0 & 0x007c0000)
1981 return; 1981 return;
1982 - env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c); 1982 + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
1983 break; 1983 break;
1984 case 28: 1984 case 28:
1985 if (t0 & 0x007c0000) 1985 if (t0 & 0x007c0000)
1986 return; 1986 return;
1987 - env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (t0 & 0x00000f83) | 1987 + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
1988 ((t0 & 0x4) << 22); 1988 ((t0 & 0x4) << 22);
1989 break; 1989 break;
1990 case 31: 1990 case 31:
1991 if (t0 & 0x007c0000) 1991 if (t0 & 0x007c0000)
1992 return; 1992 return;
1993 - env->fpu->fcr31 = t0; 1993 + env->active_fpu.fcr31 = t0;
1994 break; 1994 break;
1995 default: 1995 default:
1996 return; 1996 return;
1997 } 1997 }
1998 /* set rounding mode */ 1998 /* set rounding mode */
1999 RESTORE_ROUNDING_MODE; 1999 RESTORE_ROUNDING_MODE;
2000 - set_float_exception_flags(0, &env->fpu->fp_status);  
2001 - if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31)) 2000 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2001 + if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2002 do_raise_exception(EXCP_FPE); 2002 do_raise_exception(EXCP_FPE);
2003 } 2003 }
2004 2004
@@ -2022,13 +2022,13 @@ static inline char mips_ex_to_ieee(char xcpt) @@ -2022,13 +2022,13 @@ static inline char mips_ex_to_ieee(char xcpt)
2022 2022
2023 static inline void update_fcr31(void) 2023 static inline void update_fcr31(void)
2024 { 2024 {
2025 - int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status)); 2025 + int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2026 2026
2027 - SET_FP_CAUSE(env->fpu->fcr31, tmp);  
2028 - if (GET_FP_ENABLE(env->fpu->fcr31) & tmp) 2027 + SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
  2028 + if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
2029 do_raise_exception(EXCP_FPE); 2029 do_raise_exception(EXCP_FPE);
2030 else 2030 else
2031 - UPDATE_FP_FLAGS(env->fpu->fcr31, tmp); 2031 + UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2032 } 2032 }
2033 2033
2034 /* Float support. 2034 /* Float support.
@@ -2039,20 +2039,20 @@ static inline void update_fcr31(void) @@ -2039,20 +2039,20 @@ static inline void update_fcr31(void)
2039 /* unary operations, modifying fp status */ 2039 /* unary operations, modifying fp status */
2040 uint64_t do_float_sqrt_d(uint64_t fdt0) 2040 uint64_t do_float_sqrt_d(uint64_t fdt0)
2041 { 2041 {
2042 - return float64_sqrt(fdt0, &env->fpu->fp_status); 2042 + return float64_sqrt(fdt0, &env->active_fpu.fp_status);
2043 } 2043 }
2044 2044
2045 uint32_t do_float_sqrt_s(uint32_t fst0) 2045 uint32_t do_float_sqrt_s(uint32_t fst0)
2046 { 2046 {
2047 - return float32_sqrt(fst0, &env->fpu->fp_status); 2047 + return float32_sqrt(fst0, &env->active_fpu.fp_status);
2048 } 2048 }
2049 2049
2050 uint64_t do_float_cvtd_s(uint32_t fst0) 2050 uint64_t do_float_cvtd_s(uint32_t fst0)
2051 { 2051 {
2052 uint64_t fdt2; 2052 uint64_t fdt2;
2053 2053
2054 - set_float_exception_flags(0, &env->fpu->fp_status);  
2055 - fdt2 = float32_to_float64(fst0, &env->fpu->fp_status); 2054 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2055 + fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2056 update_fcr31(); 2056 update_fcr31();
2057 return fdt2; 2057 return fdt2;
2058 } 2058 }
@@ -2061,8 +2061,8 @@ uint64_t do_float_cvtd_w(uint32_t wt0) @@ -2061,8 +2061,8 @@ uint64_t do_float_cvtd_w(uint32_t wt0)
2061 { 2061 {
2062 uint64_t fdt2; 2062 uint64_t fdt2;
2063 2063
2064 - set_float_exception_flags(0, &env->fpu->fp_status);  
2065 - fdt2 = int32_to_float64(wt0, &env->fpu->fp_status); 2064 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2065 + fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2066 update_fcr31(); 2066 update_fcr31();
2067 return fdt2; 2067 return fdt2;
2068 } 2068 }
@@ -2071,8 +2071,8 @@ uint64_t do_float_cvtd_l(uint64_t dt0) @@ -2071,8 +2071,8 @@ uint64_t do_float_cvtd_l(uint64_t dt0)
2071 { 2071 {
2072 uint64_t fdt2; 2072 uint64_t fdt2;
2073 2073
2074 - set_float_exception_flags(0, &env->fpu->fp_status);  
2075 - fdt2 = int64_to_float64(dt0, &env->fpu->fp_status); 2074 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2075 + fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2076 update_fcr31(); 2076 update_fcr31();
2077 return fdt2; 2077 return fdt2;
2078 } 2078 }
@@ -2081,10 +2081,10 @@ uint64_t do_float_cvtl_d(uint64_t fdt0) @@ -2081,10 +2081,10 @@ uint64_t do_float_cvtl_d(uint64_t fdt0)
2081 { 2081 {
2082 uint64_t dt2; 2082 uint64_t dt2;
2083 2083
2084 - set_float_exception_flags(0, &env->fpu->fp_status);  
2085 - dt2 = float64_to_int64(fdt0, &env->fpu->fp_status); 2084 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2085 + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2086 update_fcr31(); 2086 update_fcr31();
2087 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2087 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2088 dt2 = FLOAT_SNAN64; 2088 dt2 = FLOAT_SNAN64;
2089 return dt2; 2089 return dt2;
2090 } 2090 }
@@ -2093,10 +2093,10 @@ uint64_t do_float_cvtl_s(uint32_t fst0) @@ -2093,10 +2093,10 @@ uint64_t do_float_cvtl_s(uint32_t fst0)
2093 { 2093 {
2094 uint64_t dt2; 2094 uint64_t dt2;
2095 2095
2096 - set_float_exception_flags(0, &env->fpu->fp_status);  
2097 - dt2 = float32_to_int64(fst0, &env->fpu->fp_status); 2096 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2097 + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2098 update_fcr31(); 2098 update_fcr31();
2099 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2099 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2100 dt2 = FLOAT_SNAN64; 2100 dt2 = FLOAT_SNAN64;
2101 return dt2; 2101 return dt2;
2102 } 2102 }
@@ -2106,9 +2106,9 @@ uint64_t do_float_cvtps_pw(uint64_t dt0) @@ -2106,9 +2106,9 @@ uint64_t do_float_cvtps_pw(uint64_t dt0)
2106 uint32_t fst2; 2106 uint32_t fst2;
2107 uint32_t fsth2; 2107 uint32_t fsth2;
2108 2108
2109 - set_float_exception_flags(0, &env->fpu->fp_status);  
2110 - fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->fpu->fp_status);  
2111 - fsth2 = int32_to_float32(dt0 >> 32, &env->fpu->fp_status); 2109 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2110 + fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
  2111 + fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2112 update_fcr31(); 2112 update_fcr31();
2113 return ((uint64_t)fsth2 << 32) | fst2; 2113 return ((uint64_t)fsth2 << 32) | fst2;
2114 } 2114 }
@@ -2118,11 +2118,11 @@ uint64_t do_float_cvtpw_ps(uint64_t fdt0) @@ -2118,11 +2118,11 @@ uint64_t do_float_cvtpw_ps(uint64_t fdt0)
2118 uint32_t wt2; 2118 uint32_t wt2;
2119 uint32_t wth2; 2119 uint32_t wth2;
2120 2120
2121 - set_float_exception_flags(0, &env->fpu->fp_status);  
2122 - wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->fpu->fp_status);  
2123 - wth2 = float32_to_int32(fdt0 >> 32, &env->fpu->fp_status); 2121 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2122 + wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
  2123 + wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2124 update_fcr31(); 2124 update_fcr31();
2125 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) { 2125 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
2126 wt2 = FLOAT_SNAN32; 2126 wt2 = FLOAT_SNAN32;
2127 wth2 = FLOAT_SNAN32; 2127 wth2 = FLOAT_SNAN32;
2128 } 2128 }
@@ -2133,8 +2133,8 @@ uint32_t do_float_cvts_d(uint64_t fdt0) @@ -2133,8 +2133,8 @@ uint32_t do_float_cvts_d(uint64_t fdt0)
2133 { 2133 {
2134 uint32_t fst2; 2134 uint32_t fst2;
2135 2135
2136 - set_float_exception_flags(0, &env->fpu->fp_status);  
2137 - fst2 = float64_to_float32(fdt0, &env->fpu->fp_status); 2136 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2137 + fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2138 update_fcr31(); 2138 update_fcr31();
2139 return fst2; 2139 return fst2;
2140 } 2140 }
@@ -2143,8 +2143,8 @@ uint32_t do_float_cvts_w(uint32_t wt0) @@ -2143,8 +2143,8 @@ uint32_t do_float_cvts_w(uint32_t wt0)
2143 { 2143 {
2144 uint32_t fst2; 2144 uint32_t fst2;
2145 2145
2146 - set_float_exception_flags(0, &env->fpu->fp_status);  
2147 - fst2 = int32_to_float32(wt0, &env->fpu->fp_status); 2146 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2147 + fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2148 update_fcr31(); 2148 update_fcr31();
2149 return fst2; 2149 return fst2;
2150 } 2150 }
@@ -2153,8 +2153,8 @@ uint32_t do_float_cvts_l(uint64_t dt0) @@ -2153,8 +2153,8 @@ uint32_t do_float_cvts_l(uint64_t dt0)
2153 { 2153 {
2154 uint32_t fst2; 2154 uint32_t fst2;
2155 2155
2156 - set_float_exception_flags(0, &env->fpu->fp_status);  
2157 - fst2 = int64_to_float32(dt0, &env->fpu->fp_status); 2156 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2157 + fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2158 update_fcr31(); 2158 update_fcr31();
2159 return fst2; 2159 return fst2;
2160 } 2160 }
@@ -2163,7 +2163,7 @@ uint32_t do_float_cvts_pl(uint32_t wt0) @@ -2163,7 +2163,7 @@ uint32_t do_float_cvts_pl(uint32_t wt0)
2163 { 2163 {
2164 uint32_t wt2; 2164 uint32_t wt2;
2165 2165
2166 - set_float_exception_flags(0, &env->fpu->fp_status); 2166 + set_float_exception_flags(0, &env->active_fpu.fp_status);
2167 wt2 = wt0; 2167 wt2 = wt0;
2168 update_fcr31(); 2168 update_fcr31();
2169 return wt2; 2169 return wt2;
@@ -2173,7 +2173,7 @@ uint32_t do_float_cvts_pu(uint32_t wth0) @@ -2173,7 +2173,7 @@ uint32_t do_float_cvts_pu(uint32_t wth0)
2173 { 2173 {
2174 uint32_t wt2; 2174 uint32_t wt2;
2175 2175
2176 - set_float_exception_flags(0, &env->fpu->fp_status); 2176 + set_float_exception_flags(0, &env->active_fpu.fp_status);
2177 wt2 = wth0; 2177 wt2 = wth0;
2178 update_fcr31(); 2178 update_fcr31();
2179 return wt2; 2179 return wt2;
@@ -2183,10 +2183,10 @@ uint32_t do_float_cvtw_s(uint32_t fst0) @@ -2183,10 +2183,10 @@ uint32_t do_float_cvtw_s(uint32_t fst0)
2183 { 2183 {
2184 uint32_t wt2; 2184 uint32_t wt2;
2185 2185
2186 - set_float_exception_flags(0, &env->fpu->fp_status);  
2187 - wt2 = float32_to_int32(fst0, &env->fpu->fp_status); 2186 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2187 + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2188 update_fcr31(); 2188 update_fcr31();
2189 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2189 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2190 wt2 = FLOAT_SNAN32; 2190 wt2 = FLOAT_SNAN32;
2191 return wt2; 2191 return wt2;
2192 } 2192 }
@@ -2195,10 +2195,10 @@ uint32_t do_float_cvtw_d(uint64_t fdt0) @@ -2195,10 +2195,10 @@ uint32_t do_float_cvtw_d(uint64_t fdt0)
2195 { 2195 {
2196 uint32_t wt2; 2196 uint32_t wt2;
2197 2197
2198 - set_float_exception_flags(0, &env->fpu->fp_status);  
2199 - wt2 = float64_to_int32(fdt0, &env->fpu->fp_status); 2198 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2199 + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2200 update_fcr31(); 2200 update_fcr31();
2201 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2201 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2202 wt2 = FLOAT_SNAN32; 2202 wt2 = FLOAT_SNAN32;
2203 return wt2; 2203 return wt2;
2204 } 2204 }
@@ -2207,11 +2207,11 @@ uint64_t do_float_roundl_d(uint64_t fdt0) @@ -2207,11 +2207,11 @@ uint64_t do_float_roundl_d(uint64_t fdt0)
2207 { 2207 {
2208 uint64_t dt2; 2208 uint64_t dt2;
2209 2209
2210 - set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);  
2211 - dt2 = float64_to_int64(fdt0, &env->fpu->fp_status); 2210 + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
  2211 + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2212 RESTORE_ROUNDING_MODE; 2212 RESTORE_ROUNDING_MODE;
2213 update_fcr31(); 2213 update_fcr31();
2214 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2214 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2215 dt2 = FLOAT_SNAN64; 2215 dt2 = FLOAT_SNAN64;
2216 return dt2; 2216 return dt2;
2217 } 2217 }
@@ -2220,11 +2220,11 @@ uint64_t do_float_roundl_s(uint32_t fst0) @@ -2220,11 +2220,11 @@ uint64_t do_float_roundl_s(uint32_t fst0)
2220 { 2220 {
2221 uint64_t dt2; 2221 uint64_t dt2;
2222 2222
2223 - set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);  
2224 - dt2 = float32_to_int64(fst0, &env->fpu->fp_status); 2223 + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
  2224 + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2225 RESTORE_ROUNDING_MODE; 2225 RESTORE_ROUNDING_MODE;
2226 update_fcr31(); 2226 update_fcr31();
2227 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2227 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2228 dt2 = FLOAT_SNAN64; 2228 dt2 = FLOAT_SNAN64;
2229 return dt2; 2229 return dt2;
2230 } 2230 }
@@ -2233,11 +2233,11 @@ uint32_t do_float_roundw_d(uint64_t fdt0) @@ -2233,11 +2233,11 @@ uint32_t do_float_roundw_d(uint64_t fdt0)
2233 { 2233 {
2234 uint32_t wt2; 2234 uint32_t wt2;
2235 2235
2236 - set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);  
2237 - wt2 = float64_to_int32(fdt0, &env->fpu->fp_status); 2236 + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
  2237 + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2238 RESTORE_ROUNDING_MODE; 2238 RESTORE_ROUNDING_MODE;
2239 update_fcr31(); 2239 update_fcr31();
2240 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2240 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2241 wt2 = FLOAT_SNAN32; 2241 wt2 = FLOAT_SNAN32;
2242 return wt2; 2242 return wt2;
2243 } 2243 }
@@ -2246,11 +2246,11 @@ uint32_t do_float_roundw_s(uint32_t fst0) @@ -2246,11 +2246,11 @@ uint32_t do_float_roundw_s(uint32_t fst0)
2246 { 2246 {
2247 uint32_t wt2; 2247 uint32_t wt2;
2248 2248
2249 - set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);  
2250 - wt2 = float32_to_int32(fst0, &env->fpu->fp_status); 2249 + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
  2250 + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2251 RESTORE_ROUNDING_MODE; 2251 RESTORE_ROUNDING_MODE;
2252 update_fcr31(); 2252 update_fcr31();
2253 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2253 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2254 wt2 = FLOAT_SNAN32; 2254 wt2 = FLOAT_SNAN32;
2255 return wt2; 2255 return wt2;
2256 } 2256 }
@@ -2259,9 +2259,9 @@ uint64_t do_float_truncl_d(uint64_t fdt0) @@ -2259,9 +2259,9 @@ uint64_t do_float_truncl_d(uint64_t fdt0)
2259 { 2259 {
2260 uint64_t dt2; 2260 uint64_t dt2;
2261 2261
2262 - dt2 = float64_to_int64_round_to_zero(fdt0, &env->fpu->fp_status); 2262 + dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2263 update_fcr31(); 2263 update_fcr31();
2264 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2264 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2265 dt2 = FLOAT_SNAN64; 2265 dt2 = FLOAT_SNAN64;
2266 return dt2; 2266 return dt2;
2267 } 2267 }
@@ -2270,9 +2270,9 @@ uint64_t do_float_truncl_s(uint32_t fst0) @@ -2270,9 +2270,9 @@ uint64_t do_float_truncl_s(uint32_t fst0)
2270 { 2270 {
2271 uint64_t dt2; 2271 uint64_t dt2;
2272 2272
2273 - dt2 = float32_to_int64_round_to_zero(fst0, &env->fpu->fp_status); 2273 + dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2274 update_fcr31(); 2274 update_fcr31();
2275 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2275 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2276 dt2 = FLOAT_SNAN64; 2276 dt2 = FLOAT_SNAN64;
2277 return dt2; 2277 return dt2;
2278 } 2278 }
@@ -2281,9 +2281,9 @@ uint32_t do_float_truncw_d(uint64_t fdt0) @@ -2281,9 +2281,9 @@ uint32_t do_float_truncw_d(uint64_t fdt0)
2281 { 2281 {
2282 uint32_t wt2; 2282 uint32_t wt2;
2283 2283
2284 - wt2 = float64_to_int32_round_to_zero(fdt0, &env->fpu->fp_status); 2284 + wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2285 update_fcr31(); 2285 update_fcr31();
2286 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2286 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2287 wt2 = FLOAT_SNAN32; 2287 wt2 = FLOAT_SNAN32;
2288 return wt2; 2288 return wt2;
2289 } 2289 }
@@ -2292,9 +2292,9 @@ uint32_t do_float_truncw_s(uint32_t fst0) @@ -2292,9 +2292,9 @@ uint32_t do_float_truncw_s(uint32_t fst0)
2292 { 2292 {
2293 uint32_t wt2; 2293 uint32_t wt2;
2294 2294
2295 - wt2 = float32_to_int32_round_to_zero(fst0, &env->fpu->fp_status); 2295 + wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2296 update_fcr31(); 2296 update_fcr31();
2297 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2297 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2298 wt2 = FLOAT_SNAN32; 2298 wt2 = FLOAT_SNAN32;
2299 return wt2; 2299 return wt2;
2300 } 2300 }
@@ -2303,11 +2303,11 @@ uint64_t do_float_ceill_d(uint64_t fdt0) @@ -2303,11 +2303,11 @@ uint64_t do_float_ceill_d(uint64_t fdt0)
2303 { 2303 {
2304 uint64_t dt2; 2304 uint64_t dt2;
2305 2305
2306 - set_float_rounding_mode(float_round_up, &env->fpu->fp_status);  
2307 - dt2 = float64_to_int64(fdt0, &env->fpu->fp_status); 2306 + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
  2307 + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2308 RESTORE_ROUNDING_MODE; 2308 RESTORE_ROUNDING_MODE;
2309 update_fcr31(); 2309 update_fcr31();
2310 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2310 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2311 dt2 = FLOAT_SNAN64; 2311 dt2 = FLOAT_SNAN64;
2312 return dt2; 2312 return dt2;
2313 } 2313 }
@@ -2316,11 +2316,11 @@ uint64_t do_float_ceill_s(uint32_t fst0) @@ -2316,11 +2316,11 @@ uint64_t do_float_ceill_s(uint32_t fst0)
2316 { 2316 {
2317 uint64_t dt2; 2317 uint64_t dt2;
2318 2318
2319 - set_float_rounding_mode(float_round_up, &env->fpu->fp_status);  
2320 - dt2 = float32_to_int64(fst0, &env->fpu->fp_status); 2319 + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
  2320 + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2321 RESTORE_ROUNDING_MODE; 2321 RESTORE_ROUNDING_MODE;
2322 update_fcr31(); 2322 update_fcr31();
2323 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2323 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2324 dt2 = FLOAT_SNAN64; 2324 dt2 = FLOAT_SNAN64;
2325 return dt2; 2325 return dt2;
2326 } 2326 }
@@ -2329,11 +2329,11 @@ uint32_t do_float_ceilw_d(uint64_t fdt0) @@ -2329,11 +2329,11 @@ uint32_t do_float_ceilw_d(uint64_t fdt0)
2329 { 2329 {
2330 uint32_t wt2; 2330 uint32_t wt2;
2331 2331
2332 - set_float_rounding_mode(float_round_up, &env->fpu->fp_status);  
2333 - wt2 = float64_to_int32(fdt0, &env->fpu->fp_status); 2332 + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
  2333 + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2334 RESTORE_ROUNDING_MODE; 2334 RESTORE_ROUNDING_MODE;
2335 update_fcr31(); 2335 update_fcr31();
2336 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2336 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2337 wt2 = FLOAT_SNAN32; 2337 wt2 = FLOAT_SNAN32;
2338 return wt2; 2338 return wt2;
2339 } 2339 }
@@ -2342,11 +2342,11 @@ uint32_t do_float_ceilw_s(uint32_t fst0) @@ -2342,11 +2342,11 @@ uint32_t do_float_ceilw_s(uint32_t fst0)
2342 { 2342 {
2343 uint32_t wt2; 2343 uint32_t wt2;
2344 2344
2345 - set_float_rounding_mode(float_round_up, &env->fpu->fp_status);  
2346 - wt2 = float32_to_int32(fst0, &env->fpu->fp_status); 2345 + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
  2346 + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2347 RESTORE_ROUNDING_MODE; 2347 RESTORE_ROUNDING_MODE;
2348 update_fcr31(); 2348 update_fcr31();
2349 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2349 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2350 wt2 = FLOAT_SNAN32; 2350 wt2 = FLOAT_SNAN32;
2351 return wt2; 2351 return wt2;
2352 } 2352 }
@@ -2355,11 +2355,11 @@ uint64_t do_float_floorl_d(uint64_t fdt0) @@ -2355,11 +2355,11 @@ uint64_t do_float_floorl_d(uint64_t fdt0)
2355 { 2355 {
2356 uint64_t dt2; 2356 uint64_t dt2;
2357 2357
2358 - set_float_rounding_mode(float_round_down, &env->fpu->fp_status);  
2359 - dt2 = float64_to_int64(fdt0, &env->fpu->fp_status); 2358 + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
  2359 + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2360 RESTORE_ROUNDING_MODE; 2360 RESTORE_ROUNDING_MODE;
2361 update_fcr31(); 2361 update_fcr31();
2362 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2362 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2363 dt2 = FLOAT_SNAN64; 2363 dt2 = FLOAT_SNAN64;
2364 return dt2; 2364 return dt2;
2365 } 2365 }
@@ -2368,11 +2368,11 @@ uint64_t do_float_floorl_s(uint32_t fst0) @@ -2368,11 +2368,11 @@ uint64_t do_float_floorl_s(uint32_t fst0)
2368 { 2368 {
2369 uint64_t dt2; 2369 uint64_t dt2;
2370 2370
2371 - set_float_rounding_mode(float_round_down, &env->fpu->fp_status);  
2372 - dt2 = float32_to_int64(fst0, &env->fpu->fp_status); 2371 + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
  2372 + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2373 RESTORE_ROUNDING_MODE; 2373 RESTORE_ROUNDING_MODE;
2374 update_fcr31(); 2374 update_fcr31();
2375 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2375 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2376 dt2 = FLOAT_SNAN64; 2376 dt2 = FLOAT_SNAN64;
2377 return dt2; 2377 return dt2;
2378 } 2378 }
@@ -2381,11 +2381,11 @@ uint32_t do_float_floorw_d(uint64_t fdt0) @@ -2381,11 +2381,11 @@ uint32_t do_float_floorw_d(uint64_t fdt0)
2381 { 2381 {
2382 uint32_t wt2; 2382 uint32_t wt2;
2383 2383
2384 - set_float_rounding_mode(float_round_down, &env->fpu->fp_status);  
2385 - wt2 = float64_to_int32(fdt0, &env->fpu->fp_status); 2384 + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
  2385 + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2386 RESTORE_ROUNDING_MODE; 2386 RESTORE_ROUNDING_MODE;
2387 update_fcr31(); 2387 update_fcr31();
2388 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2388 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2389 wt2 = FLOAT_SNAN32; 2389 wt2 = FLOAT_SNAN32;
2390 return wt2; 2390 return wt2;
2391 } 2391 }
@@ -2394,11 +2394,11 @@ uint32_t do_float_floorw_s(uint32_t fst0) @@ -2394,11 +2394,11 @@ uint32_t do_float_floorw_s(uint32_t fst0)
2394 { 2394 {
2395 uint32_t wt2; 2395 uint32_t wt2;
2396 2396
2397 - set_float_rounding_mode(float_round_down, &env->fpu->fp_status);  
2398 - wt2 = float32_to_int32(fst0, &env->fpu->fp_status); 2397 + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
  2398 + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2399 RESTORE_ROUNDING_MODE; 2399 RESTORE_ROUNDING_MODE;
2400 update_fcr31(); 2400 update_fcr31();
2401 - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) 2401 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2402 wt2 = FLOAT_SNAN32; 2402 wt2 = FLOAT_SNAN32;
2403 return wt2; 2403 return wt2;
2404 } 2404 }
@@ -2431,8 +2431,8 @@ uint64_t do_float_recip_d(uint64_t fdt0) @@ -2431,8 +2431,8 @@ uint64_t do_float_recip_d(uint64_t fdt0)
2431 { 2431 {
2432 uint64_t fdt2; 2432 uint64_t fdt2;
2433 2433
2434 - set_float_exception_flags(0, &env->fpu->fp_status);  
2435 - fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->fpu->fp_status); 2434 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2435 + fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2436 update_fcr31(); 2436 update_fcr31();
2437 return fdt2; 2437 return fdt2;
2438 } 2438 }
@@ -2441,8 +2441,8 @@ uint32_t do_float_recip_s(uint32_t fst0) @@ -2441,8 +2441,8 @@ uint32_t do_float_recip_s(uint32_t fst0)
2441 { 2441 {
2442 uint32_t fst2; 2442 uint32_t fst2;
2443 2443
2444 - set_float_exception_flags(0, &env->fpu->fp_status);  
2445 - fst2 = float32_div(FLOAT_ONE32, fst0, &env->fpu->fp_status); 2444 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2445 + fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2446 update_fcr31(); 2446 update_fcr31();
2447 return fst2; 2447 return fst2;
2448 } 2448 }
@@ -2451,9 +2451,9 @@ uint64_t do_float_rsqrt_d(uint64_t fdt0) @@ -2451,9 +2451,9 @@ uint64_t do_float_rsqrt_d(uint64_t fdt0)
2451 { 2451 {
2452 uint64_t fdt2; 2452 uint64_t fdt2;
2453 2453
2454 - set_float_exception_flags(0, &env->fpu->fp_status);  
2455 - fdt2 = float64_sqrt(fdt0, &env->fpu->fp_status);  
2456 - fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->fpu->fp_status); 2454 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2455 + fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
  2456 + fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2457 update_fcr31(); 2457 update_fcr31();
2458 return fdt2; 2458 return fdt2;
2459 } 2459 }
@@ -2462,9 +2462,9 @@ uint32_t do_float_rsqrt_s(uint32_t fst0) @@ -2462,9 +2462,9 @@ uint32_t do_float_rsqrt_s(uint32_t fst0)
2462 { 2462 {
2463 uint32_t fst2; 2463 uint32_t fst2;
2464 2464
2465 - set_float_exception_flags(0, &env->fpu->fp_status);  
2466 - fst2 = float32_sqrt(fst0, &env->fpu->fp_status);  
2467 - fst2 = float32_div(FLOAT_ONE32, fst2, &env->fpu->fp_status); 2465 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2466 + fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
  2467 + fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2468 update_fcr31(); 2468 update_fcr31();
2469 return fst2; 2469 return fst2;
2470 } 2470 }
@@ -2473,8 +2473,8 @@ uint64_t do_float_recip1_d(uint64_t fdt0) @@ -2473,8 +2473,8 @@ uint64_t do_float_recip1_d(uint64_t fdt0)
2473 { 2473 {
2474 uint64_t fdt2; 2474 uint64_t fdt2;
2475 2475
2476 - set_float_exception_flags(0, &env->fpu->fp_status);  
2477 - fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->fpu->fp_status); 2476 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2477 + fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2478 update_fcr31(); 2478 update_fcr31();
2479 return fdt2; 2479 return fdt2;
2480 } 2480 }
@@ -2483,8 +2483,8 @@ uint32_t do_float_recip1_s(uint32_t fst0) @@ -2483,8 +2483,8 @@ uint32_t do_float_recip1_s(uint32_t fst0)
2483 { 2483 {
2484 uint32_t fst2; 2484 uint32_t fst2;
2485 2485
2486 - set_float_exception_flags(0, &env->fpu->fp_status);  
2487 - fst2 = float32_div(FLOAT_ONE32, fst0, &env->fpu->fp_status); 2486 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2487 + fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2488 update_fcr31(); 2488 update_fcr31();
2489 return fst2; 2489 return fst2;
2490 } 2490 }
@@ -2494,9 +2494,9 @@ uint64_t do_float_recip1_ps(uint64_t fdt0) @@ -2494,9 +2494,9 @@ uint64_t do_float_recip1_ps(uint64_t fdt0)
2494 uint32_t fst2; 2494 uint32_t fst2;
2495 uint32_t fsth2; 2495 uint32_t fsth2;
2496 2496
2497 - set_float_exception_flags(0, &env->fpu->fp_status);  
2498 - fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->fpu->fp_status);  
2499 - fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->fpu->fp_status); 2497 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2498 + fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
  2499 + fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
2500 update_fcr31(); 2500 update_fcr31();
2501 return ((uint64_t)fsth2 << 32) | fst2; 2501 return ((uint64_t)fsth2 << 32) | fst2;
2502 } 2502 }
@@ -2505,9 +2505,9 @@ uint64_t do_float_rsqrt1_d(uint64_t fdt0) @@ -2505,9 +2505,9 @@ uint64_t do_float_rsqrt1_d(uint64_t fdt0)
2505 { 2505 {
2506 uint64_t fdt2; 2506 uint64_t fdt2;
2507 2507
2508 - set_float_exception_flags(0, &env->fpu->fp_status);  
2509 - fdt2 = float64_sqrt(fdt0, &env->fpu->fp_status);  
2510 - fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->fpu->fp_status); 2508 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2509 + fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
  2510 + fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2511 update_fcr31(); 2511 update_fcr31();
2512 return fdt2; 2512 return fdt2;
2513 } 2513 }
@@ -2516,9 +2516,9 @@ uint32_t do_float_rsqrt1_s(uint32_t fst0) @@ -2516,9 +2516,9 @@ uint32_t do_float_rsqrt1_s(uint32_t fst0)
2516 { 2516 {
2517 uint32_t fst2; 2517 uint32_t fst2;
2518 2518
2519 - set_float_exception_flags(0, &env->fpu->fp_status);  
2520 - fst2 = float32_sqrt(fst0, &env->fpu->fp_status);  
2521 - fst2 = float32_div(FLOAT_ONE32, fst2, &env->fpu->fp_status); 2519 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2520 + fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
  2521 + fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2522 update_fcr31(); 2522 update_fcr31();
2523 return fst2; 2523 return fst2;
2524 } 2524 }
@@ -2528,11 +2528,11 @@ uint64_t do_float_rsqrt1_ps(uint64_t fdt0) @@ -2528,11 +2528,11 @@ uint64_t do_float_rsqrt1_ps(uint64_t fdt0)
2528 uint32_t fst2; 2528 uint32_t fst2;
2529 uint32_t fsth2; 2529 uint32_t fsth2;
2530 2530
2531 - set_float_exception_flags(0, &env->fpu->fp_status);  
2532 - fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->fpu->fp_status);  
2533 - fsth2 = float32_sqrt(fdt0 >> 32, &env->fpu->fp_status);  
2534 - fst2 = float32_div(FLOAT_ONE32, fst2, &env->fpu->fp_status);  
2535 - fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->fpu->fp_status); 2531 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2532 + fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
  2533 + fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
  2534 + fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
  2535 + fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
2536 update_fcr31(); 2536 update_fcr31();
2537 return ((uint64_t)fsth2 << 32) | fst2; 2537 return ((uint64_t)fsth2 << 32) | fst2;
2538 } 2538 }
@@ -2545,10 +2545,10 @@ uint64_t do_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \ @@ -2545,10 +2545,10 @@ uint64_t do_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
2545 { \ 2545 { \
2546 uint64_t dt2; \ 2546 uint64_t dt2; \
2547 \ 2547 \
2548 - set_float_exception_flags(0, &env->fpu->fp_status); \  
2549 - dt2 = float64_ ## name (fdt0, fdt1, &env->fpu->fp_status); \ 2548 + set_float_exception_flags(0, &env->active_fpu.fp_status); \
  2549 + dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2550 update_fcr31(); \ 2550 update_fcr31(); \
2551 - if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \ 2551 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2552 dt2 = FLOAT_QNAN64; \ 2552 dt2 = FLOAT_QNAN64; \
2553 return dt2; \ 2553 return dt2; \
2554 } \ 2554 } \
@@ -2557,10 +2557,10 @@ uint32_t do_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \ @@ -2557,10 +2557,10 @@ uint32_t do_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
2557 { \ 2557 { \
2558 uint32_t wt2; \ 2558 uint32_t wt2; \
2559 \ 2559 \
2560 - set_float_exception_flags(0, &env->fpu->fp_status); \  
2561 - wt2 = float32_ ## name (fst0, fst1, &env->fpu->fp_status); \ 2560 + set_float_exception_flags(0, &env->active_fpu.fp_status); \
  2561 + wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2562 update_fcr31(); \ 2562 update_fcr31(); \
2563 - if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \ 2563 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2564 wt2 = FLOAT_QNAN32; \ 2564 wt2 = FLOAT_QNAN32; \
2565 return wt2; \ 2565 return wt2; \
2566 } \ 2566 } \
@@ -2574,11 +2574,11 @@ uint64_t do_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ @@ -2574,11 +2574,11 @@ uint64_t do_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
2574 uint32_t wt2; \ 2574 uint32_t wt2; \
2575 uint32_t wth2; \ 2575 uint32_t wth2; \
2576 \ 2576 \
2577 - set_float_exception_flags(0, &env->fpu->fp_status); \  
2578 - wt2 = float32_ ## name (fst0, fst1, &env->fpu->fp_status); \  
2579 - wth2 = float32_ ## name (fsth0, fsth1, &env->fpu->fp_status); \ 2577 + set_float_exception_flags(0, &env->active_fpu.fp_status); \
  2578 + wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
  2579 + wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2580 update_fcr31(); \ 2580 update_fcr31(); \
2581 - if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \ 2581 + if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
2582 wt2 = FLOAT_QNAN32; \ 2582 wt2 = FLOAT_QNAN32; \
2583 wth2 = FLOAT_QNAN32; \ 2583 wth2 = FLOAT_QNAN32; \
2584 } \ 2584 } \
@@ -2596,15 +2596,15 @@ FLOAT_BINOP(div) @@ -2596,15 +2596,15 @@ FLOAT_BINOP(div)
2596 uint64_t do_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ 2596 uint64_t do_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2597 uint64_t fdt2) \ 2597 uint64_t fdt2) \
2598 { \ 2598 { \
2599 - fdt0 = float64_ ## name1 (fdt0, fdt1, &env->fpu->fp_status); \  
2600 - return float64_ ## name2 (fdt0, fdt2, &env->fpu->fp_status); \ 2599 + fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
  2600 + return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2601 } \ 2601 } \
2602 \ 2602 \
2603 uint32_t do_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ 2603 uint32_t do_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2604 uint32_t fst2) \ 2604 uint32_t fst2) \
2605 { \ 2605 { \
2606 - fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status); \  
2607 - return float32_ ## name2 (fst0, fst2, &env->fpu->fp_status); \ 2606 + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
  2607 + return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2608 } \ 2608 } \
2609 \ 2609 \
2610 uint64_t do_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \ 2610 uint64_t do_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
@@ -2617,10 +2617,10 @@ uint64_t do_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \ @@ -2617,10 +2617,10 @@ uint64_t do_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
2617 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ 2617 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2618 uint32_t fsth2 = fdt2 >> 32; \ 2618 uint32_t fsth2 = fdt2 >> 32; \
2619 \ 2619 \
2620 - fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status); \  
2621 - fsth0 = float32_ ## name1 (fsth0, fsth1, &env->fpu->fp_status); \  
2622 - fst2 = float32_ ## name2 (fst0, fst2, &env->fpu->fp_status); \  
2623 - fsth2 = float32_ ## name2 (fsth0, fsth2, &env->fpu->fp_status); \ 2620 + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
  2621 + fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
  2622 + fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
  2623 + fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2624 return ((uint64_t)fsth2 << 32) | fst2; \ 2624 return ((uint64_t)fsth2 << 32) | fst2; \
2625 } 2625 }
2626 2626
@@ -2633,16 +2633,16 @@ FLOAT_TERNOP(mul, sub) @@ -2633,16 +2633,16 @@ FLOAT_TERNOP(mul, sub)
2633 uint64_t do_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ 2633 uint64_t do_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2634 uint64_t fdt2) \ 2634 uint64_t fdt2) \
2635 { \ 2635 { \
2636 - fdt0 = float64_ ## name1 (fdt0, fdt1, &env->fpu->fp_status); \  
2637 - fdt2 = float64_ ## name2 (fdt0, fdt2, &env->fpu->fp_status); \ 2636 + fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
  2637 + fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2638 return float64_chs(fdt2); \ 2638 return float64_chs(fdt2); \
2639 } \ 2639 } \
2640 \ 2640 \
2641 uint32_t do_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ 2641 uint32_t do_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2642 uint32_t fst2) \ 2642 uint32_t fst2) \
2643 { \ 2643 { \
2644 - fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status); \  
2645 - fst2 = float32_ ## name2 (fst0, fst2, &env->fpu->fp_status); \ 2644 + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
  2645 + fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2646 return float32_chs(fst2); \ 2646 return float32_chs(fst2); \
2647 } \ 2647 } \
2648 \ 2648 \
@@ -2656,10 +2656,10 @@ uint64_t do_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\ @@ -2656,10 +2656,10 @@ uint64_t do_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
2656 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ 2656 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2657 uint32_t fsth2 = fdt2 >> 32; \ 2657 uint32_t fsth2 = fdt2 >> 32; \
2658 \ 2658 \
2659 - fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status); \  
2660 - fsth0 = float32_ ## name1 (fsth0, fsth1, &env->fpu->fp_status); \  
2661 - fst2 = float32_ ## name2 (fst0, fst2, &env->fpu->fp_status); \  
2662 - fsth2 = float32_ ## name2 (fsth0, fsth2, &env->fpu->fp_status); \ 2659 + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
  2660 + fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
  2661 + fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
  2662 + fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2663 fst2 = float32_chs(fst2); \ 2663 fst2 = float32_chs(fst2); \
2664 fsth2 = float32_chs(fsth2); \ 2664 fsth2 = float32_chs(fsth2); \
2665 return ((uint64_t)fsth2 << 32) | fst2; \ 2665 return ((uint64_t)fsth2 << 32) | fst2; \
@@ -2672,18 +2672,18 @@ FLOAT_NTERNOP(mul, sub) @@ -2672,18 +2672,18 @@ FLOAT_NTERNOP(mul, sub)
2672 /* MIPS specific binary operations */ 2672 /* MIPS specific binary operations */
2673 uint64_t do_float_recip2_d(uint64_t fdt0, uint64_t fdt2) 2673 uint64_t do_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
2674 { 2674 {
2675 - set_float_exception_flags(0, &env->fpu->fp_status);  
2676 - fdt2 = float64_mul(fdt0, fdt2, &env->fpu->fp_status);  
2677 - fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->fpu->fp_status)); 2675 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2676 + fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
  2677 + fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
2678 update_fcr31(); 2678 update_fcr31();
2679 return fdt2; 2679 return fdt2;
2680 } 2680 }
2681 2681
2682 uint32_t do_float_recip2_s(uint32_t fst0, uint32_t fst2) 2682 uint32_t do_float_recip2_s(uint32_t fst0, uint32_t fst2)
2683 { 2683 {
2684 - set_float_exception_flags(0, &env->fpu->fp_status);  
2685 - fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);  
2686 - fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status)); 2684 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2685 + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
  2686 + fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2687 update_fcr31(); 2687 update_fcr31();
2688 return fst2; 2688 return fst2;
2689 } 2689 }
@@ -2695,31 +2695,31 @@ uint64_t do_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) @@ -2695,31 +2695,31 @@ uint64_t do_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
2695 uint32_t fst2 = fdt2 & 0XFFFFFFFF; 2695 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2696 uint32_t fsth2 = fdt2 >> 32; 2696 uint32_t fsth2 = fdt2 >> 32;
2697 2697
2698 - set_float_exception_flags(0, &env->fpu->fp_status);  
2699 - fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);  
2700 - fsth2 = float32_mul(fsth0, fsth2, &env->fpu->fp_status);  
2701 - fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status));  
2702 - fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->fpu->fp_status)); 2698 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2699 + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
  2700 + fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
  2701 + fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
  2702 + fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
2703 update_fcr31(); 2703 update_fcr31();
2704 return ((uint64_t)fsth2 << 32) | fst2; 2704 return ((uint64_t)fsth2 << 32) | fst2;
2705 } 2705 }
2706 2706
2707 uint64_t do_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2) 2707 uint64_t do_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
2708 { 2708 {
2709 - set_float_exception_flags(0, &env->fpu->fp_status);  
2710 - fdt2 = float64_mul(fdt0, fdt2, &env->fpu->fp_status);  
2711 - fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->fpu->fp_status);  
2712 - fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->fpu->fp_status)); 2709 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2710 + fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
  2711 + fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
  2712 + fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2713 update_fcr31(); 2713 update_fcr31();
2714 return fdt2; 2714 return fdt2;
2715 } 2715 }
2716 2716
2717 uint32_t do_float_rsqrt2_s(uint32_t fst0, uint32_t fst2) 2717 uint32_t do_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
2718 { 2718 {
2719 - set_float_exception_flags(0, &env->fpu->fp_status);  
2720 - fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);  
2721 - fst2 = float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status);  
2722 - fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->fpu->fp_status)); 2719 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2720 + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
  2721 + fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
  2722 + fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2723 update_fcr31(); 2723 update_fcr31();
2724 return fst2; 2724 return fst2;
2725 } 2725 }
@@ -2731,13 +2731,13 @@ uint64_t do_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) @@ -2731,13 +2731,13 @@ uint64_t do_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
2731 uint32_t fst2 = fdt2 & 0XFFFFFFFF; 2731 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2732 uint32_t fsth2 = fdt2 >> 32; 2732 uint32_t fsth2 = fdt2 >> 32;
2733 2733
2734 - set_float_exception_flags(0, &env->fpu->fp_status);  
2735 - fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);  
2736 - fsth2 = float32_mul(fsth0, fsth2, &env->fpu->fp_status);  
2737 - fst2 = float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status);  
2738 - fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->fpu->fp_status);  
2739 - fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->fpu->fp_status));  
2740 - fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->fpu->fp_status)); 2734 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2735 + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
  2736 + fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
  2737 + fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
  2738 + fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
  2739 + fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
  2740 + fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2741 update_fcr31(); 2741 update_fcr31();
2742 return ((uint64_t)fsth2 << 32) | fst2; 2742 return ((uint64_t)fsth2 << 32) | fst2;
2743 } 2743 }
@@ -2751,9 +2751,9 @@ uint64_t do_float_addr_ps(uint64_t fdt0, uint64_t fdt1) @@ -2751,9 +2751,9 @@ uint64_t do_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
2751 uint32_t fst2; 2751 uint32_t fst2;
2752 uint32_t fsth2; 2752 uint32_t fsth2;
2753 2753
2754 - set_float_exception_flags(0, &env->fpu->fp_status);  
2755 - fst2 = float32_add (fst0, fsth0, &env->fpu->fp_status);  
2756 - fsth2 = float32_add (fst1, fsth1, &env->fpu->fp_status); 2754 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2755 + fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
  2756 + fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
2757 update_fcr31(); 2757 update_fcr31();
2758 return ((uint64_t)fsth2 << 32) | fst2; 2758 return ((uint64_t)fsth2 << 32) | fst2;
2759 } 2759 }
@@ -2767,9 +2767,9 @@ uint64_t do_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) @@ -2767,9 +2767,9 @@ uint64_t do_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
2767 uint32_t fst2; 2767 uint32_t fst2;
2768 uint32_t fsth2; 2768 uint32_t fsth2;
2769 2769
2770 - set_float_exception_flags(0, &env->fpu->fp_status);  
2771 - fst2 = float32_mul (fst0, fsth0, &env->fpu->fp_status);  
2772 - fsth2 = float32_mul (fst1, fsth1, &env->fpu->fp_status); 2770 + set_float_exception_flags(0, &env->active_fpu.fp_status);
  2771 + fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
  2772 + fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
2773 update_fcr31(); 2773 update_fcr31();
2774 return ((uint64_t)fsth2 << 32) | fst2; 2774 return ((uint64_t)fsth2 << 32) | fst2;
2775 } 2775 }
@@ -2781,9 +2781,9 @@ void do_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ @@ -2781,9 +2781,9 @@ void do_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2781 int c = cond; \ 2781 int c = cond; \
2782 update_fcr31(); \ 2782 update_fcr31(); \
2783 if (c) \ 2783 if (c) \
2784 - SET_FP_COND(cc, env->fpu); \ 2784 + SET_FP_COND(cc, env->active_fpu); \
2785 else \ 2785 else \
2786 - CLEAR_FP_COND(cc, env->fpu); \ 2786 + CLEAR_FP_COND(cc, env->active_fpu); \
2787 } \ 2787 } \
2788 void do_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ 2788 void do_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2789 { \ 2789 { \
@@ -2793,9 +2793,9 @@ void do_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ @@ -2793,9 +2793,9 @@ void do_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2793 c = cond; \ 2793 c = cond; \
2794 update_fcr31(); \ 2794 update_fcr31(); \
2795 if (c) \ 2795 if (c) \
2796 - SET_FP_COND(cc, env->fpu); \ 2796 + SET_FP_COND(cc, env->active_fpu); \
2797 else \ 2797 else \
2798 - CLEAR_FP_COND(cc, env->fpu); \ 2798 + CLEAR_FP_COND(cc, env->active_fpu); \
2799 } 2799 }
2800 2800
2801 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) 2801 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
@@ -2814,24 +2814,24 @@ int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) @@ -2814,24 +2814,24 @@ int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2814 2814
2815 /* NOTE: the comma operator will make "cond" to eval to false, 2815 /* NOTE: the comma operator will make "cond" to eval to false,
2816 * but float*_is_unordered() is still called. */ 2816 * but float*_is_unordered() is still called. */
2817 -FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status), 0))  
2818 -FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status))  
2819 -FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) && float64_eq(fdt0, fdt1, &env->fpu->fp_status))  
2820 -FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) || float64_eq(fdt0, fdt1, &env->fpu->fp_status))  
2821 -FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) && float64_lt(fdt0, fdt1, &env->fpu->fp_status))  
2822 -FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) || float64_lt(fdt0, fdt1, &env->fpu->fp_status))  
2823 -FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) && float64_le(fdt0, fdt1, &env->fpu->fp_status))  
2824 -FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) || float64_le(fdt0, fdt1, &env->fpu->fp_status)) 2817 +FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
  2818 +FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
  2819 +FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
  2820 +FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
  2821 +FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
  2822 +FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
  2823 +FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
  2824 +FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2825 /* NOTE: the comma operator will make "cond" to eval to false, 2825 /* NOTE: the comma operator will make "cond" to eval to false,
2826 * but float*_is_unordered() is still called. */ 2826 * but float*_is_unordered() is still called. */
2827 -FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status), 0))  
2828 -FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status))  
2829 -FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) && float64_eq(fdt0, fdt1, &env->fpu->fp_status))  
2830 -FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) || float64_eq(fdt0, fdt1, &env->fpu->fp_status))  
2831 -FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) && float64_lt(fdt0, fdt1, &env->fpu->fp_status))  
2832 -FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) || float64_lt(fdt0, fdt1, &env->fpu->fp_status))  
2833 -FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) && float64_le(fdt0, fdt1, &env->fpu->fp_status))  
2834 -FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) || float64_le(fdt0, fdt1, &env->fpu->fp_status)) 2827 +FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
  2828 +FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
  2829 +FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
  2830 +FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
  2831 +FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
  2832 +FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
  2833 +FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
  2834 +FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2835 2835
2836 #define FOP_COND_S(op, cond) \ 2836 #define FOP_COND_S(op, cond) \
2837 void do_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ 2837 void do_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
@@ -2839,9 +2839,9 @@ void do_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ @@ -2839,9 +2839,9 @@ void do_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2839 int c = cond; \ 2839 int c = cond; \
2840 update_fcr31(); \ 2840 update_fcr31(); \
2841 if (c) \ 2841 if (c) \
2842 - SET_FP_COND(cc, env->fpu); \ 2842 + SET_FP_COND(cc, env->active_fpu); \
2843 else \ 2843 else \
2844 - CLEAR_FP_COND(cc, env->fpu); \ 2844 + CLEAR_FP_COND(cc, env->active_fpu); \
2845 } \ 2845 } \
2846 void do_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ 2846 void do_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2847 { \ 2847 { \
@@ -2851,9 +2851,9 @@ void do_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ @@ -2851,9 +2851,9 @@ void do_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2851 c = cond; \ 2851 c = cond; \
2852 update_fcr31(); \ 2852 update_fcr31(); \
2853 if (c) \ 2853 if (c) \
2854 - SET_FP_COND(cc, env->fpu); \ 2854 + SET_FP_COND(cc, env->active_fpu); \
2855 else \ 2855 else \
2856 - CLEAR_FP_COND(cc, env->fpu); \ 2856 + CLEAR_FP_COND(cc, env->active_fpu); \
2857 } 2857 }
2858 2858
2859 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM) 2859 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
@@ -2872,24 +2872,24 @@ flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM) @@ -2872,24 +2872,24 @@ flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2872 2872
2873 /* NOTE: the comma operator will make "cond" to eval to false, 2873 /* NOTE: the comma operator will make "cond" to eval to false,
2874 * but float*_is_unordered() is still called. */ 2874 * but float*_is_unordered() is still called. */
2875 -FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status), 0))  
2876 -FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status))  
2877 -FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_eq(fst0, fst1, &env->fpu->fp_status))  
2878 -FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_eq(fst0, fst1, &env->fpu->fp_status))  
2879 -FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_lt(fst0, fst1, &env->fpu->fp_status))  
2880 -FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_lt(fst0, fst1, &env->fpu->fp_status))  
2881 -FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_le(fst0, fst1, &env->fpu->fp_status))  
2882 -FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_le(fst0, fst1, &env->fpu->fp_status)) 2875 +FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
  2876 +FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
  2877 +FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
  2878 +FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
  2879 +FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
  2880 +FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
  2881 +FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
  2882 +FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2883 /* NOTE: the comma operator will make "cond" to eval to false, 2883 /* NOTE: the comma operator will make "cond" to eval to false,
2884 * but float*_is_unordered() is still called. */ 2884 * but float*_is_unordered() is still called. */
2885 -FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status), 0))  
2886 -FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status))  
2887 -FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_eq(fst0, fst1, &env->fpu->fp_status))  
2888 -FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_eq(fst0, fst1, &env->fpu->fp_status))  
2889 -FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_lt(fst0, fst1, &env->fpu->fp_status))  
2890 -FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_lt(fst0, fst1, &env->fpu->fp_status))  
2891 -FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_le(fst0, fst1, &env->fpu->fp_status))  
2892 -FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_le(fst0, fst1, &env->fpu->fp_status)) 2885 +FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
  2886 +FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
  2887 +FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
  2888 +FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
  2889 +FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
  2890 +FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
  2891 +FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
  2892 +FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2893 2893
2894 #define FOP_COND_PS(op, condl, condh) \ 2894 #define FOP_COND_PS(op, condl, condh) \
2895 void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ 2895 void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
@@ -2903,13 +2903,13 @@ void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ @@ -2903,13 +2903,13 @@ void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2903 \ 2903 \
2904 update_fcr31(); \ 2904 update_fcr31(); \
2905 if (cl) \ 2905 if (cl) \
2906 - SET_FP_COND(cc, env->fpu); \ 2906 + SET_FP_COND(cc, env->active_fpu); \
2907 else \ 2907 else \
2908 - CLEAR_FP_COND(cc, env->fpu); \ 2908 + CLEAR_FP_COND(cc, env->active_fpu); \
2909 if (ch) \ 2909 if (ch) \
2910 - SET_FP_COND(cc + 1, env->fpu); \ 2910 + SET_FP_COND(cc + 1, env->active_fpu); \
2911 else \ 2911 else \
2912 - CLEAR_FP_COND(cc + 1, env->fpu); \ 2912 + CLEAR_FP_COND(cc + 1, env->active_fpu); \
2913 } \ 2913 } \
2914 void do_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ 2914 void do_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2915 { \ 2915 { \
@@ -2922,48 +2922,48 @@ void do_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ @@ -2922,48 +2922,48 @@ void do_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2922 \ 2922 \
2923 update_fcr31(); \ 2923 update_fcr31(); \
2924 if (cl) \ 2924 if (cl) \
2925 - SET_FP_COND(cc, env->fpu); \ 2925 + SET_FP_COND(cc, env->active_fpu); \
2926 else \ 2926 else \
2927 - CLEAR_FP_COND(cc, env->fpu); \ 2927 + CLEAR_FP_COND(cc, env->active_fpu); \
2928 if (ch) \ 2928 if (ch) \
2929 - SET_FP_COND(cc + 1, env->fpu); \ 2929 + SET_FP_COND(cc + 1, env->active_fpu); \
2930 else \ 2930 else \
2931 - CLEAR_FP_COND(cc + 1, env->fpu); \ 2931 + CLEAR_FP_COND(cc + 1, env->active_fpu); \
2932 } 2932 }
2933 2933
2934 /* NOTE: the comma operator will make "cond" to eval to false, 2934 /* NOTE: the comma operator will make "cond" to eval to false,
2935 * but float*_is_unordered() is still called. */ 2935 * but float*_is_unordered() is still called. */
2936 -FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status), 0),  
2937 - (float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status), 0))  
2938 -FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status),  
2939 - float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status))  
2940 -FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_eq(fst0, fst1, &env->fpu->fp_status),  
2941 - !float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) && float32_eq(fsth0, fsth1, &env->fpu->fp_status))  
2942 -FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_eq(fst0, fst1, &env->fpu->fp_status),  
2943 - float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) || float32_eq(fsth0, fsth1, &env->fpu->fp_status))  
2944 -FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_lt(fst0, fst1, &env->fpu->fp_status),  
2945 - !float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) && float32_lt(fsth0, fsth1, &env->fpu->fp_status))  
2946 -FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_lt(fst0, fst1, &env->fpu->fp_status),  
2947 - float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) || float32_lt(fsth0, fsth1, &env->fpu->fp_status))  
2948 -FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_le(fst0, fst1, &env->fpu->fp_status),  
2949 - !float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) && float32_le(fsth0, fsth1, &env->fpu->fp_status))  
2950 -FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_le(fst0, fst1, &env->fpu->fp_status),  
2951 - float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) || float32_le(fsth0, fsth1, &env->fpu->fp_status)) 2936 +FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
  2937 + (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
  2938 +FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
  2939 + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
  2940 +FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
  2941 + !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
  2942 +FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
  2943 + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
  2944 +FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
  2945 + !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
  2946 +FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
  2947 + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
  2948 +FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
  2949 + !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
  2950 +FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
  2951 + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2952 /* NOTE: the comma operator will make "cond" to eval to false, 2952 /* NOTE: the comma operator will make "cond" to eval to false,
2953 * but float*_is_unordered() is still called. */ 2953 * but float*_is_unordered() is still called. */
2954 -FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status), 0),  
2955 - (float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status), 0))  
2956 -FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status),  
2957 - float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status))  
2958 -FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_eq(fst0, fst1, &env->fpu->fp_status),  
2959 - !float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) && float32_eq(fsth0, fsth1, &env->fpu->fp_status))  
2960 -FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_eq(fst0, fst1, &env->fpu->fp_status),  
2961 - float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) || float32_eq(fsth0, fsth1, &env->fpu->fp_status))  
2962 -FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_lt(fst0, fst1, &env->fpu->fp_status),  
2963 - !float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) && float32_lt(fsth0, fsth1, &env->fpu->fp_status))  
2964 -FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_lt(fst0, fst1, &env->fpu->fp_status),  
2965 - float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) || float32_lt(fsth0, fsth1, &env->fpu->fp_status))  
2966 -FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_le(fst0, fst1, &env->fpu->fp_status),  
2967 - !float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) && float32_le(fsth0, fsth1, &env->fpu->fp_status))  
2968 -FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_le(fst0, fst1, &env->fpu->fp_status),  
2969 - float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) || float32_le(fsth0, fsth1, &env->fpu->fp_status)) 2954 +FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
  2955 + (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
  2956 +FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
  2957 + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
  2958 +FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
  2959 + !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
  2960 +FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
  2961 + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
  2962 +FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
  2963 + !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
  2964 +FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
  2965 + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
  2966 +FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
  2967 + !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
  2968 +FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
  2969 + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
target-mips/translate.c
  View file @f01be15
@@ -423,7 +423,8 @@ enum { @@ -423,7 +423,8 @@ enum {
423 }; 423 };
424 424
425 /* global register indices */ 425 /* global register indices */
426 -static TCGv cpu_env, bcond, btarget, current_fpu; 426 +static TCGv cpu_env, bcond, btarget;
  427 +static TCGv fpu_fpr32[32], fpu_fpr32h[32], fpu_fpr64[32], fpu_fcr0, fpu_fcr31;
427 428
428 #include "gen-icount.h" 429 #include "gen-icount.h"
429 430
@@ -547,6 +548,18 @@ static const char *fregnames[] = @@ -547,6 +548,18 @@ static const char *fregnames[] =
547 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 548 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
548 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; 549 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
549 550
  551 +static const char *fregnames_64[] =
  552 + { "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
  553 + "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
  554 + "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
  555 + "F24", "F25", "F26", "F27", "F28", "F29", "F30", "F31", };
  556 +
  557 +static const char *fregnames_h[] =
  558 + { "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
  559 + "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
  560 + "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
  561 + "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", };
  562 +
550 #ifdef MIPS_DEBUG_DISAS 563 #ifdef MIPS_DEBUG_DISAS
551 #define MIPS_DEBUG(fmt, args...) \ 564 #define MIPS_DEBUG(fmt, args...) \
552 do { \ 565 do { \
@@ -652,57 +665,48 @@ static inline void gen_store_srsgpr (int from, int to) @@ -652,57 +665,48 @@ static inline void gen_store_srsgpr (int from, int to)
652 /* Floating point register moves. */ 665 /* Floating point register moves. */
653 static inline void gen_load_fpr32 (TCGv t, int reg) 666 static inline void gen_load_fpr32 (TCGv t, int reg)
654 { 667 {
655 - tcg_gen_ld_i32(t, current_fpu, 8 * reg + 4 * FP_ENDIAN_IDX); 668 + tcg_gen_mov_i32(t, fpu_fpr32[reg]);
656 } 669 }
657 670
658 static inline void gen_store_fpr32 (TCGv t, int reg) 671 static inline void gen_store_fpr32 (TCGv t, int reg)
659 { 672 {
660 - tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * FP_ENDIAN_IDX); 673 + tcg_gen_mov_i32(fpu_fpr32[reg], t);
661 } 674 }
662 675
663 static inline void gen_load_fpr64 (DisasContext *ctx, TCGv t, int reg) 676 static inline void gen_load_fpr64 (DisasContext *ctx, TCGv t, int reg)
664 { 677 {
665 - if (ctx->hflags & MIPS_HFLAG_F64) {  
666 - tcg_gen_ld_i64(t, current_fpu, 8 * reg);  
667 - } else {  
668 - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); 678 + if (ctx->hflags & MIPS_HFLAG_F64)
  679 + tcg_gen_mov_i64(t, fpu_fpr64[reg]);
  680 + else {
669 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); 681 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
670 682
671 - tcg_gen_ld_i32(r_tmp1, current_fpu, 8 * (reg | 1) + 4 * FP_ENDIAN_IDX);  
672 - tcg_gen_extu_i32_i64(t, r_tmp1); 683 + tcg_gen_extu_i32_i64(t, fpu_fpr32[reg | 1]);
673 tcg_gen_shli_i64(t, t, 32); 684 tcg_gen_shli_i64(t, t, 32);
674 - tcg_gen_ld_i32(r_tmp1, current_fpu, 8 * (reg & ~1) + 4 * FP_ENDIAN_IDX);  
675 - tcg_gen_extu_i32_i64(r_tmp2, r_tmp1); 685 + tcg_gen_extu_i32_i64(r_tmp2, fpu_fpr32[reg & ~1]);
676 tcg_gen_or_i64(t, t, r_tmp2); 686 tcg_gen_or_i64(t, t, r_tmp2);
677 - tcg_temp_free(r_tmp1);  
678 tcg_temp_free(r_tmp2); 687 tcg_temp_free(r_tmp2);
679 } 688 }
680 } 689 }
681 690
682 static inline void gen_store_fpr64 (DisasContext *ctx, TCGv t, int reg) 691 static inline void gen_store_fpr64 (DisasContext *ctx, TCGv t, int reg)
683 { 692 {
684 - if (ctx->hflags & MIPS_HFLAG_F64) {  
685 - tcg_gen_st_i64(t, current_fpu, 8 * reg);  
686 - } else {  
687 - TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);  
688 -  
689 - tcg_gen_trunc_i64_i32(r_tmp, t);  
690 - tcg_gen_st_i32(r_tmp, current_fpu, 8 * (reg & ~1) + 4 * FP_ENDIAN_IDX); 693 + if (ctx->hflags & MIPS_HFLAG_F64)
  694 + tcg_gen_mov_i64(fpu_fpr64[reg], t);
  695 + else {
  696 + tcg_gen_trunc_i64_i32(fpu_fpr32[reg & ~1], t);
691 tcg_gen_shri_i64(t, t, 32); 697 tcg_gen_shri_i64(t, t, 32);
692 - tcg_gen_trunc_i64_i32(r_tmp, t);  
693 - tcg_gen_st_i32(r_tmp, current_fpu, 8 * (reg | 1) + 4 * FP_ENDIAN_IDX);  
694 - tcg_temp_free(r_tmp); 698 + tcg_gen_trunc_i64_i32(fpu_fpr32[reg | 1], t);
695 } 699 }
696 } 700 }
697 701
698 static inline void gen_load_fpr32h (TCGv t, int reg) 702 static inline void gen_load_fpr32h (TCGv t, int reg)
699 { 703 {
700 - tcg_gen_ld_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX); 704 + tcg_gen_mov_i32(t, fpu_fpr32h[reg]);
701 } 705 }
702 706
703 static inline void gen_store_fpr32h (TCGv t, int reg) 707 static inline void gen_store_fpr32h (TCGv t, int reg)
704 { 708 {
705 - tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX); 709 + tcg_gen_mov_i32(fpu_fpr32h[reg], t);
706 } 710 }
707 711
708 static inline void get_fp_cond (TCGv t) 712 static inline void get_fp_cond (TCGv t)
@@ -710,10 +714,9 @@ static inline void get_fp_cond (TCGv t) @@ -710,10 +714,9 @@ static inline void get_fp_cond (TCGv t)
710 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); 714 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
711 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); 715 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
712 716
713 - tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));  
714 - tcg_gen_shri_i32(r_tmp2, r_tmp1, 24); 717 + tcg_gen_shri_i32(r_tmp2, fpu_fcr31, 24);
715 tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xfe); 718 tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xfe);
716 - tcg_gen_shri_i32(r_tmp1, r_tmp1, 23); 719 + tcg_gen_shri_i32(r_tmp1, fpu_fcr31, 23);
717 tcg_gen_andi_i32(r_tmp1, r_tmp1, 0x1); 720 tcg_gen_andi_i32(r_tmp1, r_tmp1, 0x1);
718 tcg_gen_or_i32(t, r_tmp1, r_tmp2); 721 tcg_gen_or_i32(t, r_tmp1, r_tmp2);
719 tcg_temp_free(r_tmp1); 722 tcg_temp_free(r_tmp1);
@@ -6009,8 +6012,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) @@ -6009,8 +6012,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
6009 6012
6010 gen_load_gpr(t0, rd); 6013 gen_load_gpr(t0, rd);
6011 gen_load_gpr(t1, rs); 6014 gen_load_gpr(t1, rs);
6012 - tcg_gen_ld_i32(r_tmp, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));  
6013 - tcg_gen_andi_i32(r_tmp, r_tmp, ccbit); 6015 + tcg_gen_andi_i32(r_tmp, fpu_fcr31, ccbit);
6014 tcg_gen_brcondi_i32(cond, r_tmp, 0, l1); 6016 tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
6015 tcg_temp_free(r_tmp); 6017 tcg_temp_free(r_tmp);
6016 6018
@@ -6043,8 +6045,7 @@ static inline void gen_movcf_s (int fs, int fd, int cc, int tf) @@ -6043,8 +6045,7 @@ static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
6043 6045
6044 gen_load_fpr32(fp0, fs); 6046 gen_load_fpr32(fp0, fs);
6045 gen_load_fpr32(fp1, fd); 6047 gen_load_fpr32(fp1, fd);
6046 - tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));  
6047 - tcg_gen_andi_i32(r_tmp1, r_tmp1, ccbit); 6048 + tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit);
6048 tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); 6049 tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1);
6049 tcg_gen_mov_i32(fp1, fp0); 6050 tcg_gen_mov_i32(fp1, fp0);
6050 tcg_temp_free(fp0); 6051 tcg_temp_free(fp0);
@@ -6075,8 +6076,7 @@ static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int t @@ -6075,8 +6076,7 @@ static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int t
6075 6076
6076 gen_load_fpr64(ctx, fp0, fs); 6077 gen_load_fpr64(ctx, fp0, fs);
6077 gen_load_fpr64(ctx, fp1, fd); 6078 gen_load_fpr64(ctx, fp1, fd);
6078 - tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));  
6079 - tcg_gen_andi_i32(r_tmp1, r_tmp1, ccbit); 6079 + tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit);
6080 tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); 6080 tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1);
6081 tcg_gen_mov_i64(fp1, fp0); 6081 tcg_gen_mov_i64(fp1, fp0);
6082 tcg_temp_free(fp0); 6082 tcg_temp_free(fp0);
@@ -8632,11 +8632,11 @@ static void fpu_dump_state(CPUState *env, FILE *f, @@ -8632,11 +8632,11 @@ static void fpu_dump_state(CPUState *env, FILE *f,
8632 8632
8633 8633
8634 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n", 8634 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
8635 - env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status,  
8636 - get_float_exception_flags(&env->fpu->fp_status)); 8635 + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, env->active_fpu.fp_status,
  8636 + get_float_exception_flags(&env->active_fpu.fp_status));
8637 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { 8637 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
8638 fpu_fprintf(f, "%3s: ", fregnames[i]); 8638 fpu_fprintf(f, "%3s: ", fregnames[i]);
8639 - printfpr(&env->fpu->fpr[i]); 8639 + printfpr(&env->active_fpu.fpr[i]);
8640 } 8640 }
8641 8641
8642 #undef printfpr 8642 #undef printfpr
@@ -8706,6 +8706,7 @@ void cpu_dump_state (CPUState *env, FILE *f, @@ -8706,6 +8706,7 @@ void cpu_dump_state (CPUState *env, FILE *f,
8706 8706
8707 static void mips_tcg_init(void) 8707 static void mips_tcg_init(void)
8708 { 8708 {
  8709 + int i;
8709 static int inited; 8710 static int inited;
8710 8711
8711 /* Initialize various static tables. */ 8712 /* Initialize various static tables. */
@@ -8717,10 +8718,24 @@ static void mips_tcg_init(void) @@ -8717,10 +8718,24 @@ static void mips_tcg_init(void)
8717 offsetof(CPUState, bcond), "bcond"); 8718 offsetof(CPUState, bcond), "bcond");
8718 btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, 8719 btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
8719 offsetof(CPUState, btarget), "btarget"); 8720 offsetof(CPUState, btarget), "btarget");
8720 - current_fpu = tcg_global_mem_new(TCG_TYPE_PTR,  
8721 - TCG_AREG0,  
8722 - offsetof(CPUState, fpu),  
8723 - "current_fpu"); 8721 + for (i = 0; i < 32; i++)
  8722 + fpu_fpr32[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  8723 + offsetof(CPUState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]),
  8724 + fregnames[i]);
  8725 + for (i = 0; i < 32; i++)
  8726 + fpu_fpr64[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  8727 + offsetof(CPUState, active_fpu.fpr[i]),
  8728 + fregnames_64[i]);
  8729 + for (i = 0; i < 32; i++)
  8730 + fpu_fpr32h[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  8731 + offsetof(CPUState, active_fpu.fpr[i].w[!FP_ENDIAN_IDX]),
  8732 + fregnames_h[i]);
  8733 + fpu_fcr0 = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  8734 + offsetof(CPUState, active_fpu.fcr0),
  8735 + "fcr0");
  8736 + fpu_fcr31 = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  8737 + offsetof(CPUState, active_fpu.fcr31),
  8738 + "fcr31");
8724 8739
8725 /* register helpers */ 8740 /* register helpers */
8726 #undef DEF_HELPER 8741 #undef DEF_HELPER
target-mips/translate_init.c
  View file @f01be15
@@ -489,14 +489,17 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def) @@ -489,14 +489,17 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
489 489
490 static void fpu_init (CPUMIPSState *env, const mips_def_t *def) 490 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
491 { 491 {
492 - env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext)); 492 + int i;
  493 +
  494 + for (i = 0; i < MIPS_FPU_MAX; i++)
  495 + env->fpus[i].fcr0 = def->CP1_fcr0;
493 496
494 - env->fpu->fcr0 = def->CP1_fcr0; 497 + memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
495 if (env->user_mode_only) { 498 if (env->user_mode_only) {
496 if (env->CP0_Config1 & (1 << CP0C1_FP)) 499 if (env->CP0_Config1 & (1 << CP0C1_FP))
497 env->hflags |= MIPS_HFLAG_FPU; 500 env->hflags |= MIPS_HFLAG_FPU;
498 #ifdef TARGET_MIPS64 501 #ifdef TARGET_MIPS64
499 - if (env->fpu->fcr0 & (1 << FCR0_F64)) 502 + if (env->active_fpu.fcr0 & (1 << FCR0_F64))
500 env->hflags |= MIPS_HFLAG_F64; 503 env->hflags |= MIPS_HFLAG_F64;
501 #endif 504 #endif
502 } 505 }