gwj / at91sam9263 · Commits

Commit ef29a70d18c2d551cf4bb74b8aa9638caac3391b

Authored by edgar_igl
1 parent 4586f9e9

CRIS MMU Updates 

* Add support for exec faults and for the k protection bit.
* Abort if search_pc causes recursive mmu faults.



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4349 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 28 additions and 10 deletions
target-cris/helper.c
  View file @ef29a70
@@ -79,6 +79,12 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, @@ -79,6 +79,12 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
79 miss = cris_mmu_translate(&res, env, address, rw, mmu_idx); 79 miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
80 if (miss) 80 if (miss)
81 { 81 {
  82 + if (env->exception_index == EXCP_MMU_FAULT)
  83 + cpu_abort(env,
  84 + "CRIS: Illegal recursive bus fault."
  85 + "addr=%x rw=%d\n",
  86 + address, rw);
  87 +
82 env->exception_index = EXCP_MMU_FAULT; 88 env->exception_index = EXCP_MMU_FAULT;
83 env->fault_vector = res.bf_vec; 89 env->fault_vector = res.bf_vec;
84 r = 1; 90 r = 1;
@@ -101,7 +107,7 @@ void do_interrupt(CPUState *env) @@ -101,7 +107,7 @@ void do_interrupt(CPUState *env)
101 { 107 {
102 int ex_vec = -1; 108 int ex_vec = -1;
103 109
104 - D(fprintf (stderr, "exception index=%d interrupt_req=%d\n", 110 + D(fprintf (logfile, "exception index=%d interrupt_req=%d\n",
105 env->exception_index, 111 env->exception_index,
106 env->interrupt_request)); 112 env->interrupt_request));
107 113
@@ -133,8 +139,9 @@ void do_interrupt(CPUState *env) @@ -133,8 +139,9 @@ void do_interrupt(CPUState *env)
133 } 139 }
134 140
135 if ((env->pregs[PR_CCS] & U_FLAG)) { 141 if ((env->pregs[PR_CCS] & U_FLAG)) {
136 - D(fprintf(logfile, "excp isr=%x PC=%x ERP=%x pid=%x ccs=%x cc=%d %x\n", 142 + D(fprintf(logfile, "excp isr=%x PC=%x SP=%x ERP=%x pid=%x ccs=%x cc=%d %x\n",
137 ex_vec, env->pc, 143 ex_vec, env->pc,
  144 + env->regs[R_SP],
138 env->pregs[PR_ERP], env->pregs[PR_PID], 145 env->pregs[PR_ERP], env->pregs[PR_PID],
139 env->pregs[PR_CCS], 146 env->pregs[PR_CCS],
140 env->cc_op, env->cc_mask)); 147 env->cc_op, env->cc_mask));
target-cris/mmu.c
  View file @ef29a70
@@ -32,12 +32,12 @@ @@ -32,12 +32,12 @@
32 32
33 #define D(x) 33 #define D(x)
34 34
35 -static int cris_mmu_enabled(uint32_t rw_gc_cfg) 35 +static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
36 { 36 {
37 return (rw_gc_cfg & 12) != 0; 37 return (rw_gc_cfg & 12) != 0;
38 } 38 }
39 39
40 -static int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg) 40 +static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
41 { 41 {
42 return (1 << seg) & rw_mm_cfg; 42 return (1 << seg) & rw_mm_cfg;
43 } 43 }
@@ -187,15 +187,26 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res, @@ -187,15 +187,26 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
187 set_exception_vector(0x0a, d_mmu_access); 187 set_exception_vector(0x0a, d_mmu_access);
188 set_exception_vector(0x0b, d_mmu_write); 188 set_exception_vector(0x0b, d_mmu_write);
189 */ 189 */
190 - if (!tlb_g 190 + if (!tlb_g
191 && tlb_pid != (env->pregs[PR_PID] & 0xff)) { 191 && tlb_pid != (env->pregs[PR_PID] & 0xff)) {
192 D(printf ("tlb: wrong pid %x %x pc=%x\n", 192 D(printf ("tlb: wrong pid %x %x pc=%x\n",
193 tlb_pid, env->pregs[PR_PID], env->pc)); 193 tlb_pid, env->pregs[PR_PID], env->pc));
194 match = 0; 194 match = 0;
195 res->bf_vec = vect_base; 195 res->bf_vec = vect_base;
  196 + } else if (cfg_k && tlb_k && usermode) {
  197 + D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
  198 + vaddr, lo, env->pc));
  199 + match = 0;
  200 + res->bf_vec = vect_base + 2;
196 } else if (rw == 1 && cfg_w && !tlb_w) { 201 } else if (rw == 1 && cfg_w && !tlb_w) {
197 - D(printf ("tlb: write protected %x lo=%x\n",  
198 - vaddr, lo)); 202 + D(printf ("tlb: write protected %x lo=%x pc=%x\n",
  203 + vaddr, lo, env->pc));
  204 + match = 0;
  205 + /* write accesses never go through the I mmu. */
  206 + res->bf_vec = vect_base + 3;
  207 + } else if (rw == 2 && cfg_x && !tlb_x) {
  208 + D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
  209 + vaddr, lo, env->pc));
199 match = 0; 210 match = 0;
200 res->bf_vec = vect_base + 3; 211 res->bf_vec = vect_base + 3;
201 } else if (cfg_v && !tlb_v) { 212 } else if (cfg_v && !tlb_v) {
target-cris/op_helper.c
  View file @ef29a70
@@ -60,8 +60,8 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) @@ -60,8 +60,8 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
60 saved_env = env; 60 saved_env = env;
61 env = cpu_single_env; 61 env = cpu_single_env;
62 62
63 - D(fprintf(logfile, "%s ra=%x acr=%x %x\n", __func__, retaddr,  
64 - env->regs[R_ACR], saved_env->regs[R_ACR])); 63 + D(fprintf(logfile, "%s pc=%x tpc=%x ra=%x\n", __func__,
  64 + env->pc, env->debug1, retaddr));
65 ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); 65 ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
66 if (__builtin_expect(ret, 0)) { 66 if (__builtin_expect(ret, 0)) {
67 if (retaddr) { 67 if (retaddr) {
@@ -89,7 +89,7 @@ void helper_tlb_update(uint32_t T0) @@ -89,7 +89,7 @@ void helper_tlb_update(uint32_t T0)
89 return; 89 return;
90 90
91 vaddr = cris_mmu_tlb_latest_update(env, T0); 91 vaddr = cris_mmu_tlb_latest_update(env, T0);
92 - D(printf("flush old_vaddr=%x vaddr=%x T0=%x\n", vaddr, 92 + D(fprintf(logfile, "flush old_vaddr=%x vaddr=%x T0=%x\n", vaddr,
93 env->sregs[SFR_R_MM_CAUSE] & TARGET_PAGE_MASK, T0)); 93 env->sregs[SFR_R_MM_CAUSE] & TARGET_PAGE_MASK, T0));
94 tlb_flush_page(env, vaddr); 94 tlb_flush_page(env, vaddr);
95 #endif 95 #endif