gwj / at91sam9263 · Commits

Commit ef056e439847457a5e64f134b8835e61ff53951b

Authored by balrog
1 parent bd9bdce6

Intel Mainstone II (ARM) machine by Armin Kuster. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3736 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 312 additions and 1 deletions
Makefile.target
  View file @ef056e4
... ... @@ -496,7 +496,7 @@ VL_OBJS+= arm-semi.o
496 496 VL_OBJS+= pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
497 497 VL_OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o
498 498 VL_OBJS+= pflash_cfi01.o gumstix.o
499   -VL_OBJS+= spitz.o ide.o serial.o nand.o ecc.o
  499 +VL_OBJS+= spitz.o ide.o serial.o nand.o ecc.o mainstone.o
500 500 VL_OBJS+= omap.o omap_lcdc.o omap1_clk.o omap_mmc.o omap_i2c.o
501 501 VL_OBJS+= palm.o tsc210x.o
502 502 CPPFLAGS += -DHAS_AUDIO
... ...
hw/boards.h
  View file @ef056e4
... ... @@ -93,4 +93,7 @@ extern QEMUMachine mcf5208evb_machine;
93 93 /* dummy_m68k.c */
94 94 extern QEMUMachine dummy_m68k_machine;
95 95  
  96 +/* mainstone.c */
  97 +extern QEMUMachine mainstone2_machine;
  98 +
96 99 #endif
... ...
hw/mainstone.c 0 → 100644
  View file @ef056e4
  1 +/*
  2 + * PXA270-based Intel Mainstone platforms.
  3 + *
  4 + * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
  5 + * <akuster@mvista.com>
  6 + *
  7 + * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
  8 + *
  9 + * This code is licensed under the GNU GPL v2.
  10 + */
  11 +#include "hw.h"
  12 +#include "pxa.h"
  13 +#include "arm-misc.h"
  14 +#include "sysemu.h"
  15 +#include "net.h"
  16 +#include "devices.h"
  17 +#include "boards.h"
  18 +
  19 +#define MST_ETH_PHYS 0x10000300
  20 +#define MST_FPGA_PHYS 0x08000000
  21 +
  22 +/* Mainstone FPGA for extern irqs */
  23 +#define FPGA_GPIO_PIN 0
  24 +#define MST_NUM_IRQS 16
  25 +#define MST_BASE MST_FPGA_PHYS
  26 +#define MST_LEDDAT1 0x10
  27 +#define MST_LEDDAT2 0x14
  28 +#define MST_LEDCTRL 0x40
  29 +#define MST_GPSWR 0x60
  30 +#define MST_MSCWR1 0x80
  31 +#define MST_MSCWR2 0x84
  32 +#define MST_MSCWR3 0x88
  33 +#define MST_MSCRD 0x90
  34 +#define MST_INTMSKENA 0xc0
  35 +#define MST_INTSETCLR 0xd0
  36 +#define MST_PCMCIA0 0xe0
  37 +#define MST_PCMCIA1 0xe4
  38 +
  39 +/* IRQ definitions */
  40 +#define ETHERNET_IRQ 3
  41 +
  42 +typedef struct mst_irq_state {
  43 + target_phys_addr_t target_base;
  44 + qemu_irq *parent;
  45 + qemu_irq *pins;
  46 +
  47 + uint32_t prev_level;
  48 + uint32_t leddat1;
  49 + uint32_t leddat2;
  50 + uint32_t ledctrl;
  51 + uint32_t gpswr;
  52 + uint32_t mscwr1;
  53 + uint32_t mscwr2;
  54 + uint32_t mscwr3;
  55 + uint32_t mscrd;
  56 + uint32_t intmskena;
  57 + uint32_t intsetclr;
  58 + uint32_t pcmcia0;
  59 + uint32_t pcmcia1;
  60 +} mst_irq_state;
  61 +
  62 +static void
  63 +mst_fpga_update_gpio(mst_irq_state *s)
  64 +{
  65 + uint32_t level, diff;
  66 + int bit;
  67 + level = s->prev_level ^ s->intsetclr;
  68 +
  69 + for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
  70 + bit = ffs(diff) - 1;
  71 + qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
  72 + }
  73 + s->prev_level = level;
  74 +}
  75 +
  76 +static void
  77 +mst_fpga_set_irq(void *opaque, int irq, int level)
  78 +{
  79 + mst_irq_state *s = (mst_irq_state *)opaque;
  80 +
  81 + if (level)
  82 + s->prev_level |= 1u << irq;
  83 + else
  84 + s->prev_level &= ~(1u << irq);
  85 +
  86 + if(s->intmskena & (1u << irq)) {
  87 + s->intsetclr = 1u << irq;
  88 + qemu_set_irq(s->parent[0], level);
  89 + }
  90 +}
  91 +
  92 +static uint32_t
  93 +mst_fpga_readb(void *opaque, target_phys_addr_t addr)
  94 +{
  95 + mst_irq_state *s = (mst_irq_state *) opaque;
  96 + addr -= s->target_base;
  97 +
  98 + switch (addr) {
  99 + case MST_LEDDAT1:
  100 + return s->leddat1;
  101 + case MST_LEDDAT2:
  102 + return s->leddat2;
  103 + case MST_LEDCTRL:
  104 + return s->ledctrl;
  105 + case MST_GPSWR:
  106 + return s->gpswr;
  107 + case MST_MSCWR1:
  108 + return s->mscwr1;
  109 + case MST_MSCWR2:
  110 + return s->mscwr2;
  111 + case MST_MSCWR3:
  112 + return s->mscwr3;
  113 + case MST_MSCRD:
  114 + return s->mscrd;
  115 + case MST_INTMSKENA:
  116 + return s->intmskena;
  117 + case MST_INTSETCLR:
  118 + return s->intsetclr;
  119 + case MST_PCMCIA0:
  120 + return s->pcmcia0;
  121 + case MST_PCMCIA1:
  122 + return s->pcmcia1;
  123 + default:
  124 + printf("Mainstone - mst_fpga_readb: Bad register offset "
  125 + REG_FMT " \n", addr);
  126 + }
  127 + return 0;
  128 +}
  129 +
  130 +static void
  131 +mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
  132 +{
  133 + mst_irq_state *s = (mst_irq_state *) opaque;
  134 + addr -= s->target_base;
  135 + value &= 0xffffffff;
  136 +
  137 + switch (addr) {
  138 + case MST_LEDDAT1:
  139 + s->leddat1 = value;
  140 + break;
  141 + case MST_LEDDAT2:
  142 + s->leddat2 = value;
  143 + break;
  144 + case MST_LEDCTRL:
  145 + s->ledctrl = value;
  146 + break;
  147 + case MST_GPSWR:
  148 + s->gpswr = value;
  149 + break;
  150 + case MST_MSCWR1:
  151 + s->mscwr1 = value;
  152 + break;
  153 + case MST_MSCWR2:
  154 + s->mscwr2 = value;
  155 + break;
  156 + case MST_MSCWR3:
  157 + s->mscwr3 = value;
  158 + break;
  159 + case MST_MSCRD:
  160 + s->mscrd = value;
  161 + break;
  162 + case MST_INTMSKENA: /* Mask interupt */
  163 + s->intmskena = (value & 0xFEEFF);
  164 + mst_fpga_update_gpio(s);
  165 + break;
  166 + case MST_INTSETCLR: /* clear or set interrupt */
  167 + s->intsetclr = (value & 0xFEEFF);
  168 + break;
  169 + case MST_PCMCIA0:
  170 + s->pcmcia0 = value;
  171 + break;
  172 + case MST_PCMCIA1:
  173 + s->pcmcia1 = value;
  174 + break;
  175 + default:
  176 + printf("Mainstone - mst_fpga_writeb: Bad register offset "
  177 + REG_FMT " \n", addr);
  178 + }
  179 +}
  180 +
  181 +CPUReadMemoryFunc *mst_fpga_readfn[] = {
  182 + mst_fpga_readb,
  183 + mst_fpga_readb,
  184 + mst_fpga_readb,
  185 +};
  186 +CPUWriteMemoryFunc *mst_fpga_writefn[] = {
  187 + mst_fpga_writeb,
  188 + mst_fpga_writeb,
  189 + mst_fpga_writeb,
  190 +};
  191 +
  192 +static void
  193 +mst_fpga_save(QEMUFile *f, void *opaque)
  194 +{
  195 + struct mst_irq_state *s = (mst_irq_state *) opaque;
  196 +
  197 + qemu_put_be32s(f, &s->prev_level);
  198 + qemu_put_be32s(f, &s->leddat1);
  199 + qemu_put_be32s(f, &s->leddat2);
  200 + qemu_put_be32s(f, &s->ledctrl);
  201 + qemu_put_be32s(f, &s->gpswr);
  202 + qemu_put_be32s(f, &s->mscwr1);
  203 + qemu_put_be32s(f, &s->mscwr2);
  204 + qemu_put_be32s(f, &s->mscwr3);
  205 + qemu_put_be32s(f, &s->mscrd);
  206 + qemu_put_be32s(f, &s->intmskena);
  207 + qemu_put_be32s(f, &s->intsetclr);
  208 + qemu_put_be32s(f, &s->pcmcia0);
  209 + qemu_put_be32s(f, &s->pcmcia1);
  210 +}
  211 +
  212 +static int
  213 +mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
  214 +{
  215 + mst_irq_state *s = (mst_irq_state *) opaque;
  216 +
  217 + qemu_get_be32s(f, &s->prev_level);
  218 + qemu_get_be32s(f, &s->leddat1);
  219 + qemu_get_be32s(f, &s->leddat2);
  220 + qemu_get_be32s(f, &s->ledctrl);
  221 + qemu_get_be32s(f, &s->gpswr);
  222 + qemu_get_be32s(f, &s->mscwr1);
  223 + qemu_get_be32s(f, &s->mscwr2);
  224 + qemu_get_be32s(f, &s->mscwr3);
  225 + qemu_get_be32s(f, &s->mscrd);
  226 + qemu_get_be32s(f, &s->intmskena);
  227 + qemu_get_be32s(f, &s->intsetclr);
  228 + qemu_get_be32s(f, &s->pcmcia0);
  229 + qemu_get_be32s(f, &s->pcmcia1);
  230 + return 0;
  231 +}
  232 +
  233 +static qemu_irq
  234 +*mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq)
  235 +{
  236 + mst_irq_state *s;
  237 + int iomemtype;
  238 + qemu_irq *qi;
  239 +
  240 + s = (mst_irq_state *) qemu_mallocz(sizeof(mst_irq_state));
  241 +
  242 + if (!s)
  243 + return NULL;
  244 + s->target_base = base;
  245 + s->parent = &cpu->pic[irq];
  246 +
  247 + /* alloc the external 16 irqs */
  248 + qi = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
  249 + s->pins = qi;
  250 +
  251 + iomemtype = cpu_register_io_memory(0, mst_fpga_readfn,
  252 + mst_fpga_writefn, s);
  253 + cpu_register_physical_memory(MST_BASE, 0x00100000, iomemtype);
  254 + register_savevm("mainstone_fpga", 0, 0, mst_fpga_save, mst_fpga_load, s);
  255 + return qi;
  256 +}
  257 +
  258 +enum mainstone_model_e { mainstone };
  259 +
  260 +static void mainstone_common_init(int ram_size, int vga_ram_size,
  261 + DisplayState *ds, const char *kernel_filename,
  262 + const char *kernel_cmdline, const char *initrd_filename,
  263 + const char *cpu_model, enum mainstone_model_e model, int arm_id)
  264 +{
  265 + uint32_t mainstone_ram = 0x04000000;
  266 + uint32_t mainstone_rom = 0x00800000;
  267 + struct pxa2xx_state_s *cpu;
  268 + qemu_irq *mst_irq;
  269 +
  270 + if (!cpu_model)
  271 + cpu_model = "pxa270-c5";
  272 +
  273 + /* Setup CPU & memory */
  274 + if (ram_size < mainstone_ram + mainstone_rom + PXA2XX_INTERNAL_SIZE) {
  275 + fprintf(stderr, "This platform requires %i bytes of memory\n",
  276 + mainstone_ram + mainstone_rom + PXA2XX_INTERNAL_SIZE);
  277 + exit(1);
  278 + }
  279 +
  280 + cpu = pxa270_init(mainstone_ram, ds, cpu_model);
  281 + cpu_register_physical_memory(0, mainstone_rom,
  282 + qemu_ram_alloc(mainstone_rom) | IO_MEM_ROM);
  283 +
  284 + /* Setup initial (reset) machine state */
  285 + cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
  286 +
  287 + mst_irq = mst_irq_init(cpu, MST_BASE, PXA2XX_PIC_GPIO_0);
  288 + smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);
  289 +
  290 + arm_load_kernel(cpu->env, mainstone_ram, kernel_filename, kernel_cmdline,
  291 + initrd_filename, arm_id, PXA2XX_SDRAM_BASE);
  292 +}
  293 +
  294 +static void mainstone_init(int ram_size, int vga_ram_size,
  295 + const char *boot_device, DisplayState *ds,
  296 + const char *kernel_filename, const char *kernel_cmdline,
  297 + const char *initrd_filename, const char *cpu_model)
  298 +{
  299 + mainstone_common_init(ram_size, vga_ram_size, ds, kernel_filename,
  300 + kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
  301 +}
  302 +
  303 +QEMUMachine mainstone2_machine = {
  304 + "mainstone",
  305 + "Mainstone II (PXA27x)",
  306 + mainstone_init,
  307 +};
... ...
... ... @@ -7488,6 +7488,7 @@ static void register_machines(void)
7488 7488 qemu_register_machine(&lm3s6965evb_machine);
7489 7489 qemu_register_machine(&connex_machine);
7490 7490 qemu_register_machine(&verdex_machine);
  7491 + qemu_register_machine(&mainstone2_machine);
7491 7492 #elif defined(TARGET_SH4)
7492 7493 qemu_register_machine(&shix_machine);
7493 7494 qemu_register_machine(&r2d_machine);
... ...